Semiconductor device, storage system and preparation method of semiconductor device

Abstract

The invention provides a semiconductor device, a storage system and a preparation method of the semiconductor device, relates to the technical field of semiconductor chips, and aims to solve the problem that the performance of the semiconductor device is reduced due to leakage current in the semiconductor device. The semiconductor device includes a stack structure, a channel structure, a lead-out structure, a conductive layer and a partition portion. The stacked structure comprises a plurality of gate layers which are arranged in a stacked manner; the stacked structure includes a first surface and a second surface. The channel structure penetrates through the stack structure and protrudes out of the first surface of the stack structure. The lead-out structure penetrates from the second surface to the corresponding gate layer and is connected with the corresponding gate layer. The conductive layer is arranged on the first surface; the conductive layer covers the channel structure and is connected with the channel structure. The partition part is arranged between the channel structure and the lead-out structure; the partition portion breaks the conductive layer, and the partition portion is made of an insulating material. The semiconductor device is applied to a storage system so as to realize data reading and writing operation.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor device, a storage system, and a method for preparing the semiconductor device. Background Art

[0002] As the feature size of memory cells approaches the process limit, planar processes and manufacturing technologies become challenging and costly, causing the storage density of 2D or planar NAND flash memory to approach an upper limit.

[0003] To overcome the limitations of 2D or planar NAND flash memory, the industry has developed three-dimensional memory (3D NAND) with a three-dimensional structure, which increases storage density by arranging storage cells three-dimensionally on a substrate. Among them, how to improve the electrical performance of three-dimensional memory is a problem that needs to be solved at present. Summary of the invention

[0004] Embodiments of the present disclosure provide a semiconductor device, a storage system, and a method for manufacturing a semiconductor device, aiming to solve the leakage problem in the semiconductor device so as to improve the electrical performance and reliability of the semiconductor device.

[0005] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0006] In one aspect, a semiconductor device is provided, which includes a stack structure, a channel structure, a lead structure, a conductive layer, and a partition.

[0007] The stacked structure includes multiple gate layers stacked in layers; the stacked structure includes a first surface and a second surface arranged opposite to each other in a third direction, and the third direction is the direction in which the multiple gate layers are stacked. The channel structure runs through the stacked structure and protrudes from the first surface of the stacked structure. The lead-out structure runs from the second surface to the corresponding gate layer and is connected to the corresponding gate layer. The conductive layer is arranged on the first surface; the conductive layer covers the channel structure and is connected to the channel structure. The partition portion is arranged between the channel structure and the lead-out structure; the partition portion disconnects the conductive layer, and the material of the partition portion includes an insulating material.

[0008] The disclosed embodiment of the present invention provides a partition portion to disconnect and electrically insulate a portion of the conductive layer located on the channel structure from a portion of the conductive layer located on the lead-out structure, so that the conductive layer cannot transmit the electrical signal to the conductive layer on the lead-out structure during the process of transmitting the source signal to the channel structure, thereby avoiding the generation of a loop between the gate layer near the lead-out structure and the portion of the conductive layer located on the lead-out structure, thereby avoiding the generation of leakage current, effectively improving the stability of the threshold voltage in the storage cell string of the semiconductor device, and thus improving the electrical performance and reliability of the semiconductor device.

[0009] In some embodiments, the semiconductor device further comprises a plurality of imaginary channel structures. The plurality of imaginary channel structures are disposed between the channel structure and the lead-out structure, and the plurality of imaginary channel structures penetrate the stacked structure. In the orthographic projection on the second surface, the partition portion at least partially overlaps with at least one imaginary channel structure.

[0010] In some embodiments, one end of at least one virtual channel structure protrudes from the first surface, the end of the virtual channel structure protruding from the first surface has a recess, and the partition portion fills the recess; and / or, the end surface of one end of at least one virtual channel structure is flush with the first surface or recessed relative to the first surface, and the partition portion partially covers the end surface of the virtual channel structure.

[0011] That is, part or all of one end of the virtual channel structure protruding from the first surface is removed, and the removed part of the virtual channel structure is replaced by a partition portion, so that the part of the conductive layer located on the channel structure and the part located on the lead-out structure are disconnected, and at the same time, other structures corresponding to the disconnected position of the conductive layer (for example, part or all of the end of the virtual channel structure protruding from the first surface) are removed, thereby avoiding conduction between the two disconnected parts of the conductive layer through other conductive structures (for example, conduction through the semiconductor channel layer of the virtual channel structure), so as to ensure that the conductive layer is fully disconnected and further reduce the leakage risk of the semiconductor device.

[0012] In some embodiments, the semiconductor device further includes a gate line isolation structure. The gate line isolation structure penetrates the stacked structure and extends along a first direction; the first direction is parallel to the second surface. The partition portion extends along a second direction, the second direction is parallel to the second surface, and intersects with the first direction. In the orthographic projection on the second surface, the partition portion intersects with the gate line isolation structure, so that the partition portion can cut the conductive layer into two parts in a direction perpendicular to the extension direction of the gate line, so that one of the two parts of the conductive layer after being cut is located in the storage area and the other part is located in the connection area.

[0013] In some embodiments, one end of the gate line isolation structure protrudes from the first surface, a gap is provided at the end of the gate line isolation structure protruding from the first surface, and the partition portion fills the gap to ensure sufficient disconnection of the conductive layer.

[0014] In some embodiments, the semiconductor device includes a storage area and a connection area, the connection area is disposed at least on one side of the storage area, the channel structure is disposed in the storage area, the lead structure is disposed in the connection area, and the partition is disposed in the connection area near the storage area.

[0015] By setting the partition part at a position close to the storage area in the connection area, it is ensured that of the two parts of the conductive layer disconnected by the partition part, one part is located in the storage area and the other part is located in the connection area, that is, it is ensured that the part of the conductive layer located on the channel structure and the part located on the lead-out structure are disconnected from each other, thereby enabling the transmission of electrical signals (such as source signals) of the channel structure while avoiding leakage problems in the semiconductor device.

[0016] In some embodiments, the stacked structure further includes multiple first dielectric layers and multiple sacrificial layers, the multiple first dielectric layers are alternately stacked with multiple gate layers, and a gate layer and a sacrificial layer are arranged in the same layer; the first dielectric layer is at least located in the storage area, and the sacrificial layer is located in the connection area. The lead-out structure includes a first sub-section and a second sub-section, the first sub-section is embedded in the sacrificial layer arranged in the same layer as the corresponding gate layer, and is connected to the corresponding gate layer; the second sub-section penetrates from the second surface to the sacrificial layer arranged in the same layer as the corresponding gate layer, and is connected to the first sub-section. The partition portion is located between the position where the first sub-section is connected to the corresponding gate layer and the channel structure.

[0017] That is, the partition portion disconnects the conductive layer at a position between the channel structure and the leakage position (the position where the lead structure is connected to the corresponding gate layer), thereby solving the leakage problem of the semiconductor device and improving the electrical performance and reliability of the semiconductor device.

[0018] In some embodiments, along the first direction, a minimum distance between the partition portion and the channel structure is greater than or equal to 15 μm.

[0019] By setting the minimum spacing between the partition part and the channel structure to be greater than or equal to 15 μm, on the one hand, the partition part is ensured to be located between the channel structure and the lead-out structure, and on the other hand, the disconnection position of the conductive layer is controlled to avoid affecting the normal storage function of the storage cell string in the storage area.

[0020] In some embodiments, the semiconductor device further comprises a first insulating layer. The first insulating layer is disposed on a side of the conductive layer away from the stacking structure and covers a storage area and a connection area of ​​the semiconductor device. The partition portion is integrally disposed with the first insulating layer.

[0021] The first insulating layer is used to realize the external connection of the lead-out structure. By integrally arranging the partition part with the first insulating layer, the process of preparing the partition part can be compatible with the preparation process of the external connection structure of the lead-out structure, thereby simplifying the preparation process of the semiconductor device and improving the preparation efficiency of the semiconductor device.

[0022] In some embodiments, the semiconductor device further includes a contact column, which penetrates the first insulating layer and is connected to the lead-out structure, thereby facilitating external connection of the lead-out structure.

[0023] On the other hand, a method for preparing a semiconductor device is provided, the method comprising: forming a stacking structure; the stacking structure comprises a plurality of gate layers; the stacking structure comprises a first surface and a second surface arranged opposite to each other in a third direction, the third direction being the direction in which the plurality of gate layers are stacked. Forming a channel structure; the channel structure penetrates the stacking structure and protrudes from the first surface of the stacking structure. Forming a lead-out structure; penetrating from the second surface to the corresponding gate layer and connected to the corresponding gate layer. Forming a conductive layer; the conductive layer is disposed on the first surface; the conductive layer covers the channel structure and is connected to the channel structure. Disconnecting the conductive layer; a groove is formed between the two disconnected parts of the conductive layer; the groove is located between the channel structure and the lead-out structure. Filling the groove to form a partition; the material of the partition has electrical insulation.

[0024] It can be understood that the beneficial effects that can be achieved by the method for preparing the semiconductor device provided by the above embodiments of the present disclosure can refer to the beneficial effects brought about by the design method of the semiconductor device mentioned above, and will not be repeated here.

[0025] In some embodiments, the preparation method further includes: while disconnecting the conductive layer, etching the conductive layer to form a first through hole; the first through hole exposes the lead structure. Forming an insulating layer; the insulating layer is disposed on a side of the conductive layer away from the stacked structure and covers the storage area and connection area of ​​the semiconductor device; the insulating layer fills the first through hole and the groove, and the portion of the insulating layer filling the groove forms a partition. Forming a contact column; the contact column penetrates the insulating layer and is connected to the lead structure.

[0026] By making the process of preparing the external connection structure of the lead-out structure (including forming the first through hole and preparing the insulating layer) compatible with the process of preparing the partition part, the preparation process of the semiconductor device can be simplified and the preparation efficiency of the semiconductor device can be improved.

[0027] In another aspect, a storage system is provided. The storage system includes a controller and a semiconductor device provided by any one of the above embodiments. The controller is coupled to the semiconductor device to control the semiconductor device to store data.

[0028] It can be understood that the beneficial effects that can be achieved by the storage system provided by the above embodiments of the present disclosure can refer to the beneficial effects brought about by the design method of the semiconductor device mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0030] Figure 1 is a schematic diagram of the structure of a storage system according to some embodiments;

[0031] Figure 2 is a schematic structural diagram of a semiconductor device according to some embodiments;

[0032] Figure 3 for Figure 2 The enlarged view of the structure corresponding to the dotted box A in FIG.

[0033] Figure 4 For along Figure 3 A cross-sectional view of the section line BB' in FIG.

[0034] Figure 5 is another structural schematic diagram of a semiconductor device according to some embodiments;

[0035] Figure 6 for Figure 5 The equivalent circuit diagram corresponding to the semiconductor device in;

[0036] Figure 7 The corresponding edge in the preparation process Figure 3 A cross-sectional view of the section line CC' in FIG.

[0037] Figure 8 For along Figure 3 Another cross-sectional view of the section line BB' in FIG.

[0038] Fig. 9 For along Figure 3 Another cross-sectional view of the section line BB' in FIG.

[0039] Fig.10 For along Figure 3 A cross-sectional view of the section line EE' in FIG.

[0040] Fig.11 and Fig.12 is a flow chart of manufacturing a semiconductor device according to some embodiments;

[0041] Figures 13 to 26 It is a cross-sectional view corresponding to each preparation step of the semiconductor device. DETAILED DESCRIPTION

[0042] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0043] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0044] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, ie, meaning "including, but not limited to."

[0045] In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that a particular feature, structure, material or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0046] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0047] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0048] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0049] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0050] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0051] In the context of the present disclosure, the meanings of “on,” “over,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “over” or “above” means not only “above” or “over” something, but also includes the meaning of “above” or “over” something without intervening features or layers therebetween (i.e., directly on something).

[0052] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0053] As used herein, the term "substrate" refers to a material on which subsequent material layers may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0054] The present disclosure provides an electronic device, which may be, for example, a mobile phone, a tablet computer, a personal digital assistant (PDA), a television, a smart wearable product (e.g., a smart watch, a smart bracelet), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a charging small household appliance (e.g., a soymilk machine, a sweeping robot), a drone, a radar, an aerospace equipment, a vehicle-mounted device, a vehicle, and other different types of user devices or terminal devices; the electronic device may also be a network device such as a base station. The embodiments of the present application do not impose any special restrictions on the specific form of the electronic device.

[0055] The electronic device is provided with a storage system 1000 (see Figure 1 ) in order to realize the storage of relevant data in the electronic device.

[0056] Exemplarily, the electronic device 1000 may further include at least one of a central processing unit (CPU) and a cache.

[0057] The present disclosure also provides a storage system. Figure 1 A schematic diagram of the structure of a storage system 1000 provided in an embodiment of the present disclosure.

[0058] like Figure 1 As shown, the storage system 1000 includes a semiconductor device 100 and a controller 200. The controller 200 is coupled to the semiconductor device 100 to control the semiconductor device 100 to store data.

[0059] The storage system 1000 can be applied to the above-mentioned electronic devices, for example, can be integrated or packaged in the electronic device, for example, can be packaged in the electronic device through Universal Flash Storage (UFS) or Embedded Multi Media Card (eMMC).

[0060] Alternatively, the storage system 1000 may also be integrated into a card-type memory. The card-type memory may include any one of a PC card (PCMCIA, Personal Computer 3D Memory Card International Association), a Compact Flash (CF) card, a Smart Media (SM) card, a 3D memory, a Multimedia Card (MMC), a Secure Digital Memory Card (SD), and a UFS.

[0061] Alternatively, the storage system 1000 may also be integrated into a solid state drive (SSD).

[0062] Exemplarily, the storage system 1000 may include one semiconductor device 100, or may include a plurality of semiconductor devices 100 (eg, Figure 1 shown).

[0063] Exemplarily, the aforementioned controller 200 may be configured to manage data stored in the semiconductor device 100 and communicate with an external device (eg, a host).

[0064] Exemplarily, the controller 200 may also be configured to control the operation of the semiconductor device 100 , such as controlling the semiconductor device 100 to perform read, erase, and program operations.

[0065] Exemplarily, the controller 200 may also be configured to manage various functions regarding data stored or to be stored in the semiconductor device 100 , including at least one of bad block management, garbage collection, logical to physical address conversion, and wear leveling.

[0066] Exemplarily, the controller 200 may also be configured to process an error correction code regarding data read from or written to the semiconductor device 100 .

[0067] Of course, the controller 200 may also perform any other suitable functions, such as formatting the semiconductor device 100 . For example, the controller 200 may also communicate with an external device (eg, a host) via at least one of various interface protocols.

[0068] It should be noted that the interface protocol may include at least one of the USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI Express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer interface (SCSI) protocol, enhanced minidisk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, and Firewire protocol.

[0069] By way of example, the semiconductor device 100 may be a three-dimensional memory. Alternatively, the semiconductor device 100 may be a part of a three-dimensional memory.

[0070] It should be noted that the “three-dimensional memory” may refer to a device formed by a string of memory cell transistors (eg, a NAND memory cell string) arranged in an array on a main surface of a substrate and extending in a direction perpendicular to the substrate.

[0071] The present disclosure also provides a semiconductor device 100. Figure 2 A top view of a semiconductor device 100 provided in an embodiment of the present disclosure, Figure 3 for Figure 2 The enlarged image corresponding to the dotted box A in Figure 4 For along Figure 3 A cross-sectional view of the section line BB' in FIG.

[0072] The semiconductor device 100 may be used in the aforementioned storage system 1000 , or may be used as a separate device in other electronic devices, and the present disclosure does not limit its specific application scenario.

[0073] like Figure 2 As shown, the semiconductor device 100 includes a storage area C and a connection area S. The storage area C is an area where a storage cell string is set to realize a storage function, and the connection area S is an area that can realize an external connection of the storage cell string in the storage area C. The connection area S is arranged on at least one side of the storage area C. For example, the connection area S can be arranged on one side of the storage area C; for another example, the connection area S can be arranged on two opposite sides of the storage area; Figure 2 FIG. 4 shows a case where the connection area S is arranged on one side of the storage area C. Figure 2 As shown, two adjacent storage areas C can share a connection area S.

[0074] like Figure 3 and Figure 4 As shown, the semiconductor device 100 includes a stack structure 10 , a channel structure 20 , a lead structure 30 , a conductive layer 40 and a partition 50 .

[0075] Among them, see Figure 4 The stack structure 10 may include a plurality of gate layers 11 stacked together.

[0076] See also Figure 4 The multiple gate layers 11 are stacked along the third direction Z, and two adjacent gate layers 11 are spaced apart.

[0077] It is understandable that the gate layer 11 may be stacked in multiple layers, for example, 4 layers, 16 layers, 32 layers, 64 layers, 128 layers or more layers, and the embodiments of the present disclosure are not limited to this.

[0078] Exemplarily, each gate layer 11 may include a plurality of gate lines 111 arranged along the second direction Y. Figure 3 In the figure, only one gate line 111 is taken as an example to exemplarily illustrate the structure of the gate layer 11 .

[0079] See also Figure 3 The gate line 111 extends along the first direction X and extends from the storage area C to the connection area S.

[0080] The first direction X and the second direction Y are both parallel to the plane where the gate layer 11 is located (for example, parallel to Figure 4 The first surface 1a or the second surface 1b shown in the figure), and the first direction X and the second direction Y intersect each other, for example, the first direction X and the second direction Y can be perpendicular to each other. The third direction Z is perpendicular to the first direction X and the second direction Y.

[0081] Exemplarily, the material of the gate line 111 includes a conductive material, for example, may include at least one of tungsten, cobalt, copper, aluminum, doped silicon, and metal silicide.

[0082] For example, see Figure 4 The stack structure 10 may further include a first dielectric layer 12 alternately stacked with the gate layer 11 , and the first dielectric layer 12 extends from the storage area C to the connection area S.

[0083] Exemplarily, the material of the first dielectric layer 12 may include insulating materials, for example, may include at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organic silicate glass, dielectric metal oxide (such as aluminum oxide, hafnium dioxide, etc.), silicate and organic insulating material.

[0084] The first dielectric layer 12 can electrically insulate two adjacent gate layers 11 , thereby preventing short circuits between gate lines 111 in the two gate layers 11 , thereby ensuring the stability of the semiconductor device 100 .

[0085] For example, see Figure 4 The stack structure 10 may further include a sacrificial layer 13. The sacrificial layer 13 is disposed in the same layer as the gate layer 11. The sacrificial layer 13 is located in the connection region S.

[0086] Exemplarily, the material of the sacrificial layer 13 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, amorphous silicon, amorphous carbon, and polycrystalline silicon.

[0087] For example, see Figure 4 The stacked structure 10 further includes a second dielectric layer 113, which covers the aforementioned adhesive layer 112 to enhance the insulation between the channel structure 20 and the gate line 111, thereby avoiding leakage between the two, which may lead to a decrease in the electrical performance of the semiconductor device 100, such as causing the threshold voltage of the semiconductor device 100 to drift, thereby affecting the electrical performance and stability of the semiconductor device 100.

[0088] Exemplarily, the material of the second dielectric layer 113 may include a material with a high dielectric constant, for example, a material with a dielectric constant greater than or equal to 7, for example, at least one of aluminum oxide, hafnium oxide, and tantalum oxide.

[0089] For example, see Figure 4 The stacked structure 10 may further include an adhesive layer 112 , which is disposed to cover the gate line 111 and is used to improve the adhesion between the gate line 111 and the second dielectric layer 113 .

[0090] Exemplarily, the material of the bonding layer 112 includes at least one of titanium nitride, tantalum nitride, and tungsten carbide.

[0091] See also Figure 4 The stacked structure 10 includes a first surface 1a and a second surface 1b that are arranged opposite to each other in a third direction Z.

[0092] The third direction Z is the direction in which the multiple gate layers 11 are stacked.

[0093] See also Figure 4 The channel structure 20 penetrates the stack structure 10 and protrudes from the first surface 1a of the stack structure 10, that is, extends from the first surface 1a. At least a portion of the channel structure 20 is used to store data so as to realize the storage function of the semiconductor device 100.

[0094] It is understandable that there may be multiple channel structures 20 to increase the storage capacity of the semiconductor device 100. The channel structure 20 may be cylindrical, truncated cone, or prism-shaped, etc. The embodiment of the present disclosure does not further limit the shape of the channel structure 20.

[0095] For example, Figure 4 As shown, the channel structure 20 may include, for example, a semiconductor channel layer 21 and a storage function layer 22 , and the storage function layer 22 is disposed around the semiconductor channel layer 21 .

[0096] Exemplarily, the material of the semiconductor channel layer 21 may include semiconductor materials, and the semiconductor materials may include single crystal silicon, polycrystalline silicon, single crystal germanium, III-V group compound semiconductor materials, II-VI group compound semiconductor materials, and other suitable semiconductor materials.

[0097] For example, see Figure 4 The storage function layer 22 may include, for example, a blocking layer 221, a charge trapping layer 222 and a tunneling layer 223. The materials of the blocking layer 221, the charge trapping layer 222, the tunneling layer 223 and the semiconductor channel layer 21 may be silicon oxide, silicon nitride, silicon oxide and polysilicon, respectively, to form an "ONOP" structure.

[0098] It is understandable that the embodiments of the present disclosure only illustrate the channel structure 20 by taking the ONOP structure and some materials of the structure as examples, and do not limit its specific structure. It is understandable that the channel structure 20 may also include other film layers, or more or fewer film layers than the aforementioned examples, or the material of the film layer may include other unmentioned materials.

[0099] For example, see Figure 4 The storage function layer 22 extends from the second surface 1b of the stacked structure 10 to the first surface 1a of the stacked structure 10. The semiconductor channel layer 21 extends through the stacked structure 10, and one end of the semiconductor channel layer 21 protrudes from the first surface 1a of the stacked structure 10.

[0100] For example, see Figure 4 The channel structure 20 may further include a channel filling layer 23 , and the channel filling layer 23 is disposed on a side of the semiconductor channel layer 21 away from the storage function layer 22 to provide mechanical support.

[0101] By way of example, the channel filling layer 23 may include gaps so as to relieve structural stress of the semiconductor device 100 .

[0102] Exemplarily, the material of the channel filling layer 23 includes an insulating material, for example, may include at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organic silicate glass, dielectric metal oxides (such as aluminum oxide, hafnium dioxide, etc.) and their silicates, and organic insulating materials.

[0103] The stacked structure 10 and the channel structure 20 may form a plurality of memory cell strings M. Figure 5 A schematic diagram of the structure of a storage unit string M provided in an embodiment of the present disclosure, Figure 6 It is the equivalent circuit diagram corresponding to the storage cell string M.

[0104] For example, see Figure 5 and Figure 6, the memory cell string M may include a plurality of transistors T, a transistor T (eg Figure 6 T1~T6 in the figure can be set as a memory cell, and these transistors T are connected together to form a memory cell string M.

[0105] A transistor T can be formed by a channel structure 20 and a gate line 111 surrounding the channel structure 20, wherein the two ends of the channel structure 20 in the memory cell string M are electrically connected to the source line SL and the bit line BL, respectively, and the gate line 111 is configured to control the conduction state of the transistor T, that is, to control the conduction state between the source line SL and the bit line BL.

[0106] Wherein, illustratively, along the third direction Z, the gate line 111 closest to the first surface 1a in the stacked structure 10 is constructed as a source selection gate SGS, and the source selection gate SGS is configured to control the conduction state of the transistor T6, thereby controlling the conduction state of the source channel in the memory cell string M. The gate line 111 closest to the second surface 1b in the stacked structure 10 (for example, the gate line 111 farthest from the source selection gate SGS among the multiple gate lines 111) is constructed as a drain selection gate SGD, and the drain selection gate SGD is configured to control the conduction state of the transistor T1, thereby controlling the conduction state of the drain channel in the memory cell string M. The gate line 111 located in the middle part of the stacked structure 10 can be constructed as a plurality of word lines WL, for example, including word line WL0, word line WL1, word line WL2, and word line WL3. By writing different voltages on the word line WL, data writing, reading, and erasing of each memory cell (eg, transistors T2, T3, T4, T5) in the memory cell string M can be completed.

[0107] See also Figure 4 The lead-out structure 30 penetrates from the second surface 1b to the corresponding gate layer 11 and is connected to the corresponding gate layer 11. Specifically, the lead-out structure 30 is connected to the gate line 111 in the corresponding gate layer 11.

[0108] The lead-out structure 30 is used to lead out the gate line 111 so as to transmit an external gate signal to the gate line 111 in the gate layer 11 , thereby achieving control over the channel structure 20 .

[0109] It should be noted that the “corresponding gate layer 11” here refers to the gate layer 11 that needs to transmit electrical signals through a certain lead-out structure 30, which corresponds to the lead-out structure 30. For example, the third gate layer 11 in the direction from the second surface 1b to the first surface 1a corresponds to the lead-out structure 30 connected to it. Then, the lead-out structure 30 will penetrate the film layer where the first and second gate layers 11 of the stacked structure 10 are located, and then be connected to the third gate layer 11.

[0110] It is understandable that there may be multiple lead-out structures 30 , and each gate line 111 may correspond to one lead-out structure 30 .

[0111] For example, see Figure 4 , the lead-out structure 30 is located in the connection area S.

[0112] Exemplarily, the lead-out structure 30 may be a self-aligned contact (SCT for short) structure.

[0113] For example, see Figure 4 The lead-out structure 30 may include a first sub-portion 31 and a second sub-portion 32 that are connected.

[0114] Among them, see Figure 4 The first sub-section 31 is disposed in the same layer and connected to the corresponding gate layer 11, for example, see Figure 4 The first sub-portion 31 is embedded in the sacrificial layer 13 which is arranged in the same layer as the corresponding gate layer 11, that is, the first sub-portion 31, the corresponding gate layer 11, and the corresponding sacrificial layer 13 (that is, the sacrificial layer 13 in which the first sub-portion 31 is embedded) are arranged in the same layer.

[0115] See also Figure 4 The second sub-portion 32 penetrates from the second surface 1b to the sacrificial layer 13 disposed on the same layer as the corresponding gate layer 11 and is connected to the first sub-portion 31. That is, the second sub-portion 32 penetrates to the corresponding sacrificial layer 13 to achieve connection with the first sub-portion 31.

[0116] One end of the second sub-portion 32 away from the first sub-portion 31 is used to connect to a conductive structure (such as a word line) outside the stack structure 10 so as to transmit an external electrical signal to the gate line 111 in the gate layer 11 through the second sub-portion 32 and the first sub-portion 31 in sequence.

[0117] Exemplarily, the thickness of the first sub-portion 31 is the same as or approximately the same as the thickness of a gate layer 11 .

[0118] For example, the materials of the first sub-portion 31 and the second sub-portion 32 may include at least one of tungsten, cobalt, copper, aluminum, doped polysilicon and metal silicide. The materials of the first sub-portion 31 and the second sub-portion 32 and the gate layer 11 may be the same or different.

[0119] Exemplarily, the first sub-section 31 and the second sub-section 32 may be an integrally formed structure, so as to improve the reliability of the electrical contact between the first sub-section 31 and the second sub-section 32 .

[0120] For example, see Figure 4The lead-out structure 30 may further include an electrical isolation layer 33 located between the second sub-portion 32 and the stacked structure 10 so as to improve the electrical insulation between the lead-out structure 30 and other gate layers 11 except the corresponding gate layer 11, thereby improving the reliability of the lead-out structure 30 in the semiconductor device 100.

[0121] Exemplarily, the material of the electrical isolation layer 33 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organic silicate glass, dielectric metal oxides (eg, aluminum oxide, hafnium dioxide, etc.) and silicates thereof, and organic insulating materials.

[0122] For example, see Figure 4 The lead-out structure 30 may further include a receiving cavity 34 formed by the second sub-portion 32. Exemplarily, the receiving cavity 34 is filled with insulating material.

[0123] Exemplarily, the accommodating cavity 34 is filled with insulating material, so as to provide mechanical support for the lead-out structure 30 , improve the mechanical strength of the electrical contact between the first sub-portion 31 and the second sub-portion 32 , and thus improve the reliability of the semiconductor device 100 .

[0124] Exemplarily, the insulating material filled in the accommodating cavity 34 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organic silicate glass, dielectric metal oxides (such as aluminum oxide, hafnium dioxide, etc.) and their silicates, and organic insulating materials.

[0125] Exemplarily, an air gap may be provided in the aforementioned accommodation cavity 34 .

[0126] It is understandable that the number of the air gaps may be one or more. In some embodiments, the air gaps may be formed when the accommodating cavity 34 is filled with insulating material to reduce the structural stress of the lead-out structure 30 and improve the reliability of the semiconductor device 100 .

[0127] It is understandable that the lead-out structure 30 is only exemplarily described in the embodiment of the present disclosure, and the lead-out structure 30 may also be other structures, shapes or materials that can realize external connection of the gate line 111, and the embodiment of the present disclosure is not limited to this.

[0128] See also Figure 4 , the conductive layer 40 is disposed on the first surface 1a.

[0129] Exemplarily, the material of the conductive layer 40 may include a semiconductor material, for example, single crystal silicon, single crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials.

[0130] Exemplarily, the conductive layer 40 may be partially or fully doped. For example, the conductive layer 40 may include a doped region doped with a P-type or N-type dopant. The conductive layer 40 may also include a non-doped region.

[0131] See also Figure 4 , the conductive layer 40 covers the channel structure 20 and is connected to the channel structure 20 .

[0132] For example, see Figure 4 The semiconductor channel layer 21 of the channel structure 20 penetrates the stack structure 10, and one end protrudes from the first surface 1a of the stack structure 10, so that the source end of the memory cell string M leaks out (for example, equivalent to leaking the source end of the transistor T6), and the conductive layer 40 at least partially covers and adheres to the surface of the semiconductor channel layer 21, thereby achieving coupling with the source end of the memory cell string M.

[0133] See also Figure 3 and Figure 4 The conductive layer 40 at least partially covers the first surface 1a of the stacked structure 10, and at least part of the conductive layer 40 contacts the ends of the plurality of channel structures 20 protruding from the first surface 1a, so that the plurality of channel structures 20 can realize a common source.

[0134] For example, see Figure 4 The conductive layer 40 may include a first sublayer 41 and a second sublayer 42. The second sublayer 42 is located between the first sublayer 41 and the stacked structure 10.

[0135] For example, the first sublayer 41 can be used as a source layer (i.e., a source line SL). For example, the first sublayer 41 covers the channel structure 20 and is connected to the channel structure 20 (e.g., connected to the semiconductor channel layer 21 of the channel structure 20) so as to transmit a source signal to the memory cell string M.

[0136] By way of example, the material of the second sub-layer 42 may be polysilicon.

[0137] For example, see Figure 4 The second sublayer 42 is disposed on the first surface 1a of the stacked structure 10, and the channel structure 20 runs through the second sublayer 42. The second sublayer 42 can increase the mechanical strength of the semiconductor device 100 and improve the reliability of the semiconductor device 100 on the one hand, and can serve as an etching stop layer in the process of removing the storage function layer 22 of the channel structure 20 protruding from the first surface 1a, so as to avoid damage to the stacked structure 10 and the portion of the channel structure 20 located in the stacked structure 10.

[0138] For example, the first sub-layer 41 and the second sub-layer 42 may be crystallized into one after a subsequent annealing process, and may serve together as a source layer of the semiconductor device 100 .

[0139] For example, see Figure 3 The semiconductor device 100 further includes a dummy channel structure 60. The dummy channel structure 60 may be located in the connection region S.

[0140] For example, see Figure 4 , at least a portion of the dummy channel structure 60 may have the same structure as the channel structure 20. For example, see Figure 4 The dummy channel structure 60 may also include a semiconductor channel layer and a storage function layer, and the storage function layer is arranged around the semiconductor channel layer.

[0141] Exemplarily, the dummy channel structure 60 may be integrally formed with the channel structure 20 , and the dummy channel structure 60 may provide mechanical support for a region of the semiconductor device 100 that does not need to have a storage function (eg, the connection region S), thereby preventing the stack structure 10 in the region from collapsing.

[0142] For example, see Figure 4 The semiconductor channel layer of the virtual channel structure 60 penetrates the stacked structure 10, and one end protrudes from the first surface 1a of the stacked structure 10. The aforementioned conductive layer 40 at least partially covers and adheres to the surface of the semiconductor channel layer, that is, the virtual channel structure 60 and the channel structure 20 are both electrically connected to the conductive layer 40.

[0143] It should be noted that the aforementioned “channel structure 20” can be understood as a structure located in the storage area C that can realize the storage function. Although the aforementioned “virtual channel structure 60” can be the same as the channel structure 20, it does not play the role of storing information.

[0144] See also Figure 3 and Figure 4 The partition portion 50 is disposed between the channel structure 20 and the lead-out structure 30. The partition portion 50 disconnects the conductive layer 40, and the material of the partition portion 50 includes an insulating material.

[0145] That is, the partition portion 50 is used to disconnect the portion of the conductive layer 40 located on the channel structure 20 from the portion of the conductive layer 40 located on the lead-out structure 30 , and to electrically insulate the two portions of the conductive layer 40 .

[0146] Exemplarily, the material of the partition portion 50 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organic silicate glass, dielectric metal oxides (such as aluminum oxide, hafnium dioxide, etc.), silicates and organic insulating materials, or may also include other materials with electrical insulating properties.

[0147] Understandably, see Figure 4In the case where the conductive layer 40 includes a first sub-layer 41 and a second sub-layer 42 , the partition portion 50 disconnects the first sub-layer 41 and also disconnects the second sub-layer 42 .

[0148] Exemplarily, the aforementioned “arranged between the channel structure 20 and the lead-out structure 30” can be understood as that the partition portion 50 is arranged between the region where the plurality of channel structures 20 are located and the region where the plurality of lead-out structures 30 are located, or it can also be understood as that each lead-out structure 30 has a partition portion 50 between the channel structure 20 corresponding to the gate layer 11 to which it is electrically connected (i.e., the channel structure 20 that penetrates the gate layer 11).

[0149] For example, see Figure 3 The partition portion 50 may be in the shape of an elongated strip, or may be in the shape of a folded line or other shapes that meet the aforementioned conditions (being disposed between the channel structure 20 and the lead-out structure 30). The present application does not impose any limitation on the specific shape.

[0150] Exemplarily, the partition portion 50 may be located on the first surface 1 a , that is, the partition portion 50 extends from the upper surface of the conductive layer 40 through the conductive layer 40 until it extends to the first surface 1 a , thereby ensuring that the conductive layer 40 is fully disconnected.

[0151] Alternatively, the side surface of the partition portion 50 facing the second surface 1b may be substantially flush with the side surface of the lead-out structure 30 away from the second surface 1b, for example, flush with the upper surface of the first sub-portion 31, so that the contact column is formed above the etching lead-out structure 30 (see Figure 8 In the process of forming the contact pillar 90 in the lead-out structure 30 to realize the external connection, the conductive layer 40 can be simultaneously etched and the partition portion 50 can be formed. That is, the external connection structure of the lead-out structure 30 and the partition portion 50 can be simultaneously prepared, thereby reducing the difficulty of preparing the semiconductor device 100 and improving the preparation efficiency.

[0152] Figure 7 In the process of preparing the lead-out structure 30, Figure 3 Cross-sectional view along section line CC'.

[0153] like Figure 7 As shown, in the process of preparing the lead-out structure 30, it is necessary to penetrate at least a portion of the stacked structure 10 and remove a portion of the sacrificial layer 13 to form a space 30' that can be filled with the lead-out structure 30. The portion of the sacrificial layer 13 can be removed by etching, see Figure 7During the etching process, the etching liquid may penetrate into the gate layer 11 disposed on the same layer as the sacrificial layer 13, thereby thinning or even etching away the second dielectric layer 113 around the gate line 111 adjacent to the lead-out structure 30, thereby greatly reducing the electrical insulation around the gate line 111, which may easily lead to leakage between the gate line 111 and the adjacent conductive structure (e.g., the semiconductor channel layer of the dummy channel structure 60) (the leakage position can be seen in FIG. Figure 7 The dotted box D in the figure) seriously affects the storage function of the semiconductor device 100. For example, the leakage current may cause the threshold voltage of the transistor T in the channel structure 20 to drift, affecting the electrical performance and stability of the semiconductor device 100.

[0154] The embodiment of the present disclosure provides a partition portion 50 to disconnect and electrically insulate a portion of the conductive layer 40 located on the channel structure 20 from a portion of the conductive layer 40 located on the lead-out structure 30, so that during the process of transmitting a source signal to the channel structure 20, the conductive layer 40 cannot transmit an electrical signal to the conductive layer 40 on the lead-out structure 30, thereby avoiding the generation of a loop between the gate layer 11 near the lead-out structure 30 and the portion of the conductive layer 40 located on the lead-out structure 30, thereby avoiding the generation of leakage current, effectively improving the stability of the threshold voltage in the storage cell string M of the semiconductor device 100, and thereby improving the electrical performance and reliability of the semiconductor device 100.

[0155] Figure 8 and Fig. 9 For along Figure 3 Another cross-sectional view of the section line BB' in FIG.

[0156] In some embodiments, Figure 8 and Fig. 9 As shown, the semiconductor device 100 further includes a plurality of dummy channel structures 60 located between the channel structure 20 and the lead-out structure 30 , and the plurality of dummy channel structures 60 penetrate the stacked structure 10 .

[0157] See also Figure 3 In the orthographic projection on the second surface 1b, the partition portion 50 at least partially overlaps with the at least one dummy channel structure 60. That is, the orthographic projection of the partition portion 50 on the second surface 1b at least partially overlaps with the orthographic projection of the at least one dummy channel structure 60 on the second surface 1b.

[0158] For example, see Figure 3 , Figure 4 , Figure 8 and Fig. 9 At least a portion of the aforementioned partition portion 50 may be disposed on a dummy channel structure 60 located between the channel structure 20 and the lead-out structure 30 .

[0159] For example, Figure 4 , Figure 8 and Fig. 9 As shown, the structure of at least a portion of the dummy channel structure 60 is the same as the structure of the aforementioned channel structure 60 .

[0160] Alternatively, illustratively, the structure of at least part of the dummy channel structure 60 may also be different from the structure of the channel structure 20. For example, at least part of the dummy channel structure 60 may be filled with at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organic silicate glass, dielectric metal oxide (such as aluminum oxide, hafnium dioxide, etc.) and its silicate, and organic insulating material. The embodiments of the present disclosure do not limit the specific structure of the dummy channel structure 60.

[0161] For example, Figure 8 As shown, one end of at least one dummy channel structure 60 protrudes from the first surface 1 a , and the end of the dummy channel structure 60 protruding from the first surface 1 a has a recess U1 , and the partition portion 50 fills the recess U1 .

[0162] Or, for example, Fig. 9 As shown, an end surface of one end of at least one dummy channel structure 60 is flush with the first surface 1 a or recessed relative to the first surface 1 a , and a portion of the partition portion 50 covers the end surface of the dummy channel structure 60 .

[0163] That is, part or all of the end of the virtual channel structure 60 protruding from the first surface 1a is removed, and the removed part of the virtual channel structure 60 is replaced by the partition portion 50, so that the part of the conductive layer 40 located on the channel structure 20 and the part located on the lead-out structure 30 are disconnected, and at the same time, other structures corresponding to the disconnected position of the conductive layer 40 (for example, part or all of the end of the virtual channel structure 60 protruding from the first surface 1a) are removed, thereby avoiding conduction between the two disconnected parts of the conductive layer 40 through other conductive structures (for example, conduction through the semiconductor channel layer of the virtual channel structure 60), so as to ensure that the conductive layer 40 is fully disconnected, and further reduce the leakage risk of the semiconductor device 100.

[0164] Fig.10 For along Figure 3 Another cross-sectional view of the section line EE' in FIG.

[0165] In some embodiments, Fig.10 As shown, the semiconductor device 100 further includes a gate line isolation structure 70 .

[0166] See also Figure 2 and Figure 3 , the gate line isolation structure 70 extends along the first direction X. Figure 4The gate line isolation structure 70 is disposed throughout the stack structure 10 .

[0167] For example, see Figure 3 The gate line isolation structure 70 extends from the storage area C to the connection area S.

[0168] Exemplarily, the gate line isolation structure 70 may be disposed between two gate lines 111 adjacent to each other along the second direction Y, so as to facilitate the two gate lines 111 to transmit electrical signals independently of each other.

[0169] Exemplarily, the gate line isolation structure 70 may include an insulating material disposed on the sidewalls, and also include a conductive material filled in a receiving cavity formed by the insulating material. The insulating material on the sidewalls electrically isolates the conductive material in the cavity, and the conductive material in the cavity may be in electrical contact with the conductive layer 40, so that the electrical signal on the conductive layer 40 can be transmitted through the gate line isolation structure 70.

[0170] Exemplarily, the insulating material on the sidewall may include at least one of silicon nitride, silicon oxynitride, doped silicon oxide, organic silicate glass, dielectric metal oxides (such as aluminum oxide, hafnium dioxide, etc.) and silicates thereof, and organic insulating materials. The conductive material filled in the cavity may include at least one of tungsten, cobalt, copper, aluminum, doped polysilicon, and metal silicide.

[0171] See also Figure 3 , the partition portion 50 extends along the second direction Y. Fig.10 In the orthographic projection on the second surface 1 b , the partition portion 50 intersects with the gate line isolation structure 70 .

[0172] That is, the extension direction of the partition portion 50 intersects with the extension direction of the gate line isolation structure 70. For example, the extension directions of the two may be perpendicular to each other, and the orthographic projection of the partition portion 50 on the second surface 1b overlaps with the orthographic projection of the gate line isolation structure 70 on the second surface 1b.

[0173] For example, see Figure 4 At least a portion of the partition portion 50 may be disposed across the gate line isolation structure 70 .

[0174] It can be understood that the size of the partition portion 50 in the second direction Y is approximately the same as the size of the conductive layer 40 in the second direction Y, so that the partition portion 50 completely disconnects the conductive layer 40, thereby achieving sufficient insulation between the portion of the conductive layer 40 located on the channel structure 20 and the portion located on the lead-out structure 30.

[0175] By setting the extension direction of the partition portion 50 to intersect with the extension direction of the gate line isolation structure 70, and setting the orthographic projection of the partition portion 50 on the second surface 1b to overlap with the orthographic projection of the gate line isolation structure 70 on the second surface 1b, the partition portion 50 can cut the conductive layer 40 into two parts in the extension direction perpendicular to the gate line 111, so that one part of the two parts of the conductive layer 40 after cutting is located in the storage area C, and the other part is located in the connection area S, that is, it is ensured that the part of the conductive layer 40 located on the channel structure 20 and the part located on the lead-out structure 30 are disconnected from each other, thereby ensuring that the aforementioned leakage problem in the semiconductor device 100 can be solved and the electrical performance and reliability of the semiconductor device 100 can be improved.

[0176] Exemplarily, one end of the gate line isolation structure 70 protrudes from the first surface 1 a , and a notch U2 is provided at the end of the gate line isolation structure 70 protruding from the first surface 1 a , and the partition portion 50 fills the notch U2 .

[0177] That is, the partition portion 50 sequentially penetrates the conductive layer 40 and part of the gate line isolation structure 70 from the upper surface of the conductive layer 40 (the side surface away from the second surface 1b) to the first surface 1a, thereby ensuring that the conductive layer 40 is fully disconnected.

[0178] In some embodiments, Figure 2 , Figure 3 , Figure 4 , Figure 8 and Fig. 9 As shown, the semiconductor device 100 includes a storage area C and a connection area S, wherein the connection area S is arranged on at least one side of the storage area C (for example, the connection area S can be arranged on both the left and right sides of a storage area C), the aforementioned channel structure 20 is arranged in the storage area C, and the aforementioned lead-out structure 30 is arranged in the connection area S.

[0179] See also Figure 3 The partition portion 50 is disposed in the connection area S near the storage area C. Specifically, the partition portion 50 is disposed in the connection area S, and is disposed closer to the storage area C than the lead-out structure 30 .

[0180] By setting the partition part 50 at a position close to the storage area C in the connection area S, it is ensured that of the two parts of the conductive layer 40 disconnected by the partition part 50, one part is located in the storage area C, and the other part is located in the connection area S, that is, it is ensured that the part of the conductive layer 40 located on the channel structure 20 and the part located on the lead-out structure 30 are disconnected from each other, thereby enabling the transmission of electrical signals (such as source signals) of the channel structure 20 while avoiding leakage problems in the semiconductor device 100.

[0181] In some embodiments, see Figure 3, along the first direction X, the minimum spacing d between the partition portion 50 and the channel structure 20 is greater than or equal to 15 μm. That is, the spacing between the partition portion 50 and the channel structure 20 closest to the partition portion 50 along the first direction X is greater than or equal to 15 μm. For example, the spacing may be 15 μm, 18.3 μm, 25.75 μm, or 30 μm.

[0182] By setting the minimum spacing d between the partition portion 50 and the channel structure 20 to be greater than or equal to 15 μm, on the one hand, the partition portion 50 is ensured to be located between the channel structure 20 and the lead-out structure 30 , and on the other hand, the disconnection position of the conductive layer 40 is controlled to avoid affecting the normal storage function of the storage cell string M in the storage area C.

[0183] In some embodiments, the partition portion 50 is disposed between the position where the lead-out structure 30 is connected to the corresponding gate layer 11 and the channel structure 20. Figure 4 The partition portion 50 is disposed between a position where the first sub-portion 31 is connected to the corresponding gate layer 11 and the channel structure 20 .

[0184] That is, the partition portion 50 disconnects the conductive layer 40 at a position between the channel structure 20 and the leakage position (the position where the lead structure 30 is connected to the corresponding gate layer 11), thereby solving the leakage problem of the semiconductor device 100 and improving the electrical performance and reliability of the semiconductor device 100.

[0185] In some embodiments, the orthographic projection of the partition portion 50 on the second surface 1b covers the orthographic projection of the position where the lead-out structure 30 is connected to the corresponding gate layer 11 on the second surface 1b. That is, the conductive layer 40 located at the position where the lead-out structure 30 is connected to the corresponding gate layer 11 (i.e., the leakage position) is removed, thereby avoiding leakage problems in the semiconductor device 100.

[0186] In some embodiments, Figure 8 , Fig. 9 and Fig.10 As shown, the semiconductor device 100 further includes a first insulating layer 81 , which is disposed on a side of the conductive layer 40 away from the stacked structure 10 and covers the storage region C and the connection region S of the semiconductor device 100 .

[0187] See also Figure 8 , Fig. 9 and Fig.10 , the partition portion 50 is embedded in the first insulating layer 81 .

[0188] Exemplarily, the partition portion 50 may be made of the same material as the first insulating layer 81 . In this case, the partition portion 50 is integrally provided with the first insulating layer 81 .

[0189] The first insulating layer 81 is used to cover the conductive layer 40 to prevent the conductive layer 40 and other conductive structures from having unexpected electrical connection. The partition part 50 is integrally arranged with the first insulating layer 81. On the one hand, the stability of the partition part 50 can be improved. On the other hand, the two can be integrally formed, thereby reducing the difficulty of preparing the partition part 50 and improving the preparation efficiency.

[0190] Exemplarily, the material of the first insulating layer 81 is a material with electrical insulation properties. For example, the material of the first insulating layer 81 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organic silicate glass, dielectric metal oxides (such as aluminum oxide, hafnium dioxide, etc.) and their silicates, and organic insulating materials, but the present disclosure is not limited to this.

[0191] In some embodiments, Figure 8 and Fig. 9 As shown, the semiconductor device 100 further includes a contact column 90. The contact column 90 penetrates the first insulating layer 81 and is connected to the lead-out structure 30. The contact column 90 is used to realize the external connection of the lead-out structure 30.

[0192] For example, see Figure 8 and Fig. 9 In the case where the lead-out structure 30 includes a first sub-portion 31 and a second sub-portion 32 , the contact pillar 90 is disposed on a side of the first sub-portion 31 away from the second surface 1 b and is electrically connected to the first sub-portion 31 .

[0193] Exemplarily, it can be understood that each lead-out structure 30 is correspondingly provided with a contact pillar 90 .

[0194] It is understandable that the contact pillar 90 has a conductive property. For example, the material of the contact pillar 90 may include at least one of tungsten, cobalt, copper, aluminum, and metal silicide, or may be other conductive materials.

[0195] In some embodiments, see Figure 4 , Figure 8 and Fig. 9 , the semiconductor device 100 may further include a peripheral device 101 .

[0196] The peripheral device 101 may include at least a peripheral circuit. The peripheral circuit may be any suitable digital, analog, and / or mixed signal control and sensing circuit, including but not limited to a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a gate driver), a charge pump, a current or voltage reference, or any active or passive component of the circuit (e.g., a transistor, a diode, a resistor, or a capacitor). The peripheral circuit may also include any other circuit compatible with an advanced logic process, including a logic circuit (e.g., a processor and a programmable logic device (PLD) or a storage circuit (e.g., a static random access three-dimensional memory (SRAM)).

[0197] The aforementioned storage cell string M and other structures are connected to the peripheral device 101 , and the peripheral device 101 is used to control access to the storage cell string M. For example, the peripheral device 101 can control writing data to the storage cell string M, or control reading data from the storage cell string M.

[0198] Exemplarily, the peripheral device 101 may include a word line selection circuit, a bit line selection circuit, a control circuit, and a read / write circuit.

[0199] Among them, when performing read and write operations on the storage cell string M, the read and write circuit transmits control signals to the word line selection circuit and the bit line selection circuit through the control circuit. The word line selection circuit selects a column of transistors T, and the bit line selection circuit selects a row of transistors T. The word line selection circuit and the bit line selection circuit jointly determine the address of the transistor T to be accessed.

[0200] In order to prepare the above-mentioned semiconductor device 100 , the embodiment of the present disclosure further provides a method for preparing the semiconductor device 100 .

[0201] Fig.11 and Fig.12 A flow chart of the preparation of a semiconductor device 100 provided in an embodiment of the present disclosure, Figures 13 to 26 1 and 2 are cross-sectional views corresponding to various preparation steps of the semiconductor device 100 .

[0202] like Fig.11 As shown, the method for preparing the semiconductor device 100 includes the following steps S1 to S6:

[0203] S1: Fig.13 , Fig.15 and Fig.16 As shown, a stacked structure 10 is formed.

[0204] For example, see Fig.16The stacked structure 10 includes a plurality of first dielectric layers 12 , a plurality of gate layers 11 and a plurality of sacrificial layers 13 .

[0205] Among them, see Fig.16 The multi-layer first dielectric layer 12 and the multi-layer gate layer 11 are alternately stacked, and the gate layer 11 and the sacrificial layer 13 are arranged in the same layer.

[0206] For example, see Figures 13 to 26 The semiconductor device 100 includes a storage area C and a connection area S, the gate layer 11 is at least located in the storage area C, and the sacrificial layer 13 is located in the connection area S.

[0207] See also Figures 13 to 26 The aforementioned stacked structure 10 includes a first surface 1 a and a second surface 1 b that are arranged opposite to each other in a third direction Z, and the third direction Z is a direction in which the multiple gate layers 11 are stacked.

[0208] Exemplarily, the step of forming the stacked structure 10 (ie, step S1) may include the following steps S11 to S13:

[0209] S11: Fig.13 As shown, an initial stacking structure 2 is formed on a substrate 1 .

[0210] Exemplarily, the aforementioned substrate 1 may be a single-layer substrate. Alternatively, in some other embodiments, the substrate 1 may also be a composite substrate. For example, the substrate 1 may include polysilicon layers and silicon oxide layers alternately stacked along the third direction Z.

[0211] Illustratively, the composite substrate may be formed by ion implantation.

[0212] See also Fig.13 , the initial stacking structure 2 has a storage area C and a connection area S.

[0213] See also Fig.13 The initial stacking structure 2 includes a first dielectric layer 12 and a sacrificial layer 13 stacked along a third direction Z.

[0214] At least the portion of the sacrificial layer 13 located in the storage area C will be replaced by the gate layer 11 in a subsequent process.

[0215] For example, the initial stacking structure 2 can be formed on one side of the substrate 1 by using any thin film deposition process including chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0216] Exemplarily, before forming the initial stacked structure 2 , step S1 may further include forming at least one etch stop layer on the substrate 1 .

[0217] For example, see Fig.13 , a first etch stop layer 3A and a second etch stop layer 3B (ie, the aforementioned second sub-layer 42 ) are formed on the substrate 1 .

[0218] The first etch stop layer 3A can be used as an etch stop layer when the substrate 1 is subsequently removed, which helps to control the process uniformity during the process of removing the substrate 1 and can protect the stacked structure 10 from damage during the process of removing the substrate 1.

[0219] The material of the first etch stop layer 3A may include an insulating material, for example, may include at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organic silicate glass, dielectric metal oxides (such as aluminum oxide, hafnium dioxide, etc.) and their silicates, and organic insulating materials.

[0220] Exemplarily, the material of the first etch stop layer 3A may be the same as the material of any layer in the aforementioned storage function layer 22, for example, the same as the material of the barrier layer in the storage function layer 22. For example, the materials of the first etch stop layer 3A and the barrier layer in the storage function layer 22 are both silicon oxide.

[0221] The second etch stop layer 3B can be used as an etch stop layer when subsequently removing the portion of the channel structure 20 and the dummy channel structure 60 protruding from the stack structure 10 , which also helps to control process uniformity and protect the stack structure 10 from damage during the process.

[0222] The material of the second etch stop layer 3B includes semiconductor materials, for example, single crystal silicon, polycrystalline silicon, single crystal germanium, III-V group compound semiconductor materials, II-VI group compound semiconductor materials and other suitable semiconductor materials.

[0223] Exemplarily, the second etch stop layer 3B may be made of the same material as the source line SL (ie, the aforementioned first sub-layer 41 ). For example, the second etch stop layer 3B and the source line SL may both be made of polysilicon.

[0224] S12: Fig.15 As shown, a gate gap 4 is formed, and an etching solution is injected through the gate gap 4 to etch at least a portion of the sacrificial layer 13 located in the storage area C to form a cavity U'.

[0225] For example, see Fig.15 The gate slit 4 penetrates the initial stacked structure 2 in a direction perpendicular to the substrate 1 , and the gate slit 4 is an opening facing away from the first surface 1 a .

[0226] By injecting etching solution into the opening, a portion of the sacrificial layer 13 is removed. It is understandable that the etching range and etching position of the sacrificial layer 13 can be controlled by controlling the volume of the etching solution injected into the opening of the gate gap 4.

[0227] By way of example, the process of forming the gate gap 4 may include wet etching or dry etching.

[0228] For example, see Fig.15 , the portion of the sacrificial layer 13 located in the connection region S may also be etched to form a cavity U'.

[0229] For example, see Fig.15 , the portion of the sacrificial layer 13 located in the connection area S is retained, and this portion facilitates the subsequent formation of the lead-out structure 30 .

[0230] S13: Fig.16 As shown, the cavity U′ is filled with a gate material to form a gate layer 11 , and the gate gap 4 is filled to form a gate line isolation structure 70 .

[0231] For example, see Fig.16 The formed gate layer 11 is arranged on the same layer as the sacrificial layer 13 which has not been etched away.

[0232] Exemplarily, step S13 may further include filling materials into the cavity U′ for multiple times to sequentially form the adhesive layer 112 , the second dielectric layer 113 and the gate line 111 .

[0233] Exemplarily, the gate material may be filled into the cavity U' through the opening of the aforementioned gate gap 4. The gate layer 11 may be prepared by any thin film deposition process, such as ALD, CVD, PVD and the like.

[0234] For example, see Fig.16 The formed gate line isolation structure 70 penetrates the stack structure 10 and can divide the stack structure 10 into a plurality of memory blocks.

[0235] Exemplarily, the step of forming the gate line isolation structure 70 may include, after forming the gate layer 11 , coating an insulating material on the inner wall of the gate gap 4 , and then filling the gate gap 4 with a conductive material to form the gate line isolation structure 70 .

[0236] S2: Fig.14 As shown, a channel structure 20 is formed.

[0237] See also Fig.16 The channel structure 20 penetrates the stack structure 10 and protrudes from the first surface 1 a of the stack structure 10 .

[0238] Exemplarily, the channel structure 20 includes a semiconductor channel layer 21 and a storage function layer 22 . For the specific structure, please refer to the description of the semiconductor device 100 in the above embodiment, which will not be described in detail here.

[0239] It is understood that the preparation order of the above-mentioned step S1 and step S2 can be interlaced with each other. For example, step S2 can be performed before completing step S12 or after S11. That is, the preparation of the channel structure 20 is performed after the initial stacking structure 2 is formed. Fig.14 The formed channel structure 20 penetrates the initial stacked structure 2 .

[0240] For example, see Fig.14 The step S2 may further include forming a dummy channel structure 60. Exemplarily, the dummy channel structure 60 may have the same structure as the channel structure 20.

[0241] Exemplarily, the step of forming the channel structure 20 may include opening a storage channel hole in a direction perpendicular to the substrate 1, wherein the storage channel hole penetrates the initial stacked structure 2. A storage function layer 22 and a semiconductor channel layer 21 are sequentially formed in the storage channel hole, and a channel filling layer 23 is filled in the accommodation space surrounded by the semiconductor channel layer 21.

[0242] For example, the storage channel hole may be formed by a dry etching process or a wet etching process, and the storage function layer 22 and the semiconductor channel layer 21 may be formed by any thin film deposition process of CVD, PVD and ALD.

[0243] S3: Fig.17 As shown, a lead-out structure 30 is formed.

[0244] See also Fig.17 The lead-out structure 30 penetrates from the second surface 1 b to the corresponding gate layer 11 and is connected to the corresponding gate layer 11 .

[0245] By way of example, the lead-out structure 30 may be formed by any thin film deposition process of CVD, PVD and ALD.

[0246] For example, see Fig.17 , the lead-out structure 30 may include a first sub-section 31 and a second sub-section 32. In the case where the lead-out structure 30 includes the first sub-section 31 and the second sub-section 32, the aforementioned step S3 may include:

[0247] The stack structure 10 is etched to form a contact hole penetrating at least a portion of the stack structure 10 .

[0248] For example, a photoresist layer is formed on the side of the stacked structure 10 away from the substrate 1, and a via hole is formed on the photoresist layer by using an exposure and development process. Based on the patterned photoresist layer, the stacked structure 10 is etched to form a contact hole.

[0249] It should be noted that there may be multiple contact holes, each of which exposes a corresponding sacrificial layer 13 (the sacrificial layer 13 disposed on the same layer as the gate layer 11 to which the lead-out structure 30 is to be connected). It is understandable that the contact hole is used to form the lead-out structure 30 in the subsequent process, and each lead-out structure 30 will correspond to and be electrically connected to a gate layer 11.

[0250] An electrical isolation layer 33 is formed in the contact hole, and the electrical isolation layer 33 covers the sidewall and bottom (with Fig.17 The orientation in is used as a reference).

[0251] It should be noted that the electrical isolation layer 33 is used to prevent the subsequently formed lead-out structure 30 from being electrically connected to the gate layer 11 corresponding to the sidewall of the contact hole.

[0252] The portion of the electrical isolation layer 33 located at the bottom of the contact hole is removed so as to expose the sacrificial layer 13 corresponding to the contact hole.

[0253] An etching solution is injected through the contact hole to remove at least a portion of the sacrificial layer 13 corresponding to the contact hole, thereby forming an etching cavity.

[0254] It can be understood that the etching cavity is provided in the same layer as the gate layer, and the etching cavity leaks out of the side wall of the gate layer 11 , so that the first sub-portion 31 filled subsequently can be in electrical contact with the gate layer 11 .

[0255] A conductive material is filled into the etching cavity to form a first sub-portion 31 .

[0256] The contact hole is filled with a conductive material to form the second sub-portion 32 .

[0257] Exemplarily, forming the second subsection 32 may include:

[0258] Fill the contact hole with conductive material to form an initial second sub-portion. Etch the initial second sub-portion to form a receiving cavity 34. Fill the receiving cavity 34 with insulating material. Cover the top of the receiving cavity 34 with conductive material, and the covered part and the side wall of the receiving cavity 34 together form the second sub-portion 32.

[0259] It is understandable that the aforementioned embodiments of the present disclosure only provide illustrative descriptions of the preparation process of the lead-out structure 30, and do not limit the specific preparation process of the lead-out structure 30. Any other preparation process that can prepare the lead-out structure 30 is within the protection scope of the present disclosure.

[0260] Illustratively, the preparation order of the aforementioned S1 to S3 can be arranged arbitrarily if feasible, and the present application does not impose any limitation on this.

[0261] Exemplarily, the method for preparing the semiconductor device 100 may further include:

[0262] Q1: If Fig.18 As shown, a peripheral device 101 is formed.

[0263] Exemplarily, the peripheral device 101 may be bonded to the structure obtained in the aforementioned step S3 by using X-tacking technology.

[0264] For example, in some embodiments, before bonding, a process of applying treatment to the bonding surface may be included, such as plasma treatment, wet treatment and / or heat treatment, so as to improve the bonding effect.

[0265] Exemplarily, before forming the peripheral device 101, the process may further include forming an array interconnect layer 300 (see Fig.18 ), the array interconnect layer 300 may be coupled to the memory cell string M (see, for example, Fig.18 , the array interconnect layer 300 is coupled to one end of the channel structure 20 close to the peripheral device 101) so as to transmit an electrical signal to the memory cell string M.

[0266] For example, the array interconnect layer 300 may include at least one interconnect conductor layer. The interconnect conductor layer may include a plurality of connection lines, such as a bit line BL to transmit a drain signal to the memory cell string M, or a word line connection line coupled to the word lines WL0-WL3.

[0267] Exemplarily, the array interconnect layer 300 may also include one or more interlayer insulating layers, and a plurality of local contacts R insulated from each other by these interlayer insulating layers. The local contacts R may, for example, include a bit line contact for coupling with the bit line BL in the interconnect conductor layer, or may also include a drain selection gate contact for coupling with the drain selection gate.

[0268] The materials of the interconnect conductor layer and the interconnect conductor layer may be conductive materials, and the conductive materials may include at least one of tungsten, cobalt, copper, aluminum, and metal silicide, and may also be other suitable materials.

[0269] The peripheral device 101 and the stacked structure 10 can be bonded via the array interconnect layer 300. During the bonding process, the bonding contacts in the peripheral device 101 and the contacts in the array interconnect layer 300 can be aligned and contacted with each other, thereby achieving electrical connection between the channel structure 20 and the peripheral device 101.

[0270] Exemplarily, the method for preparing the semiconductor device 100 may further include:

[0271] Q2: If Fig.19 As shown, the substrate 1 is removed, and the channel structure 20 and the storage function layer 22 of the portion of the dummy channel structure 60 protruding from the first surface 1 a are removed.

[0272] See also Fig.19 After removing the substrate 1 and the storage function layer 22, the semiconductor channel layer 21 of the channel structure 20 and the dummy channel structure 60 can be exposed, thereby facilitating electrical connection between the semiconductor channel layer 21 and the source line SL (ie, the conductive layer 40) in subsequent processes.

[0273] It is understandable that the aforementioned step Q1 and step Q2 can be arranged after step S3, and the order of step Q1 and step Q2 can be interchanged, and in step Q2, the order of removing the substrate 1 and removing the storage functional layer can be interchanged, and the present application does not impose any restrictions on this.

[0274] For example, in the aforementioned step Q2, the first etch stop layer 3A may be used as an etch stop layer when removing the substrate 1, thereby avoiding damage to the stacked structure 10 and other structures during the process of removing the substrate 1.

[0275] For example, in the aforementioned step Q2, the portion of the channel structure 20 extending out of the stacked structure 10 and the portion of the dummy channel structure 60 extending out of the stacked structure 10 may be etched by dry etching or wet etching. For example, by adopting a wet etching process, the portion of the channel structure 20 extending out of the stacked structure 10 and the portion of the dummy channel structure 60 extending out of the stacked structure 10 are isotropically etched, so that the semiconductor channel layer of the channel structure 20 and the semiconductor channel layer 21 of the dummy channel structure 60 are exposed.

[0276] Exemplarily, the second etch stop layer 3B may be used as an etch stop layer when removing the channel structure 20 and the storage function layer 22 of the dummy channel structure 60 , thereby avoiding damage to the stack structure 10 and other structures during the process.

[0277] Exemplarily, when the material of the second etch stop layer 3B is the same as the material of any one of the blocking layer 221, the charge capture layer 222 and the tunneling layer 223 in the storage functional layer, for example, when the material of the second etch stop layer 3B is the same as the material of the blocking layer 221, at least a portion of the second etch stop layer 3B may also be removed in step Q2.

[0278] Exemplarily, after removing the storage function layer 22 of the channel structure 20 and the dummy channel structure 60 , the method for preparing the semiconductor device 100 may further include: ion doping the semiconductor channel layer 21 .

[0279] For example, a plasma implantation process may be used to implant ions into the semiconductor channel layer 21 to improve adhesion and conductivity between the source line SL and the semiconductor channel layer 21. The implanted ions may include metal ions, such as tungsten ions.

[0280] For example, see Fig.19 , at least a portion of the semiconductor channel layer 21 protruding from the first surface 1 a is ion implanted.

[0281] S4: Fig. 20 As shown, a conductive layer 40 is formed.

[0282] See also Fig. 20 The conductive layer 40 is disposed on the first surface 1 a and covers the channel structure 20 and is connected to the channel structure 20 .

[0283] For example, see Fig. 20 The conductive layer 40 covers the semiconductor channel layer 21 of the channel structure 20 to achieve electrical connection with the semiconductor channel layer 21, thereby facilitating transmission of electrical signals to the channel structure 20, such as transmission of source signals.

[0284] For example, see Fig. 20 The conductive layer 40 also covers the dummy channel structure 60 and is electrically connected to the dummy channel structure 60 .

[0285] For example, see Fig. 20 In the case where the conductive layer 40 includes the first sublayer 41 and the second sublayer 42, the second sublayer 42 is formed in step S4, and the second sublayer 42 serves as the source line SL and covers the first sublayer 41, the channel structure 20 and the dummy channel structure 60. The first sublayer 41 may be at least part of the second etch stop layer 3B remaining in step Q2.

[0286] For example, see Fig. 20 In some embodiments, the second sub-layer 42 has a uniform thickness. For example, the second sub-layer 42 may be formed by any thin film deposition process including chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0287] For example, in some other embodiments, the surface of the second sublayer 42 away from the stack structure 10 is parallel to the first surface 1a of the stack structure 10. For example, the initial source layer can be formed by any thin film deposition process of CVD, PVD and ALD, and then the surface of the initial source layer is flattened by a planarization process to form the second sublayer 42.

[0288] S5: Fig.21 He Ru Fig. 22 As shown, the conductive layer 40 is disconnected.

[0289] See also Fig. 22 A trench V is formed between the two disconnected parts of the conductive layer 40 . The trench V is located between the channel structure 20 and the lead-out structure 30 .

[0290] For example, see Fig. 22 , the trench V may be located on the dummy channel structure 60 and replaces a portion of the dummy channel structure 60 protruding from the first surface 1 a .

[0291] For example, see Fig. 22 In the case where the conductive layer 40 includes the first sub-layer 41 and the second sub-layer 42 , the first sub-layer 41 is disconnected and the second sub-layer 42 is also disconnected in step S5 .

[0292] For example, see Fig.21 and Fig. 22 , step S5 may include:

[0293] S51: Fig.21 As shown, a second insulating layer 82 and a mask P are formed.

[0294] Among them, see Fig.21 The second insulating layer 82 covers the side of the conductive layer 40 away from the stacked structure 10 , and the mask P is disposed on the side of the second insulating layer 82 away from the conductive layer 40 .

[0295] See also Fig.21 The mask P has an opening, and the opening reveals the position to be etched, so that the conductive layer 40 can be etched later to achieve the disconnection of the conductive layer 40.

[0296] For example, see Fig.21 Step S51 may further include forming a third etch stop layer 3C.

[0297] See also Fig.21 The third etch stop layer 3C is disposed between the conductive layer 40 and the second insulating layer 82 , and the third etch stop layer 3C is used to protect the conductive layer 40 from being damaged during the subsequent removal of the second insulating layer 82 .

[0298] S52: Fig. 22As shown, etching is performed according to the mask P to disconnect the conductive layer 40 and remove the second insulating layer 82 .

[0299] For example, see Fig. 22 During the etching process according to the mask P, the etching depth can extend into the stacked structure 10 to ensure that the conductive layer 40 is fully disconnected.

[0300] For example, see Fig.23 and Fig.24 After disconnecting the conductive layer 40 , the method for preparing the semiconductor device 100 may further include:

[0301] The third etch stop layer 3C is removed, and the conductive layer 40 is annealed.

[0302] Wherein, illustratively, this step may include:

[0303] S53: See Fig.23 , a portion of the third etch stop layer 3C parallel to the first surface 1 a is removed.

[0304] Through step S53 , the surface of the conductive layer 40 away from the first surface 1 a can be exposed, so as to facilitate subsequent heat treatment of the conductive layer 40 .

[0305] S54: See Fig.24 , heat-treat the conductive layer 40 and remove the remaining third etch stop layer 3C.

[0306] For example, see Fig.24 By performing heat treatment on the conductive layer 40 , which may include annealing, sintering or other processes on the conductive layer 40 , the conductive layer 40 may be silicidated and the conductive performance of the conductive layer 40 may be improved.

[0307] For example, see Fig.23 and Fig.24 In the case where the conductive layer 40 includes a first sublayer 41 and a second sublayer 42 , after the conductive layer 40 is heat treated in step S54 , the first sublayer 41 and the second sublayer 42 can be combined into one, thereby further improving the stability and conductivity of the conductive layer 40 .

[0308] Through step S53, only the portion of the third etch stop layer 3C parallel to the first surface 1a is removed, and the conductive layer 40 is leaked so that the conductive layer 40 can be heat-treated. At the same time, the portion of the third etch stop layer 3C located on the side walls of the channel structure 20 and the virtual channel structure 60 is retained, thereby preventing the portion of the channel structure 20 and the virtual channel structure 60 protruding from the first surface 1a from collapsing during the heat treatment of the conductive layer 40.

[0309] S6: Fig.25 As shown, the trench V is filled to form a partition portion 50 .

[0310] The material of the partition portion 50 has electrical insulation properties, thereby achieving electrical insulation between the two disconnected parts of the conductive layer 40 .

[0311] The semiconductor device 100 obtained by the preparation method is provided with a partition portion 50, so that the portion of the conductive layer 40 located on the channel structure 20 and the portion of the conductive layer 40 located on the lead-out structure 30 are disconnected from each other and electrically insulated from each other, so that in the process of transmitting the source signal to the channel structure 20, the conductive layer 40 cannot transmit the electrical signal to the conductive layer 40 on the lead-out structure 30, thereby avoiding the generation of a loop between the gate layer 11 near the lead-out structure 30 and the portion of the conductive layer 40 located on the lead-out structure 30, thereby avoiding the generation of leakage current, effectively improving the stability of the threshold voltage in the storage cell string M of the semiconductor device 100, thereby improving the electrical performance and reliability of the semiconductor device 100.

[0312] In some embodiments, Fig.12 As shown, the method for preparing the semiconductor device 100 may further include the following steps S7 to S9:

[0313] S7: Fig. 22 As shown, while the conductive layer 40 is disconnected, the conductive layer 40 is etched to form a first through hole H1.

[0314] That is, the step of disconnecting the conductive layer 40 (ie, step S5 ) can be performed simultaneously with the step of forming the first through hole H1 , thereby simplifying the manufacturing process of the semiconductor device 100 and improving the manufacturing efficiency of the semiconductor device 100 .

[0315] See also Fig. 22 The first through hole H1 exposes the lead-out structure 30 , for example, the first through hole H1 exposes the first sub-portion 31 in the lead-out structure 30 , thereby facilitating the subsequent external connection of the lead-out structure 30 .

[0316] For example, see Fig. 22 When the groove V and the first through hole H1 are formed simultaneously, the depths of the groove V and the first through hole H1 may be substantially the same, for example, the bottoms of both reach the plane where the side surface of the first sub-portion 31 away from the second surface 1b is located.

[0317] It can be understood that the aforementioned embodiments only provide exemplary descriptions of the depths of the groove V and the first through hole H1, and the embodiments of the present disclosure do not limit this. For example, the depths of the groove V and the first through hole H1 may be different, the bottom of the groove V may reach the first surface 1a, and the depth of the first through hole H1 may reach the plane where the side surface of the first sub-portion 31 away from the second surface 1b is located.

[0318] S8: Fig.25 As shown, an insulating layer 80 is formed.

[0319] See also Fig.25 The insulating layer 80 is disposed on a side of the conductive layer 40 away from the stacked structure 10 and covers the storage area C and the connection area S of the semiconductor device 100 .

[0320] See also Fig.25 The insulating layer 80 fills the first through hole H1 and the trench V, wherein the portion of the insulating layer 80 filling the trench V forms the partition 50. The portion of the insulating layer 80 filling the first through hole H1 can prevent the lead-out structure 30 from having unexpected electrical connection.

[0321] By way of example, the insulating layer 80 may be formed by any thin film deposition process of CVD, PVD and ALD.

[0322] It can be understood that the portion of the insulating layer 80 other than the partition portion 50 may be equivalent to the aforementioned first insulating layer 81 .

[0323] By achieving simultaneous preparation of the partition portion 50 during the preparation of the insulating layer 80 , that is, making the process of preparing the partition portion 50 compatible with the preparation process of the external connection structure of the lead-out structure 30 , the preparation process of the semiconductor device 100 can also be simplified and the preparation efficiency of the semiconductor device 100 can be improved.

[0324] S9: Fig.26 As shown, contact studs 90 are formed.

[0325] See also Fig.26 The contact pillar 90 penetrates the insulating layer 80 and is connected to the lead-out structure 30 .

[0326] Illustratively, before forming the contact column 90, the preparation method may further include forming a second through hole penetrating the insulating layer 80, wherein the second through hole is located on a side of the lead-out structure 30 away from the stacking structure 10, and is used to leak out the lead-out structure 30. After the aforementioned contact column 90 is filled in the second through hole, it is electrically connected to the lead-out structure 30.

[0327] Exemplarily, the diameter of the second through hole is smaller than the diameter of the first through hole H1 , so that a portion of insulating material is retained on the sidewall of the first through hole H1 , thereby preventing the contact pillar 90 from contacting conductive structures such as the conductive layer 40 .

[0328] For example, see Fig.26 The orthographic projection of the contact column 90 on the second surface 1b is located within the range of the orthographic projection of the lead-out structure 30 on the second surface 1b, that is, the contact column 90 is arranged above the lead-out structure 30, so that the contact column 90 can connect the lead-out structure 30 to the outside.

[0329] Illustratively, in this step, other conductive structures may also be formed simultaneously. For example, a source contact may be formed. The source contact is located on the side of the conductive layer 40 away from the stacked structure 10, penetrates the insulating layer 80, and is electrically connected to the conductive layer 40 so as to achieve external connection of the conductive layer 40.

[0330] Exemplarily, the source contact may be located in two disconnected portions of the conductive layer 40 , over a portion covering the channel structure 20 , thereby facilitating transmission of a source signal to the channel structure 20 .

[0331] Understandably, see Fig.26 At least a portion of the insulating layer 80 is arranged on a side of the second surface 1b of the lead-out structure 30 away from the stacked structure 10, and the orthographic projection of the contact pillar 90 on the second surface 1b is located within the range of the orthographic projection of the lead-out structure 30 on the second surface 1b, so that it is convenient for the contact pillar 90 to be connected to the lead-out structure 30 after penetrating the insulating layer 80, thereby facilitating the external structure to transmit the external signal to the lead-out structure 30.

[0332] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that: include: A stacked structure, comprising a plurality of gate layers stacked in layers; the stacked structure comprising a first surface and a second surface arranged opposite to each other in a third direction, the third direction being a direction in which the plurality of gate layers are stacked; a channel structure, penetrating the stacked structure and protruding from the first surface of the stacked structure; A lead-out structure extending from the second surface to the corresponding gate layer and connected to the corresponding gate layer; A conductive layer, disposed on the first surface; the conductive layer covers the channel structure and is connected to the channel structure; The partition part is arranged between the channel structure and the lead-out structure; the partition part disconnects the conductive layer, and the material of the partition part includes insulating material.

2. The semiconductor device according to claim 1, wherein: Also includes: a plurality of dummy channel structures disposed between the channel structure and the lead-out structure, wherein the plurality of dummy channel structures penetrate the stacked structure; Wherein, in the orthographic projection on the second surface, the partition portion at least partially overlaps with at least one of the dummy channel structures.

3. The semiconductor device according to claim 2, characterized in that One end of at least one of the dummy channel structures protrudes from the first surface, the end of the dummy channel structure protruding from the first surface has a recess, and the partition portion fills the recess; and / or, An end surface of one end of at least one of the dummy channel structures is flush with the first surface or recessed relative to the first surface, and a portion of the partition portion covers the end surface of the dummy channel structure.

4. The semiconductor device according to claim 1, wherein: Also includes: A gate line isolation structure, which penetrates the stack structure and extends along a first direction; The first direction is parallel to the second surface; Wherein, the partition portion extends along a second direction, the second direction is parallel to the second surface and intersects with the first direction; In an orthographic projection on the second surface, the partition portion intersects the gate line isolation structure.

5. The semiconductor device according to claim 4, characterized in that One end of the gate line isolation structure protrudes from the first surface, and a notch is provided at the end of the gate line isolation structure protruding from the first surface, and the partition portion fills the notch.

6. The semiconductor device according to claim 1, wherein: include: a storage area and a connection area, wherein the connection area is provided on at least one side of the storage area; The channel structure is disposed in the storage area, the lead-out structure is disposed in the connection area, and the partition portion is disposed in a position of the connection area close to the storage area.

7. The semiconductor device according to claim 6, characterized in that The stacked structure further includes a plurality of first dielectric layers and a plurality of sacrificial layers, wherein the plurality of first dielectric layers and the plurality of gate layers are alternately stacked, and a gate layer and a sacrificial layer are arranged in the same layer; the first dielectric layer is at least located in the storage area, and the sacrificial layer is located in the connection area; The lead-out structure includes a first sub-section and a second sub-section, wherein the first sub-section is embedded in a sacrificial layer provided at the same layer as the corresponding gate layer and connected to the corresponding gate layer; the second sub-section penetrates from the second surface to the sacrificial layer provided at the same layer as the corresponding gate layer and is connected to the first sub-section; The partition portion is located between a position where the first sub-portion is connected to the corresponding gate layer and the channel structure.

8. The semiconductor device according to claim 1, wherein: Along the first direction, a minimum distance between the partition portion and the channel structure is greater than or equal to 15 μm.

9. The semiconductor device according to any one of claims 1 to 8, characterized in that: Also includes: A first insulating layer, disposed on a side of the conductive layer away from the stacked structure and covering a storage area and a connection area of ​​the semiconductor device; The partition portion is integrally provided with the first insulating layer.

10. The semiconductor device according to claim 9, characterized in that Also includes: A contact column penetrates the first insulating layer and is connected to the lead-out structure.

11. A method for preparing a semiconductor device, characterized in that: include: forming a stacked structure; the stacked structure comprising a plurality of gate layers; the stacked structure comprising a first surface and a second surface arranged opposite to each other in a third direction, the third direction being a direction in which the plurality of gate layers are stacked; forming a channel structure; the channel structure penetrates the stack structure and protrudes from the first surface of the stack structure; Forming a lead-out structure; penetrating from the second surface to the corresponding gate layer and connecting to the corresponding gate layer; forming a conductive layer; The conductive layer is disposed on the first surface; the conductive layer covers the channel structure and is connected to the channel structure; The conductive layer is disconnected; a groove is formed between the two disconnected parts of the conductive layer; the groove is located between the channel structure and the lead-out structure; The trench is filled to form a partition portion; the material of the partition portion has electrical insulation properties.

12. The preparation method according to claim 11, characterized in that: Also includes: While disconnecting the conductive layer, etching the conductive layer to form a first through hole; The first through hole exposes the lead-out structure; forming an insulating layer; The insulating layer is disposed on a side of the conductive layer away from the stacked structure and covers the storage area and the connection area of ​​the semiconductor device; the insulating layer fills the first through hole and the groove, and a portion of the insulating layer filling the groove forms the partition portion; forming a contact column; The contact column penetrates the insulating layer and is connected to the lead-out structure.

13. A storage system, characterized in that: include: The semiconductor device according to any one of claims 1 to 10; The controller is coupled to the semiconductor device to control the semiconductor device to store data.

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