Semiconductor device, semiconductor module, and manufacturing method

Abstract

The invention provides a semiconductor device which improves characteristics such as saturation current and on-voltage of the semiconductor device. The semiconductor device includes a portion that operates as a transistor including a gate trench portion to which a gate voltage is applied, an emitter region in contact with the gate trench portion, and a base region in contact with the gate trench portion. When the ambient temperature is 25 DEG C, a threshold voltage at which the transistor transitions from an off state to an on state is greater than a first voltage at which the transistor is on.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, a semiconductor module and a manufacturing method. Background Art

[0002] Conventionally, in semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors), there is known a technique for adjusting characteristics by changing the arrangement of emitter regions or the like (see, for example, Patent Documents 1 to 3).

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2008-91491

[0006] Patent Document 2: Japanese Patent Application Laid-Open No. 10-173170

[0007] Patent Document 3: Japanese Patent Application Laid-Open No. 9-283755 Summary of the invention

[0008] Technical issues

[0009] In semiconductor devices, it is desired to improve characteristics such as saturation current and on-voltage.

[0010] Technical Solution

[0011] In order to solve the above-mentioned problems, in a first aspect of the present invention, there is provided a semiconductor device, which includes a semiconductor substrate and a portion that operates as a transistor, wherein the semiconductor substrate has an upper surface and a lower surface and is provided with a drift region of a first conductivity type. In the above-mentioned semiconductor device, the transistor may include a gate groove portion, wherein the gate groove portion has a gate conductive portion to which a gate voltage is applied, and a gate insulating film surrounding the gate conductive portion. In any of the above-mentioned semiconductor devices, the transistor may include an emitter region of a first conductivity type, wherein the emitter region is provided in the semiconductor substrate so as to be exposed on the upper surface and is in contact with the gate groove portion. In any of the above-mentioned semiconductor devices, the transistor may include a base region of a second conductivity type, wherein the base region is provided between the emitter region and the drift region and is in contact with the gate groove portion. In any of the above-mentioned semiconductor devices, a first voltage may be applied to the gate groove portion as the gate voltage when the transistor is turned on. In any of the above-mentioned semiconductor devices, when the ambient temperature is 25°C, the threshold voltage at which the transistor changes from the off state to the on state may be greater than half of the first voltage.

[0012] In any of the above semiconductor devices, the threshold voltage may be greater than or equal to 55% of the first voltage.

[0013] In any of the above semiconductor devices, the threshold voltage may be greater than or equal to 60% of the first voltage.

[0014] In any of the above semiconductor devices, the threshold voltage may be greater than or equal to 70% of the first voltage.

[0015] In any of the semiconductor devices described above, a second voltage may be applied to the gate trench portion when the transistor is turned off. In any of the semiconductor devices described above, the threshold voltage may be closer to the first voltage than an intermediate voltage between the first voltage and the second voltage.

[0016] In any of the above semiconductor devices, a ratio of a difference between the threshold voltage and the second voltage to a difference between the first voltage and the second voltage may be 55% or more.

[0017] In any of the above semiconductor devices, a ratio of a difference between the threshold voltage and the second voltage to a difference between the first voltage and the second voltage may be 60% or more.

[0018] In any of the above semiconductor devices, a ratio of a difference between the threshold voltage and the second voltage to a difference between the first voltage and the second voltage may be 70% or less.

[0019] In any of the semiconductor devices described above, the second voltage may be 0 V. In any of the semiconductor devices described above, the second voltage may be -15 V.

[0020] In any of the above semiconductor devices, a plurality of the gate trench portions may be arranged side by side. In any of the above semiconductor devices, two dummy trench portions may be arranged between two of the gate trench portions.

[0021] The difference between the first voltage and the second voltage can be set to Vge (V), and the total length of the portion of the emitter region in contact with the gate trench portion per unit area, that is, the total emitter width can be set to W E (cm / cm 2 ), and the threshold voltage is set to Vth (V). In any of the above semiconductor devices, the total emitter width W E The following formula can be satisfied:

[0022] 0.9×6.39×10 5 / (Vge+1.5-Vth) 2 ≤W E ≤1.1×6.39×10 5 / (Vge+1.5-Vth) 2 .

[0023] In any of the semiconductor devices described above, on the upper surface of the semiconductor substrate, the first direction of the gate trench portion may be a length direction. In any of the semiconductor devices described above, the length of the emitter region in the first direction may be longer than the length of the emitter region in a second direction orthogonal to the first direction.

[0024] Any of the above-mentioned semiconductor devices may have a contact region of the second conductivity type, and the contact region is provided in the semiconductor substrate so as to be exposed on the upper surface and is in contact with the gate groove portion. In any of the above-mentioned semiconductor devices, on the upper surface of the semiconductor substrate, the first direction of the gate groove portion may be a length direction. In any of the above-mentioned semiconductor devices, at a position in contact with the gate groove portion, the emitter region and the contact region may be alternately arranged along the first direction. In any of the above-mentioned semiconductor devices, at a position in contact with the gate groove portion, the length of the emitter region in the first direction may be longer than the length of the contact region in the first direction.

[0025] In any of the above semiconductor devices, at a position in contact with the gate trench portion, a length of the emitter region in the first direction may be at least twice a length of the contact region in the first direction.

[0026] In a second aspect of the present invention, there is provided a semiconductor module including: the semiconductor device according to the first aspect; and a control unit that applies the gate voltage to the semiconductor device.

[0027] In a third aspect of the present invention, a method for manufacturing a semiconductor device is provided, wherein the semiconductor device includes a semiconductor substrate and a portion that operates as a transistor, wherein the semiconductor substrate has an upper surface and a lower surface and is provided with a drift region of a first conductivity type. The transistor may include: a gate groove portion having a gate conductive portion to which a gate voltage is applied and a gate insulating film surrounding the gate conductive portion, wherein the first direction is a length direction; an emitter region of a first conductivity type, which is provided in the semiconductor substrate so as to be exposed on the upper surface and in contact with the gate groove portion; and a base region of a second conductivity type, which is provided between the emitter region and the drift region and in contact with the gate groove portion. In the above manufacturing method, a first characteristic showing a relationship between an on-voltage of the transistor and a threshold voltage of the transistor at a set value of the saturation current may be estimated based on a saturation current of the transistor, a capacitance of the gate insulating film, and a set value of a channel length, wherein the channel length is a length of the base region in contact with the gate groove portion in the depth direction of the semiconductor substrate. In any of the above manufacturing methods, the on-voltage and the threshold voltage may be determined based on the first characteristic. Any of the above manufacturing methods can manufacture the semiconductor device in a manner that satisfies the determined on-voltage and the threshold voltage.

[0028] Any of the above manufacturing methods may determine the on-voltage, and determine the threshold voltage corresponding to the on-voltage based on the first characteristic.

[0029] Any of the above manufacturing methods may determine the threshold voltage, and determine the turn-on voltage corresponding to the threshold voltage based on the first characteristic.

[0030] It should be noted that the above invention summary does not list all the features of the present invention. In addition, sub-combinations of these feature groups can also constitute inventions. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a diagram showing an example of the semiconductor device 100 .

[0032] Figure 2 yes Figure 1 An example of an enlarged view of region D.

[0033] Figure 3 It is shown Figure 2 A diagram showing an example of an aa section of .

[0034] Figure 4 It is shown Figure 2 A diagram showing an example of the bb cross section.

[0035] Figure 53 is a graph showing the relationship between the threshold voltage and the saturation current with respect to the doping concentration of the base region 14 .

[0036] Figure 6 2 is a diagram showing the IV output characteristics of the semiconductor device 100 for each threshold voltage Vth.

[0037] Figure 7 FIG. 1 is a diagram showing an example of a region D of the semiconductor device 100 according to the embodiment.

[0038] Figure 8 It is shown Figure 7 A diagram showing an example of the cc cross section in FIG.

[0039] Fig. 9 It is shown Figure 8 A diagram showing an example of the doping concentration distribution at the mm line.

[0040] Fig.10 FIG. 1 is a diagram showing another example of the structure of the semiconductor device 100 in the region D of the embodiment.

[0041] Fig.11 It is shown Fig.10 A diagram showing an example of a dd cross section.

[0042] Fig.12 FIG. 1 is a diagram showing another example of the structure of the semiconductor device 100 in the region D of the embodiment.

[0043] Fig.13 1 is a diagram showing the semiconductor device 100. CE -V CE Figure 1 shows an example of a characteristic.

[0044] Fig.14 2 is a diagram showing the relationship between the threshold voltage and the on-voltage of the semiconductor device 100 .

[0045] Fig.15 FIG. 1 is a diagram showing another example of the structure of the semiconductor device 100 in the region D of the embodiment.

[0046] Fig.16 The diagram shows a part of the steps in the method for manufacturing the semiconductor device 100 .

[0047] Explanation of symbols

[0048] 10: semiconductor substrate; 11: P-type peripheral well region; 12: emitter region; 14: base region; 15: contact region; 16: storage region; 18: drift region; 20: buffer region; 21: upper surface; 22: collector region; 23: lower surface; 24: collector electrode; 30: dummy groove portion; 32: dummy insulating film; 34: dummy conductive portion; 38: interlayer insulating film; 40: gate groove portion; 42: gate insulating film; 44: gate conductive portion; 52: emitter electrode; 60: mesa portion; 70: transistor portion; 90: edge terminal structure portion; 100: semiconductor device; 130: gate wiring; 160: active portion; 161: first end edge; 162: second end edge; 164: gate pad; 200: semiconductor module; 210: first characteristic DETAILED DESCRIPTION

[0049] Hereinafter, the present invention will be described by way of the embodiments of the invention, but the following embodiments do not limit the invention involved in the claims. In addition, all combinations of features described in the embodiments are not necessarily essential to the technical means of the invention.

[0050] In this specification, one side in a direction parallel to the depth direction of the semiconductor substrate is referred to as "upper", and the other side is referred to as "lower". Of the two main surfaces of a substrate, layer, or other component, one surface is referred to as an upper surface, and the other surface is referred to as a lower surface. The "upper" and "lower" directions are not limited to the direction of gravity or the direction when the semiconductor device is actually installed.

[0051] In this specification, sometimes the rectangular coordinate axes of the X-axis, Y-axis, and Z-axis are used to explain technical matters. The rectangular coordinate axes only determine the relative positions of the components and do not limit specific directions. For example, the Z-axis is not limited to indicating the height direction relative to the ground. It should be noted that the +Z-axis direction and the -Z-axis direction are opposite directions to each other. When the Z-axis direction is recorded without recording the positive or negative, it refers to the direction parallel to the +Z-axis and the -Z-axis.

[0052] In this specification, the orthogonal axes parallel to the upper surface and the lower surface of the semiconductor substrate are referred to as the X-axis and the Y-axis. In addition, the axis perpendicular to the upper surface and the lower surface of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis is sometimes referred to as the depth direction. In addition, in this specification, the direction including the X-axis and the Y-axis and parallel to the upper surface and the lower surface of the semiconductor substrate is sometimes referred to as the horizontal direction.

[0053] The region from the center in the depth direction of the semiconductor substrate to the upper surface of the semiconductor substrate is sometimes referred to as the upper surface side. Similarly, the region from the center in the depth direction of the semiconductor substrate to the lower surface of the semiconductor substrate is sometimes referred to as the lower surface side.

[0054] In this specification, when the term "same" or "equal" is used, it may include a case where there is an error due to manufacturing variation, etc. The error is within 10%, for example.

[0055] In this specification, the conductivity type of the doped region doped with impurities is set to P type or N type for description. In this specification, impurities sometimes specifically refer to one of N type donors and P type acceptors, and sometimes are described as dopants. In this specification, doping refers to the introduction of donors or acceptors into a semiconductor substrate to form a semiconductor exhibiting N type conductivity or a semiconductor exhibiting P type conductivity.

[0056] In this specification, the doping concentration refers to the concentration of donors or acceptors in thermal equilibrium. In this specification, the net doping concentration refers to the actual concentration obtained by adding the polarity of the charges when the donor concentration is set to the concentration of positive ions and the acceptor concentration is set to the concentration of negative ions. As an example, if the donor concentration is set to N D , and the acceptor concentration is set to N A , then the net doping concentration at any position becomes N D -N A In this specification, the net doping concentration may be described simply as the doping concentration.

[0057] A donor has the function of supplying electrons to a semiconductor. An acceptor has the function of taking electrons from a semiconductor. Donors and acceptors are not limited to the impurities themselves. For example, a VOH defect formed by a combination of vacancies (V), oxygen (O), and hydrogen (H) present in a semiconductor functions as a donor for supplying electrons. In this specification, a VOH defect is sometimes referred to as a hydrogen donor.

[0058] In this specification, when it is recorded as P+ type or N+ type, it means that the doping concentration is higher than the doping concentration of P type or N type, and when it is recorded as P- type or N- type, it means that the doping concentration is lower than the doping concentration of P type or N type. Unless otherwise specified, the unit system in this specification is the SI unit system. Although the unit of length is sometimes expressed in cm, each calculation can be performed after conversion to meters (m).

[0059] In this specification, chemical concentration refers to the atomic density of impurities measured independently of the state of electrical activation. Chemical concentration (atomic density) can be measured by, for example, secondary ion mass spectrometry (SIMS). The above-mentioned net doping concentration can be measured by voltage-capacitance measurement (CV method). In addition, the carrier concentration measured by the extended resistance measurement method (SR method) can be used as the net doping concentration. The carrier concentration measured by the CV method or the SR method can be used as a value in thermal equilibrium. In addition, in the N-type region, the donor concentration is much greater than the acceptor concentration, so the carrier concentration in the region can also be set to the donor concentration. Similarly, in the P-type region, the carrier concentration in the region can also be set to the acceptor concentration. In this specification, the doping concentration of the N-type region is sometimes referred to as the donor concentration, and the doping concentration of the P-type region is sometimes referred to as the acceptor concentration.

[0060] In addition, when the concentration distribution of the donor, acceptor or net doping has a peak, the peak value can be used as the concentration of the donor, acceptor or net doping in the region. In the case where the concentration of the donor, acceptor or net doping is almost uniform, the average value of the concentration of the donor, acceptor or net doping in the region can also be used as the concentration of the donor, acceptor or net doping. In this specification, atoms / cm is used to express the concentration per unit volume. 3 or / cm 3 This unit is used for donor or acceptor concentration or chemical concentration in a semiconductor substrate. The atoms symbol can also be omitted.

[0061] The carrier concentration measured by the SR method can be lower than the concentration of the donor or acceptor. In the range of current flow when measuring the spreading resistance, there is a case where the carrier mobility of the semiconductor substrate is lower than the value of the carrier mobility in the crystalline state. The disorder (disorder) of the crystal structure caused by lattice defects, etc., scatters the carriers, resulting in a decrease in carrier mobility.

[0062] The concentration of donors or acceptors calculated from the carrier concentration measured by the CV method or the SR method may be lower than the chemical concentration of the element representing the donor or acceptor. As an example, the donor concentration of phosphorus or arsenic that serves as a donor in a silicon semiconductor, or the acceptor concentration of boron that serves as an acceptor, is about 99% of their chemical concentrations. On the other hand, the donor concentration of hydrogen that serves as a donor in a silicon semiconductor is about 0.1% to 10% of the chemical concentration of hydrogen. Each concentration in this specification may be a value at room temperature. As an example, the value at room temperature may be a value of 300K (Kelvin) (about 26.9°C).

[0063] Figure 11 is a diagram showing an example of a semiconductor module 200. The semiconductor module 200 includes a semiconductor device 100 and a control unit 190. The semiconductor device 100 is, for example, a semiconductor chip formed on a semiconductor substrate 10. The control unit 190 is a circuit that controls the switch of the semiconductor device 100 by applying a gate voltage to the semiconductor device 100. The control unit 190 generates a predetermined first voltage or a second voltage as a gate voltage. The first voltage is a voltage generated as a gate voltage when the semiconductor device 100 is turned on. The second voltage is a voltage generated as a gate voltage when the semiconductor device 100 is turned off. The semiconductor module 200 may include a housing that accommodates the semiconductor device 100 and the control unit 190. The housing may be formed of a resin. In other examples, the control unit 190 may also be arranged outside the housing.

[0064] Figure 1 1 is a diagram showing an example of a semiconductor device 100. Figure 1 , the positions of the components projected onto the upper surface of the semiconductor substrate 10 are shown. Figure 1 In FIG. 1 , only some components of the semiconductor device 100 are shown, and some components are omitted.

[0065] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate, but the material of the semiconductor substrate 10 is not limited to silicon.

[0066] The semiconductor substrate 10 has a first end side 161 and a second end side 162 when viewed from above. In this specification, the state of viewing from above refers to the state of viewing from the upper surface side of the semiconductor substrate 10. The semiconductor substrate 10 of this example has two sets of first end sides 161 that are opposite to each other when viewed from above. In addition, the semiconductor substrate 10 of this example has two sets of second end sides 162 that are opposite to each other when viewed from above. Figure 1 In the embodiment, the first end side 161 is parallel to the X-axis direction. The second end side 162 is parallel to the Y-axis direction. In addition, the Z-axis is perpendicular to the upper surface of the semiconductor substrate 10. In addition, the first end side 161 is perpendicular to the extension direction or length direction of the gate groove portion described later. The second end side 162 is parallel to the extension direction or length direction of the gate groove portion described later.

[0067] The semiconductor substrate 10 is provided with an active portion 160. The active portion 160 is a region where a main current flows in the depth direction between the upper surface and the lower surface of the semiconductor substrate 10 when the semiconductor device 100 is in operation. An emitter electrode is provided above the active portion 160, but Figure 1 Omitted in .

[0068] In this example, a transistor section 70 such as an IGBT that operates as a transistor is provided in the active section 160. In another example, the transistor section 70 and a diode section including a diode element such as a FWD (Free Wheel Diode) can be alternately arranged along a predetermined arrangement direction on the upper surface of the semiconductor substrate 10. In this example, one transistor section 70 is provided, but a plurality of transistor sections 70 may be provided. A P+ type well region and a gate flow channel may be provided between the transistor sections 70.

[0069] The transistor portion 70 has a P+ type collector region in a region in contact with the lower surface of the semiconductor substrate 10. In addition, the transistor portion 70 has a surface MOS structure periodically arranged on the upper surface side of the semiconductor substrate 10, and the surface MOS structure has an N+ type emitter region, a P- type base region, an N- type drift region, a gate conductive portion, and a gate insulating film.

[0070] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. The semiconductor device 100 of this example has a gate pad 164. The semiconductor device 100 may have pads such as an anode pad, a cathode pad, and a current detection pad. Each pad is arranged near the first end 161. The vicinity of the first end 161 refers to the area between the first end 161 and the emitter electrode when viewed from above. When the semiconductor device 100 is actually installed, each pad can be connected to an external circuit via wiring such as a wire.

[0071] A gate potential is applied to the gate pad 164. The gate pad 164 is electrically connected to the conductive portion of the gate trench portion of the active portion 160. The semiconductor device 100 includes a gate wiring 130 that connects the gate pad 164 to the gate trench portion. Figure 1 In FIG. 1 , the gate wiring 130 is indicated by oblique hatching.

[0072] The gate wiring 130 is arranged between the active portion 160 and the first end side 161 or between the active portion 160 and the second end side 162 when viewed from above. The gate wiring 130 of this example surrounds the active portion 160 when viewed from above. The region surrounded by the gate wiring 130 when viewed from above may also be set as the active portion 160. In addition, the gate wiring 130 is connected to the gate pad 164. The gate wiring 130 is arranged above the semiconductor substrate 10. The gate wiring 130 may be a metal wiring containing aluminum or the like. The gate wiring 130 may be provided separately from the emitter electrode.

[0073] The P-type peripheral well region 11 is arranged to overlap with the gate wiring 130. That is, similarly to the gate wiring 130, the P-type peripheral well region 11 surrounds the active portion 160 when viewed from above. The P-type peripheral well region 11 is also arranged to extend with a predetermined width in a range that does not overlap with the gate wiring 130. The P-type peripheral well region 11 is a region of the second conductivity type. The P-type peripheral well region 11 of this example is of P+ type. The doping concentration of the P-type peripheral well region 11 can be 5.0×10 17 atoms / cm 3 Above and 5.0×10 19 atoms / cm 3 The doping concentration of the P-type peripheral well region 11 may also be 2.0×10 18 atoms / cm 3 Above and 2.0×10 19 atoms / cm 3 the following.

[0074] The semiconductor device 100 may include a temperature sensing portion (not shown) which is a PN junction diode formed of polysilicon or the like, and a current detection portion (not shown) which simulates the operation of the transistor portion 70 provided in the active portion 160. The temperature sensing portion may be connected to the anode pad and the cathode pad via wiring. When the temperature sensing portion is provided, it is preferably provided at the center of the semiconductor substrate 10 in the X-axis direction and the Y-axis direction.

[0075] The semiconductor device 100 of this example includes an edge termination structure portion 90 between the active portion 160 and the first edge 161 or between the active portion 160 and the second edge 162 in a plan view. The edge termination structure portion 90 of this example is arranged between the peripheral gate wiring 130 and the first edge 161 or between the peripheral gate wiring 130 and the second edge 162. The edge termination structure portion 90 alleviates the electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure portion 90 may include at least one of a guard ring, a field plate, and a surface electric field reduction portion that surrounds the active portion 160 and is provided in an annular shape.

[0076] Figure 2 yes Figure 1 An example of an enlarged view of region D. Figure 2 A comparative example of the structure of region D is shown. Region D includes Figure 1 The region including the transistor portion 70 of the active portion 160 is shown. Figure 2, the structure of the upper surface of the semiconductor substrate 10 in the region D is shown. In the region D, the semiconductor device 100 includes one or more gate groove portions 40, one or more emitter regions 12, and one or more contact regions 15. The semiconductor device 100 may further include one or more dummy groove portions 30. In this specification, the gate groove portion 40 and the dummy groove portion 30 are sometimes referred to as groove portions, respectively. When simply referred to as a groove portion in this specification, the groove portion may be any one of the gate groove portion 40 and the dummy groove portion 30.

[0077] The gate groove portion 40 has a length in the first direction on the upper surface of the semiconductor substrate 10. In this example, the gate groove portion 40 is provided to extend along the Y-axis direction as the first direction. The gate groove portion 40 is provided from the upper surface of the semiconductor substrate 10 to the inside of the semiconductor substrate 10. A gate conductive portion formed of a conductive material such as polysilicon is arranged inside the gate groove portion 40. The gate conductive portion is connected to the gate wiring 130 (see Figure 1 ) are electrically connected and a predetermined gate voltage is applied.

[0078] In a second direction intersecting the first direction, a plurality of grooves are arranged at predetermined intervals. The second direction in this example is an X-axis direction orthogonal to the first direction (Y-axis direction). Figure 2 As shown in FIG. 1 , the groove portion adjacent to the gate groove portion 40 in the Y-axis direction may be the dummy groove portion 30. However, the gate groove portions 40 may be arranged adjacent to each other in the Y-axis direction. Figure 2 As shown, the trench portion adjacent to the dummy trench portion 30 in the Y-axis direction may be a gate trench portion 40 or a dummy trench portion 30. In the Y-axis direction, one or more dummy trench portions 30 may be disposed between two gate trench portions 40.

[0079] The region of the semiconductor substrate 10 sandwiched between the two grooves in the X-axis direction is defined as a mesa portion 60. Both ends of the mesa portion 60 in the X-axis direction are the boundaries with the respective grooves. The depth position of the lower end of the mesa portion 60 is the same as the depth position of the lower end of at least one of the grooves on both sides.

[0080] The emitter region 12 is an N+ type region exposed on the upper surface of the semiconductor substrate 10. The emitter region 12 is connected to the gate groove portion 40. The emitter region 12 can be set in each mesa portion 60 connected to the gate groove portion 40. The length of an emitter region 12 in the Y-axis direction is set to Y11, and the length in the X-axis direction is set to X11. The length X11 is the same as the width of the mesa portion 60 in the X-axis direction. The length X11 is greater than the length Y11. The emitter region 12 in this example has a length in the X-axis direction. Each emitter region 12 can have a band shape extending in the X-axis direction. In this example, the length direction of the emitter region 12 is orthogonal to the length direction of the groove portion. In this specification, the structure in which the length of the emitter region 12 in the X-axis direction is the same as the width of the mesa portion 60 in the X-axis direction is sometimes referred to as an emitter orthogonal type.

[0081] The contact region 15 is a P-type region exposed on the upper surface of the semiconductor substrate 10 in the mesa portion 60 and connected to the emitter electrode. The contact region 15 may be a partial region of the base region described later, or may be a P+-type region having a higher doping concentration than the base region. When the contact region 15 has a higher doping concentration than the base region, the contact resistance between the contact region 15 and the emitter electrode can be reduced.

[0082] The contact regions 15 are alternately arranged with the emitter regions 12 along the Y-axis direction. The contact regions 15 and the emitter regions 12 may be alternately arranged along the Y-axis direction at least at a position in contact with the gate trench portion 40. The contact region 15 also has a length in the X-axis direction. The width of the contact region 15 in the X-axis direction is equal to the width of the mesa portion 60 in the X-axis direction.

[0083] Figure 3 It is shown Figure 2 The aa section is an XZ section passing through the emitter region 12. The semiconductor device 100 of this example includes the semiconductor substrate 10, the interlayer insulating film 38, the emitter electrode 52, and the collector electrode 24 in this section.

[0084] The emitter electrode 52 is provided above the upper surface 21 of the semiconductor substrate 10. A portion of the upper surface 21 of the semiconductor substrate 10 is covered by the interlayer insulating film 38. The emitter electrode 52 is in contact with at least a portion of the upper surface 21 of the semiconductor substrate 10 that is not covered by the interlayer insulating film 38. The emitter electrode 52 of this example is in contact with the emitter region 12. As described later, the emitter electrode 52 is also in contact with the contact region 15.

[0085] The emitter electrode 52 is formed of a material containing a metal. For example, at least a portion of the emitter electrode 52 is formed of aluminum or an aluminum-silicon alloy such as a metal alloy such as AlSi, AlSiCu, etc. The emitter electrode 52 may have a barrier metal formed of titanium or titanium nitride, etc., below the region formed of aluminum, etc. The barrier metal may be in contact with the semiconductor substrate 10. The emitter electrode 52 may also have a metal plug formed of tungsten, etc., below the region formed of aluminum, etc. The metal plug may have a portion formed below the upper surface 21 of the semiconductor substrate 10.

[0086] The collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10. The collector electrode 24 is formed of a metal material such as aluminum, similarly to the emitter electrode 52. In this specification, the direction connecting the emitter electrode 52 and the collector electrode 24 (Z-axis direction) is referred to as the depth direction.

[0087] The interlayer insulating film 38 is provided on the upper surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 is a film including at least one of an insulating film such as silicate glass to which impurities such as boron or phosphorus are added, a thermal oxide film, and other insulating films. The interlayer insulating film 38 may cover each trench portion.

[0088] A P-type base region 14 is provided in each mesa portion 60. The base region 14 is connected to the gate groove portion 40. The base region 14 may be connected to the groove portions on both sides of the mesa portion 60, respectively. At least a portion of the base region 14 is provided below the emitter region 12. The base region 14 may be connected to the emitter region 12. If a predetermined first voltage is applied to the gate groove portion 40, the surface layer of the base region 14 connected to the gate groove portion 40 is inverted to an N-type region to form a channel. Through the channel, the emitter region 12 is electrically connected to the drift region 18 described later.

[0089] As described later, the base region 14 is also provided below the contact region 15. The base region 14 is in contact with the contact region 15. As described above, a portion of the base region 14 can function as the contact region 15. The base region 14 in this example is a P-type region having a lower doping concentration than the contact region 15. The doping concentration of the base region 14 can be 3.0×10 17 atoms / cm 3 the following.

[0090] The semiconductor substrate 10 has an N-type drift region 18. The doping concentration of the emitter region 12 is higher than the doping concentration of the drift region 18. The drift region 18 is arranged below the base region 14. The drift region 18 can be connected to the base region 14. In another example, an N+ type accumulation region 16 with a doping concentration higher than the doping concentration of the drift region 18 can be arranged between the drift region 18 and the base region 14. By providing the accumulation region 16, an electron injection enhancement effect (Injection Enhancement Effect) can be generated, thereby reducing the on-state voltage of the semiconductor device 100.

[0091] A P+ type collector region 22 is provided between the drift region 18 and the lower surface 23 of the semiconductor substrate 10. The doping concentration of the collector region 22 is higher than the doping concentration of the base region 14. The collector region 22 may contain the same acceptor as the base region 14, or may contain an acceptor different from the base region 14. The acceptor of the collector region 22 is, for example, boron. The elements that serve as acceptors are not limited to the above examples. The collector region 22 is exposed at the lower surface 23 of the semiconductor substrate 10 and is connected to a collector electrode 24. The collector electrode 24 may be in contact with the entire lower surface 23 of the semiconductor substrate 10.

[0092] An N+ type buffer region 20 may be provided between the drift region 18 and the collector region 22. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may have one or more concentration peaks having a higher doping concentration than the doping concentration of the drift region 18. The doping concentration of the concentration peak refers to the doping concentration at the top of the concentration peak. In addition, the doping concentration of the drift region 18 may use the average value of the doping concentration in a region where the doping concentration distribution is approximately flat.

[0093] The buffer region 20 can be formed by ion implanting N-type dopants such as hydrogen (protons) or phosphorus. The buffer region 20 of this example is formed by ion implanting hydrogen. The buffer region 20 can function as a field stop layer that prevents the depletion layer extending from the lower end of the base region 14 from reaching the collector region 22.

[0094] One or more gate grooves 40 are provided on the upper surface 21 side of the semiconductor substrate 10. In this example, a plurality of gate grooves 40 are provided on the upper surface 21 side of the semiconductor substrate 10. In this example, each gate groove 40 penetrates the base region 14 from the upper surface 21 of the semiconductor substrate 10 to reach the drift region 18. The method of manufacturing by forming the groove portion through the doped region is not limited to the order of forming the groove portion after forming the doped region. The method of forming the doped region between the groove portions after forming the groove portion is also included in the method of the groove portion penetrating the doped region.

[0095] The gate trench portion 40 has a trench-shaped gate trench provided on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate conductive portion 44 is formed of polysilicon as a conductive material. The gate insulating film 42 is provided in a manner covering the inner wall of the gate trench. The gate insulating film 42 can be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate trench at a position closer to the inner side than the gate insulating film 42. That is, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10.

[0096] The gate conductive portion 44 in the gate trench portion 40 is provided longer than the base region 14 in the depth direction. The gate trench portion 40 in this cross section is covered by the interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. Figure 3 Positions other than the illustrated cross section are electrically connected to the gate wiring 130 .

[0097] The dummy groove portion 30 has the same structure as the gate groove portion 40. The dummy groove portion 30 of this example has a dummy groove in a groove shape, a dummy insulating film 32, and a dummy conductive portion 34. The structures of the dummy groove, the dummy insulating film 32, and the dummy conductive portion 34 are the same as those of the gate groove, the gate insulating film 42, and the gate conductive portion 44. The dummy groove portion 30 in this cross section is covered by the interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The dummy conductive portion 34 is not Figure 3 Positions outside the illustrated cross section are electrically connected to the emitter electrode 52 .

[0098] Figure 4 It is shown Figure 2 FIG. bb is an example of a cross section of FIG. bb is an XZ cross section passing through the contact region 15. The cross section bb has the same structure as the cross section aa except that the contact region 15 is provided instead of the emitter region 12. The contact region 15 is in contact with the emitter electrode 52 on the upper surface 21 of the semiconductor substrate 10. The contact region 15 of this example is in contact with the base region 14.

[0099] exist Figures 2 to 4The MOS structure provided on the upper surface 21 of the semiconductor substrate 10 described in the description has a saturation characteristic that the collector current is saturated even if the voltage between the collector and the emitter is increased. As a result, the semiconductor device 100 has a short-circuit tolerance characteristic that the element will not be destroyed as long as it lasts for a certain period of time in a short-circuit state where a large current and a large voltage are applied simultaneously. In a state obtained by advancing the miniaturization of the device, if a MOS structure is formed in all the mesa portions 60, the saturation current becomes very large, so sometimes a sparse structure (inter-introduction structure) in which a MOS structure is not formed in a part of the mesa portion 60, or an emitter orthogonal structure in which an emitter region 12 having a length in the X-axis direction is discretely arranged in the Y-axis direction is used to suppress the saturation current. However, if the saturation current is suppressed in such a structure, the on-state voltage becomes higher.

[0100] The current saturation characteristic of the MOS structure is expressed by the following equation (1).

[0101]

Mathematical formula 1

[0102]

[0103] Isat represents the saturation current, Z represents the total emitter width of the emitter region 12 (i.e. the total length in the Y-axis direction), μn represents the mobility of electrons, Cox represents the capacitance of the gate insulating film 42, Lch represents the channel length in the Z-axis direction, Vge represents the gate-emitter voltage, and Vth represents the threshold voltage.

[0104] The channel resistance Rch of the MOS structure is expressed by the following equation (2).

[0105]

Mathematical formula 2

[0106]

[0107] Comparing equation (1) and equation (2), it can be seen that if the saturation current Isat is reduced, the channel resistance Rch becomes larger, and if the saturation current Isat is increased, the channel resistance Rch becomes smaller. That is, it becomes the following trade-off correlation: if the saturation current is reduced in order to improve the short-circuit tolerance of the semiconductor device 100, the on-voltage will increase. For example, in a sparse emitter structure, the emitter region 12 is formed in a portion of the mesa portion 60, so the supply of electron current to the drift region 18 becomes sparse in the X-axis direction, the flow of current becomes uneven, and the on-voltage increases. In addition, in an emitter orthogonal structure in which the emitter region 12 having a length in the X-axis direction is discretely arranged in the Y-axis direction, there is a limit in increasing the length Z (equivalent to the channel width) of the gate groove portion 40 connected to the emitter region 12.

[0108] In the following description, numerical values ​​of a semiconductor element having a withstand voltage class of 1200 V and a rated current of 150 A are used.

[0109] Figure 5 is a graph showing the relationship between the threshold voltage and the saturation current with respect to the doping concentration of the base region 14. In this example, Figures 2 to 4 The characteristics of the emitter-orthogonal semiconductor device 100 described in FIG. Figure 5 As shown, the higher the doping concentration of the base region 14 is, the lower the threshold voltage is and the greater the saturation current is.

[0110] Figure 6 2 is a diagram showing the IV output characteristics of the semiconductor device 100 for each threshold voltage Vth.

[0111] The IV output characteristic is a characteristic showing the relationship between the collector current and the collector voltage.

[0112] The rated current of 100 is set in the saturation region where the collector current changes with the collector voltage. The threshold voltage Vth of the on-voltage (collector voltage) of the semiconductor device 100 at the rated current is high. Figure 4 and Figure 5 The correlation of the trade-off is shown in that if the doping concentration of the base region 14 is adjusted to reduce the saturation current, the on-voltage increases.

[0113] Figure 7 1 is a diagram showing an example of region D of the semiconductor device 100 of the embodiment. In the semiconductor device 100 of the embodiment, the doping concentration of the base region 14 is adjusted to increase the threshold voltage Vth and reduce the saturation current. By increasing the threshold voltage and reducing the saturation current, the on-voltage increases, but in the semiconductor device 100 of the embodiment, the total emitter width Z is adjusted to suppress the increase in the on-voltage or reduce the on-voltage. Thus, a relatively low on-voltage and a relatively low saturation current can be taken into account. Alternatively, the on-voltage can be reduced while maintaining the saturation current.

[0114] The semiconductor device 100 of this example adjusts the total emitter width Z by adjusting the configuration of the emitter region 12 on the upper surface 21. For example, by making the length Y1 of the emitter region 12 in the Y-axis direction larger than the length X1 in the X-axis direction, the total emitter width Z can be increased. By increasing the total emitter width Z, the saturation current amount increases and the on-voltage decreases.

[0115] The length Y1 may be more than 1.5 times the length X1, more than 2 times the length X1, or more than 3 times the length X1. The length X1 of the emitter region 12 in the X-axis direction may be the same as the width of the mesa portion 60 in the X-axis direction. In this case, the emitter region 12 is continuously arranged along the X-axis direction from a position where it is connected to one of the two groove portions adjacent to each other in the X-axis direction to a position where it is connected to the other. The length of the contact region 15 in the X-axis direction may be the same as the length of the emitter region 12 in the X-axis direction. In another example, the length X1 of the emitter region 12 may be smaller than the width of the mesa portion 60 in the X-axis direction. In this case, the emitter region 12 is configured to be in contact with the gate groove portion 40, and is not in contact with other groove portions (e.g., the dummy groove portion 30) adjacent to the gate groove portion 40.

[0116] The length Y1 of the emitter region 12 may be greater than the length Y2 of the contact region 15 in the Y-axis direction. Thus, the total emitter width Z can be increased. The length Y1 may be 1.5 times or more of the length Y2, or may be 2 times or more of the length Y2, or may be 3 times or more of the length Y2. The length of the emitter region 12 and the contact region 15 in the Y-axis direction is the length at the position where they are in contact with the gate trench portion 40.

[0117] Figure 8 It is shown Figure 7 FIG. 1 is a diagram showing an example of a cc cross section in FIG. The cc cross section is an XZ cross section through the emitter region 12. The doping concentration of the base region 14 of the semiconductor device 100 of this example is Figure 3 Except for the doping concentration of the base region 14, the semiconductor device 100 of this example has the same Figures 1 to 6 The semiconductor device 100 has the same structure as described in the above. The base region 14 of this example is a P-type region with a higher doping concentration than the base region 14 of the comparative example. By increasing the doping concentration of the base region 14, the surface layer of the base region 14 is less likely to be inverted to an N-type, so that the threshold voltage of the semiconductor device 100 becomes higher. The threshold voltage is the voltage at which the transistor changes from the off state to the on state. As an example, the threshold voltage is calculated by using a straight line to calculate the collector current-gate voltage characteristic (I CE -Vge characteristics) is approximated by the waveform of the linear operation region, the collector current I on the straight line CE The value of the gate voltage Vge when it is 0.

[0118] A first voltage or a second voltage is applied to the gate groove portion 40 as the gate voltage Vge, the first voltage being a voltage when a transistor such as an IGBT is turned on, and the second voltage being a voltage when the transistor portion 70 is turned off. As an example, the first voltage is 15V and the second voltage is 0V. The second voltage may also be a voltage with a different sign from the first voltage. The second voltage may also be a voltage with a different sign from the first voltage and the same absolute value. The second voltage may also be -15V. Figure 1 The illustrated control section 190 may generate a first voltage and a second voltage.

[0119] In the semiconductor device 100 of this example, the threshold voltage when the ambient temperature is 25°C is greater than half of the first voltage. For example, when the first voltage is 15V, the threshold voltage is greater than 7.5V. The threshold voltage can be closer to the first voltage than the intermediate voltage between the first voltage and the second voltage. The intermediate voltage between the first voltage and the second voltage is the average voltage of the first voltage and the second voltage. For example, when the first voltage is 15V and the second voltage is 0V, the intermediate voltage is 7.5V. In this case, the threshold voltage of this example is greater than 7.5V. In this specification, the threshold voltage when the ambient temperature is 25°C is referred to as the threshold voltage. In the semiconductor device 100 of the comparative example, the threshold voltage is about 6.0V. By increasing the threshold voltage, the saturation current is reduced.

[0120] like Figure 7 As described in , the semiconductor device 100 of this example can reduce the on-voltage although the saturation current increases by adjusting the configuration of the emitter region 12. Therefore, by increasing the total emitter width Z within the range of the saturation current that decreases due to the increase in the threshold voltage, the saturation current increases, thereby maintaining or reducing the saturation current and reducing the on-voltage.

[0121] The threshold voltage Vth may be 55% or more of the first voltage. The threshold voltage Vth may be 65% or more of the first voltage, or 65% or more of the first voltage. The larger the threshold voltage Vth is, the smaller the saturation current can be, and the greater the room for reducing the on-state voltage. When the first voltage is 15V, the threshold voltage may be 8.5V or more, or 9.5V or more, or 10V or more. If the threshold voltage Vth is too large, the semiconductor device 100 is difficult to turn on. The ratio of the threshold voltage Vth to the first voltage may be 80% or less, or 70% or less.

[0122] The difference between the first voltage and the second voltage is set to a reference voltage Vs. For example, when the first voltage is 15V and the second voltage is 0V, the reference voltage Vs is 15-0=15V. The difference between the threshold voltage Vth and the second voltage is set to a relative voltage Vr. For example, when the second voltage is 0V, the relative voltage Vr is Vth-0=Vth. The ratio of the relative voltage Vr to the reference voltage Vs can be 55% or more. The ratio of the relative voltage Vr to the reference voltage Vs can also be 60% or more, or even 65% or more. The larger the relative voltage, the smaller the saturation current can be, and the greater the room for reducing the on-state voltage. When the first voltage is 15V and the second voltage is 0V, the threshold voltage can be 8.5V or more, 9.5V or more, or even 10V or more.

[0123] If the counter voltage Vr is too large, it is difficult for the semiconductor device 100 to turn on. The ratio of the counter voltage Vr to the reference voltage Vs may be 80% or less, or 70% or less.

[0124] Fig. 9 It is shown Figure 8 The mm line is a straight line that passes through the emitter region 12, the base region 14, and the reservoir region 16 in the mesa portion 60 that is connected to the gate trench portion 40 and is parallel to the Z axis. The mm line may pass through the emitter region 12, the base region 14, and the reservoir region 16 near the gate trench portion 40 or at a position that is connected to the gate trench portion 40. Fig. 9 The solid line shows Figure 8 The doping concentration distribution of the semiconductor device 100 of the embodiment is shown by the dotted line. Figure 3 Doping concentration distribution of the semiconductor device 100 according to the comparative example.

[0125] The emitter region 12, the base region 14, and the reservoir region 16 may each have a peak of doping concentration in the depth direction. The doping concentration distribution except for the base region 14 is the same in the embodiment and the comparative example.

[0126] The maximum value of the doping concentration in the base region 14 of the embodiment is set to the doping concentration Db in the base region 14. By increasing the doping concentration Db, the threshold voltage Vth of the semiconductor device 100 can be increased and the saturation current can be reduced. Figure 8 In the example of FIG. 1 , the doping concentration Db may be 4.0×10 17 atoms / cm 3 The doping concentration Db can be 5.0×10 17 atoms / cm 3 Above, it can also be 6.0×1017 atoms / cm 3 Above, it can also be 7.0×10 17 atoms / cm 3 The doping concentration Db can be 1.0×10 18 atoms / cm 3 Below, it can also be 8.0×10 17 atoms / cm 3 Below, it can also be 7.0×10 17 atoms / cm 3 Below, so that the threshold voltage Vth does not become too high.

[0127] Fig.10 FIG. 1 is a diagram showing another example of the structure of the semiconductor device 100 in the region D of the embodiment. In the semiconductor device 100 of this embodiment, the arrangement of the emitter region 12 and the contact region 15 is the same as that of FIG. Figure 7 The example shown is different. Other structures are Figures 1 to 9 The semiconductor device 100 of any embodiment described in is the same.

[0128] In this example, the length X1 of the emitter region 12 in the X-axis direction is smaller than the width of the mesa portion 60 in the X-axis direction. The emitter region 12 is connected to the gate groove portion 40, and is not connected to the adjacent dummy groove portion 30 of the gate groove portion 40. A contact region 15 is arranged between the emitter region 12 and the dummy groove portion 30. The contact region 15 is also arranged between the emitter regions 12 discretely arranged in the Y-axis direction. According to this example, even if the length Y1 of the emitter region 12 in the Y-axis direction is increased, the area of ​​the contact region 15 exposed on the upper surface of the mesa portion 60 can be ensured. Therefore, it is easy to adjust the on-voltage. In this specification, a structure in which the length X1 of the emitter region 12 in the X-axis direction is smaller than the width of the mesa portion 60 in the X-axis direction is sometimes referred to as an emitter parallel type.

[0129] The length Y1 of the emitter region 12 may be more than twice the length X1, more than three times the length X1, or more than five times the length X1. By making the length Y1 larger than the length X1, the length of the channel formed below the emitter region 12 in the Y-axis direction can be increased, thereby improving the channel density.

[0130] like Fig.10 As shown, in one mesa portion 60, a plurality of emitting regions 12 may be arranged separately from each other along the Y-axis direction. The distance between two adjacent emitting regions 12 in the Y-axis direction (in Fig.10The length Y2 of the contact area 15 may be smaller than the length Y1, or may be less than half of the length Y1, or may be less than 1 / 4 of the length Y1, or may be less than 1 / 10 of the length Y1. In another example, only one emission area 12 may be continuously arranged in the Y-axis direction of a mesa portion 60. In this case, the length Y1 of the emission area 12 may be more than half of the length of the mesa portion 60 in the Y-axis direction, or may be more than 3 / 4 of the length of the mesa portion 60 in the Y-axis direction.

[0131] Fig.11 It is shown Fig.10 FIG. dd cross section is an example of a dd cross section. The dd cross section is an XZ plane passing through the emitter region 12 and the contact region 15. As described above, the emitter region 12 is arranged in contact with the gate groove portion 40 and is not in contact with the dummy groove portion 30. The contact region 15 is arranged between the emitter region 12 and the dummy groove portion 30. The structure other than the emitter region 12 and the contact region 15 is the same as Figures 1 to 9 The semiconductor device 100 of any embodiment described in is the same.

[0132] Fig.12 FIG. 1 is a diagram showing another example of the structure of the semiconductor device 100 in the region D of the embodiment. In the semiconductor device 100 of this embodiment, only one emitter region 12 is provided continuously along the Y-axis direction in one mesa portion 60. Figures 1 to 11 The same is true for the semiconductor device 100 of any of the embodiments described in . According to this example, the total emitter width Z can be further increased.

[0133] Fig.13 1 is a diagram showing the semiconductor device 100. CE -V CE An example of the characteristics of the graph. Fig.13 , the characteristics of a plurality of semiconductor devices 100 having different threshold voltages Vth are shown. Fig.13 In the example of , the threshold voltage Vth is varied by varying the doping concentration of the base region 14. In addition, the total channel width Z is adjusted so that the saturation current of each semiconductor device 100 is substantially constant (approximately 500 A).

[0134] like Fig.13 As shown in the figure, for example, the larger the threshold voltage Vth is, the higher the on-state voltage (collector-emitter voltage V CE ) is smaller. According to the semiconductor device 100 of the embodiment, the saturation current can be maintained or reduced and the on-voltage can be reduced. The saturation current of the semiconductor device 100 can be adjusted to be more than 3 times the rated current and less than 7 times the rated current.

[0135] Fig.142 is a diagram showing the relationship between the threshold voltage and the on-voltage of the semiconductor device 100 . Fig.13 and Fig.14 The first voltage in is 15V, and the second voltage is 0V. Fig.14 In, with Fig.13 Similarly to the example of , the on-voltage when the total channel width Z is adjusted so that the saturation current amount is substantially constant is shown. Fig.14 In the figure, the square-marked plot points correspond to Figure 2 or Figure 7 The semiconductor device 100 of the orthogonal channel type is shown. The black square plot points correspond to Figure 2 The comparative example shown. Fig.14 The circularly marked points correspond to Fig.10 The emitter parallel type semiconductor device 100 is shown. Fig.14 In the example, each plotted point is approximated by a dotted straight line. This straight line shows the relationship between the threshold voltage and the on-voltage when the saturation current is maintained at the same level as in the comparative example. In this specification, this straight line is sometimes referred to as the first characteristic 210. Fig.14 As shown, by increasing the threshold voltage and adjusting the total channel width Z, the on-voltage can be reduced while maintaining the saturation current amount.

[0136] The emitter parallel semiconductor device 100 can maintain the contact area between the contact region 15 and the emitter electrode 52 and increase the upper limit value of the total channel width Z. Fig.14 As shown, the emitter parallel type semiconductor device 100 can maintain the saturation current by increasing the total channel width Z even if the threshold voltage is higher than that of the emitter orthogonal type semiconductor device 100. By making the emitter parallel type semiconductor device 100, the on-voltage can be further reduced.

[0137] The threshold voltage, the resistance of the channel, and the on-voltage before adjusting the doping concentration of the base region 14 and the total channel width Z are set to Vth1, R1, and V1. In addition, the threshold voltage, the resistance of the channel, and the on-voltage after adjusting the doping concentration of the base region 14 and the total channel width Z while maintaining the saturation current are set to Vth2, R2, and V2. The resistance of the channel is the resistance in the depth direction of the region where the base region 14 connected to the gate trench portion 40 is inverted to the N type by applying a gate voltage to the gate trench portion 40.

[0138] According to equation (2), the resistance ratio R2 / R1 is expressed by the following equation (3).

[0139] R2 / R1=(Vge-(Vth2-1.5)) / (Vge-(Vth1-1.5))

[0140] Vge is the difference between the first voltage and the second voltage, and is, for example, 15 V. In addition, if the temperature rises by 10°C, the threshold voltage Vth of the semiconductor device 100 decreases by approximately -0.1 V. In equation (3), 1.5 V is subtracted from each threshold voltage in order to convert the threshold voltage at room temperature to the threshold voltage when the chip temperature is 175°C.

[0141] The amount of reduction in the on-state voltage V1-V2 is expressed by the following equation (4).

[0142] V1-V2=V1-V1(R2 / R1)=(1-(R2 / R1))×V1

[0143] =((Vth2-Vth1) / (16.5-Vth1))×V1

[0144] In the formula (4), Vge=15V is assumed.

[0145] For example, when the collector-emitter voltage is 1200 V, the on-voltage V1 is about 0.4 V. In addition, the threshold voltage Vth1 before adjustment is set to about 6 V. Therefore, the amount of reduction in the on-voltage ΔVon=V1-V2 is expressed by the following equation (5).

[0146] ΔVon=3.81×10 -2 (Vth-6)

[0147] Here, Vth in equation (5) is the adjusted threshold voltage Vth2.

[0148] The threshold voltage Vth of the semiconductor device 100 may be determined so that the amount of reduction ΔVon of the on-voltage is equal to or greater than 0.1 V. In this case, according to the equation (4), the threshold voltages Vth1 and Vth2 satisfy the following equation.

[0149] Vth2≥4.13+0.75Vth1

[0150] When Vth1 is 6V, Vth2 is equal to or higher than 8.6V. The threshold voltage of the semiconductor device 100 can be equal to or higher than 8.6V.

[0151] The threshold voltage Vth of the semiconductor device 100 may be determined so that the amount of drop ΔVon of the on-voltage is equal to or greater than 0.15 V. In this case, according to the equation (4), the threshold voltages Vth1 and Vth2 satisfy the following equation.

[0152] Vth2≥6.19+0.625Vth1

[0153] When Vth1 is 6 V, Vth2 is equal to or higher than 9.9 V. The threshold voltage of the semiconductor device 100 can be equal to or higher than 9.9 V.

[0154] The total emitter width per unit area before adjustment is set to W E1 (cm / cm 2 ), the total emitter width per unit area adjusted while maintaining the saturation current is set to W E2 (cm / cm 2 ). Total emitter width W E It is the total length in the Y-axis direction of the portion where the emitter region 12 and the gate trench portion 40 are in contact with each other per unit area.

[0155] According to equations (1) and (2), the total emitter width W E2 and the total emitter width W E1 This becomes the following formula (6).

[0156] W E2 =((Vge-(Vth1-1.5)) 2 / (Vge-(Vth2-1.5)) 2 )×W E1

[0157] =((16.5-Vth1) 2 / (16.5-Vth2) 2 )×W E1

[0158] In this example, the total emitter width W before adjustment is E1 5.8×10 3 (cm / cm 2 ).

[0159] In this case, the total emitter width W E2 It becomes the following formula (7).

[0160] W E2 =(110.25 / (16.5-Vth2) 2 )×5.8×10 3

[0161] =6.39×10 5 / (16.5-Vth2) 2

[0162] The total emitter width W of the semiconductor device 100 E The following formula (8) can be satisfied.

[0163] 0.9×6.39×10 5 / (16.5-Vth) 2 ≤W E2 ≤1.1×6.39×10 5 / (16.5-Vth)2

[0164] The equation (8) can also be expressed as follows using the gate voltage Vge.

[0165] 0.9×6.39×10 5 / (Vge+1.5-Vth) 2 ≤W E2 ≤1.1×6.39×10 5 / (Vge+1.5-Vth) 2

[0166] The threshold voltage Vth satisfies any of the conditions described in this specification for the adjusted threshold voltage Vth2. For example, the threshold voltage Vth is closer to the first voltage than an intermediate voltage between the first voltage and the second voltage.

[0167] As described above, if the threshold voltage Vth of the semiconductor device 100 is determined so that the amount of reduction ΔVon of the on-state voltage is greater than or equal to 0.1 V, the threshold voltage of the semiconductor device 100 is greater than or equal to 8.6 V. According to equation (6) and the like, when the amount of reduction ΔVon of the on-state voltage is set to greater than or equal to 0.1 V, the total emitter width W E It can be set to 1.02×10 4 (cm / cm 2 ) or more. In addition, when the reduction amount ΔVon of the on-state voltage is set to 0.15V or more, the total emitter width W E It can be set to 1.47×10 4 (cm / cm 2 )above.

[0168] For the semiconductor device 100 of this example, the length Lch of the channel (i.e., the base region 14) in the depth direction is about 2 μm, the gate insulating film 42 is a thermal oxide film of silicon, and the thickness of the gate insulating film 42 is 110 nm. The length Lch of the semiconductor device 100 can be greater than 1.5 μm and less than 2.5 μm, and the thickness of the gate insulating film 42 can be greater than 55 nm and less than 165 nm. For the semiconductor device 100, the ratio of the number of gate trench portions 40 to the number of dummy trench portions 30 in the X-axis direction can be 1 to 2. While satisfying these conditions, the total emitter width W of the semiconductor device 100 is E It can satisfy formula (8).

[0169] Fig.15 FIG. 2 is a diagram showing another example of the structure of the semiconductor device 100 in the region D of the embodiment. Figure 2 As shown in FIG. 1 and FIG. 2 , the semiconductor device 100 includes a plurality of gate trench portions 40 arranged side by side in the X-axis direction. Figure 2In the example of FIG. 1 , a dummy groove portion 30 is provided between two gate groove portions 40 in the X-axis direction. In this example, two dummy groove portions 30 are provided between two gate groove portions 40 in the X-axis direction. In the mesa portion 60 sandwiched by the two dummy groove portions 30, a contact region 15 can be provided instead of the emitter region 12. The structure of the mesa portion 60 connected to the gate groove portion 40 is similar to that of FIG. Figures 1 to 14 The semiconductor device 100 of any embodiment described in the above is the same. Fig.15 , an emitter orthogonal type is shown as the configuration of the emitter region 12, but the configuration of the emitter region 12 may also be an emitter parallel type.

[0170] The total emitter width Z is the length of the emitter region 12 in the Y-axis direction that is in contact with the gate trench portion 40. Therefore, if the density of the gate trench portion 40 in the X-axis direction becomes lower, the upper limit value of the total emitter width Z becomes lower. Fig.15 The density ratio of the gate trench portion 40 to the dummy trench portion 30 is 1:2, and the density ratio of the gate trench portion 40 to the dummy trench portion 30 is 1:2. Figure 2 In this case, when the density ratio of the gate trench portion 40 to the dummy trench portion 30 is 1:1, Fig.15 In the example of , the upper limit value of the total emitter width Z becomes smaller.

[0171] If the upper limit of the total emitter width Z becomes smaller, the adjustment range of the saturation current amount by adjusting the total emitter width Z becomes smaller. Therefore, if the threshold voltage Vth is excessively increased, the saturation current amount cannot be maintained even if the total emitter width Z is adjusted. Fig.15 In the structure where the ratio of the number of gate grooves 40 to the number of dummy grooves 30 is 1 to 2, the ratio of the difference between the threshold voltage Vth and the second voltage to the difference between the first voltage and the second voltage can be 70% or less. Thus, the on-voltage can be reduced while maintaining the saturation current. In this case, the threshold voltage Vth can be, for example, 10.5V or less.

[0172] exist Figure 2 In the case of a structure in which the ratio of the number of gate groove portions 40 to the number of dummy groove portions 30 is 1:1, the upper limit of the total emitter width Z becomes larger. In this case, the ratio of the difference between the threshold voltage Vth and the second voltage to the difference between the first voltage and the second voltage can be 80% or less. Thus, the on-state voltage can be reduced while maintaining the saturation current. The threshold voltage Vth in this case can be, for example, 12V or less. In the case other than the withstand voltage level of 1200V, the total emitter width W can be E Adjust to W E =W E1200V*1200 / [Withstand voltage rating]. [Withstand voltage rating] indicates the voltage value of the withstand voltage rating of the semiconductor device. For example, when the withstand voltage rating of the semiconductor device is 1200V, [Withstand voltage rating] is 1200. E1200V It is the total emitter width of a semiconductor device with a withstand voltage rating of 1200V.

[0173] Fig.16 100 is a diagram showing a part of the steps in the method for manufacturing the semiconductor device 100. The manufacturing method of this example includes a characteristic estimation step S1002, a design step S1004, and a manufacturing step S1006.

[0174] In the characteristic estimation step S1002, the first characteristic of the semiconductor device 100 is estimated. The first characteristic 210 is a characteristic showing the relationship between the on-voltage of the transistor unit 70 and the threshold voltage Vth of the transistor unit at the set value of the saturation current. For example, the first characteristic 210 is given by Fig.14 In the characteristic estimation step S1002, the first characteristic 210 is estimated based on the saturation current Isat of the transistor portion 70, the capacitance Cox of the gate insulating film 42, and the set value of the channel length Lch, which is the length of the base region 14 and the gate trench portion 40 in the depth direction of the semiconductor substrate 10. In the characteristic estimation step S1002, the voltage value of the first voltage and the voltage value of the second voltage can be obtained.

[0175] The set value of the saturation current Isat can be determined according to the specifications that the semiconductor device 100 should meet. The set value of the capacitance Cox of the gate insulating film 42 can be calculated according to the shape such as the material and thickness of the gate insulating film 42 of the semiconductor device 100 to be manufactured. The set value of the channel length Lch can be calculated according to the thickness in the depth direction of the base region 14 in contact with the gate trench portion 40 in the semiconductor device 100 to be manufactured.

[0176] In the characteristic estimation step S1002, the first characteristic 210 may be estimated using equation (1). In the characteristic estimation step S1002, a first voltage (eg, 15 V) may be used as the gate voltage Vge in equation (1).

[0177] In the design step S1004, the on-voltage and threshold voltage of the semiconductor device 100 are determined based on the first characteristic 210. In the design step S1004, after determining the on-voltage that the semiconductor device 100 should meet, the threshold voltage corresponding to the on-voltage can be determined based on the first characteristic 210. In the design step S1004, the range of on-voltage that the semiconductor device 100 can obtain can be determined based on whether the semiconductor device 100 is an emitter orthogonal type or an emitter parallel type. In the design step S1004, the on-voltage can be determined within the range. In other examples, in the design step S1004, after determining the threshold voltage that the semiconductor device 100 should meet, the on-voltage corresponding to the threshold voltage can be determined based on the first characteristic 210.

[0178] In manufacturing step S1006, the semiconductor device 100 is manufactured in a manner that satisfies the determined on-voltage and threshold voltage. In manufacturing step S1006, the total channel width Z is determined based on the on-voltage. The relationship between the on-voltage and the total channel width Z can be calculated by simulation or can be determined in advance by experiment. The total channel width W per unit area can be determined in a manner that satisfies equation (8). E In manufacturing step S1006, the doping concentration Db of the base region 14 is determined based on the threshold voltage. The relationship between the threshold voltage and the doping concentration Db of the base region 14 can be calculated by simulation, or can be determined in advance by experiment. In manufacturing step S1006, the semiconductor device 100 is manufactured in such a way as to achieve the determined total channel width Z and doping concentration Db. Thus, it is possible to manufacture a semiconductor device 100 in which the on-voltage is reduced while maintaining or reducing the saturation current.

[0179] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various changes or improvements can be made to the above embodiments. According to the description of the claims, the method to which such changes or improvements are made can also be included in the technical scope of the present invention.

[0180] It should be noted that the execution order of each process such as actions, sequences, steps and stages in the apparatus, system, program and method shown in the claims, specifications and drawings can be implemented in any order unless it is specifically stated "before...", "in advance", etc., and the result of the previous process is not used in the subsequent process. Even if the action flow in the claims, specifications and drawings is described using "first", "next", etc. for convenience, it does not mean that it must be implemented in this order.

Claims

1. A semiconductor device, characterized in that: A semiconductor substrate having a portion that operates as a transistor, wherein the semiconductor substrate has an upper surface and a lower surface and is provided with a drift region of a first conductivity type, The transistor has: a gate trench portion having a gate conductive portion to which a gate voltage is applied and a gate insulating film surrounding the gate conductive portion; An emitter region of a first conductivity type, which is disposed in the semiconductor substrate so as to be exposed on the upper surface and is in contact with the gate trench portion; as well as A base region of the second conductivity type is disposed between the emitter region and the drift region and is in contact with the gate trench portion. When the transistor is turned on, a first voltage is applied to the gate trench portion as the gate voltage. When the ambient temperature is 25° C., a threshold voltage at which the transistor changes from an off state to an on state is greater than half of the first voltage.

2. The semiconductor device according to claim 1, wherein: The threshold voltage is greater than 55% of the first voltage.

3. The semiconductor device according to claim 1, wherein: The threshold voltage is greater than 60% of the first voltage.

4. The semiconductor device according to claim 1, wherein: The threshold voltage is greater than 70% of the first voltage.

5. The semiconductor device according to claim 1, wherein: When the transistor is turned off, a second voltage is applied to the gate trench portion. The threshold voltage is closer to the first voltage than an intermediate voltage between the first voltage and the second voltage.

6. The semiconductor device according to claim 5, wherein: A ratio of a difference between the threshold voltage and the second voltage to a difference between the first voltage and the second voltage is greater than or equal to 55%.

7. The semiconductor device according to claim 5, wherein: A ratio of a difference between the threshold voltage and the second voltage to a difference between the first voltage and the second voltage is greater than or equal to 60%.

8. The semiconductor device according to claim 5, wherein: A ratio of a difference between the threshold voltage and the second voltage to a difference between the first voltage and the second voltage is 70% or less.

9. The semiconductor device according to claim 5, wherein: The second voltage is 0V.

10. The semiconductor device according to claim 5, wherein: The second voltage is -15V.

11. The semiconductor device according to any one of claims 1 to 10, characterized in that A plurality of the gate trench portions are arranged side by side, Two dummy trench portions are arranged between the two gate trench portions.

12. The semiconductor device according to any one of claims 5 to 10, characterized in that The difference between the first voltage and the second voltage is set to Vge, whose unit is V, and the total length of the portion of the emitter region in contact with the gate trench portion per unit area, that is, the total emitter width is set to W. E , the unit is cm / cm 2 , and the threshold voltage is set to Vth, whose unit is V, the total emitter width W E Satisfy the following formula: 0.9×6.39×10 5 / (Vge+1.5-Vth) 2 ≤W E ≤1.1×6.39×10 5 / (Vge+1.5-Vth) 2 。 13. The semiconductor device according to any one of claims 1 to 10, characterized in that On the upper surface of the semiconductor substrate, the first direction of the gate trench portion is a length direction, The length of the emitting region in the first direction is longer than the length of the emitting region in a second direction orthogonal to the first direction.

14. The semiconductor device according to any one of claims 1 to 10, characterized in that The semiconductor device further includes a contact region of a second conductivity type, the contact region being provided in the semiconductor substrate so as to be exposed on the upper surface and being in contact with the gate trench portion. On the upper surface of the semiconductor substrate, the first direction of the gate trench portion is a length direction, At a position in contact with the gate trench portion, the emitter region and the contact region are alternately arranged along the first direction, At a position in contact with the gate trench portion, a length of the emitter region in the first direction is longer than a length of the contact region in the first direction.

15. The semiconductor device according to claim 14, wherein: At a position in contact with the gate trench portion, a length of the emitter region in the first direction is at least twice a length of the contact region in the first direction.

16. A semiconductor module, characterized in that: have: The semiconductor device according to claim 1; and A control unit applies the gate voltage to the semiconductor device.

17. A manufacturing method, characterized in that: A method for manufacturing a semiconductor device, wherein the semiconductor device includes a semiconductor substrate and a portion that operates as a transistor, wherein the semiconductor substrate has an upper surface and a lower surface and is provided with a drift region of a first conductivity type. The transistor has: a gate trench portion having a gate conductive portion to which a gate voltage is applied and a gate insulating film surrounding the gate conductive portion, wherein the first direction is a length direction; An emitter region of a first conductivity type, which is disposed in the semiconductor substrate so as to be exposed on the upper surface and is in contact with the gate trench portion; as well as A base region of the second conductivity type is disposed between the emitter region and the drift region and is in contact with the gate trench portion, In the manufacturing method, a first characteristic is estimated based on a saturation current of the transistor, a capacitance of the gate insulating film, and a set value of a channel length, the channel length being a length of the base region in contact with the gate trench portion in a depth direction of the semiconductor substrate, the first characteristic showing a relationship between an on-voltage of the transistor and a threshold voltage of the transistor at the set value of the saturation current, determining the on-voltage and the threshold voltage based on the first characteristic, The semiconductor device is manufactured in such a manner that the determined on-voltage and the threshold voltage are satisfied.

18. The manufacturing method according to claim 17, characterized in that: The on-voltage is determined, and the threshold voltage corresponding to the on-voltage is determined based on the first characteristic.

19. The manufacturing method according to claim 17, characterized in that: The threshold voltage is determined, and the turn-on voltage corresponding to the threshold voltage is determined based on the first characteristic.

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