Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, and the method comprises the steps: forming a mask layer with an opening in a preset region on a semiconductor layer, and carrying out the anisotropic etching of the semiconductor layer based on the mask layer, so as to obtain a first groove with a linear side wall; an insulating protection layer is formed on the side wall of the first groove, isotropic etching is carried out on the semiconductor layer to obtain a second groove which is located below the first groove and connected with the first groove, the second groove is provided with a rounded side wall and a rounded bottom wall, and the maximum transverse width of the second groove is larger than that of the first groove; forming an insulating filling layer in the first groove and the second groove; when the isolation groove is formed, anisotropic etching is carried out firstly and then isotropic etching is carried out, on one hand, the bottom area of the isolation structure can be increased, the carrier path is prolonged, the divided voltage is larger, and the method is more suitable for a high-voltage device, and on the other hand, the bottom of the isolation region is rounded, and easy breakdown caused by sharp corners can be prevented.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors and relates to a semiconductor device and a manufacturing method thereof. Background Art

[0002] In order to improve the pressure-bearing capacity of the device, the prior art proposes a lateral drift metal oxide semiconductor (LDMOS) transistor, the structure of which includes: a first well region and a second well region located in a substrate, the first well region and the second well region having different conductive ion types, and a gate structure located on the first well region and the second well region; a source-end doping layer and a drain-end doping layer respectively located in the substrate on both sides of the gate structure, the drain-end doping layer being located in the second well region, the source-end doping layer being located in the first well region, the source-end doping layer and the drain-end doping layer having source and drain ions, and the source-drain ion conductivity type is the same as the well ion conductivity type of the first well region.

[0003] Usually, an isolation region is provided between the gate structure and the drain-doped layer. The path for the carriers of the drain-doped layer to reach the gate structure needs to bypass the isolation region. When a drain voltage is applied to the drain-doped layer, the path for the carriers generated by the drain voltage to reach the gate structure via the second well region also becomes longer. The longer the path, the more carriers generated by the drain voltage are neutralized, thereby reducing the number of drain carriers reaching the gate structure and the potential generated by the drain carriers, thereby achieving voltage division of the drain voltage.

[0004] The device isolation area in the prior art has the following problems:

[0005] (1) There are limited ways to increase the voltage division of the drain voltage. In order to increase the source-drain breakdown voltage BV, the distance between the drain contact hole and the polysilicon gate needs to be increased, which makes the lateral size of the device larger, which is not in line with the trend of miniaturization of semiconductor devices and does not meet the application requirements in high-voltage devices.

[0006] (2) The bottom of the isolation region is relatively sharp, which causes the electric field to be easily concentrated at the sharp corners, making it easy for breakdown to occur, thereby reducing the breakdown voltage of the LDMOS device.

[0007] Therefore, how to provide a semiconductor device and a method for manufacturing the same to increase the voltage division of the isolation region and improve the breakdown voltage of the device while maintaining a relatively small lateral size of the device has become an important technical problem that needs to be solved urgently by those skilled in the art. Summary of the invention

[0008] In view of the shortcomings of the prior art described above, an object of the present invention is to provide a semiconductor device and a method for manufacturing the same, so as to solve the problem in the prior art that it is difficult to improve the voltage withstand capability of the device without increasing the lateral size of the device and / or the problem that the voltage withstand capability of the device is reduced due to the sharp corners of the isolation structure that easily lead to tip discharge.

[0009] To achieve the above object and other related objects, the present invention provides a method for manufacturing a semiconductor device, comprising the following steps:

[0010] Providing a semiconductor layer, forming a mask layer on the semiconductor layer, wherein the mask layer has an opening in a preset area;

[0011] Anisotropically etching the semiconductor layer based on the mask layer to obtain a first trench in the semiconductor layer, wherein the first trench has a straight sidewall;

[0012] forming an insulating protection layer on the sidewalls of the first trench;

[0013] isotropically etching the semiconductor layer based on the mask layer and the insulating protection layer to obtain a second trench in the semiconductor layer, wherein the second trench is located below the first trench and connected to the first trench, the second trench has a rounded sidewall and a rounded bottom wall, and the maximum lateral width of the second trench is greater than the maximum lateral width of the first trench;

[0014] An insulating filling layer is formed in the first trench and the second trench.

[0015] Optionally, before forming an insulating filling layer in the first trench and the second trench, the method further includes the following steps: performing inversion ion implantation in the semiconductor layer at the bottom of the second trench to form an inversion bottom doping layer.

[0016] Optionally, after forming an insulating filling layer in the first trench and the second trench, the method further includes the following steps:

[0017] Etching back the insulating filling layer and the insulating protection layer to expose a portion of the sidewall of the first trench;

[0018] isotropically etching the semiconductor layer based on the mask layer to obtain a third trench in the semiconductor layer, wherein the third trench extends laterally from the exposed sidewall of the first trench into the semiconductor layer, and the third trench has a rounded sidewall;

[0019] Filling the third trench and the first trench with an insulating material.

[0020] Optionally, the straight sidewall is perpendicular to the plane where the semiconductor layer is located; or the straight sidewall is inclined relative to the plane where the semiconductor layer is located, and an angle between the straight sidewall and the normal to the plane where the semiconductor layer is located is less than 10°.

[0021] Optionally, the insulating protection layer and the insulating filling layer are made of the same material.

[0022] Optionally, the semiconductor layer includes a first conductive type substrate and a second conductive type drift region located in the first conductive type substrate, the second conductive type drift region starts from the upper surface of the first conductive type substrate and extends downward, the first trench and the second trench are located in the second conductive type drift region, the first conductive type is P type or N type, and the second conductive type is opposite to the first conductive type.

[0023] Optionally, the semiconductor device includes LDMOS, and the manufacturing method further includes the following steps:

[0024] Forming a first conductive type body region in the first conductive type substrate, the first conductive type body region starting from the upper surface of the first conductive type substrate and extending downward, the first conductive type body region being located at one side of the second conductive type drift region and adjacent to the second conductive type drift region, and the bottom surface of the first conductive type body region being higher than the bottom surface of the second conductive type drift region;

[0025] forming a second conductive type source region and a second conductive type drain region, wherein the second conductive type source region is located on the upper surface layer of the first conductive type body region and is spaced apart from the second conductive type drift region by a preset distance, and the second conductive type drain region is located on the upper surface layer of the second conductive type drift region and is located on a side of the first trench away from the second conductive type source region and is spaced apart from the first trench by a preset distance;

[0026] A gate structure is formed on the substrate, wherein a main portion of the gate structure is located between the second conductive type source region and the first trench.

[0027] The present invention also provides a semiconductor device, comprising:

[0028] Semiconductor layer;

[0029] An isolation structure is located in the semiconductor layer, and the isolation structure includes a first isolation part and a second isolation part, the first isolation part has a straight side wall, the second isolation part is located below the first isolation part and connected to the first isolation part, the second isolation part has a rounded side wall and a rounded bottom wall, and the maximum lateral width of the second isolation part is greater than the maximum lateral width of the first isolation part.

[0030] Optionally, the semiconductor device further includes an inversion bottom doping layer, wherein the inversion bottom doping layer is located below the isolation structure and connected to the second isolation portion.

[0031] Optionally, the isolation structure further includes a third isolation portion, which is located above the first isolation portion and connected to the first isolation portion, the third isolation portion has a rounded sidewall, and the maximum lateral width of the third isolation portion is greater than the maximum lateral width of the first isolation portion.

[0032] Optionally, the semiconductor layer includes a first conductive type substrate and a second conductive type drift region located in the first conductive type substrate, the second conductive type drift region starts from the upper surface of the first conductive type substrate and extends downward, the first trench and the second trench are located in the second conductive type drift region, the first conductive type is P type or N type, and the second conductive type is opposite to the first conductive type.

[0033] Optionally, the semiconductor device includes an LDMOS, and the LDMOS includes:

[0034] a first conductive type body region, located in the first conductive type substrate, the first conductive type body region starting from the upper surface of the first conductive type substrate and extending downward, the first conductive type body region being located at one side of the second conductive type drift region and adjacent to the second conductive type drift region, and the bottom surface of the first conductive type body region being higher than the bottom surface of the second conductive type drift region;

[0035] A second conductive type source region, located on an upper surface layer of the first conductive type body region and spaced apart from the second conductive type drift region by a preset distance;

[0036] A second conductive type drain region, located on an upper surface layer of the second conductive type drift region and located on a side of the first trench away from the second conductive type source region and spaced a preset distance from the first trench;

[0037] A gate structure is located on the substrate, and a main portion of the gate structure is located between the second conductive type source region and the first trench.

[0038] As described above, the manufacturing method of the semiconductor device of the present invention includes the following steps: providing a semiconductor layer, forming a mask layer on the semiconductor layer, the mask layer having an opening in a preset area; anisotropically etching the semiconductor layer based on the mask layer to obtain a first groove in the semiconductor layer, the first groove having a straight sidewall; forming an insulating protection layer on the sidewall of the first groove; isotropically etching the semiconductor layer based on the mask layer and the insulating protection layer to obtain a second groove in the semiconductor layer, the second groove is located below the first groove and connected to the first groove, the second groove has a rounded sidewall and a rounded bottom wall, and the maximum lateral width of the second groove is greater than the maximum lateral width of the first groove; forming an insulating filling layer in the first groove and the second groove. In the manufacturing method of the present invention, when forming the isolation groove, anisotropic etching is first performed and then isotropic etching is performed, which can increase the bottom area of ​​the isolation structure on the one hand, extend the carrier path, thereby increasing the voltage division, and is more suitable for high-voltage devices, and on the other hand, rounding the bottom of the isolation area can prevent easy breakdown caused by sharp corners. The semiconductor device of the present invention can obtain a larger source-drain breakdown voltage (BV) when the lateral size of the device is small, which is beneficial to the application of the device under high voltage. The bottom rounded area of ​​the isolation area can eliminate the problem of current and electric field concentration caused by the bottom sharp corner, thereby achieving uniform distribution of current and electric field at the bottom, and can also make the impact ionization zone of the device evenly distributed and improve the breakdown voltage of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 The process flow chart of the method for manufacturing a semiconductor device of the present invention is shown.

[0040] Figure 2 The schematic diagram shows a structure obtained after a mask layer with an opening is formed on a semiconductor layer according to the method for manufacturing a semiconductor device of the present invention.

[0041] Figure 3 The schematic diagram shows the structure obtained after the method for manufacturing a semiconductor device of the present invention performs anisotropic etching on the semiconductor layer based on the mask layer to obtain a first trench in the semiconductor layer.

[0042] Figure 4 It is a schematic diagram showing the structure obtained after depositing an insulating protection layer on the inner wall of the first trench and the upper surface of the mask layer in the method for manufacturing a semiconductor device of the present invention.

[0043] Figure 5 It is a schematic diagram showing the structure obtained after removing the portion of the insulating protection layer located on the bottom wall of the first trench and the portion located on the upper surface of the mask layer according to the method for manufacturing the semiconductor device of the present invention.

[0044] Figure 6The schematic diagram of the structure obtained after the semiconductor layer 101 is isotropically etched based on the mask layer and the insulating protection layer to obtain a second trench in the semiconductor layer according to the method for manufacturing the semiconductor device of the present invention.

[0045] Figure 7 It is a schematic diagram showing the structure obtained after performing inversion ion implantation in the semiconductor layer at the bottom of the second trench to form an inversion bottom doping layer in the method for manufacturing a semiconductor device of the present invention.

[0046] Figure 8 The schematic diagram shows the structure obtained after the insulating filling layer is formed in the first trench and the second trench according to the manufacturing method of the semiconductor device of the present invention.

[0047] Fig. 9 It is a schematic diagram showing the structure obtained after removing the mask layer in the method for manufacturing a semiconductor device of the present invention.

[0048] Fig.10 It is a schematic diagram showing the structure obtained after etching back the insulating filling layer and the insulating protection layer to expose a portion of the sidewall of the first trench in the method for manufacturing the semiconductor device of the present invention.

[0049] Fig.11 The schematic diagram shows the structure obtained after the method for manufacturing a semiconductor device of the present invention is based on isotropic etching of the semiconductor layer through a mask layer to obtain a third trench in the semiconductor layer.

[0050] Fig.12 It is a schematic diagram showing the structure obtained after the insulating material is filled into the third trench and the first trench according to the manufacturing method of the semiconductor device of the present invention.

[0051] Fig.13 It is a schematic diagram showing the structure obtained after removing the mask layer in the method for manufacturing a semiconductor device of the present invention.

[0052] Fig.14 Shown is a schematic diagram of an LDMOS structure manufactured by the method for manufacturing a semiconductor device of the present invention.

[0053] Description of Reference Numerals

[0054] Steps S1 to S5 101 Semiconductor layer

[0055] 1011 first conductive type substrate

[0056] 1012 second conductivity type drift region

[0057] 102 Mask layer

[0058] 103 Opening

[0059] 104 First Groove

[0060] 105 Insulation protective layer

[0061] 106 Second Groove

[0062] 107 Inversion bottom doping layer

[0063] 108 Insulation filling layer

[0064] 109 Third Groove

[0065] 110 Insulation material

[0066] 111 First conductivity type body region

[0067] 112 second conductivity type source region

[0068] 113 Second conductivity type drain region

[0069] 114 Gate Structure

[0070] 114a Gate dielectric layer

[0071] 114b gate conductive layer

[0072] 115 Isolation Structure DETAILED DESCRIPTION

[0073] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0074] See also Figures 1 to 14 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0075] The present invention provides a method for manufacturing a semiconductor device. Figure 1 , shown as a process flow chart of the method, comprising the following steps:

[0076] S1: providing a semiconductor layer, and forming a mask layer on the semiconductor layer, wherein the mask layer has an opening in a preset area;

[0077] S2: performing anisotropic etching on the semiconductor layer based on the mask layer to obtain a first trench in the semiconductor layer, wherein the first trench has a straight sidewall;

[0078] S3: forming an insulating protection layer on the sidewalls of the first trench;

[0079] S4: isotropically etching the semiconductor layer based on the mask layer and the insulating protection layer to obtain a second trench in the semiconductor layer, wherein the second trench is located below the first trench and connected to the first trench, the second trench has a rounded sidewall and a rounded bottom wall, and the maximum lateral width of the second trench is greater than the maximum lateral width of the first trench;

[0080] S5: forming an insulating filling layer in the first trench and the second trench.

[0081] Combine the following Figures 2 to 14 Each step of the method for manufacturing a semiconductor device of the present invention is described in detail.

[0082] First see Figure 2 , perform the step S1: provide a semiconductor layer 101, form a mask layer 102 on the semiconductor layer 101, and the mask layer 102 has an opening 103 in a preset area.

[0083] As an example, the material of the semiconductor layer 101 may be silicon, silicon carbide or other suitable semiconductor materials. One or more doping regions may be prefabricated in the semiconductor layer 101 as required.

[0084] As an example, the mask layer 102 may include a silicon nitride layer or other suitable material layer, and the opening 103 may be formed by a patterning process such as photolithography and etching.

[0085] Please see again Figure 3 , performing the step S2: performing anisotropic etching on the semiconductor layer 101 based on the mask layer 102 to obtain a first trench 104 in the semiconductor layer 101, wherein the first trench 104 has a straight sidewall.

[0086] As an example, the anisotropic etching includes dry etching.

[0087] As an example, the straight side wall can be perpendicular to the plane where the semiconductor layer 101 is located, or can be inclined relative to the plane where the semiconductor layer 101 is located. When the straight side wall is inclined relative to the plane where the semiconductor layer 101 is located, the angle between the straight side wall and the normal to the plane where the semiconductor layer is located is less than 10°.

[0088] Please see again Figure 4 and Figure 5 , executing the step S3: forming an insulating protection layer 105 on the sidewall of the first trench 104 by chemical vapor deposition, physical vapor deposition or other suitable methods.

[0089] As an example, Figure 4 As shown, the insulating protection layer 105 is first deposited on the inner wall of the first trench 104 and the upper surface of the mask layer 102, and then Figure 5 As shown, the portion of the insulating protection layer 105 located on the bottom wall of the first trench 104 is removed, and the portion of the insulating protection layer 105 located on the side wall of the first trench 104 is retained to protect the side wall of the first trench 104 from being etched in the subsequent etching process.

[0090] As an example, while removing the portion of the insulating protection layer 105 located on the bottom wall of the first trench 104, the portion of the insulating protection layer 105 located on the upper surface of the mask layer 102 may be removed or retained as needed. Figure 5 What is presented is a situation where the portion of the insulating protection layer 105 located on the upper surface of the mask layer 102 is removed.

[0091] As an example, the material of the insulating protection layer 105 may be silicon oxide or other suitable insulating materials, and the method of removing the portion of the insulating protection layer 105 located on the bottom wall of the first trench 104 may include dry etching.

[0092] Please see again Figure 6 , execute the step S4: based on the mask layer 102 and the insulating protection layer 105, the semiconductor layer 101 is isotropically etched to obtain a second groove 106 in the semiconductor layer 101, the second groove 106 is located below the first groove 104 and connected to the first groove 104, the second groove 106 has a rounded side wall and a rounded bottom wall, and the maximum lateral width of the second groove 106 is greater than the maximum lateral width of the first groove 104.

[0093] As an example, the method for implementing the isotropic etching includes wet etching, and the specific formula of the etching solution can be prepared according to the material of the semiconductor layer 101, the required etching rate, etc.

[0094] Since the second trench 106 has a larger maximum lateral width (relative to the first trench 104), the bottom area of ​​the isolation region can be further expanded, so that the carrier path is extended, thereby increasing the voltage division and being more suitable for high-voltage devices. In addition, the second trench 106 has rounded sidewalls and a rounded bottom wall, which can effectively prevent easy breakdown caused by sharp corners of the isolation structure.

[0095] In one embodiment, after the second trench 106 is formed, a subsequent insulating filling layer forming step may be performed.

[0096] In another embodiment, see Figure 7 Alternatively, before the insulating filling layer is formed, inversion ion implantation may be performed in the semiconductor layer 101 at the bottom of the second trench 106 to form an inversion bottom doping layer 107 .

[0097] Specifically, during the ion implantation process, the mask layer 102 having the opening 103 and the insulating protection layer 105 located on the sidewalls of the first trench 104 are used as masks for ion implantation, so that ion implantation is performed only around the rounded bottom of the second trench 106, and no ion implantation occurs on the sidewalls of the isolation area trench formed by the first trench 104 and the second trench 106, which will further increase the carrier path.

[0098] Please see again Figure 8 , executing the step S5: forming an insulating filling layer 108 in the first trench 104 and the second trench 106 by chemical vapor deposition, physical vapor deposition or other suitable methods.

[0099] As an example, the insulating filling layer 108 and the insulating protection layer 105 may be made of the same material or different materials. Preferably, the insulating filling layer 108 and the insulating protection layer 105 are made of the same material, such as silicon oxide, because on the one hand, stratification is not easy to occur, and on the other hand, for the etching back scheme described later, the same material is conducive to the control of the etching back degree.

[0100] In one embodiment, see Fig. 9 , further comprising the step of removing the mask layer 102, wherein a portion of the insulating filling layer 108 that is higher than the upper surface of the semiconductor layer 101 is also removed.

[0101] At this point, a semiconductor device is manufactured, the semiconductor device includes a semiconductor layer 101 and an isolation structure located in the semiconductor layer 101, the isolation structure includes a first isolation portion (a portion located in the first trench 104) and a second isolation portion (a portion located in the second trench 106), the first isolation portion has a straight sidewall, the second isolation portion is located below the first isolation portion and connected to the first isolation portion, the second isolation portion has a rounded sidewall and a rounded bottom wall, and the maximum lateral width of the second isolation portion is greater than the maximum lateral width of the first isolation portion. In some embodiments, the semiconductor device further includes an inverted bottom doped layer 107, the inverted bottom doped layer 107 is located below the isolation structure and connected to the second isolation portion.

[0102] Specifically, the isolation structure in the semiconductor device has the advantages of a large surface area, a long voltage-dividing path, and no sharp corners, which is beneficial to improving the voltage-withstanding performance of the semiconductor device.

[0103] As an example, in order to further improve the withstand voltage performance of the semiconductor device, in another embodiment, after forming the insulating filling layer 108, the mask layer 102 may not be removed, but the mask layer 102 may be used for back etching, and then the insulating material may be filled after isotropic etching. This method further increases the carrier path and enhances the voltage division effect on the one hand, and increases the isolation effect of the isolation area on the other hand, and the entire process is completed using the same mask, which can reduce the process difficulty and cost.

[0104] Combine the following Figure 10-13 Describe the key steps of the program in detail:

[0105] First see Fig.10 ,exist Figure 8 On the basis of the structure shown, the insulating filling layer 108 and the insulating protection layer 105 are etched back to expose a portion of the sidewall of the first trench 104 .

[0106] Specifically, the depth of the back etching is less than the depth of the first groove 104 . The specific degree of the back etching can be adjusted as needed and is not excessively limited here.

[0107] Please see again Fig.11 Based on the mask layer 102, the semiconductor layer 101 is isotropically etched to obtain a third trench 109 in the semiconductor layer 101. The third trench 109 extends laterally from the exposed sidewall of the first trench 104 into the semiconductor layer 101. The third trench 109 has a rounded sidewall.

[0108] Specifically, similar to step S4, the method for implementing the isotropic etching includes wet etching, and the specific formula of the etching solution can be prepared according to the material of the semiconductor layer 101, the required etching rate, etc.

[0109] Please see again Fig.12 , filling the insulating material 110 in the third trench 109 and the first trench 104 by chemical vapor deposition, physical vapor deposition or other suitable methods.

[0110] As an example, the insulating material 110 and the insulating filling layer 108 are made of the same material, such as silicon oxide.

[0111] Please see again Fig.13, the mask layer 102 is removed, wherein the portion of the insulating material 110 that is higher than the upper surface of the semiconductor layer 101 is also removed.

[0112] At this point, a semiconductor device is manufactured, which includes a semiconductor layer 101 and an isolation structure located in the semiconductor layer 101, wherein the isolation structure includes a first isolation portion (a portion located in the lower section of the first trench 104), a second isolation portion (a portion located in the second trench 106) and a third isolation portion (a portion located in the upper section of the first trench 104), wherein the first isolation portion has a straight sidewall, the second isolation portion is located below the first isolation portion and connected to the first isolation portion, the second isolation portion has a rounded sidewall and a rounded bottom wall, the maximum lateral width of the second isolation portion is greater than the maximum lateral width of the first isolation portion, the third isolation portion is located above the first isolation portion and connected to the first isolation portion, the third isolation portion has a rounded sidewall, and the maximum lateral width of the third isolation portion is greater than the maximum lateral width of the first isolation portion. In some embodiments, the semiconductor device further includes an inverted bottom doped layer 107, wherein the inverted bottom doped layer 107 is located below the isolation structure and connected to the second isolation portion.

[0113] Specifically, relative to Fig. 9 The isolation structure shown in Fig.13 The isolation structure shown in has a stronger voltage division effect and a better isolation effect.

[0114] It should be noted that the method for manufacturing a semiconductor device of the present invention is applicable to the manufacture of a lateral drift metal oxide semiconductor (LDMOS) transistor or other types of power devices.

[0115] As an example, see Fig.14 In these devices, the semiconductor layer 101 includes a first conductive type substrate 1011 and a second conductive type drift region 1012 located in the first conductive type substrate 1011, the second conductive type drift region 1012 starts from the upper surface of the first conductive type substrate 1011 and extends downward, the first trench 104 and the second trench 106 are located in the second conductive type drift region 1012, the first conductive type is P type or N type, and the second conductive type is opposite to the first conductive type.

[0116] An application example of the method for manufacturing a semiconductor device of the present invention is described below by taking LDMOS as an example, wherein after forming the isolation structure 115, the following steps are further included:

[0117] (1) Please continue reading Fig.14A first conductive type body region 111 is formed in the first conductive type substrate 1011 by ion implantation or other suitable methods. The first conductive type body region 111 starts from the upper surface of the first conductive type substrate 1011 and extends downward. The first conductive type body region 111 is located on one side of the second conductive type drift region 1012 and is adjacent to the second conductive type drift region 1012.

[0118] (2) Ion implantation or other suitable methods are used to form a second conductive type source region 112 and a second conductive type drain region 113, wherein the second conductive type source region 112 is located on the upper surface layer of the first conductive type body region 111 and is separated from the second conductive type drift region 1012 by a preset distance, and the second conductive type drain region 113 is located on the upper surface layer of the second conductive type drift region 1012 and is located on the side of the first trench 104 away from the second conductive type source region 112 and is separated from the first trench 104 by a preset distance.

[0119] (3) forming a gate structure 114 on the substrate, wherein a main portion of the gate structure 114 is located between the second conductivity type source region 112 and the first trench 104 .

[0120] In some embodiments, one end of the gate structure 114 may just connect with the second conductive type source region 112 , or a portion may extend horizontally above the second conductive type source region 112 , and the other end of the gate structure 114 may just connect with the first trench 104 , or a portion may extend horizontally above the first trench 104 .

[0121] As an example, the gate structure 114 includes a gate dielectric layer 114a and a gate conductive layer 114b located on the gate dielectric layer 114a. The gate dielectric layer 114a may be made of silicon oxide or other suitable dielectric materials, and the gate conductive layer 114b may be made of polysilicon or other suitable materials.

[0122] Specifically, in the above-mentioned LDMOS structure, the isolation trench is formed by an isotropic + anisotropic etching process, and the surface area of ​​the trench is large, so that the isolation structure 115 located therein also has a larger surface area, and the voltage division path becomes longer, so that the number of drain carriers reaching the gate structure is reduced, and the potential generated by the drain carriers is reduced, thereby achieving voltage division of the drain voltage.

[0123] It should be pointed out that, depending on the specific process, Fig.14 The insulating material constituting the isolation structure 115 may be filled in stages or in one go, for example, Figure 8In the case shown, the isolation structure 115 includes the insulating protection layer 105 and the insulating filling layer 108, that is, the formation of the insulating material constituting the isolation structure 115 includes at least two deposition processes. Fig.12 In the illustrated case, the isolation structure 115 includes the insulating protection layer 105, the insulating filling layer 108 and the insulating material 110. That is, the formation of the insulating material constituting the isolation structure 115 includes at least three deposition processes. These insulating materials deposited in multiple times can be made of the same material, or different materials can be used as needed. When these insulating materials deposited in multiple times are made of the same material, the isolation structure 115 may not have a visible boundary, for example Fig.14 The isolation structure 115 is in an integrated form. Of course, in other embodiments, the insulating material constituting the isolation structure 115 can also be filled at one time, for example, by adjusting Figure 8 In the process of the corresponding embodiment, before forming the insulating filling layer 108 in the first groove 104 and the second groove 106, the insulating protection layer 105 located on the side wall of the first groove 104 is first removed, so that the insulating filling layer 108 deposited subsequently will constitute the entire filling part of the isolation structure 115, that is, the insulating material constituting the isolation structure 115 is integrated.

[0124] As an example, Fig.14 The arrows are used to show the carrier path. When a drain voltage is applied to the drain region, the carriers generated by the drain voltage travel along the side walls of the upper part of the isolation region, the arc side walls of the lower part of the isolation region, and around the bottom inversion doped region, so that the carrier path becomes longer. The longer the path, the more carriers generated by the drain voltage are neutralized, resulting in more voltage division, thereby improving the voltage resistance of the semiconductor device.

[0125] The present invention can obtain a larger source-drain breakdown voltage (BV) when the lateral size of the device is small, which is beneficial to the application of the device under high voltage. The bottom rounded area of ​​the isolation area can eliminate the problem of current and electric field concentration caused by the bottom sharp corner, thereby achieving uniform distribution of current and electric field at the bottom, and can also make the impact ionization zone of the device evenly distributed and improve the breakdown voltage of the device.

[0126] In summary, the manufacturing method of the semiconductor device of the present invention includes the following steps: providing a semiconductor layer, forming a mask layer on the semiconductor layer, the mask layer having an opening in a preset area; anisotropically etching the semiconductor layer based on the mask layer to obtain a first groove in the semiconductor layer, the first groove having a straight sidewall; forming an insulating protection layer on the sidewall of the first groove; isotropically etching the semiconductor layer based on the mask layer and the insulating protection layer to obtain a second groove in the semiconductor layer, the second groove is located below the first groove and connected to the first groove, the second groove has a rounded sidewall and a rounded bottom wall, and the maximum lateral width of the second groove is greater than the maximum lateral width of the first groove; forming an insulating filling layer in the first groove and the second groove; removing the mask layer. In the manufacturing method of the present invention, when forming the isolation groove, anisotropic etching is first performed and then isotropic etching is performed, which can increase the bottom area of ​​the isolation structure on the one hand, extend the carrier path, thereby increasing the voltage division, and is more suitable for high-voltage devices, and on the other hand, rounding the bottom of the isolation area can prevent easy breakdown caused by sharp corners. The semiconductor device of the present invention can obtain a larger source-drain breakdown voltage (BV) when the device has a smaller lateral size, which is beneficial to the application of the device under high voltage. The bottom rounded area of ​​the isolation area can eliminate the problem of current and electric field concentration caused by the bottom sharp corner, thereby achieving uniform distribution of the current and electric field at the bottom, and also making the impact ionization area of ​​the device evenly distributed and improving the breakdown voltage of the device. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0127] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The following steps are involved: Providing a semiconductor layer, forming a mask layer on the semiconductor layer, wherein the mask layer has an opening in a preset area; Anisotropically etching the semiconductor layer based on the mask layer to obtain a first trench in the semiconductor layer, wherein the first trench has a straight sidewall; forming an insulating protection layer on the sidewalls of the first trench; isotropically etching the semiconductor layer based on the mask layer and the insulating protection layer to obtain a second trench in the semiconductor layer, wherein the second trench is located below the first trench and connected to the first trench, the second trench has a rounded sidewall and a rounded bottom wall, and the maximum lateral width of the second trench is greater than the maximum lateral width of the first trench; An insulating filling layer is formed in the first trench and the second trench.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: Before forming an insulating filling layer in the first trench and the second trench, the method further includes the following steps: performing inversion ion implantation in the semiconductor layer at the bottom of the second trench to form an inversion bottom doping layer.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: After forming an insulating filling layer in the first trench and the second trench, the method further includes the following steps: Etching back the insulating filling layer and the insulating protection layer to expose a portion of the sidewall of the first trench; isotropically etching the semiconductor layer based on the mask layer to obtain a third trench in the semiconductor layer, wherein the third trench extends laterally from the exposed sidewall of the first trench into the semiconductor layer, and the third trench has a rounded sidewall; Filling the third trench and the first trench with an insulating material.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: The straight side wall is perpendicular to the plane where the semiconductor layer is located; or the straight side wall is inclined relative to the plane where the semiconductor layer is located, and the angle between the straight side wall and the normal line of the plane where the semiconductor layer is located is less than 10°.

5. The method for manufacturing a semiconductor device according to any one of claim 1, characterized in that: The insulating protection layer and the insulating filling layer are made of the same material.

6. The method for manufacturing a semiconductor device according to any one of claims 1 to 5, characterized in that: The semiconductor layer includes a first conductive type substrate and a second conductive type drift region located in the first conductive type substrate, the second conductive type drift region starts from the upper surface of the first conductive type substrate and extends downward, the first trench and the second trench are located in the second conductive type drift region, the first conductive type is P type or N type, and the second conductive type is opposite to the first conductive type.

7. The method for manufacturing a semiconductor device according to claim 6, wherein: The semiconductor device comprises LDMOS, and the manufacturing method further comprises the following steps: Forming a first conductive type body region in the first conductive type substrate, the first conductive type body region starting from the upper surface of the first conductive type substrate and extending downward, the first conductive type body region being located at one side of the second conductive type drift region and adjacent to the second conductive type drift region, and the bottom surface of the first conductive type body region being higher than the bottom surface of the second conductive type drift region; forming a second conductive type source region and a second conductive type drain region, wherein the second conductive type source region is located on the upper surface layer of the first conductive type body region and is spaced apart from the second conductive type drift region by a preset distance, and the second conductive type drain region is located on the upper surface layer of the second conductive type drift region and is located on a side of the first trench away from the second conductive type source region and is spaced apart from the first trench by a preset distance; A gate structure is formed on the substrate, wherein a main portion of the gate structure is located between the second conductive type source region and the first trench.

8. A semiconductor device, characterized in that: include: Semiconductor layer; An isolation structure is located in the semiconductor layer, and the isolation structure includes a first isolation part and a second isolation part, the first isolation part has a straight side wall, the second isolation part is located below the first isolation part and connected to the first isolation part, the second isolation part has a rounded side wall and a rounded bottom wall, and the maximum lateral width of the second isolation part is greater than the maximum lateral width of the first isolation part.

9. The semiconductor device according to claim 8, characterized in that: The semiconductor device further includes an inversion bottom doping layer, which is located below the isolation structure and connected to the second isolation portion.

10. The semiconductor device according to claim 8, wherein: The isolation structure also includes a third isolation portion, which is located above the first isolation portion and connected to the first isolation portion. The third isolation portion has a rounded sidewall, and the maximum lateral width of the third isolation portion is greater than the maximum lateral width of the first isolation portion.

11. The semiconductor device according to any one of claims 8 to 10, characterized in that: The semiconductor layer includes a first conductive type substrate and a second conductive type drift region located in the first conductive type substrate, the second conductive type drift region starts from the upper surface of the first conductive type substrate and extends downward, the first trench and the second trench are located in the second conductive type drift region, the first conductive type is P type or N type, and the second conductive type is opposite to the first conductive type.

12. The semiconductor device according to claim 11, characterized in that The semiconductor device comprises an LDMOS, and the LDMOS comprises: A first conductive type body region is located in the first conductive type substrate, the first conductive type body region starts from the upper surface of the first conductive type substrate and extends downward, the first conductive type body region is located on one side of the second conductive type drift region and is adjacent to the second conductive type drift region, and the bottom surface of the first conductive type body region is higher than the a bottom surface of the second conductivity type drift region; A second conductive type source region, located on an upper surface layer of the first conductive type body region and spaced a preset distance from the second conductive type drift region; A second conductive type drain region, located on an upper surface layer of the second conductive type drift region and located on a side of the first trench away from the second conductive type source region and spaced a preset distance from the first trench; A gate structure is located on the substrate, and a main portion of the gate structure is located between the second conductive type source region and the first trench.

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