Strain silicon channel MOS device with SOI structure and preparation method thereof
By introducing dual -axis and single -axis stress in the SOI structure of the MOS device, the current MOS device's anti -radiation resistance ability and insufficient load migration rate have been solved, and the performance of the device is significantly improved.
Patent Information
- Application Number
- CN202411469929.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-21
- Publication Date
- 2025-01-28
AI Technical Summary
Current MOS devices have small radiation resistance and carrier mobility, resulting in poor device performance.
The MOS device with a SOI structure with SOI structure is used to set up a large strain silicon layer with different sidelines on the surface area on the surface of the SOI substrate to introduce dual -axis stress on the surface of the surface, and set the density insulation on the surface of the device. The film is introduced to the introduction of single -axis stress to improve the migration rate of carriers.
Through the composite effects of single -axis stress and dual axis stress, the migration rate of load is significantly improved, and the anti -radiation capacity and overall performance of the device are improved.
Smart Images
Figure CN119384007A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a strained silicon channel MOS device with an SOI structure and a preparation method thereof. Background Art
[0002] With the development of integrated circuits in the field of space applications and the limitations of Moore's Law, the radiation hardening technology of electronic devices and the manufacturing process of nanodevices have been constantly advancing. Under irradiation conditions, electronic components will produce a variety of radiation effects such as total dose, single particles, and transient radiation, which will reduce the performance of the device. In addition, as the feature size of the device decreases, the short channel effect becomes more and more obvious. At low feature sizes, parasitic effects such as device surface scattering, drain-induced barrier reduction and punch-through, impact ionization, and hot carriers become more and more obvious, causing the degradation of the device's electrical performance, which poses a challenge to the continuous improvement of device performance.
[0003] Some new technologies have emerged in nano-IC design to continue Moore's Law and improve the radiation resistance of devices, such as multi-gate structure, Silicon-On-Insulator (SOI) structure, strained silicon, etc. Among them, strained silicon technology is widely used in integrated circuits due to its simple process, better compatibility with traditional silicon process, and high mobility.
[0004] However, the redundant doping anti-radiation technology used in the preparation of the current strained silicon structure MOS device makes the MOS device only have the ability to resist total dose radiation, and the metal silicide strain introduction technology used can only introduce a single type of stress into the MOS device, making the radiation resistance and carrier mobility of the current MOS device small, thereby making the performance of the current MOS device poor. Summary of the invention
[0005] The embodiment of the present invention provides a strained silicon channel MOS device with an SOI structure and a preparation method thereof, which can solve the problems of low radiation resistance and carrier mobility and poor device performance of current MOS devices.
[0006] In a first aspect, an embodiment of the present invention provides a strained silicon channel MOS device of an SOI structure, comprising:
[0007] SOI substrate;
[0008] A strained silicon layer, the strained silicon layer is disposed on the upper surface of the SOI substrate, wherein the lattice constant of the material of the strained silicon layer is different from the lattice constant of the material of the upper surface of the SOI substrate;
[0009] A silicon cap layer, wherein the silicon cap layer is arranged on the upper surface of the strained silicon layer;
[0010] The source and drain are both arranged on the upper surface of the SOI substrate, and the source and drain are respectively located on both sides of the strained silicon layer;
[0011] A gate oxide layer, the gate oxide layer is arranged on the upper surface of the silicon cap layer and covers a portion of the upper surface of the source electrode and the drain electrode;
[0012] A gate, the gate being arranged on an upper surface of the gate oxide layer;
[0013] A first sidewall and a second sidewall, the first sidewall is arranged on the upper surface of the source and covers the gate oxide layer and the side of the gate near the source, and the second sidewall is arranged on the upper surface of the drain and covers the gate oxide layer and the side of the gate near the drain;
[0014] A continuous dense insulating film is arranged on the upper surfaces of the source electrode, the drain electrode, the gate electrode, and the surfaces of the first sidewall and the second sidewall.
[0015] In a second aspect, an embodiment of the present invention provides a method for preparing a strained silicon channel MOS device without an SOI structure, the method comprising:
[0016] preparing an SOI substrate;
[0017] Growing a fully strained silicon layer on the upper surface of the SOI substrate, wherein the lattice constant of the material of the fully strained silicon layer is different from the lattice constant of the material of the upper surface of the SOI substrate;
[0018] Depositing a full silicon cap layer on the upper surface of the fully strained silicon layer;
[0019] Depositing a full gate oxide layer on the upper surface of the full silicon cap layer;
[0020] Depositing a gate on a portion of the upper surface of the full gate oxide layer, and etching the upper surface of the full gate oxide layer and both sides of the gate until the full silicon cap layer is exposed to form a gate oxide layer;
[0021] Depositing an insulating layer on the upper surface of the full silicon cap layer close to the gate and on both sides of the gate and the gate oxide layer, and etching the insulating layer deposited on the full silicon cap layer to only retain the insulating layer deposited on both sides of the gate and the gate oxide layer to form a sidewall;
[0022] Ion implantation is performed on the fully strained silicon layer and the full silicon cap layer on both sides of the gate to form a source and a drain in the fully strained silicon layer and the full silicon cap layer, and a strained silicon layer and a silicon cap layer stacked from bottom to top are formed between the drain and the source, wherein the length of the strained silicon layer and the silicon cap layer is less than the length of the gate;
[0023] A continuous dense insulating film is deposited on the upper surface of the source, drain, gate and the surface of the sidewall to obtain a strained silicon channel MOS device with an SOI structure.
[0024] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: according to the MOS device provided by the present invention, by setting an SOI substrate with an SOI structure, the MOS device can have the ability to resist single particle radiation; by setting a dense insulating film on the upper surfaces of the gate, the drain and the source, the MOS device can have the ability to resist total dose radiation; by setting a strained silicon layer with a lattice constant different from the lattice constant of the material on its upper surface in the channel region on the upper surface of the SOI substrate, biaxial compressive stress can be introduced in the region based on the lattice mismatch principle; uniaxial stress can be introduced in the channel region through the dense insulating film; thereby, the carrier mobility is improved through the combined action of uniaxial stress and biaxial stress, thereby improving the device performance. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] Figure 1 A schematic structural diagram of an SOI substrate provided in an embodiment of the present invention;
[0026] Figure 2 A schematic structural diagram of a strained silicon channel MOS device with an SOI structure provided by an embodiment of the present invention;
[0027] Figure 3 A schematic diagram of a process for preparing a SOI substrate provided in an embodiment of the present invention;
[0028] Figure 4 A schematic diagram of a scenario for preparing an SOI substrate provided in an embodiment of the present invention;
[0029] Figure 5 A flowchart of a method for preparing a strained silicon channel MOS device with an SOI structure provided by an embodiment of the present invention;
[0030] Figure 6a-6g A schematic diagram of a preparation scenario of a strained silicon channel MOS device with an SOI structure provided in an embodiment of the present invention. DETAILED DESCRIPTION
[0031] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.
[0032] Example 1
[0033] Figure 1 The structure diagram of a SOI substrate provided by an embodiment of the present invention is shown. As an example but not limitation, the SOI substrate 1 may include a first substrate silicon layer 11, a buried oxide layer 12, a second substrate silicon layer 13 and a silicon buffer layer 14 stacked sequentially from bottom to top.
[0034] Specifically, the buried oxide layer 12 may be disposed on the upper surface of the first substrate silicon layer 11 , the second substrate silicon layer 13 may be disposed on the upper surface of the buried oxide layer 12 , and the silicon buffer layer 14 may be disposed on the upper surface of the second substrate silicon layer 13 .
[0035] Exemplarily, the SOI structure is a structure in which an insulating layer is provided between two silicon substrates, and has excellent characteristics such as resistance to single particle irradiation, instantaneous irradiation, and reduction of device latch-up effect.
[0036] In one example, the first substrate silicon layer 11 and the second substrate silicon layer 13 may be N-type doped silicon wafers.
[0037] For example, the doping concentration range of the first substrate silicon layer 11 and the second substrate silicon layer 13 may include 1e17cm -3 -5e17cm -3 .
[0038] Exemplarily, the thickness of the first substrate silicon layer 11 may be 100-200 nm.
[0039] Exemplarily, the thickness of the second substrate silicon layer 13 may be 20-50 nm.
[0040] In one example, the buried oxide layer 12 may be made of SiO 2 and may have a thickness of 150-200 nm.
[0041] In one example, the silicon buffer layer 14 may be an N-type doped silicon layer with a relatively low doping concentration, and its thickness may be 80-100 nm. The silicon buffer layer 14 with a low doping concentration can improve the quality of the epitaxial substrate.
[0042] For example, the silicon buffer layer 14 may have a concentration of 1e16 cm -3 of a phosphorus-doped silicon layer.
[0043] Example 2
[0044] Based on Example 1 Figure 2 The structure diagram of a strained silicon channel MOS device of an SOI structure provided by an embodiment of the present invention is shown. As an example but not limitation, the MOS device 100 may include an SOI substrate 1, a strained silicon layer 2, a silicon cap layer 3, a source 4, a drain 5, a gate oxide layer 6, a gate 7, a sidewall 8 and a continuous dense insulating film 9.
[0045] In some embodiments, see Figure 2, the strained silicon layer 2 can be arranged on the upper surface of the SOI substrate 1, and the silicon cap layer 3 is arranged on the upper surface of the strained silicon layer 2. The source 4 and the drain 5 are both arranged on the upper surface of the SOI substrate 1 and distributed on both sides of the strained silicon layer 2. The gate oxide layer 6 is arranged on the upper surface of the silicon cap layer 3 and covers part of the upper surface of the source 4 and the drain 5. The gate 7 is arranged on the upper surface of the gate oxide layer 6. The sidewall 8 can include two parts, namely, a first sidewall 81 and a second sidewall 82. The first sidewall 81 is arranged on the upper surface of the source 4 and covers the side of the gate oxide layer 6 and the gate 7 close to the source 4, and the second sidewall 82 is arranged on the upper surface of the drain 5 and covers the side of the gate oxide layer 6 and the gate 7 close to the drain 5. The upper surfaces of the source 4, the drain 5, the gate 7 and the surface of the sidewall 8 are covered with a continuous dense insulating film layer 9.
[0046] Exemplarily, the lattice constant of the material of the strained silicon layer is different from the lattice constant of the material of the upper surface of the SOI substrate.
[0047] Specifically, when the two materials contact to form a heterojunction, the material epitaxially grown on the substrate is forced to adapt to the lattice constant of the substrate material, and this pressure forces the lattice structure of the epitaxial layer to deform. In the epitaxial layer and the substrate, the material with a larger lattice constant forms tensile strain, and the smaller one forms compressive strain. Therefore, when the strained silicon layer 2 with different lattice constants grows on the upper surface of the SOI substrate 1, biaxial compressive stress will be generated. Since the strained silicon layer 2 is arranged between the source 4 and the drain 5, that is, the channel region of the MOS device 100, the channel region of the MOS device 100 will be subjected to biaxial compressive stress.
[0048] Because the dense insulating film 9 has compressive stress, it will expand in the horizontal direction under the action of chemical bonds. By making the dense insulating film 9 contact the source and drain, under the action of the lattice mismatch principle, the expansion force will drive the structure of the source 4 and the drain 5 to expand, and the total length of the device is constant, the channel will be compressed, so that the channel area of the MOS device 100 will also be subject to uniaxial compressive stress. When the dense insulating film 9 is relatively loose, the channel area of the MOS device 100 is subject to uniaxial compressive stress in the channel direction; when the dense insulating film 9 is relatively tight, the channel area of the MOS device 100 is subject to uniaxial tensile stress along the channel direction. Therefore, the channel will be subject to the composite stress formed by the superposition of biaxial stress and uniaxial stress. The superposition of multiple stresses can increase the mobility of carriers in the channel of the MOS device 100, thereby enhancing the current transport capacity of the device; and effectively reduce power consumption and significantly improve device performance.
[0049] It should be understood that the dense insulating film with the loose structure is only looser than the insulating film with the compact structure, but still belongs to the category of the compact structure compared with the commonly used insulating films.
[0050] In addition, since the dense insulating film 9 has a dense structure, its dielectric properties are more superior, and it has the advantages of strong blocking ability for movable ions, compact structure, and low pinhole density; therefore, it can play a role in resisting total dose radiation.
[0051] In a possible implementation, the lattice constant of the material of the strained silicon layer may be greater than that of the upper surface material of the SOI substrate.
[0052] In one example, the material of the strained silicon layer 2 may include SiGe, and the thickness thereof may range from 10 to 15 nm.
[0053] For example, the strained silicon layer 2 may have a doping concentration of 1e16 cm -3 Phosphorus-doped SiGe.
[0054] In a possible implementation, both the source 4 and the drain 5 may be P-type doped junctions, and the depth range of the doped junctions may include 30-40 nm.
[0055] In a possible implementation, the gate oxide layer 6 may be made of SiO 2 and have a thickness of 3-5 nm.
[0056] In a possible implementation, the gate 7 may be made of polysilicon, and its thickness may be 300-500 nm.
[0057] In a possible implementation, the material of the sidewall 8 may include SiO 2 .
[0058] In a possible implementation, the material of the dense insulating film 9 may include SIN, and the thickness thereof may be 100-200 nm.
[0059] According to the MOS device provided by the present invention, by providing an SOI substrate with an SOI structure, the MOS device can be made to have the ability to resist single particle radiation; by providing a dense insulating film on the upper surfaces of the gate, the drain and the source, the MOS device can be made to have the ability to resist total dose radiation; by providing a strained silicon layer with a lattice constant different from the lattice constant of the material on the upper surface of the SOI substrate in the channel region, biaxial compressive stress can be introduced in the region based on the lattice mismatch principle; uniaxial stress can be introduced in the channel region through the dense insulating film; thereby, the carrier mobility is improved through the combined action of the uniaxial stress and the biaxial stress, thereby improving the device performance.
[0060] Example 3
[0061] Based on Example 1, Figure 3The flowchart of a method for preparing an SOI substrate provided by an embodiment of the present invention is shown. As an example but not a limitation, the method for preparing an SOI substrate may include steps S301-S304, and each step is described below.
[0062] S301, surface oxidation is performed on the upper surface of the first silicon wafer and the lower surface of the second silicon wafer, and hydrogen is injected into the second silicon wafer to obtain an oxidized first silicon wafer and an oxidized and hydrogen-injected second silicon wafer.
[0063] In one example, see Figure 4 Two N-type doped silicon wafers can be selected, one serving as the first silicon wafer to make the first substrate silicon layer 11 and a portion of the buried oxide layer 12 , and the other serving as the second silicon wafer to make the second substrate silicon layer 13 and another portion of the buried oxide layer 12 .
[0064] Exemplarily, the upper surface of the first silicon wafer and the lower surface of the second silicon wafer can be surface oxidized, and hydrogen can be injected into the second silicon wafer to obtain an oxidized first silicon wafer with an oxide layer of 200-500nm and an oxidized hydrogen-injected second silicon wafer with an oxide layer of 200-500nm.
[0065] S302, polishing the upper surface of the first silicon wafer after oxidation and the lower surface of the second silicon wafer after oxidation and hydrogen implantation.
[0066] In one example, the oxide layers of the two silicon wafers may be polished using a chemical mechanical polishing process.
[0067] S303, bonding the upper surface of the polished first silicon wafer and the lower surface of the polished second silicon wafer, and heating to peel off excess material on the upper surface of the polished second silicon wafer to obtain a first substrate silicon layer, a buried oxide layer, and a second substrate silicon layer.
[0068] In one example, see Figure 4 The polished first silicon wafer and the polished second silicon wafer can be placed in an ultra-high vacuum environment, and the upper surface of the first silicon wafer and the upper surface of the second silicon wafer can be bonded at a temperature of 350°C to form a buried oxide layer 12; the oxidized portion of the first silicon wafer (i.e., the buried oxide layer) is the first substrate silicon layer 11.
[0069] In one example, the temperature of the bonded first and second silicon wafers can be raised to 100-200° C. so that the second silicon wafer breaks at the injected hydrogen to strip off excess material on the upper surface of the second silicon wafer, retaining 20-50 nm of silicon material to obtain a second substrate silicon layer 13 .
[0070] Exemplarily, the first substrate silicon layer 11 , the buried oxide layer 12 and the second substrate silicon layer 13 constitute a basic SOI structure.
[0071] S304, growing a silicon buffer layer on the upper surface of the second substrate silicon layer to obtain an SOI substrate.
[0072] In one example, an ultra-high vacuum chemical vapor deposition process can be used to grow a 80-100 nm thick low-doped silicon buffer layer on the upper surface of the second substrate silicon layer 13 at 550-650° C. to improve the quality of the epitaxial substrate, forming a Figure 1 The SOI substrate shown.
[0073] Example 4
[0074] Based on Example 3 Figure 5 The flowchart of the method for preparing a strained silicon channel MOS device of SOI structure provided by the embodiment of the present invention is shown. As an example but not a limitation, the method for preparing the MOS device 100 may include steps S501-S508, and each step is described below.
[0075] S501, preparing an SOI substrate.
[0076] For example, the SOI substrate preparation method in Example 3 can be used to prepare Figure 1 The SOI substrate 1 is shown in FIG.
[0077] S502, growing a fully strained silicon layer on the upper surface of the SOI substrate.
[0078] In one example, a fully strained silicon layer covering the entire upper surface of the SOI substrate 1 can be deposited on the upper surface of the SOI substrate using an ultra-high vacuum chemical vapor deposition process to obtain a Figure 6a The structure shown.
[0079] For example, if the material of the strained silicon layer 2 is SiGe, the fully strained silicon layer can be prepared by introducing GeH 4 gas and setting the flow ratio of SiH 4 to GeH 4 to be about 2.3.
[0080] Exemplarily, the strained silicon layer 2 may be a part of a fully strained silicon layer.
[0081] Optionally, the germanium component in the strained silicon layer 2 should not be too high, otherwise strain relaxation will occur; therefore, the germanium component parameter in the strained silicon layer 2 may be 0.3.
[0082] Since there is a 4.17% lattice mismatch between Si and Ge, when large-sized Ge atoms are doped into Si crystals, the lattice spacing will increase, so the lattice constant of SiGe is greater than that of Si. When the two materials contact to form a heterojunction, the material epitaxially grown thereon will be forced to adapt to the lattice of the substrate material. This pressure will force the lattice structure of the epitaxial layer to deform and the material to produce strain. That is, when a SiGe layer (less than a critical thickness) is grown on a Si substrate, the SiGe alloy will produce compressive strain. The generation of SiGe lamination compressive strain increases the carrier mobility and changes the device band structure, thereby improving the performance of the MOS device 100.
[0083] S503, depositing a full silicon cap layer on the upper surface of the fully strained silicon layer.
[0084] In one example, a chemical vapor deposition process can be used to epitaxially grow a 5nm-10nm thick full silicon cap layer on the fully strained silicon layer at 600-750°C to cover the entire upper surface thereof, so as to obtain Figure 6b The structure shown.
[0085] S504, depositing a full gate oxide layer on the upper surface of the full silicon cap layer, and depositing a gate on a portion of the upper surface of the full gate oxide layer.
[0086] In one example, a high temperature dry oxygen oxidation process may be used to prepare a full gate oxide layer, and then a chemical vapor deposition process may be used to deposit the gate 7 .
[0087] In another example, if the fully strained silicon layer is made of SiGe material, due to the characteristics of SiGe material, a high temperature dry oxygen oxidation process cannot be used to prepare a full gate oxide layer, and a chemical vapor deposition process can be used to deposit the full gate oxide layer and the gate.
[0088] For example, a layer of SiO2 with a thickness of 3-5 nm can be deposited on the surface of the full silicon cap layer at 600-800° C. to obtain a full gate oxide layer, and then a 300-500 nm polysilicon layer is deposited on a portion of the upper surface of the full gate oxide layer to form a gate 7, so as to obtain Figure 6c The structure shown.
[0089] S505, etching is performed on both sides of the gate on the upper surface of the full gate oxide layer until the full silicon cap layer is exposed to form a gate oxide layer.
[0090] For example, the gate oxide layer 6 can be obtained by etching away the portion not in contact with the gate 7 in the full gate oxide layer (see Figure 6d ).
[0091] S506, depositing an insulating layer on the upper surface of the full silicon cap layer close to the gate and on the two sides of the gate and the gate oxide layer, and then etching the insulating layer on the upper surface of the full silicon cap layer to retain only the insulating layer deposited on the sides of the gate and the gate oxide layer to form a side wall.
[0092] In one example, before depositing the insulating layer, lightly doped drain ions may be implanted in the preset source and drain regions; then, a chemical vapor deposition process is used to deposit an insulating layer on the upper surface of the full silicon cap layer near the gate 7, to obtain a structure such as Figure 6e Finally, using a dry etching process, the insulating layer on the upper surface of the full silicon cap layer is etched away, leaving only the insulating layer on the side of the gate 7 and the gate oxide layer 6 to form a side wall, and the obtained Figure 6f The structure shown.
[0093] For example, the implanted ions may be boron ions, and the implantation dose is 1e12 cm -3 , the energy is 10KeV, and the injection angle is a small angle of 70°.
[0094] For example, a SiO2 insulating layer with a thickness of 5-15 nm can be deposited at 600-800°C.
[0095] S507, ion implantation is performed on the fully strained silicon layer and the full silicon cap layer on both sides of the gate to form a source and a drain in the fully strained silicon layer and the full silicon cap layer, and a strained silicon layer and a silicon cap layer stacked from bottom to top are formed between the drain and the source.
[0096] In one example, ion implantation technology can be used to implant ions in the regions on both sides of the gate in the fully strained silicon layer and the full silicon cap layer; then annealing is performed to activate the impurities to form the source 4 and the drain 5, and the following is obtained: Figure 6g Between the source 4 and the drain 5, the portion of the full strained silicon layer that has not been ion-implanted is the strained silicon layer 2, and the portion of the full silicon cap layer that has not been ion-implanted is the silicon cap layer 3.
[0097] Exemplarily, the ion implanted region may also include a portion of the fully strained silicon layer and the full silicon cap layer located below the gate oxide layer, so that the length of the formed strained silicon layer 2 is smaller than the length of the gate level 7 .
[0098] S508, depositing a continuous dense insulating film on the upper surface of the source, the drain, the gate and the surface of the sidewall to obtain a strained silicon channel MOS device with an SOI structure.
[0099] In one example, a low-frequency power source can be used to deposit a dense insulating film 9 on the upper surface of the source 4, the drain 5, the gate 7 and the surface of the sidewall 8 by plasma enhanced chemical vapor deposition, so as to obtain Figure 2 The structure shown.
[0100] Exemplarily, the dense insulating film 9 can be deposited at a temperature of 200-500° C., a pressure range of 400-500 Torr, a low-frequency power source frequency of 100 kHz, and a power range of 150-300W.
[0101] When the material of the dense insulating film is SiN, a low-frequency power source can be used to introduce high-energy particle bombardment. The high-energy particle bombardment can cause the atomic ions to combine or redistribute. The atomic ion combination and redistribution will make the microstructure of the film denser. The dense structural characteristics of the film have a very high blocking ability, which enhances the MOS device 100's ability to resist total radiation.
[0102] In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.
[0103] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification.
[0104] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.
[0105] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, any modifications made without departing from the concept of the present invention should be deemed to belong to the protection scope of the present invention.
Claims
1. A strained silicon channel MOS device of SOI structure, characterized in that: include: SOI substrate; A strained silicon layer, the strained silicon layer is disposed on the upper surface of the SOI substrate, wherein the lattice constant of the material of the strained silicon layer is different from the lattice constant of the material of the upper surface of the SOI substrate; A silicon cap layer, wherein the silicon cap layer is disposed on an upper surface of the strained silicon layer; A source electrode and a drain electrode, wherein the source electrode and the drain electrode are both arranged on the upper surface of the SOI substrate, and the source electrode and the drain electrode are respectively located on two sides of the strained silicon layer; A gate oxide layer, the gate oxide layer is disposed on the upper surface of the silicon cap layer and covers a portion of the upper surfaces of the source electrode and the drain electrode; A gate, the gate being arranged on an upper surface of the gate oxide layer; A first sidewall spacer and a second sidewall spacer, wherein the first sidewall spacer is disposed on the upper surface of the source and covers the gate oxide layer and the side of the gate near the source, and the second sidewall spacer is disposed on the upper surface of the drain and covers the gate oxide layer and the side of the gate near the drain; A continuous dense insulating film is arranged on the upper surfaces of the source, the drain, and the gate, and on the surfaces of the first sidewall and the second sidewall.
2. The MOS device according to claim 1, characterized in that: The SOI substrate comprises: a first substrate silicon layer; A buried oxide layer, wherein the buried oxide layer is arranged on the upper surface of the first substrate silicon layer; a second substrate silicon layer, wherein the second substrate silicon layer is arranged on an upper surface of the buried oxide layer; A silicon buffer layer is disposed on the upper surface of the second substrate silicon layer.
3. The MOS device according to claim 1, characterized in that: The lattice constant of the material of the strained silicon layer is greater than the lattice constant of the material of the upper surface of the SOI substrate.
4. The MOS device according to claim 3, characterized in that: The material of the strained silicon layer includes: SiGe.
5. The MOS device according to claim 1, characterized in that: The thickness of the strained silicon layer is 10-15 nm.
6. The MOS device according to claim 1, characterized in that: The material of the dense insulating film includes: SIN.
7. The MOS device according to claim 1, characterized in that: The thickness of the dense insulating film includes: 100nm-200nm.
8. A method for preparing a strained silicon channel MOS device of SOI structure, characterized in that include: preparing an SOI substrate; Growing a fully strained silicon layer on the upper surface of the SOI substrate, wherein the lattice constant of the material of the fully strained silicon layer is different from the lattice constant of the material of the upper surface of the SOI substrate; Depositing a full silicon cap layer on the upper surface of the fully strained silicon layer; Depositing a full gate oxide layer on the upper surface of the full silicon cap layer; Depositing a gate on a portion of the upper surface of the full gate oxide layer, and etching the upper surface of the full gate oxide layer and both sides of the gate until the full silicon cap layer is exposed to form a gate oxide layer; Depositing an insulating layer on a portion of the upper surface of the full silicon cap layer close to the gate and on both sides of the gate and the gate oxide layer, and etching the insulating layer deposited on the full silicon cap layer to only retain the insulating layer deposited on both sides of the gate and the gate oxide layer to form a sidewall; Performing ion implantation on the fully strained silicon layer and the full silicon cap layer at both sides of the gate, respectively, to form a source and a drain in the fully strained silicon layer and the full silicon cap layer, and forming a strained silicon layer and a silicon cap layer stacked from bottom to top between the drain and the source, wherein the length of the strained silicon layer and the silicon cap layer is less than the length of the gate; A continuous dense insulating film is deposited on the source, the drain, the upper surface of the gate and the surface of the sidewall to obtain a strained silicon channel MOS device with an SOI structure.
9. The preparation method according to claim 8, characterized in that: Depositing a continuous dense insulating film on the source, the drain, the upper surface of the gate and the surface of the sidewall, comprising: The dense insulating film is deposited on the source electrode, the drain electrode, the upper surface of the gate electrode and the surface of the sidewall by using a plasma enhanced chemical vapor deposition method using a low frequency power source.
10. The preparation method according to claim 8, characterized in that: The SOI substrate comprises a first substrate silicon layer, a buried oxide layer, a second substrate silicon layer and a silicon buffer layer stacked in sequence from bottom to top; Wherein, the preparation of the SOI substrate comprises: Surface oxidation is performed on the upper surface of the first silicon wafer and the lower surface of the second silicon wafer, and hydrogen is injected into the second silicon wafer to obtain an oxidized first silicon wafer and an oxidized and hydrogen-injected second silicon wafer; Polishing the upper surface of the oxidized first silicon wafer and the lower surface of the oxidized hydrogen-implanted second silicon wafer; Bonding the upper surface of the first silicon wafer after polishing and the lower surface of the second silicon wafer after polishing to obtain a first substrate silicon layer, a buried oxide layer and an unoxidized portion of the second silicon wafer stacked in sequence from bottom to top, wherein the first substrate silicon layer is the unoxidized portion of the first silicon wafer, and the buried oxide layer is composed of the oxidized portion of the first silicon wafer and the second silicon wafer after bonding; Raising the temperature to peel off the upper surface of the second silicon wafer to obtain the second substrate silicon layer located on the buried oxide layer; A silicon buffer layer is grown on the upper surface of the second substrate silicon layer to obtain the SOI substrate.