Semiconductor device with electrostatic discharge protection

Abstract

The invention relates to a semiconductor device with electrostatic discharge protection. A semiconductor device, such as a fin field effect transistor FinFET, can provide advantages in terms of electrostatic discharge protection. The semiconductor device includes a fin having an undoped region, a first doped region, a second doped region, and a third doped region positioned between the first doped region and the second doped region. The semiconductor device further includes a gate disposed on the undoped region of the fin, a silicide layer disposed on the third doped region, and an interconnect disposed on the silicide layer to form a drain.

Description

Technical Field

[0001] The present disclosure relates generally to semiconductor technology. More particularly, the present disclosure relates to semiconductor device structures that can be used to provide electrostatic discharge (ESD) protection. Background Art

[0002] Semiconductor device structures including fin field effect transistors (FinFETs) and, more specifically, laterally diffused metal oxide semiconductors (LDMOS) can be used in high power applications such as power amplifiers, radio frequency (RF) amplifiers, and power transistors for radio and wireless communication systems. As the demand for high power applications increases, research and development efforts continue to advance semiconductor technology to meet foundry manufacturing capabilities and capacity and enhance the functionality of various electronic devices and circuits. Summary of the invention

[0003] In one aspect, the present disclosure provides a semiconductor device comprising: a fin comprising an undoped region, a first doped region, a second doped region, and a third doped region positioned between the first doped region and the second doped region; a gate disposed on the undoped region of the fin; a silicide layer disposed on the third doped region of the fin; and an interconnect disposed on the silicide layer to form a drain.

[0004] In another aspect, the present disclosure provides a circuit comprising: a substrate; and a semiconductor device comprising: a fin comprising an undoped region, a first doped region, a second doped region, and a third doped region positioned between the first doped region and the second doped region; a gate disposed on the undoped region of the fin; a silicide layer disposed on the third doped region; and an interconnect disposed on the silicide layer to form a drain.

[0005] In another aspect, the present disclosure provides a semiconductor device comprising: a fin, comprising an undoped region, a first doped region, a second doped region, a third doped region positioned between the first doped region and the second doped region, and a fourth doped region; a gate disposed on the undoped region of the fin; a first silicide layer disposed on the third doped region; a second silicide layer disposed on the fourth doped region; a first interconnect disposed on the first silicide layer to form a drain; and a second interconnect disposed on the second silicide layer to form a source. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 A top view of an example semiconductor device according to some aspects of the present disclosure is shown.

[0007] Figure 2Demonstration of some aspects of the present disclosure Figure 1 A cross section of an example semiconductor device.

[0008] Figure 3 Demonstrating some aspects of the present disclosure Figure 1 A virtual representation of an example semiconductor device. DETAILED DESCRIPTION

[0009] In the following description, for the purpose of explanation, numerous details are set forth to provide a thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that other aspects may be practiced without some of the details. Different examples are described herein, and although various features are attributed to the examples, it should be understood that features described with respect to one example may also be combined with other examples. However, for the same reason, a single feature or several features of any described example should not be considered essential to each example, because other examples may omit such features.

[0010] When an element is referred to herein as being "connected" or "coupled" to another element, it is understood that the element may be directly connected to the other element, or that there may be intervening elements between the elements. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, it is understood that there may be no intervening elements in the "direct" connection between the elements. However, the presence of a direct connection does not exclude other connections in which there may be intervening elements.

[0011] When an element is referred to herein as being "disposed" in some manner relative to another element (e.g., disposed on, disposed between, disposed below, disposed adjacent to, or disposed in some other relative manner), it is understood that the element may be disposed directly relative to the other element (e.g., disposed directly on the other element) or that there may be intervening elements between the elements. Conversely, when an element is referred to as being "directly disposed" relative to another element, it is understood that there are no intervening elements in the "direct" instance. However, the presence of a direct placement does not exclude other instances in which there may be intervening elements.

[0012] Likewise, when an element is referred to herein as a "layer," it is understood that the layer may be a single layer or may include multiple layers. For example, a conductive layer may include a plurality of different conductive materials or multiple layers of different conductive materials, and a dielectric layer may include a plurality of dielectric materials or multiple layers of dielectric materials. When a layer is described as being coupled or connected to another layer, it is understood that the coupled or connected layer may include an intervening element that is present between the coupled or connected layers. Conversely, when a layer is referred to as being "directly" connected or coupled to another layer, it is understood that there are no intervening elements between the layers. However, the presence of a directly coupled or connected layer does not exclude other connections in which an intervening element may be present.

[0013] In addition, the terms left, right, front, back, top, bottom, forward, reverse, clockwise and counterclockwise are used only for explanation purposes and are not limited to any fixed direction or orientation. Instead, they are only used to indicate the relative position and / or direction between the various parts of an object and / or component.

[0014] In addition, unless otherwise indicated, all numbers used herein to indicate quantities, dimensions, etc. are to be understood as being modified by the term "approximately" in all instances. In this application, unless otherwise specifically stated, the use of the singular includes the plural, and the use of the terms "and" and "or" means "and / or" unless otherwise indicated. In addition, the use of the terms "includes" and "have" as well as other forms (such as "includes, included", "has, have and had") should be considered non-exclusive. Moreover, unless otherwise specifically stated, terms such as "element" or "component" cover both elements and components including one unit and elements and components including more than one unit.

[0015] Although some features and aspects have been described with respect to examples, those skilled in the art will recognize that numerous modifications are possible. For example, the methods and processes described herein may be implemented using hardware components, custom integrated circuits (ICs), programmable logic, and / or any combination thereof. In addition, although for ease of description, the various methods and processes described herein may be described with respect to specific structural and / or functional components, the methods provided by the various embodiments are not limited to any specific structural and / or functional architecture but may be implemented with any suitable hardware configuration. Similarly, although some functionality is attributed to one or more system components, unless the context indicates otherwise, this functionality may be distributed throughout various other system components according to several embodiments.

[0016] In addition, although the procedures of the methods and processes described herein are described in a particular order for ease of description, the various procedures may be reordered, added, and / or omitted according to various embodiments unless the context otherwise indicates. In addition, the procedures described with respect to one method or process may be incorporated into other described methods or processes; similarly, system components described according to a specific structural architecture and / or with respect to one system may be organized into alternative structural architectures and / or incorporated into other described systems. Therefore, although those embodiments are described as having or not having some features for ease of description and to illustrate aspects of various embodiments, unless the context otherwise indicates, the various components and / or features described herein with respect to a specific example may be replaced, added, and / or subtracted from other described embodiments. Therefore, although several examples are described above, it should be understood that the present disclosure is intended to cover all modifications and equivalents within the scope of the appended claims.

[0017] refer to Figure 1 , showing a top view of an example semiconductor device 100 according to some aspects of the present disclosure. The semiconductor device 100 can be implemented as various types of semiconductor devices, such as various different types and combinations of transistor structures. For example, the semiconductor device 100 can be a non-planar (three-dimensional) FinFET device, such as an LDMOS device. Figure 1 , semiconductor device 100 includes a plurality of fins (channels), including fin 140. As will be appreciated by those of skill, the term "fin" as used herein refers to any conductive fin or other channel-type structure used in semiconductor device 100, and should not unduly limit the scope of the claims. The different fins of semiconductor device 100 may be formed using any suitable material, such as silicon, and may be disposed in a substantially parallel relationship to one another. Fin 140 is shown to include various doped regions, including doped region 142, doped region 144, doped region 146, doped region 148, and doped region 242. Semiconductor device 100 is also shown to include gates 164 and 264, and trenches 190 and 290.

[0018] Trench 190 may be disposed between gate 164 and doped region 144, and trench 290 may be disposed between doped region 148 and gate 264. Thus, trench 190 may also be disposed between doped region 142 and doped region 144. Trench 190 and trench 290 may be formed using any suitable photolithography and etching techniques. The specific locations of trench 190 and trench 290 may provide advantages in various electrical properties of semiconductor device 100 (e.g., preventing current leakage, etc.). Gate 264 may be the gate of a second transistor that is separate from the transistor associated with gate 164. As described in detail below, advantages in preventing electrostatic discharge may be provided due to the drain terminal design of semiconductor device 100. From Figure 1 As can be seen from the top view shown in FIG. 1 , doped region 146 is disposed between doped region 144 and doped region 148 .

[0019] refer to Figure 2 According to some aspects of the present disclosure, Figure 1 1 , which illustrates a portion of the semiconductor device 100 in more detail. Figure 2 The cross section shown in Figure 1 The various components of the semiconductor device 100 that can be seen in FIG. 1 include the gate 164 , the trench 190 , the doped region 142 , the doped region 144 , the doped region 146 , and the doped region 148 . Figure 2 Additional components of semiconductor device 100 are also visible, including substrate 110 , well 122 , well 124 , shallow trench isolation (STI) 132 , STI 134 , and STI 136 . Figure 2Also shown are various undoped regions of the fin 140 , including an undoped region 141 , an undoped region 143 , an undoped region 145 , an undoped region 147 , an undoped region 149 , and an undoped region 151 . Figure 2 Silicide layers 172 and 176 are further shown, as well as interconnects 182 , 184 , and 186 .

[0020] The substrate 110 may be formed of a silicon material (e.g., crystalline silicon) and / or other suitable materials or combinations of materials. The substrate 110 may be implemented using various manufacturing techniques, such as using a silicon-on-insulator (SOI) structure, a bulk semiconductor structure, an alloy semiconductor, a compound semiconductor, germanium, and / or various other suitable materials and combinations thereof. The substrate 110 generally provides a base for forming components of the semiconductor device 100 thereon. It should be appreciated that the semiconductor device 100 may be implemented in various different types of circuits, resulting in various types of integrated circuit (IC) chips.

[0021] In some examples, well 122 may be implemented as a p-type well, and well 124 may be implemented as an n-type well. That is, well 122 may be doped with a p-type dopant, such as boron and / or other similar p-type dopants, and well 124 may be doped with an n-type dopant, such as arsenic, phosphorus, and / or other similar dopants. Wells 122 and 124 may be regions of substrate 110 such that wells 122 and 124 are formed as doped silicon material. Wells 122 and 124 may also be formed at least partially separate from substrate 110, such as being at least partially formed within various types of oxide layers and / or other insulating / dielectric layers. In particular, as Figure 2 140, doped region 144, undoped region 147, doped region 146, undoped region 149, and doped region 148 of fin 140 may be disposed on well 124. Since well 124 may be an n-type well, this structure provides an inherent ballast resistor at the drain of semiconductor device 100, as described in further detail below. Furthermore, doped region 142 may be disposed on well 122, as shown in FIG. Figure 2 Displayed in.

[0022] The shallow trench isolation 132, the shallow trench isolation 134, and the shallow trench isolation 136 may be formed by etching trenches in the semiconductor device 100. For example, after etching the trench 190, the shallow trench isolation 134 may be formed by depositing a dielectric material at least partially within the trench 190. The shallow trench isolation 132 and the shallow trench isolation 136 may be formed in a similar manner. The dielectric material used to form the shallow trench isolation 132, the shallow trench isolation 134, and the shallow trench isolation 136 may be, for example, silicon oxide, silicon nitride, and / or other suitable materials and combinations of materials. The shallow trench isolation 132, the shallow trench isolation 134, and the shallow trench isolation 136 may generally prevent current leakage between different components of the semiconductor device 100.

[0023] The gate 164 may be formed using polysilicon material and / or another suitable material or combination of materials (eg, a metal gate). The voltage applied to the gate 164 may generally control the operation and conductivity of the semiconductor device 100. Figure 2 , spacers may be formed at least partially around gate 164 to electrically isolate gate 164 and prevent charge leakage. Spacers may be formed using materials having a high dielectric constant, such as silicon nitride, silicon oxide, and / or other suitable materials and combinations thereof. In addition, a gate oxide layer may be formed between gate 164 and fin 140 (e.g., using thermal oxidation) using materials such as silicon nitride, aluminum oxide, silicon dioxide, and / or other suitable materials and combinations thereof. In some examples, a silicide layer similar to silicide layer 172 and silicide layer 176 described below may be formed on gate 164 (e.g., using a trench silicidation process). As shown in FIG. Figure 1 The gate 264 shown in FIG. 2 can be formed in a similar manner to the gate 164 .

[0024] For example, silicide layer 172 may be formed on doped region 142 using a trench silicidation process. Silicide layer 176 may also be formed on doped region 146 using a trench silicidation process or another similar type of process. Silicide layer 172 and silicide layer 176 may generally be formed using a combination of silicon and a certain type of metal (e.g., a transition metal), among other possible implementations. Silicide layer 172 may be formed on doped region 142 to provide electrical contact for a transistor source terminal. Silicide layer 176 may be formed on doped region 146 to provide electrical contact for a transistor drain terminal. The trench silicidation process used to form silicide layer 172 and silicide layer 176 may generally include deposition of metal and heating of the wafer, followed by etching to expose silicide layer 172 and silicide layer 176 in the active region of semiconductor device 100. Top surfaces (from the top of doped region 142, doped region 144, doped region 146, and doped region 148) of doped region 142, doped region 144, doped region 146, and doped region 148 may be formed using a trench silicidation process or another similar type of process. Figure 2 14 (from the perspective shown in FIG. 14 ) may extend above the top surfaces of undoped regions 141, 143, 145, 147, 149, and 151. Thus, the heights of doped regions 142, 144, 146, and 148 may be greater than the heights of undoped regions 141, 143, 145, 147, 149, and 151. This structure including the height difference provides a raised source / drain (RSD) structure having favorable electrical properties for preventing electrostatic discharge.

[0025] Interconnect 182 may be disposed on silicide layer 172 to form a transistor source terminal and provide a connection between semiconductor device 100 (e.g., a FinFET) and one or more additional circuit elements (e.g., other components of an integrated circuit, such as other FinFETs). Interconnect 184 may be disposed on gate 164 to form a transistor gate terminal and also provide a connection between semiconductor device 100 and one or more additional circuit elements. As described, in some examples, a silicide layer similar to silicide layer 172 and silicide layer 176 may be formed on gate 164, and then interconnect 184 may be formed on the silicide layer. Interconnect 186 may be disposed on silicide layer 176 to form a transistor drain terminal and provide a connection between semiconductor device 100 and one or more additional circuit elements. As shown, interconnect 186 does not contact doped region 144 or doped region 146 of fin 140. Any suitable interconnect structures and materials may be used to form interconnects 182, 184, and 186. Interconnects 182, 184, and 186 may be implemented as conductive copper vias, for example, as well as other possible methods for implementing interconnects 182, 184, and 186. The term "interconnect" as used herein refers to any structure for forming one or more electrical connections between components of semiconductor device 100, and should not unduly limit the scope of the claims.

[0026] The doped regions 142, 144, 146, and 148 may each be an in-situ doped epitaxial region on the fin 140. The doped regions 142, 144, 146, and 148 may be formed using various suitable doping techniques, including doping the fin 140 (e.g., a silicon fin) using phosphorus or another suitable dopant. As a result of a doping process (e.g., an ion implantation process, etc.), the doped regions 142, 144, 146, and 148 of the fin 140 may exhibit different electrical properties than the undoped regions 141, 143, 145, 147, 149, and 151 of the fin 140. For example, after doping pure silicon with phosphorus, additional valence electrons may be added that become unbounded to individual atoms and allow doped regions 142 , 144 , 146 , and 148 of fin 140 to exhibit properties of a conductive semiconductor material.

[0027] like Figure 2, doped region 142 may be disposed between undoped region 141 and undoped region 143. Doped region 144 may be disposed between undoped region 145 and undoped region 147. Doped region 146 may be disposed between undoped region 147 and undoped region 149. Doped region 148 may be disposed between undoped region 149 and undoped region 151. Furthermore, trench 190 may be disposed between undoped region 143 and undoped region 145. The geometric relationship between (i) doped region 144 and doped region 146, and (ii) doped region 148 and doped region 146 may generally be symmetrical to provide an inherent ballast resistor at the drain of semiconductor device 100. That is, the distances between (i) doped region 144 and doped region 146, and (ii) doped region 148 and doped region 146 may be equal. Thus, the length of undoped region 147 (along cross section AA') may be equal to the length of undoped region 149. In this sense, it will be appreciated that the term "equal" does not necessarily mean completely equal, as manufacturing process variations may introduce a certain degree of error during manufacturing. For example, taking into account process variations, the difference in the distance between doped region 144 and doped region 146 and the distance between doped region 148 and doped region 146 may be between 1 picometer and 5 nanometers, and the difference in the length of undoped region 147 and the length of undoped region 149 may also be between 1 picometer and 5 nanometers.

[0028] The substantially symmetrical relationship of doped region 144, doped region 146, and doped region 148 may provide an inherent ballast resistor within semiconductor device 100. The resistance of the inherent ballast resistor may increase as the current flowing through fin 140 increases, and the resistance of the inherent ballast resistor may decrease as the current flowing through fin 140 decreases. In some instances, the use of silicide layers (e.g., silicide layer 172 and silicide layer 176) may cause some undesirable device characteristics, including current congestion at the shallow silicide surface. However, the added inherent ballast resistor may mitigate these undesirable characteristics without requiring additional manufacturing steps and without requiring the use of additional masks during the manufacturing process. In some instances, the human body model (HBM) voltage of semiconductor device 100 may be improved by the added inherent ballast resistor without significantly affecting the breakdown voltage. Therefore, semiconductor device 100 may provide better electrostatic discharge protection when compared to a structure that does not include such an inherent ballast resistor.

[0029] In some examples, the operating voltage of the semiconductor device 100 may be in a range from 1 volt to 15 volts. The height of the fin 140 may be in a range from 35 nanometers to 60 nanometers. The length of the gate 164 (along the direction of the fin 140) may be in a range from 200 nanometers to 1 micrometer (micron). The length of the trench 190 (along the direction of the fin 140) may be in a range from 100 nanometers to 1 micrometer (micron). Under these operating conditions and design parameters, the electrostatic discharge prevention functionality provided by the added inherent ballast resistor may be particularly advantageous.

[0030] refer to Figure 3 , according to some aspects of the present disclosure, an illustration of displaying a virtual representation of a semiconductor device 100 is shown. Figure 3 Each of doped regions 142, 144, 146, and 148 can be seen in FIG. Figure 3 144 and 146 and (ii) the doped region 148 and 146 are generally symmetrical to provide an inherent ballast resistor at the drain of the semiconductor device 100. That is, the distances between (i) the doped region 144 and the doped region 146 and (ii) the doped region 148 and 146 can be approximately equal. For example, to account for process variations, the difference in the distance between the doped region 144 and the doped region 146 and the distance between the doped region 148 and the doped region 146 can be between 1 picometer and 5 nanometers.

Claims

1. A semiconductor device comprising: A fin comprising an undoped region, a first doped region, a second doped region, and a third doped region positioned between the first doped region and the second doped region; a gate disposed on the undoped region of the fin; a silicide layer disposed on the third doped region of the fin; and An interconnect is disposed on the silicide layer to form a drain. 2 . The semiconductor device of claim 1 , wherein the interconnect does not contact the first doped region or the second doped region. The semiconductor device according to claim 1 , wherein a height of the third doped region is greater than a height of the undoped region. 4 . The semiconductor device of claim 1 , wherein a difference between a distance between the first doped region and the third doped region and a distance between the second doped region and the third doped region is between 1 picometer and 5 nanometers.

5. The semiconductor device according to claim 1, wherein: The fin includes a fourth doped region; A second silicide layer is disposed on the fourth doped region; and A second interconnect is disposed on the second silicide layer to form a source. 6 . The semiconductor device of claim 5 , wherein the fin comprises a trench positioned between the first doped region and the fourth doped region. The semiconductor device of claim 1 , wherein a height of the fin is between 35 nanometers and 60 nanometers. 8 . The semiconductor device of claim 1 , wherein a length of the gate disposed on the undoped region of the fin is between 200 nanometers and 1 micrometer.

9. The semiconductor device of claim 1, wherein an operating voltage of the semiconductor device is between 1 volt and 15 volts. 10 . The semiconductor device of claim 6 , wherein a length of the trench positioned between the first doped region and the fourth doped region is between 100 nanometers and 1 micrometer. 11 . The semiconductor device of claim 6 , wherein the semiconductor device comprises a second gate disposed on a second undoped region of the fin. 12 . The semiconductor device of claim 11 , wherein the fin comprises a second trench positioned between the third doped region and the second undoped region.

13. The semiconductor device according to claim 1, wherein: The undoped region includes a first undoped region; The fin includes a second undoped region disposed between the first doped region and the third doped region; The fin includes a third undoped region disposed between the second doped region and the third doped region; and A difference between a length of the second undoped region and a length of the third undoped region is between 1 picometer and 5 nanometers. 14 . The semiconductor device of claim 13 , wherein the first doped region, the second doped region, the third doped region, the first undoped region, and the second undoped region are disposed on an n-type well.

15. A circuit comprising: substrate; and A semiconductor device comprising: A fin comprising an undoped region, a first doped region, a second doped region, and a third doped region positioned between the first doped region and the second doped region; a gate disposed on the undoped region of the fin; a silicide layer disposed on the third doped region; and An interconnect is disposed on the silicide layer to form a drain. 16 . The circuit of claim 15 , wherein the fin comprises a trench positioned between the first doped region and the undoped region.

17. The circuit of claim 15, wherein: The interconnect does not contact the first doped region or the second doped region; and The height of the third doped region is greater than the height of the undoped region.

18. The circuit of claim 15, wherein: The height of the fin is between 35 nanometers and 60 nanometers; and The length of the gate disposed on the undoped region of the fin is between 200 nanometers and 1 micron.

19. A semiconductor device comprising: A fin, comprising an undoped region, a first doped region, a second doped region, a third doped region positioned between the first doped region and the second doped region, and a fourth doped region; a gate disposed on the undoped region of the fin; a first silicide layer disposed on the third doped region; a second silicide layer disposed on the fourth doped region; a first interconnect disposed on the first silicide layer to form a drain; and A second interconnect is disposed on the second silicide layer to form a source.

20. The semiconductor device according to claim 19, wherein: The first interconnect does not contact the first doped region or the second doped region; The height of the third doped region is greater than the height of the undoped region; The difference between the distance between the first doped region and the third doped region and the distance between the second doped region and the third doped region is between 1 picometer and 5 nanometers; and The fin includes a trench positioned between the first doped region and the fourth doped region.

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