Semiconductor device and method of manufacturing semiconductor device

Abstract

A semiconductor device and a method of manufacturing a semiconductor device are disclosed. The semiconductor device includes a substrate, a fin structure disposed on the substrate, and a gate structure. The gate structure includes a high-k gate oxide layer disposed on the fin structure, a diffusion barrier layer disposed on the high-k gate oxide layer, and a metal layer disposed on the diffusion barrier layer. The semiconductor device also includes a gate spacer disposed on the diffusion barrier layer, and a source / drain (S / D) region disposed on the fin structure. A sidewall of the S / D region is in contact with a sidewall of the high-k gate oxide layer.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a semiconductor device and a method of manufacturing the semiconductor device. Background Art

[0002] As semiconductor technology advances, there is an increasing demand for higher storage capacity, faster processing systems, higher performance, and lower costs. To meet these demands, the semiconductor industry continues to scale down the size of semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs), including planar MOSFETs, fin field effect transistors (diffusion barrier FinFETs), and all-around gate field effect transistors (GAA FETs). This scaling down increases the complexity of semiconductor manufacturing processes. Summary of the invention

[0003] Some embodiments of the present disclosure provide a semiconductor device, which includes: a substrate; a fin structure disposed on the substrate; a gate structure, which includes: a high-k gate oxide layer disposed on the fin structure, a first diffusion barrier layer disposed on the high-k gate oxide layer, and a metal layer disposed on the first diffusion barrier layer; a gate spacer disposed on the first diffusion barrier layer; and a source / drain (S / D) region disposed on the fin structure, wherein the sidewalls of the source / drain region are in contact with the sidewalls of the high-k gate oxide layer.

[0004] Other embodiments of the present disclosure provide a semiconductor device, which includes: a substrate; a gate structure, which includes: an oxide layer disposed on the substrate, a first diffusion barrier layer disposed on the oxide layer, and a metal layer disposed on the first diffusion barrier layer; a gate spacer disposed on the first diffusion barrier layer; and a source / drain (S / D) region disposed in the substrate, wherein a top surface of the source / drain region is disposed below the oxide layer.

[0005] Another embodiment of the present disclosure provides a method for manufacturing a semiconductor device, the method comprising: forming a first oxide layer and a second oxide layer on a substrate; forming a first diffusion barrier layer on the second oxide layer; forming a polysilicon structure on the first diffusion barrier layer; forming a gate spacer on the first diffusion barrier layer and on the polysilicon structure; and replacing the polysilicon structure with a second diffusion barrier layer and a metal layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures.

[0007] Figure 1A An isometric view of a semiconductor device having a diffusion barrier layer in accordance with some embodiments is shown.

[0008] Figures 1B to 1D Different cross-sectional views of a semiconductor device having a diffusion barrier layer according to some embodiments are shown.

[0009] Figure 2A and Figure 2B Different cross-sectional views of another semiconductor device having a diffusion barrier layer in accordance with some embodiments are shown.

[0010] Figure 3 is a flow chart of a method of manufacturing a semiconductor device having a diffusion barrier layer according to some embodiments.

[0011] Figures 4 to 16 Isometric and cross-sectional views of a semiconductor device having a diffusion barrier layer at various stages of its fabrication process are shown in accordance with some embodiments.

[0012] Fig.17 is a flow chart of a method of manufacturing a semiconductor device having a diffusion barrier layer according to some embodiments.

[0013] Figures 18 to 22 Cross-sectional views of another semiconductor device having a diffusion barrier layer at various stages of its fabrication process are shown in accordance with some embodiments.

[0014] Exemplary embodiments will now be described with reference to the accompanying drawings. In the drawings, like reference numbers generally indicate identical, functionally similar, and / or structurally similar elements. DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments or examples for implementing the different components of the present application. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. As used herein, forming a first component on a second component means that the first component is formed to be in direct contact with the second component. In addition, the present disclosure may repeat reference numerals and / or characters in various instances. The repetition itself does not indicate the relationship between the various embodiments and / or configurations discussed.

[0016] For ease of description, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0017] It should be noted that references to "one embodiment," "embodiment," "exemplary embodiment," and "example" in the specification mean that the described embodiment may include specific components, structures, or characteristics, but each embodiment may not necessarily include specific components, structures, or characteristics. In addition, such phrases do not necessarily refer to the same embodiment. In addition, when a specific component, structure, or characteristic is described in conjunction with an embodiment, whether or not explicitly described, it is within the knowledge of those skilled in the art to implement such component, structure, or characteristic in conjunction with other embodiments.

[0018] It should be understood that the phraseology or terminology herein is used for the purpose of description rather than limitation, so that the phraseology or terminology of this specification is to be interpreted by those skilled in the relevant art based on the teachings herein.

[0019] In some embodiments, the terms "about" and "substantially" may indicate a value of a given amount that varies within 5-20% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%, ±10%, ±10-15%, ±15-20% of the value). These values ​​are merely examples and are not intended to be limiting. The terms "about" and "substantially" may refer to a percentage of a value as interpreted by a person skilled in the relevant art based on the teachings herein.

[0020] The fin structures disclosed herein may be patterned by any suitable method. For example, the fin structure may be patterned using one or more photolithography processes, including a double patterning process or a multiple patterning process. The double patterning process or the multiple patterning process may combine the photolithography process and the self-alignment process, thereby allowing the creation of patterns having, for example, a smaller pitch than that obtainable using a single direct photolithography process. For example, a sacrificial layer is formed over a substrate and the sacrificial layer is patterned using a photolithography process. Using a self-alignment process, spacers are formed next to the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fin structure.

[0021] The present disclosure provides an exemplary gate structure with a diffusion barrier layer located in a FET (e.g., FinFET and MOSFET), and an exemplary method for forming such a FET to improve threshold voltage control in the FET. In some embodiments, the exemplary gate structure of the FET may include a high-k gate oxide layer, a first diffusion barrier layer and a second diffusion barrier layer disposed on the high-k gate oxide layer, and a gate metal fill layer disposed on the first diffusion barrier layer and the second diffusion barrier layer. In some embodiments, the first diffusion barrier layer and the second diffusion barrier layer may be arranged to prevent or minimize metal atoms from diffusing from the gate metal fill layer to the high-k gate oxide layer. The presence of such diffused metal atoms in the high-k gate oxide layer may cause the threshold voltage in the FET to vary, and thereby deteriorate device performance. In some embodiments, the first diffusion barrier layer may be formed to have an amorphous structure and a structural density, which may limit the concentration of metal atoms diffused from the gate metal fill layer to the first diffusion barrier layer to about 10 atomic % or less. Similarly, the second diffusion barrier layer can be formed to have an amorphous structure and a structural density that can limit the concentration of metal atoms diffused from the gate metal filling layer into the second diffusion barrier layer to between about 10 atomic % and about 50 atomic %. Within these concentration limits, diffusion of metal atoms into the high-k gate oxide layer can be prevented or minimized.

[0022] Figure 1A An isometric view of a semiconductor device 100 is shown in accordance with some embodiments. In some embodiments, semiconductor device 100 may represent a FinFET and may be referred to as “FinFET 100 .” Figure 1B , Figure 1C and Figure 1D A semiconductor device 100 according to some embodiments is shown along Figure 1A For simplicity, Figure 1B , Figure 1C and Figure 1D Shows Figure 1A Cross-sectional views of additional structures not shown. Unless otherwise noted, Figures 1A to 1D The discussion of elements having the same reference numerals applies to each other.

[0023] refer to Figure 1A and Figure 1BIn some embodiments, the semiconductor device 100 may include (i) a substrate 104, (ii) a shallow trench isolation (STI) region 106 disposed on the substrate 104, (iii) a fin structure 108 disposed on the substrate 104, (iv) an S / D region 110 disposed on the fin structure 108, (v) a gate structure 112 surrounding a portion of the fin structure 108 extending above the STI region 106, (vi) a gate spacer 114 disposed along a sidewall of the gate structure 112, (vii) an etch stop layer (ESL) 116 disposed directly on the S / D region 110, (viii) an ILD layer 118 disposed directly on the ESL 116, (ix) an S / D contact structure 120 disposed on the S / D region 110, and (x) a gate contact structure 122 disposed on the gate structure 112.

[0024] The semiconductor device 100 may be formed on a substrate 104. In some embodiments, the substrate 104 may be a semiconductor material such as silicon, germanium (Ge), silicon germanium (SiGe), a silicon-on-insulator (SOI) structure, and combinations thereof. In addition, the substrate 104 may be doped with a p-type dopant (e.g., boron, indium, aluminum, or gallium) or an n-type dopant (e.g., phosphorus or arsenic). In some embodiments, the STI region 106 may include an insulating material such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbon nitride (SiCN), silicon oxycarbonitride (SiOCN), and silicon germanium oxide (SiGeO2). x ).

[0025] In some embodiments, the fin structure 108 may include a material similar to the substrate 104. The fin structure 108 may have elongated sides extending along the X-axis. The S / D region 110 may include an epitaxially grown semiconductor material such as Si and an n-type dopant such as phosphorus and other suitable n-type dopants for the n-type FinFET 100. The S / D region 110 may include an epitaxially grown semiconductor material such as Si and SiGe and a p-type dopant such as boron and other suitable p-type dopants for the p-type FinFET 100. Depending on the context, the S / D region 110 may be referred to individually or collectively as a source or a drain.

[0026] The gate structure 112 may be a multi-layer structure and may include (i) an interface oxide (IL) layer 112A, (ii) a high-k (HK) gate oxide layer 112B, (iii) a first diffusion barrier layer 112C, (iv) a second diffusion barrier layer 112D, (v) a work function metal (WFM) layer 112E, (vi) a gate metal filling layer 112F, (vii) a conductive capping layer 112G, and (viii) an insulating capping layer 112H.

[0027] In some embodiments, the IL layer 112A may be disposed directly on the portion of the fin structure 108 that extends over the STI region 106, as described below with reference to Figures 4 to 6 In some embodiments, the IL layer 112A may include SiO2, SiGeO x or germanium oxide (GeO x ), and the IL layer 112A may have a thickness T1 of about 1 nm to about 20 nm. In some embodiments, the HK gate oxide layer 112B may be disposed directly on the IL layer 112A and disposed on a portion of the fin structure 108 extending above the STI region 106, as described below with reference to Figures 4 to 6 As described. In some embodiments, HK gate oxide layer 112B may include a high-k dielectric material such as hafnium oxide (HfO2), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O3), hafnium silicate (HfSiO4), zirconium oxide (ZrO2), and zirconium silicate (ZrSiO2), and HK gate oxide layer 112B may have a thickness T2 of about 1 nm to about 50 nm. In some embodiments, the sidewalls of IL layer 112A and HK gate oxide layer 112B may be vertical, such as Figure 1B As shown by the solid lines in FIG. 1 , the sidewalls of the IL layer 112A and the HK gate oxide layer 112B may also be tapered, such as Figure 1B In some embodiments, the sidewalls of the IL layer 112A and the HK gate oxide layer 112B may contact the sidewalls of the S / D region 110 .

[0028] In some embodiments, the first diffusion barrier layer 112C may be disposed directly on the HK gate oxide layer 112B and disposed on a portion of the fin structure 108 extending over the STI region 106, as described below with reference to Figures 4 to 6 As described. In some embodiments, the first diffusion barrier layer 112C may include a metal nitride layer, such as a titanium nitride (TiN) layer, wherein metal atoms serve as dopants in the metal nitride layer. The metal atoms diffuse from the gate metal filling layer 112F through the WFM layer 112E and the second diffusion barrier layer 112D into the first diffusion barrier layer 112C. In some embodiments, when the gate metal filling layer 112F includes an Al layer, the metal atoms may include aluminum (Al) atoms.

[0029] In some embodiments, the first diffusion barrier layer 112C may be arranged to prevent or minimize diffusion of these metal atoms from the gate metal filling layer 112F into the HK gate oxide layer 112B. The presence of such diffused metal atoms in the HK gate oxide layer 112B may cause a threshold voltage variation in the semiconductor device 100 and thereby deteriorate device performance. In order to prevent or minimize such diffusion of metal atoms, the first diffusion barrier layer 112C may be formed in an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process (described below) to have an amorphous structure and a structural density that may limit the concentration of metal atoms diffused from the gate metal filling layer 112F into the first diffusion barrier layer 112C to about 10 atomic % or less. By limiting the concentration of diffused metal atoms to about 10 atomic % or less, diffusion of metal atoms into the HK gate oxide layer 112B may be prevented or minimized. In some embodiments, the first diffusion barrier layer 112C may include a conductive metal nitride, such as TiN having a Ti concentration of about 30 atomic % to about 70 atomic % and an Al dopant concentration of about 1 atomic % to about 10 atomic %. In some embodiments, the sidewalls of the first diffusion barrier layer 112C may be vertical, such as Figure 1B As shown by the solid line in FIG. 1 , the sidewall of the first diffusion barrier layer 112C may also be tapered, as shown in FIG. Figure 1B In some embodiments, the sidewall of the first diffusion barrier layer 112C may be in contact with the sidewall of the ESL 116 but not in contact with the S / D region 110 .

[0030] In some embodiments, the second diffusion barrier layer 112D may be disposed directly on the first diffusion barrier layer 112C and may have a U-shaped cross-sectional profile. In some embodiments, the second diffusion barrier layer 112D may include a metal nitride layer, such as a tantalum nitride (TaN) layer that is different from the metal nitride layer of the first diffusion barrier layer 112C. Similar to the first diffusion barrier layer 112C, the metal nitride layer of the second diffusion barrier layer 112D may include metal atoms as dopants that diffuse from the gate metal fill layer 112F through the WFM layer 112E. In some embodiments, when the gate metal fill layer 112F includes an Al layer, the metal atoms may include Al atoms.

[0031] In some embodiments, in addition to the first diffusion barrier layer 112C, the second diffusion barrier layer 112D may be arranged to prevent or minimize metal atoms from diffusing from the gate metal filling layer 112F into the HK gate oxide layer 112B. Similar to the first diffusion barrier layer 112C, the second diffusion barrier layer 112.D may be formed in an ALD process or a CVD process (described below) to have an amorphous structure and a structural density that may limit the concentration of metal atoms diffusing from the gate metal filling layer 112F into the second diffusion barrier layer 112D to between about 10 atomic % and about 50 atomic %. By limiting the concentration of diffused metal atoms to between about 10 atomic % and about 50 atomic %, the concentration of diffused metal atoms in the first diffusion barrier layer 112C may be limited to 10 atomic % or less, which in turn may prevent or minimize metal atoms from diffusing into the HK gate oxide layer 112B. In some embodiments, the second diffusion barrier layer 112D may have a thickness T4 that is greater than the thickness T3 of the first diffusion barrier layer 112C. In some embodiments, the thicknesses T3 and T4 may be about 2 nm to about 10 nm. Within this thickness range, diffusion of metal atoms into the HK gate oxide layer 112B may be sufficiently prevented or minimized without affecting device size and manufacturing cost.

[0032] In some embodiments, the WFM layer 112E may include Ti, titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum (TaAl), or tantalum aluminum carbide (TaAlC). In some embodiments, the WFM layer 112E may include an alloy of Ti and Al. In some embodiments, the gate metal filling layer 112F may include a suitable conductive material, such as tungsten (W), Ti, silver (Ag), ruthenium (Ru), molybdenum (Mo), copper (Cu), cobalt (Co), Al, iridium (Ir), nickel (Ni), metal alloys, and combinations thereof.

[0033] In some embodiments, the insulating capping layer 112H may be disposed directly on the conductive capping layer 112G. The insulating capping layer 112H may protect the underlying conductive capping layer 112G from structural and / or compositional degradation during subsequent processing of the semiconductor device 100. In some embodiments, the insulating capping layer 112H may include a nitride material such as SiN, and the insulating capping layer 112H may have a thickness of about 5 nm to about 10 nm to sufficiently protect the underlying conductive capping layer 112G.

[0034] In some embodiments, the conductive capping layer 112G may be directly disposed on the second diffusion barrier layer 112D, the WFM layer 112E, and the gate metal filling layer 112F. The conductive capping layer 112G may provide a conductive interface between the gate metal filling layer 112F and the gate contact structure 122 to electrically connect the gate metal filling layer 112F to the gate contact structure 112 without directly forming the gate contact structure 122 on the gate metal filling layer 112F or in the gate metal filling layer 112F. The gate contact structure 122 is not formed directly on the gate metal filling layer 112F or in the gate metal filling layer 112F to prevent contamination by any processing material used to form the gate contact structure 122. Contamination of the gate metal filling layer 112F may degrade device performance. Therefore, in the case of using the conductive capping layer 112G, the gate structure 112 may be electrically connected to the gate contact structure 122 without affecting the integrity of the gate structure 112. In some embodiments, the conductive capping layer 112G may include a metal material such as W, Ru, Mo, Co, other suitable metal materials, and combinations thereof.

[0035] In some embodiments, the gate structure 112 may be electrically isolated from the adjacent S / D region 110 by a gate spacer 114. In some embodiments, each gate spacer 114 may be directly disposed on the first diffusion barrier layer 112C and disposed on a portion of the HK gate oxide layer 112B and the IL layer 112A. In some embodiments, the gate spacer 114 may include a nitride spacer 114A and an oxide spacer 114B. In some embodiments, the nitride spacer 114A may have an L-shaped cross-sectional profile. In some embodiments, a horizontal portion of the nitride spacer 114A may be directly disposed on the first diffusion barrier layer 112C, and a vertical portion of the nitride spacer 114A may be directly disposed along a sidewall of the second diffusion barrier layer 112D. In some embodiments, the oxide spacer 114B may be directly disposed on the nitride spacer 114A. In some embodiments, the nitride spacer 114A may include silicon nitride (SiN x ), and may not include an oxide material. In some embodiments, the oxide spacer 114B may include silicon oxide (SiO x ), and may not include nitride materials.

[0036] In some embodiments, the ESL 116 may be disposed directly on the S / D region 110 (eg, Figure 1A shown in Figure 1BIn some embodiments, the ESL 116 may have a dielectric constant of about 4 to about 7 and may include dielectric materials such as lanthanum oxide (LaO), aluminum oxide (Al2O3), yttrium oxide (Y2O3), tantalum carbonitride (TaCN), zirconium silicide (ZrSi), SiOCN, SiOC, SiCN, zirconium nitride (ZrN), zirconium aluminum oxide (ZrAlO), TiO2, Ta2O3, ZrO2, HfO2, SiN, hafnium silicide (HfSi), aluminum oxynitride (AlON), SiO2, SiC, and zinc oxide (ZnO). In some embodiments, the ILD layer 118 may be disposed directly on the ESL 116 (e.g., Figure 1A shown in Figure 1B 112H). In some embodiments, the ILD layer 118 may include an insulating material such as SiO2, SiN, SiON, SiCN, and SiOCN. In some embodiments, the top surfaces of the ILD layer 118, the ESL 116, and the insulating cap layer 112H may be substantially coplanar with each other.

[0037] In some embodiments, the S / D contact structure 120 may include (i) a silicide layer 120A disposed in the S / D region 110, and (ii) a contact plug 120B disposed on the silicide layer 120A. In some embodiments, the silicide layer 120A in the n-type FinFET 100 may include titanium silicide (Ti x Si y ), Tantalum silicide (Ta x Si y ), molybdenum silicide (Mo x Si y ), zirconium silicide (Zr x Si y ), Hafnium Silicide (Hf x Si y ), scandium silicide (Sc x Si y ), yttrium silicide (Y x Si y ), terbium silicide (Tb x Si y ), Lutetium silicide (Lu x Si y ), Erbium Silicide (Er x Si y ), Ytterbium silicide (Yb x Si y ), europium silicide (Eu x Si y ), Thorium Silicide (Th x Si y), other suitable metal silicide materials, or combinations thereof. In some embodiments, the silicide layer 120A in the p-type FinFET 100 may include nickel silicide (Ni x Si y ), cobalt silicide (Co x Si y ), manganese silicide (Mn x Si y ), tungsten silicide (W x Si y ), iron silicide (Fe x Si y ), rhodium silicide (Rh x Si y ), palladium silicide (Pd x Si y ), ruthenium silicide (Ru x Si y ), platinum silicide (Pt x Si y ), iridium silicide (Ir x Si y ), Os x Si y ), other suitable metal silicide materials, or combinations thereof. In some embodiments, the contact plug 120B may include a conductive material having a low resistivity (e.g., a resistivity of about 50 μΩ-cm, about 40 μΩ-cm, about 30 μΩ-cm, about 20 μΩ-cm, or about 10 μΩ-cm), such as Co, W, Ru, Al, Mo, iridium (Ir), nickel (Ni), osmium (Os), rhodium (Rh), other suitable conductive materials having a low resistivity, and combinations thereof. In some embodiments, the gate contact structure 122 may include a conductive material similar to the conductive material of the contact plug 120B.

[0038] refer to Figure 1C In some embodiments, the semiconductor device 100 may have a HK gate oxide layer 112B*, a first diffusion barrier layer 112C*, and a second diffusion barrier layer 112D*, instead of Figure 1B The HK gate oxide layer 112B, the first diffusion barrier layer 112C, and the second diffusion barrier layer 112D are respectively applicable to the HK gate oxide layer 112B*, the first diffusion barrier layer 112C*, and the second diffusion barrier layer 112D* unless otherwise mentioned. In some embodiments, the first diffusion barrier layer 112C* is disposed between the spacers 114, such as Figure 1C As shown, rather than Figure 1BAs shown in FIG. 1 , the first diffusion barrier layer 112C is disposed below the spacer 114. As a result, the horizontal portion of the nitride spacer 114A is disposed directly on the HK gate oxide layer 112B*, and the vertical portion of the nitride spacer 114A is disposed directly along the sidewall of the first diffusion barrier layer 112C*. In some embodiments, similar to the second diffusion barrier layer 112D*, the first diffusion barrier layer 112C* may have a U-shaped cross-sectional profile instead of Figure 1B The vertical portion of the second diffusion barrier layer 112D* is disposed directly on the vertical portion of the first diffusion barrier layer 112C*, and the horizontal portion of the second diffusion barrier layer 112D* is disposed directly on the horizontal portion of the first diffusion barrier layer 112C*.

[0039] refer to Figure 1D In some embodiments, the semiconductor device 100 may have an IL layer 112A**, a HK gate oxide layer 112B**, and a first diffusion barrier layer 112C**, instead of Figure 1B The stack of IL layer 112A, HK gate oxide layer 112B, and first diffusion barrier layer 112C is disposed between spacers 114, such as the spacers 114. Figure 1D As shown, rather than Figure 1B As shown in FIG. 1 , the nitride spacer 114A is disposed under the spacer 114 like a stack of the IL layer 112A, the HK gate oxide layer 112B, and the first diffusion barrier layer 112C. As a result, the nitride spacer 114A is disposed directly on the fin structure 108, and the sidewalls of the IL layer 112A**, the HK gate oxide layer 112B**, and the first diffusion barrier layer 112C** are in contact with the sidewalls of the nitride spacer 114A.

[0040] Figure 2A and Figure 2B 2 shows different cross-sectional views of a semiconductor device 200 according to some embodiments. In some embodiments, the semiconductor device 200 may represent a MOSFET and may be referred to as “MOSFET 200 ”. Unless otherwise noted, Figure 2A and Figure 2B The discussion of elements having the same reference numerals applies to each other.

[0041] refer to Figure 2AIn some embodiments, the semiconductor device 200 may include (i) a substrate 204, (ii) an STI region 206 disposed on the substrate 204, (iii) an S / D region 210 disposed in the substrate 204, (iv) a gate structure 212 disposed on the substrate 204, (v) a gate spacer 214 disposed along a sidewall of the gate structure 212, and (vi) an ILD layer 118 disposed directly on the gate spacer 214 and the STI region 206. Unless otherwise mentioned, the discussion of the substrate 104, the STI region 106, and the ILD layer 118 applies to the substrate 204, the STI region 206, and the ILD layer 218.

[0042] In some embodiments, the S / D region 210 may include a doped region in the substrate 204. The doped region may include an n-type dopant (such as phosphorus and other suitable n-type dopants for n-type MOSFET 200) or a p-type dopant (such as boron and other suitable p-type dopants for p-type MOSFET 200).

[0043] The gate structure 212 may be a multi-layer structure, and may include (i) an IL layer 212A, (ii) a HK gate oxide layer 212B, (iii) a first diffusion barrier layer 212C, (iv) a second diffusion barrier layer 212D, (v) a WFM layer 212E, and (vi) a gate metal filling layer 212F. Unless otherwise mentioned, the discussion of the IL layer 112A, the HK gate oxide layer 112B, the first diffusion barrier layer 112C, the second diffusion barrier layer 112D, the WFM layer 112E, and the gate metal filling layer 112F is applicable to the IL layer 212A, the HK gate oxide layer 212B, the first diffusion barrier layer 212C, the second diffusion barrier layer 212D, the WFM layer 212E, and the gate metal filling layer 212F, respectively.

[0044] refer to Figure 2B In some embodiments, the semiconductor device 200 may have a HK gate oxide layer 212B*, a first diffusion barrier layer 212C*, and a second diffusion barrier layer 2120D*, instead of Figure 2A The HK gate oxide layer 212B, the first diffusion barrier layer 212C, and the second diffusion barrier layer 212D in the embodiment of the present invention are shown in FIG. Unless otherwise mentioned, the discussion of the HK gate oxide layer 212B, the first diffusion barrier layer 212C, and the second diffusion barrier layer 212D is applicable to the HK gate oxide layer 212B*, the first diffusion barrier layer 212C*, and the second diffusion barrier layer 212D*, respectively. In some embodiments, as Figure 2B As shown, the first diffusion barrier layer 212C* is disposed between the spacers 214, rather than Figure 2AAs shown in FIG. 1 , the first diffusion barrier layer 212C is disposed below the spacer 214. As a result, the bottom surface of the gate spacer 214 is disposed directly on the HK gate oxide layer 112B*, and the sidewalls of the gate spacer 214 are disposed directly along the sidewalls of the first diffusion barrier layer 212C*. In some embodiments, similar to the second diffusion barrier layer 212D*, the first diffusion barrier layer 212C* may have a U-shaped cross-sectional profile instead of Figure 2A The vertical portion of the second diffusion barrier layer 212D* is disposed directly on the vertical portion of the first diffusion barrier layer 212C*, and the horizontal portion of the second diffusion barrier layer 212D* is disposed directly on the horizontal portion of the first diffusion barrier layer 212C*.

[0045] Figure 3 is manufactured according to some embodiments having Figure 1B 1. For purposes of illustration, reference will be made to an exemplary method 300 of a semiconductor device 100 of FIG. Figures 4 to 16 The exemplary manufacturing process of manufacturing semiconductor device 100 is described as follows. Figure 3 According to some embodiments, Figure 4 is an isometric view of semiconductor device 100, and Figure 5 The semiconductor device 100 is manufactured at a stage along Figure 4 BB is a cross-sectional view of the semiconductor device 100. According to some embodiments, Figure 6 is an isometric view of semiconductor device 100, and Figure 7 Another manufacturing stage of the semiconductor device 100 is along Figure 6 1 is a cross-sectional view of the semiconductor device 100 along line CC. According to some embodiments, Figures 8 to 16 The semiconductor device 100 is manufactured at various stages along the Figure 1A 1 is a cross-sectional view of the semiconductor device 100 along line AA of FIG. Depending on the specific application, the operations may be performed in a different order or not performed. It should be noted that the method 300 may not produce a complete semiconductor device 100. Accordingly, it is understood that additional processes may be provided before, during, and after the method 300, and some other processes may only be briefly described herein. Unless otherwise mentioned, Figures 1A to 1D and Figures 4 to 16 The discussion of elements having the same reference numerals applies to each other.

[0046] refer to Figure 3 In operation 305, a fin structure is formed on the substrate. Figure 4 and Figure 5As described, a fin structure 108 is formed on a substrate 104. In some embodiments, the formation of the fin structure 108 may include patterning the substrate 104 using one or more photolithography processes (including double patterning or multiple patterning processes). After forming the fin structure 108, the STI region 106 may be formed, such as Figure 4 shown.

[0047] refer to Figure 3 In operation 310, a first oxide layer and a second oxide layer are formed on the fin structure. Figure 4 and Figure 5 As described, an IL layer 112A (also referred to as a “first oxide layer 112A”) and a HK gate oxide layer 112B (also referred to as a “second oxide layer 112B”) are formed on the fin structure 108. In some embodiments, the formation of the IL layer 112A may include performing an oxidation process on the surface of the fin structure 108 exposed above the STI region 106. In some embodiments, the oxidation process may be performed in an oxidation environment at a temperature of about 30° C. to about 200° C. or at other suitable oxidation temperatures. In some embodiments, the oxidation environment may include a combination of ozone (O3), a mixture of ammonium hydroxide and hydrogen peroxide, water, and / or a mixture of hydrochloric acid and hydrogen peroxide, water. In some embodiments, the oxidation process may be performed in an oxygen environment at a temperature of about 400° C. to about 600° C. or in a steam and oxygen environment.

[0048] In some embodiments, the formation of the HK gate oxide layer 112B may include depositing an oxide layer having a high-k dielectric material, such as hafnium oxide (HfO2), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O3), zirconium oxide (ZrO2), and zirconium silicate (ZrSiO2), on the IL layer 112A. In some embodiments, after forming the first diffusion barrier layer 112C in a subsequent operation 315, a portion of the oxide layer (not shown) on the STI region 106 that is not covered by the first diffusion barrier layer 112C may be etched to form the HK gate oxide layer 112B, such as Figure 4 and Figure 5 shown.

[0049] refer to Figure 3 In operation 315, a first diffusion barrier layer is formed on the second oxide layer. Figure 4 and Figure 5As described, a first diffusion barrier layer 112C is formed on the HK gate oxide layer 112B. In some embodiments, the formation of the first diffusion barrier layer 112C may include depositing two or more metal nitride monolayers (not shown) on the HK gate oxide layer 112B. Each metal nitride monolayer may be deposited in an ALD cycle. In some embodiments, after depositing each metal nitride monolayer, the total thickness of the metal nitride layer deposited on the HK gate oxide layer 112B may be measured. After reaching the desired total thickness T3 of the metal nitride layer, the ALD process may be terminated.

[0050] The sequential deposition of the metal nitride monolayer may form a first diffusion barrier layer 112C having higher conformality, higher thickness uniformity (e.g., thickness uniformity is about 10% to about 50% higher), and higher density (e.g., density is about 10% to about 50% higher) than a similar metal nitride layer having the same thickness as the first diffusion barrier layer 112C formed in a physical vapor deposition (PVD) process. The higher density of the first diffusion barrier layer 112C may minimize the diffusion of metal atoms (e.g., Al atoms) from the gate metal fill layer 112F into the first diffusion barrier layer 112C, and maintain the metal atom concentration in the first diffusion barrier layer 112C at or below about 10 atomic %. In addition, the higher thickness uniformity across the first diffusion barrier layer 112C may prevent or minimize structural weaknesses in the first diffusion barrier layer 112C through which metal atoms may diffuse. If there is a thickness non-uniformity across the first diffusion barrier layer 112C, the structural weakness may occur in a relatively thin area. Thus, by using the highly dense and highly uniform first diffusion barrier layer 112C, the concentration of metal atoms diffusing from the gate metal filling layer 112F through the first diffusion barrier layer 112C into the HK gate oxide layer 112B can be prevented or minimized, so as to improve device performance.

[0051] In some embodiments, the formation of the first diffusion barrier layer 112C may include the following sequential operations: (i) performing an ALD cycle (e.g., one ALD cycle) to deposit a metal nitride monolayer (not shown) on the HK gate oxide layer 112B; (ii) performing another ALD cycle (e.g., one ALD cycle) to deposit another metal nitride monolayer (not shown) on the underlying metal nitride monolayer in the ALD process; (iii) measuring the total thickness of the metal nitride layer deposited on the HK gate oxide layer 112B; (iv) determining whether the measured total thickness is equal to thickness T3; (v) if the measured total thickness is less than thickness T3, repeating steps (ii)-(iv); (vi) terminating the ALD process after reaching the thickness T3 of the metal nitride layer; and (vii) etching a horizontal portion of the metal nitride layer on the STI region 106 to form the first diffusion barrier layer 112C, as shown in FIG. Figure 4 and Figure 5 In some embodiments, the metal nitride layer can be evaluated to determine whether it is amorphous after each metal nitride monolayer is deposited.

[0052] In some embodiments, performing an ALD cycle to form each monolayer of a metal nitride layer (e.g., a TiN layer) may include the following sequential operations: (i) flowing a metal precursor gas (e.g., titanium tetrachloride (TiCl4)) onto the HK gate oxide layer 112B or onto a metal nitride monolayer formed in a previous ALD cycle; (ii) purging to flush out gas phase reactants; (iii) flowing a nitrogen precursor gas (e.g., ammonia (NH3)) to react with a chemically adsorbed metal precursor on the HK gate oxide layer 112B or on the metal nitride monolayer (e.g., TiN monolayer) formed in a previous ALD cycle and form a metal nitride monolayer; and (iv) purging byproducts (e.g., hydrogen chloride (HCl) gas and nitrogen (N) gas) formed during the reaction between the metal and nitrogen precursors. In some embodiments, the chemical reaction between the metal and nitrogen precursors may be represented by a chemical reaction formula: 6TiCl4+8NH3→6TiN+24HCl+4N2. In some embodiments, the first diffusion barrier layer 112C may be formed using a CVD process. The parameters of the CVD process (eg, RF power, DC power, and / or argon and nitrogen flow ratio) may be adjusted to achieve a higher density of the first diffusion barrier layer 112C than achieved in a PVD process.

[0053] refer to Figure 3 In operation 320, a polysilicon structure is formed on the first diffusion barrier layer. Figure 6 and Figure 7As described above, a polysilicon structure 612 is directly formed on the first diffusion barrier layer 112C. In some embodiments, the formation of the polysilicon structure 612 may include the following operations in sequence: (i) Figure 4 and (ii) performing a patterning process (eg, a photolithography process) on the polysilicon layer to form a polysilicon structure 612, such as Figure 6 and Figure 7 In some embodiments, a hard mask layer 624 may be formed during the formation of the polysilicon structure 612 .

[0054] refer to Figure 3 In operation 325, a gate spacer is formed along the sidewalls of the polysilicon structure and on the first diffusion barrier layer. Figure 8 and Fig. 9 As described above, a gate spacer 114 having spacers 114A and 114B is formed along the sidewalls of the polysilicon structure 612 and on the first diffusion barrier layer 112C. In some embodiments, the formation of the gate spacer 114 may include the following operations in sequence: (i) Figure 6 and Figure 7 A nitride layer 814A is deposited directly on the structure, such as Figure 8 (ii) directly depositing an oxide layer 814B on the nitride layer 814A to form Figure 8 (iii) Figure 8 (iv) etching the horizontal portion of the oxide layer 814B to form the spacer 114B, such as Fig. 9 and (v) etching the exposed portion of the dense nitride layer 814A after etching the oxide layer 814B to form a spacer 114A, such as Fig. 9 shown.

[0055] After forming the gate spacer 114, portions of the IL layer 112A, HK gate oxide layer 112B, and first diffusion barrier layer 112C that are not located below the polysilicon structure 612 and the spacer 114 may be removed, and a surface portion of the fin structure 108 may be exposed, as shown in FIG. Fig. 9 In some embodiments, portions of the IL layer 112A, the HK gate oxide layer 112B, and the first diffusion barrier layer 112C may be removed by a wet etching process or a dry etching process.

[0056] refer to Figure 3 In operation 330, S / D regions are formed on the fin structure. Fig.10 and Fig.11As described, the S / D region 110 is formed on the fin structure 108. In some embodiments, the formation of the S / D region 110 may include the following operations in sequence: (i) etching through Fig. 9 The exposed surface portion of the fin structure 108 is used to form the S / D opening 1010, such as Fig.10 and (ii) epitaxially growing a semiconductor material (eg, Si or SiGe) having an n-type or p-type dopant in the S / D opening 1010, as Fig.11 After forming the S / D region 110, an ESL 116 and an ILD layer 118 may be formed. Fig.11 shown.

[0057] See also Figure 3 In operation 335, the polysilicon structure is replaced with a second diffusion barrier layer, a WFM layer, and a gate metal filling layer. Fig.12 and Fig.13 As described, replacing the polysilicon structure 612 with the second diffusion barrier layer 112D, the WFM layer 112E, and the gate metal filling layer 112F. In some embodiments, replacing the polysilicon structure 612 with the second diffusion barrier layer 112D, the WFM layer 112E, and the gate metal filling layer 112F may include the following operations in sequence: (i) etching the polysilicon structure 612 to form a gate opening 1212, such as Fig.12 (ii) depositing a second diffusion barrier layer 112D in the gate opening 1212; (iii) depositing a WFM layer 112E on the second diffusion barrier layer 112D; (iv) depositing a gate metal filling layer 112F on the WFM layer 112E; and (v) performing a chemical mechanical polishing (CMP) process to make the top surfaces of the second diffusion barrier layer 112D, the WFM layer 112E, and the gate metal filling layer 112F substantially coplanar with the top surface of the ILD layer 118, as shown in FIG. Fig.13 shown.

[0058] The deposition of the second diffusion barrier layer 112D may include depositing another metal nitride layer (e.g., TaN) that is different from the metal nitride layer (e.g., TiN) of the first diffusion barrier layer 112C. Similar to the process of depositing the first diffusion barrier layer 112C, in some embodiments, the deposition of the second diffusion barrier layer 112D may include the following sequential operations: (i) performing an ALD cycle (e.g., one ALD cycle) to deposit a TaN monolayer (not shown) in the gate opening 1212; (ii) performing another ALD cycle (e.g., one ALD cycle) to deposit another TaN monolayer (not shown) on the underlying TaN monolayer; (iii) measuring the total thickness of the TaN layer deposited in the gate opening 1212; (iv) determining whether the measured total thickness is equal to thickness T4; (v) if the measured total thickness is less than thickness T4, repeating steps (ii)-(iv); (vi) terminating the ALD process after reaching thickness T4 of the TaN layer. In some embodiments, the TaN layer may be evaluated to determine whether it is amorphous after each monolayer is deposited. In some embodiments, the ALD cycle for depositing each TaN monolayer may be similar to the TiN monolayer deposited in operation 315 for the first diffusion barrier layer 112C, except that a Ta precursor is used instead of a Ti precursor (eg, TiCl 4 ). In some embodiments, the second diffusion barrier layer 112D may be formed using a CVD process.

[0059] The sequential deposition of the single layers may form a second diffusion barrier layer 112D having higher conformality and higher density (e.g., about 10% to about 50% higher density) than a similar metal nitride layer having the same thickness as the second diffusion barrier layer 112D formed in a PVD process. The higher density of the second diffusion barrier layer 112D may minimize the diffusion of metal atoms (e.g., Al atoms) from the gate metal fill layer 112F into the second diffusion barrier layer 112D and maintain the metal atom concentration in the second diffusion barrier layer 112D at or below about 50 atomic %. As a result, the higher density of the second diffusion barrier layer 112D, combined with the higher density of the first diffusion barrier layer 112C (described above), may minimize the metal atom concentration that diffuses from the gate metal fill layer 112F through the second diffusion barrier layer 112D into the first diffusion barrier layer 112C to or below about 10 atomic %.

[0060] refer to Figure 3 In operation 340, a gate capping layer is formed on the second diffusion barrier layer, the WFM layer, and the gate metal filling layer. Fig.14 and Fig.15As described, a gate capping layer having a conductive capping layer 112G and an insulating capping layer 112H is formed on the second diffusion barrier layer 112D, the WFM layer 112E, and the gate metal filling layer 112F. In some embodiments, the formation of the conductive capping layer 112G may include (i) etching the second diffusion barrier layer 112D, the WFM layer 112E, and the gate metal filling layer 112F to form an opening 1412, such as Fig.14 and (ii) depositing a conductive material of the conductive cover layer 112G in the opening 1412, such as Fig.15 In some embodiments, the formation of the insulating capping layer 112H may include: (i) depositing a material of the insulating capping layer 112H on the conductive capping layer 112G to fill the opening 1412; and (ii) performing a CMP process on the deposited material of the insulating capping layer 112H so that the top surface of the insulating capping layer 112H is substantially coplanar with the top surface of the ILD layer 118, as shown in FIG. Fig.15 shown.

[0061] refer to Figure 3 In operation 345, a contact structure may be formed on the S / D region and in the gate cap layer. Fig.16 As shown, an S / D contact structure 120 is formed on the S / D region 110 , and a gate contact structure 122 is formed in the conductive capping layer 112G and the insulating capping layer 112H.

[0062] In some embodiments, the above-referenced Figures 3 to 16 The method 300 forms a Figure 1C The semiconductor device 100 of the cross-sectional view of FIG. 1 is different in that (i) operation 320 may be performed after operation 310; (ii) a polysilicon structure 612 may be directly formed on the HK gate oxide layer 112B in operation 320, instead of directly forming the polysilicon structure 612 on the first diffusion barrier layer 112C in operation 320; and (iii) a spacer 114A may be directly formed on the HK gate oxide layer 112B in operation 325, instead of directly forming the spacer 114A on the first diffusion barrier layer 112C in operation 325. A, (iv) in operation 335, after removing the polysilicon structure 612 and before forming the second diffusion barrier layer 112D, a first diffusion barrier layer 112C may be formed in the gate opening 1212 instead of forming the first diffusion barrier layer 112C in operation 315; and (v) in operation 340, a conductive capping layer 112G may be formed directly on the first diffusion barrier layer 112C, and a conductive capping layer 112G may be formed directly on the second diffusion barrier layer 112D, the WFM layer 112E and the gate metal filling layer 112F.

[0063] In some embodiments, the above reference may be used Figures 3 to 16 The method 300 forms a Figure 1D The semiconductor device 100 of the cross-sectional view is shown in FIG. 3 , except that (i) portions of the IL layer 112A, the HK gate oxide layer 112B, and the first diffusion barrier layer 112C that are not located below the polysilicon structure 612 and the spacers 114A and 114B may be removed after the polysilicon structure 612 is formed in operation 320, instead of being removed after the spacers 114A and 114B are formed in operation 325; and (ii) the spacer 114A may be formed directly on the fin structure 108 in operation 325, instead of forming the spacer 114A directly on the first diffusion barrier layer 112C in operation 325.

[0064] Fig.17 is manufactured according to some embodiments having Figure 2A 1700 of an exemplary method of a semiconductor device 200 of a cross-sectional view. For the purpose of illustration, reference will be made to Figures 18 to 22 The exemplary manufacturing process of manufacturing the semiconductor device 200 is described as follows. Fig.17 The operations shown in . Figures 18 to 22 1700 is a cross-sectional view of a semiconductor device 200 at various stages of manufacturing the semiconductor device 200 according to some embodiments. Depending on the specific application, the operations may be performed in a different order or not performed. It should be noted that the method 1700 may not produce a complete semiconductor device 200. Accordingly, it is understood that additional processes may be provided before, during, and after the method 1700, and some other processes may only be briefly described herein. Unless otherwise mentioned, Figure 2A , Figure 2B and Figures 18 to 22 The discussion of elements having the same reference numerals applies to each other.

[0065] refer to Fig.17 In operation 1705, a first oxide layer and a second oxide layer are formed on the substrate. Fig.18 As described, an IL layer 212A (also referred to as a “first oxide layer 212A”) and a HK gate oxide layer 212B (also referred to as a “second oxide layer 212B”) are formed on the substrate 204. In some embodiments, the process of forming the IL layer 212A and the HK gate oxide layer 212B can be the same as that described in reference to Figures 3 to 5 The processes for forming the IL layer 112A and the HK gate oxide layer 112B in operation 310 are respectively the same.

[0066] See also Fig.17 In operation 1710, a first diffusion barrier layer is formed on the second oxide layer. Fig.18As described above, a first diffusion barrier layer 212C is formed on the HK gate oxide layer 212B. In some embodiments, the process of forming the first diffusion barrier layer 212C can be the same as that described in reference to Figures 3 to 5 The process of forming the first diffusion barrier layer 112C in operation 315 is the same as described above. After forming the first diffusion barrier layer 212C, the STI region 206 may be formed, such as Fig.19 shown.

[0067] See also Fig.17 In operation 1715, a polysilicon structure is formed on the first diffusion barrier layer. Fig.19 As shown, a polysilicon structure 1912 is formed directly on the first diffusion barrier layer 212C.

[0068] See also Fig.17 In operation 1720, S / D regions are formed in the substrate. For example, as shown in FIG. Fig. 20 As described, the S / D region 210 is formed in the substrate 204. In some embodiments, the formation of the S / D region 210 may include forming a doped region in the substrate 204 by performing a doping process in the substrate 204 through the first oxide layer 212A and the second oxide layer 212B and the first diffusion barrier layer 212C.

[0069] See also Fig.17 In operation 1725, a gate spacer is formed along the sidewalls of the polysilicon structure and on the first diffusion barrier layer. Fig. 20 As shown, a gate spacer 214 is formed along the sidewall of the polysilicon structure 1912 and on the first diffusion barrier layer 212C. An ILD layer 218 may be formed after forming the gate spacer 214. Fig. 20 shown.

[0070] See also Fig.17 In operation 1730, the polysilicon structure is replaced with a second diffusion barrier layer, a WFM layer, and a gate metal filling layer. Fig.21 and Fig. 22 As described, replacing the polysilicon structure 1912 with the second diffusion barrier layer 212D, the WFM layer 212E, and the gate metal filling layer 212F. In some embodiments, replacing the polysilicon structure 1912 with the second diffusion barrier layer 212D, the WFM layer 212E, and the gate metal filling layer 212F may include the following operations in sequence: (i) etching the polysilicon structure 1912 to form a gate opening 2112, such as Fig.21(ii) depositing a second diffusion barrier layer 212D in the gate opening 2112; (iii) depositing a WFM layer 212E on the second diffusion barrier layer 212D; (iv) depositing a gate metal filling layer 212F on the WFM layer 212E; and (v) performing a CMP process to make the top surfaces of the second diffusion barrier layer 212D, the WFM layer 212E, and the gate metal filling layer 212F substantially coplanar with the top surface of the ILD layer 218, as shown in FIG. Fig. 22 shown.

[0071] In some embodiments, the above-referenced Figures 17 to 22 The method 1700 is used to form a Figure 2B The semiconductor device 200 of the cross-sectional view is different in that (i) operation 1715 can be performed after operation 1705; (ii) a polysilicon structure 1912 can be directly formed on the HK gate oxide layer 212B in operation 1715, instead of directly forming the polysilicon structure 1912 on the first diffusion barrier layer 212C in operation 1710; (iii) a spacer 214 can be directly formed on the HK gate oxide layer 212B in operation 1725, instead of directly forming the spacer 214 on the first diffusion barrier layer 212C in operation 1725; and (iv) a first diffusion barrier layer 212C can be formed in the gate opening 2112 in operation 1730, after removing the polysilicon structure 1912 and before forming the second diffusion barrier layer 212D, instead of forming the first diffusion barrier layer 212C in operation 1710.

[0072] The present disclosure provides exemplary gate structures (e.g., gate structures 112 and 212) with diffusion barriers (e.g., diffusion barriers 112C, 112D, 212C, and 212D) in FETs (e.g., FinFETs 100 and MOSFETs 200), and exemplary methods of forming such FETs (e.g., methods 300 and 1700) to improve threshold voltage control in the FETs. In some embodiments, the exemplary gate structure of the FET may include a high-k gate oxide layer (e.g., high-k gate oxide layer 112B or 212B), a first diffusion barrier layer and a second diffusion barrier layer (e.g., first diffusion barrier layer 112C and second diffusion barrier layer 112D or first diffusion barrier layer 212C and second diffusion barrier layer 212D) disposed on the high-k gate oxide layer, and a gate metal fill layer (e.g., gate metal fill layer 112F or 212F) disposed on the first diffusion barrier layer and the second diffusion barrier layer. In some embodiments, the first diffusion barrier layer and the second diffusion barrier layer may be arranged to prevent or minimize metal atoms (e.g., Al atoms) from diffusing from the gate metal fill layer to the high-k gate oxide layer. The presence of such diffused metal atoms in the high-k gate oxide layer may cause the threshold voltage in the FET to change and thereby deteriorate device performance. In some embodiments, the first diffusion barrier layer may be formed to have an amorphous structure and a structural density that may limit the concentration of metal atoms diffused from the gate metal fill layer into the first diffusion barrier layer to about 10 atomic % or less. Similarly, the second diffusion barrier layer may be formed to have an amorphous structure and a structural density that may limit the concentration of metal atoms diffused from the gate metal fill layer into the second diffusion barrier layer to between about 10 atomic % and about 50 atomic %. Within these concentration limits, metal atoms may be prevented or minimized from diffusing into the high-k gate oxide layer.

[0073] In some embodiments, a semiconductor device includes a substrate, a fin structure disposed on the substrate, and a gate structure. The gate structure includes a high-k gate oxide layer disposed on the fin structure, a diffusion barrier layer disposed on the high-k gate oxide layer, and a metal layer disposed on the diffusion barrier layer. The semiconductor device also includes a gate spacer disposed on the diffusion barrier layer and an S / D region disposed on the fin structure. The sidewall of the S / D region contacts the sidewall of the high-k gate oxide layer.

[0074] In some embodiments, a semiconductor device includes a substrate and a gate structure. The gate structure includes an oxide layer disposed on the substrate, a diffusion barrier layer disposed on the oxide layer, and a metal layer disposed on the diffusion barrier layer. The semiconductor device also includes a gate spacer disposed on the diffusion barrier layer and an S / D region disposed in the substrate. The top surface of the S / D region contacts the bottom surface of the oxide layer.

[0075] In some embodiments, a semiconductor device is provided, the semiconductor device comprising: a substrate; a fin structure disposed on the substrate; a gate structure, the gate structure comprising: a high-k gate oxide layer disposed on the fin structure, a first diffusion barrier layer disposed on the high-k gate oxide layer, and a metal layer disposed on the first diffusion barrier layer; a gate spacer disposed on the first diffusion barrier layer; and a source / drain (S / D) region disposed on the fin structure, wherein the sidewalls of the S / D region contact the sidewalls of the high-k gate oxide layer. In some embodiments, the gate spacer is disposed on the top surface of the first diffusion barrier layer. In some embodiments, the gate spacer is disposed on the top surface of the high-k gate oxide layer and along the sidewalls of the first diffusion barrier layer. In some embodiments, the gate spacer is disposed on a first top surface portion of the first diffusion barrier layer, and wherein the metal layer is disposed on a second top surface portion of the first diffusion barrier layer. In some embodiments, a horizontal portion of the gate spacer is disposed on the first diffusion barrier layer, and wherein a vertical portion of the gate spacer is disposed on the metal layer. In some embodiments, a horizontal portion of the gate spacer is disposed on the high-k gate oxide layer, and wherein a vertical portion of the gate spacer is disposed on the first diffusion barrier layer. In some embodiments, the semiconductor device further comprises a second diffusion barrier layer disposed on the first diffusion barrier layer, wherein: a horizontal portion of the gate spacer is disposed on the first diffusion barrier layer; and a vertical portion of the gate spacer is disposed on the second diffusion barrier layer. In some embodiments, the first diffusion barrier layer comprises a U-shaped cross-sectional profile. In some embodiments, the semiconductor device further comprises an etch stop layer disposed on the S / D region, wherein a sidewall of the etch stop layer contacts a sidewall of the first diffusion barrier layer. In some embodiments, the first diffusion barrier layer comprises a metal dopant having a concentration of about 1 atomic % to about 10 atomic %.

[0076] In some embodiments, a semiconductor device is provided, the semiconductor device comprising: a substrate; a gate structure, the gate structure comprising: an oxide layer disposed on the substrate, a first diffusion barrier layer disposed on the oxide layer, and a metal layer disposed on the first diffusion barrier layer; a gate spacer disposed on the first diffusion barrier layer; and a source / drain (S / D) region disposed in the substrate, wherein the top surface of the S / D region is disposed below the oxide layer. In some embodiments, the semiconductor device further comprises a high-k oxide layer disposed between the oxide layer and the first diffusion barrier layer. In some embodiments, the gate spacer is disposed on the top surface of the first diffusion barrier layer. In some embodiments, the gate spacer is disposed on the top surface of the oxide layer and along the sidewall of the first diffusion barrier layer. In some embodiments, the first diffusion barrier layer comprises a titanium nitride layer and an aluminum dopant disposed in the titanium nitride layer. In some embodiments, the semiconductor device further comprises a second diffusion barrier layer disposed on the first diffusion barrier layer, wherein the second diffusion barrier layer comprises a tantalum nitride layer and an aluminum dopant disposed in the tantalum nitride layer.

[0077] In some embodiments, a method includes forming a first oxide layer and a second oxide layer on a substrate, forming a first diffusion barrier layer on the second oxide layer, forming a polysilicon structure on the first diffusion barrier layer, forming a gate spacer on the first diffusion barrier layer and on the polysilicon structure, and replacing the polysilicon structure with the second diffusion barrier layer and a metal layer. In some embodiments, forming the first diffusion barrier layer includes depositing a metal nitride monolayer on the second oxide layer. In some embodiments, forming the first diffusion barrier layer includes depositing an amorphous metal nitride layer on the second oxide layer. In some embodiments, the method also includes doping a region in the substrate through the first oxide layer, the second oxide layer, and the first diffusion barrier layer to form a source / drain region.

[0078] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, comprising: substrate; A fin structure is disposed on the substrate; The gate structure includes: A high-k gate oxide layer is disposed on the fin structure, a first diffusion barrier layer disposed on the high-k gate oxide layer, and a metal layer, disposed on the first diffusion barrier layer; a gate spacer disposed on the first diffusion barrier layer; and A source / drain region is disposed on the fin structure, wherein a sidewall of the source / drain region contacts a sidewall of the high-k gate oxide layer.

2. The semiconductor device according to claim 1, wherein The gate spacer is disposed on a top surface of the first diffusion barrier layer.

3. The semiconductor device according to claim 1, wherein The gate spacer is disposed on a top surface of the high-k gate oxide layer and along a sidewall of the first diffusion barrier layer.

4. The semiconductor device according to claim 1, wherein: The gate spacer is disposed on a first top surface portion of the first diffusion barrier layer, and Wherein, the metal layer is disposed on a second top surface portion of the first diffusion barrier layer.

5. The semiconductor device according to claim 1, wherein A horizontal portion of the gate spacer is disposed on the first diffusion barrier layer, and Wherein, the vertical portion of the gate spacer is disposed on the metal layer.

6. The semiconductor device according to claim 1, wherein A horizontal portion of the gate spacer is disposed on the high-k gate oxide layer, and Wherein, a vertical portion of the gate spacer is disposed on the first diffusion barrier layer.

7. The semiconductor device according to claim 1, further comprising a second diffusion barrier layer disposed on the first diffusion barrier layer, wherein: A horizontal portion of the gate spacer is disposed on the first diffusion barrier layer; and A vertical portion of the gate spacer is disposed on the second diffusion barrier layer.

8. The semiconductor device according to claim 1, wherein The first diffusion barrier layer includes a U-shaped cross-sectional profile.

9. A semiconductor device comprising: substrate; The gate structure includes: an oxide layer disposed on the substrate, a first diffusion barrier layer disposed on the oxide layer, and a metal layer, disposed on the first diffusion barrier layer; a gate spacer disposed on the first diffusion barrier layer; and A source / drain region is disposed in the substrate, wherein a top surface of the source / drain region is disposed below the oxide layer.

10. A method for manufacturing a semiconductor device, comprising: forming a first oxide layer and a second oxide layer on the substrate; forming a first diffusion barrier layer on the second oxide layer; forming a polysilicon structure on the first diffusion barrier layer; forming a gate spacer on the first diffusion barrier layer and on the polysilicon structure; as well as The polysilicon structure is replaced with a second diffusion barrier layer and a metal layer.

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