High-end semiconductor chip and manufacturing method thereof

Abstract

The invention belongs to the technical field of semiconductor chips, and particularly relates to a high-end semiconductor chip and a manufacturing method thereof.The cellular structure of a transverse semiconductor device of the semiconductor chip comprises a device active layer, and the device active layer comprises a source region, a drift region and a drain region which are sequentially arranged in the transverse direction of the semiconductor device; a gate region is arranged above one side, close to the drift region, of the source region, the field plate structure is arranged in the length direction of the drift region, the two ends of the field plate structure are connected with a gate and a drain respectively, the field plate structure comprises a plurality of semiconductor substrates, and included angles exist between the semiconductor substrates and the horizontal line. The multiple field plate units are sequentially connected in the transverse direction of the device and are in a continuous tooth shape, so that the passing path of impurity atoms between the drain electrode and the grid electrode is longer, the doping concentration in a field plate structure area is smaller, the resistivity of a drift region is increased in a disguised mode, the carrier mobility can be reduced by arranging the field plate structure, and the breakdown voltage of the device is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor chips, and in particular relates to a high-end semiconductor chip and a method for manufacturing the same. Background Art

[0002] With the development of integrated circuit technology and applications, power semiconductor devices, as the core components of power integrated circuits (Power Integrated Circuit), have the capabilities of rectification, inversion, frequency conversion and power amplification, and are widely used in new energy, smart home appliances, the Internet of Things and other fields.

[0003] Power semiconductor devices are one of the core devices in power electronic circuits and are widely used in motor drives, automobiles, power supplies, etc. In addition to the active area for conducting current, power devices also include a non-active area (i.e., terminal area) located outside the active area. The terminal area is used to alleviate the junction curvature effect to ensure the breakdown voltage of the active area, prevent the device from breaking down at the edge of the chip, and ensure that the device is not affected by the outside world in harsh working environments. As a power semiconductor device, the lateral diffused metal oxide semiconductor device has the characteristics of high reliability, high integration and fast switching speed, and is widely used in power integrated circuits such as gate driver integrated circuits, analog switch integrated circuits and power management integrated circuits. Traditional lateral semiconductor devices increase the device breakdown voltage by reducing the doping concentration of the drift region, that is, increasing the resistivity of the drift region, but this will cause a sharp increase in the on-resistance of the device. The withstand voltage of lateral semiconductor devices is mainly borne by the reverse biased PN junction inside the device in the off state. The field plate structure can be used to reduce the electric field peak of the reverse biased PN junction, thereby increasing the breakdown voltage of the device. However, the breakdown voltage of the LDMOS with a traditional field plate structure is still not high enough, and the breakdown voltage is also affected by the processing technology and the resistivity of the drift region, and is greatly affected by process fluctuations, resulting in a smaller process window for LDMOS and increased manufacturing difficulty.

[0004] The super junction is introduced into the lateral SOI power MOSFET (SOILDMOS), which reduces the on-resistance while improving the withstand voltage; however, in order to obtain high-performance super junction SOILDMOS, it is difficult to achieve. First, the electrical performance of the "super junction" device is very sensitive to charge imbalance, and the width and concentration of the P column area and the N column area must be precisely controlled in the process, otherwise the electrical performance of the device will be degraded; secondly, in order to obtain better electrical performance, the P column area and the N column area need to have a large depth-to-width ratio, that is, multiple epitaxy, multiple injections and annealing are used. Both of the above points increase the difficulty and cost of the process. Thirdly, the super junction SOILDMOS has a substrate-assisted depletion effect, which affects the charge balance between the P column area and the N column area, resulting in a decrease in the breakdown voltage. Summary of the invention

[0005] In view of the above-mentioned deficiencies in the prior art, the present invention provides a high-end semiconductor chip and a manufacturing method thereof to solve the problems in the above-mentioned background technology.

[0006] In order to solve the above technical problems, the present invention adopts the following technical solutions: A high-end semiconductor chip, the cell structure of its lateral semiconductor device includes an insulating dielectric layer, a semiconductor substrate located below the insulating dielectric layer, and a device active layer located above the insulating dielectric layer, wherein the device active layer includes a source region, a drift region, and a drain region arranged in sequence along the lateral direction of the semiconductor device, a gate region is arranged above the side of the source region close to the drift region, and also includes a field plate structure arranged along the length direction of the drift region, the two ends of the field plate structure are respectively connected to the gate and the drain, and the field plate structure includes a plurality of semiconductor substrates, and there is an angle between the semiconductor substrates and the horizontal line, that is, the semiconductor substrates are not arranged horizontally.

[0007] Furthermore, a plurality of semiconductor substrates are grouped in pairs to form a field plate unit, the two semiconductor substrates of the field plate unit are arranged in parallel one behind the other, and the plurality of field plate units are sequentially connected along the lateral direction of the device to form a continuous tooth shape.

[0008] Furthermore, the angle between two adjacent field plate units is a right angle, and the angle between the semiconductor substrate and the horizontal line is 45°.

[0009] Furthermore, an interlayer dielectric layer is provided between the semiconductor substrates at the connection between two adjacent field plate units.

[0010] Furthermore, the material of the interlayer dielectric layer is an insulating material.

[0011] Furthermore, the semiconductor substrate at both ends of the field plate structure is respectively connected to the gate and the drain through contact holes.

[0012] Furthermore, there are multiple field plate structures, and the multiple field plate structures are arranged in parallel one after the other.

[0013] Furthermore, the lateral semiconductor device is a lateral diffused metal oxide semiconductor device or a lateral insulated gate bipolar transistor.

[0014] A method for manufacturing a lateral semiconductor device, comprising: S1: providing a semiconductor substrate, and forming a drift region, a well region, a source region, and a drain region on the semiconductor substrate; S2: etching a trench in the drift region so that the bottom of the trench is in contact with the semiconductor substrate, thermally growing an oxide layer in the trench, etching the oxide layer, and retaining the oxide layer at the bottom and sidewall of the trench as a field oxygen dielectric layer; S3: forming a polysilicon gate in the trench; S4: bonding field plate structure on the surface of the trench; S5: Depositing metal in the source region and the drain region to form a source metal electrode and a drain metal electrode.

[0015] Compared with the prior art, the present invention has the following beneficial effects: when the lateral semiconductor device of the chip is working, when the device is subjected to reverse voltage, the potential of the source electrode and the gate is zero, the drain is at a high potential, and the drain is reversely transmitted to the gate through the field plate structure. Due to the strong coupling between the two semiconductor substrates of the field plate unit, the high potential of the drain can be evenly distributed in the entire drift region, thereby modulating the surface and internal electric field of the drift region, and avoiding the premature breakdown of the drift region to cause the device breakdown voltage to decrease. A plurality of field plate units are connected in sequence along the lateral direction of the device, forming a continuous tooth shape, so that the distance that the impurity atoms pass between the drain and the gate is longer. Compared with the straight-line distance, when the number of impurity atoms doped is the same, the doping concentration in the field plate structure area is smaller, and the resistivity of the drift region is increased in disguise. Compared with directly reducing the doping concentration of the drift region, the field plate structure can reduce the carrier mobility and improve the breakdown voltage of the device. In addition, the semiconductor substrate is used as a field plate structure to avoid the load effect existing in the surface field plate formation process, so that the semiconductor device can achieve a more efficient and reliable terminal structure design. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A front view of a lateral semiconductor device of a high-end semiconductor chip of the present invention; Figure 2 A schematic structural diagram of a lateral semiconductor device of a high-end semiconductor chip of the present invention; Figure 3 A top view of a lateral semiconductor device of a high-end semiconductor chip of the present invention; Figure 4 It is a top view of a lateral semiconductor device of a high-end semiconductor chip provided by the second embodiment of the present invention; Figure 5 is a flow chart of a method for manufacturing a lateral semiconductor device provided by an embodiment of the present invention; The reference numerals in the drawings of the specification include: Semiconductor substrate (100), insulating dielectric layer (200), source region (300), P-type body region (301), P-type body contact region (302), N-type source region (303), source electrode S (304), gate (400), gate dielectric (401), polysilicon gate (402), drift region (500), drain region (600), drain (601), field plate structure (700), field plate unit (701), semiconductor substrate (702), and interlayer dielectric layer (703). DETAILED DESCRIPTION

[0017] The present invention will be described in detail below with reference to the accompanying drawings.

[0018] The embodiment of the present invention provides a high-end semiconductor chip, wherein the cell structure of the lateral semiconductor device includes an insulating dielectric layer, a substrate located below the insulating dielectric layer and in contact with the insulating dielectric layer, and a device active layer located above the insulating dielectric layer and in contact with the insulating dielectric layer; the device active layer includes a source region structure, a gate structure, a drift region structure, and a drain region structure in sequence along the lateral direction of the device; the drift region structure includes a field plate structure connected to the gate structure and the drain region structure, and the field plate structure includes a plurality of semiconductor substrates arranged obliquely formed on the substrate, wherein each two of the plurality of semiconductor substrates are grouped together to form a field plate unit, wherein the two semiconductor substrates of the field plate unit are parallel to each other, and the plurality of field plate units are sequentially connected along the lateral direction of the device to form a continuous tooth shape. The angle between two adjacent field plate units is a right angle. The present invention arranges a plurality of continuously connected field plate units in the drift region, connects the gate and the drain through the field plate units, and when the device is subjected to reverse voltage, the drain is reversely transmitted to the gate through the continuous field plate units. Since the two semiconductor substrates of the field plate units are parallel to each other and tilted, and the angle between the two adjacent field plate units is a right angle, the field strengths in the two adjacent field plate units are of the same magnitude and perpendicular to each other, and the combined field strength direction of the two adjacent field plate units is horizontally parallel to the field strength direction in the drift region, thereby modulating the electric field on the surface and inside of the drift region, so that the electric field peak value of the drift region is effectively reduced, and the breakdown voltage is improved. At the same time, the substrate-assisted depletion effect is weakened, the drift region ion doping process window is expanded, and the manufacturing difficulty of the lateral semiconductor device is reduced.

[0019] Embodiment 1: like Figure 1-3As shown, a high-end semiconductor chip of the present invention has a cellular structure of a lateral semiconductor device including an insulating dielectric layer 200, a semiconductor substrate 100 located below the insulating dielectric layer 200, and a device active layer located above the insulating dielectric layer 200, wherein the device active layer includes a source region 300, a drift region 500, and a drain region 600 arranged in sequence along the lateral direction of the semiconductor device, a gate region 400 is arranged above the source region 300 near the drift region 500, and also includes a field plate structure 700 arranged along the length direction of the drift region 500, and the field plate structure 700 includes a plurality of semiconductor substrates 702, and there is an angle between the semiconductor substrate 702 and the horizontal line, that is, the semiconductor substrate 702 is not arranged horizontally, and the angle is not equal to 90°. A plurality of semiconductor substrates are divided into a group of two to form a field plate unit 701, and the two semiconductor substrates of the field plate unit are parallel to each other one after the other, and the plurality of field plate units 701 are connected in sequence along the lateral direction of the device, forming a continuous tooth shape, and the two ends of the field plate structure 700 are respectively connected to the gate 400 and the drain 601. An interlayer dielectric layer 703 is provided between the semiconductor substrate 702 at the connection of two adjacent field plate units 701. The angle between the two adjacent field plate units 701 is a right angle, and the angle between the semiconductor substrate 702 and the horizontal line is 45°. The field strengths in the two adjacent field plate units are of the same magnitude and perpendicular to each other, and the combined field strength direction in the two adjacent field plate units is horizontally parallel to the field strength direction in the drift region, thereby modulating the electric field on the surface and inside of the drift region, so that the electric field peak value of the drift region is effectively reduced and the breakdown voltage is improved. The resistivity of the semiconductor substrate 702 is 0.002 to 1000Ω.cm, and the thickness is 5 to 800μm. The interlayer dielectric layer 703 can be an insulating material such as silicon dioxide or silicon nitride, and its thickness is 0.01um to 5um. The semiconductor substrate 702 is connected to the gate 400 and the drain 601 through a contact hole.

[0020] When the lateral semiconductor device of the high-end semiconductor chip provided in this embodiment is working, when the device is subjected to reverse voltage, the potential of the source electrode S304 and the gate 400 is zero, the drain 601 is at a high potential, and the drain reversely transmits the potential to the gate 400 through the field plate structure 700. Due to the strong coupling between the two semiconductor substrates 702 of the field plate unit 701, the high potential of the drain can be evenly distributed in the entire drift region, thereby modulating the surface and internal electric fields of the drift region, and avoiding the drift region from being broken down prematurely, causing the breakdown voltage of the device to decrease. Multiple field plate units 701 are connected in sequence along the lateral direction of the device in a continuous tooth shape, so that the distance for impurity atoms to pass between the drain 601 and the gate 400 is longer. Compared with the straight-line distance, when the number of impurity atoms doped is the same, the doping concentration in the field plate structure 700 area is smaller, which increases the resistivity of the drift region in disguise. Compared with directly reducing the doping concentration of the drift region, by setting the field plate structure 700, the carrier mobility can be reduced and the breakdown voltage of the device can be improved. In addition, the semiconductor substrate serves as a field plate structure to avoid the load effect existing in the surface field plate formation process, so that the semiconductor device can achieve a more efficient and reliable terminal structure design.

[0021] Embodiment 2: like Figure 4As shown, the present invention is a high-end semiconductor chip, and the cell structure of the lateral semiconductor device includes an insulating dielectric layer 200, a semiconductor substrate 100 located below the insulating dielectric layer 200, and a device active layer located above the insulating dielectric layer 200, wherein the device active layer includes a source region 300, a drift region 500 and a drain region 600 arranged in sequence along the lateral direction of the semiconductor device, a gate region 400 is arranged above the side of the source region 300 close to the drift region 500, and also includes a field plate structure 700 arranged along the length direction of the drift region 500, the number of the field plate structures 700 is multiple, and the multiple field plate structures 700 are arranged in parallel one after the other, and the field plate structure 700 includes a plurality of semiconductor substrates 702, and there is an angle between the semiconductor substrate 702 and the horizontal line, that is, the semiconductor substrate 702 is not arranged horizontally, and the angle is not equal to 90°. A plurality of semiconductor substrates are grouped into two to form a field plate unit 701. The two semiconductor substrates of the field plate unit are parallel to each other, one in front of the other. The multiple field plate units 701 are connected in sequence along the lateral direction of the device, forming a continuous tooth shape. The two ends of the field plate structure 700 are respectively connected to the gate 400 and the drain 601. An interlayer dielectric layer 703 is provided between the semiconductor substrates 702 at the connection of two adjacent field plate units 701. The material of the interlayer dielectric layer 703 is an insulating material. The angle between the two adjacent field plate units 701 is a right angle, and the angle between the semiconductor substrate 702 and the horizontal line is 45°. The field strengths in the two adjacent field plate units are of the same magnitude and perpendicular to each other. The combined field strength direction in the two adjacent field plate units is horizontal and parallel to the field strength direction in the drift region, thereby modulating the electric field on the surface and inside of the drift region, so that the electric field peak value of the drift region is effectively reduced and the breakdown voltage is improved. The resistivity of the semiconductor substrate 702 is 0.002-1000Ω.cm, and the thickness is 5-800μm. The interlayer dielectric layer 703 can be made of insulating materials such as silicon dioxide or silicon nitride, and the thickness is 0.01um-5um. The semiconductor substrate 702 is connected to the gate 400 and the drain 601 through contact holes.

[0022] When the lateral semiconductor device of the high-end semiconductor chip provided in this embodiment is working, when the device is subjected to reverse voltage, the potential of the source electrode S304 and the gate 400 is zero, the drain 601 is at a high potential, and the drain reversely transmits the potential to the gate 400 through the field plate structure 700. Due to the strong coupling between the two semiconductor substrates 702 of the field plate unit 701, the high potential of the drain can be evenly distributed in the entire drift region, thereby modulating the surface and internal electric fields of the drift region, and avoiding the drift region from being broken down prematurely, causing the breakdown voltage of the device to decrease. Multiple field plate units 701 are connected in sequence along the lateral direction of the device, forming a continuous tooth shape, so that the distance for impurity atoms to pass between the drain 601 and the gate 400 is longer. Compared with the straight-line distance, when the number of impurity atoms doped is the same, the doping concentration in the field plate structure 700 area is smaller, which increases the resistivity of the drift region in disguise. Compared with directly reducing the doping concentration of the drift region, it can reduce the carrier mobility and improve the breakdown voltage of the device. In addition, the semiconductor substrate is used as a field plate structure to avoid the load effect existing in the surface field plate formation process, so that the semiconductor device can achieve a more efficient and reliable terminal structure design. By setting multiple field plate structures 700 to form multiple carrier migration channels, the performance is better than setting one field plate structure 700.

[0023] In the above embodiments of the present invention, the lateral semiconductor device may be a lateral diffused metal oxide semiconductor device (LDMOS), a lateral insulated gate bipolar transistor (L-IGBT) or a lateral super junction insulated gate bipolar transistor (L-SJ-IGBT), or a device structure of other wide bandgap semiconductor materials such as GaN and SiC.

[0024] The method for manufacturing a lateral semiconductor device provided in the present application comprises at least the following steps: S1: providing a semiconductor substrate, and forming a drift region, a well region, a source region, and a drain region on the semiconductor substrate; S2: etching a trench in the drift region so that the bottom of the trench is in contact with the semiconductor substrate, thermally growing an oxide layer in the trench, etching the oxide layer, and retaining the oxide layer at the bottom and sidewall of the trench as a field oxygen dielectric layer; S3: forming a polysilicon gate in the trench; S4: bonding field plate structure on the surface of the trench; S5: Depositing metal in the source region and the drain region to form a source metal electrode and a drain metal electrode.

[0025] In the above step S1, a drift region is formed on a semiconductor substrate by epitaxy; a region of a well region is defined by photolithography on a semiconductor substrate, and boron ions are implanted and annealed at high temperature to form a well region; a region of a source region and a drain region is defined by photolithography on a semiconductor substrate, and arsenic ions are implanted and pushed to form an N+ region of the source and drain. Alternatively, after forming the source region and the drain region, a region of a collector is defined by photolithography on a semiconductor substrate, and boron ions are implanted, and an annealing process is performed to form a P+ contact region (i.e., a P+ collector).

[0026] In a specific embodiment, the semiconductor substrate may be a FZ or CZ wafer, or a SOI substrate. The SOI substrate includes an isolation oxide layer, on which structures such as a drift region, a well region, a source region, and a drain region are formed.

[0027] In the above step S3, a gate oxide layer is grown by thermal oxidation on the substrate, a dielectric material (silicon dioxide or silicon nitride) is deposited in the trench to form an interlayer dielectric, the interlayer dielectric is etched to form a contact hole and boron ions are implanted; polysilicon is deposited, and the polysilicon is etched to form a polysilicon gate.

[0028] In the above step S3, the bonding method is permanent bonding, for example, it can be achieved by hybrid bonding.

[0029] The above are only embodiments of the present invention, and the circuits, electronic components and modules involved are all prior art, which can be fully implemented by those skilled in the art. It is needless to say that the content protected by this application does not involve improvements to software and methods. The common sense such as the known specific structures and characteristics in the scheme is not described in detail here. Ordinary technicians in the relevant field know all the common technical knowledge in the technical field of the invention before the application date or priority date, can obtain all the prior art in the field, and have the ability to apply conventional experimental means before that date. Ordinary technicians in the relevant field can improve and implement this scheme in combination with their own abilities under the enlightenment given by this application. Some typical known structures or known methods should not become obstacles for ordinary technicians in the relevant field to implement this application. It should be pointed out that for those skilled in the art, without departing from the structure of the present invention, several deformations and improvements can be made, which should also be regarded as the scope of protection of the present invention, and these will not affect the effect of the implementation of the present invention and the practicality of the patent.

Claims

1. A high-end semiconductor chip, wherein the cell structure of a lateral semiconductor device comprises an insulating dielectric layer (200), a semiconductor substrate (100) located below the insulating dielectric layer (200), and a device active layer located above the insulating dielectric layer (200), wherein the device active layer comprises a source region (300), a drift region (500), and a drain region (600) sequentially arranged along the lateral direction of the semiconductor device, and a gate region (400) is arranged above the source region (300) on a side close to the drift region (500), characterized in that: It also includes a field plate structure (700) arranged along the length direction of the drift region (500), the two ends of the field plate structure (700) are respectively connected to the gate (400) and the drain (601), and the field plate structure (700) includes a plurality of semiconductor substrates (702), and an angle exists between the semiconductor substrates (702) and the horizontal line.

2. A high-end semiconductor chip as claimed in claim 1, characterized in that: A plurality of semiconductor substrates are grouped in pairs to form a field plate unit (701), the two semiconductor substrates of the field plate unit are arranged in parallel, one behind the other, and the plurality of field plate units (701) are connected in sequence along the lateral direction of the device to form a continuous tooth shape.

3. A high-end semiconductor chip as claimed in claim 2, characterized in that: The angle between two adjacent field plate units (701) is a right angle, and the angle between the semiconductor substrate (702) and the horizontal line is 45°.

4. A high-end semiconductor chip as claimed in claim 3, characterized in that: An interlayer dielectric layer (703) is provided between the semiconductor substrates (702) at the connection between two adjacent field plate units (701).

5. A high-end semiconductor chip as claimed in claim 4, characterized in that: The material of the interlayer dielectric layer (703) is an insulating material.

6. A high-end semiconductor chip as claimed in claim 5, characterized in that: The semiconductor substrate (702) at both ends of the field plate structure (700) is respectively connected to the gate (400) and the drain (601) through contact holes.

7. A high-end semiconductor chip as claimed in claim 1, characterized in that: There are a plurality of field plate structures (700), and the plurality of field plate structures (700) are arranged in parallel, one behind the other.

8. A high-end semiconductor chip as claimed in claim 1, characterized in that: The lateral semiconductor device is a lateral diffused metal oxide semiconductor device or a lateral insulated gate bipolar transistor.

9. A method for manufacturing a lateral semiconductor device, characterized in that: The lateral semiconductor device is the lateral semiconductor device according to claim 1, and the method comprises: S1: providing a semiconductor substrate, and forming a drift region, a well region, a source region, and a drain region on the semiconductor substrate; S2: etching a trench in the drift region so that the bottom of the trench is in contact with the semiconductor substrate, thermally growing an oxide layer in the trench, etching the oxide layer, and retaining the oxide layer at the bottom and sidewall of the trench as a field oxygen dielectric layer; S3: forming a polysilicon gate in the trench; S4: bonding field plate structure on the surface of the trench; S5: Depositing metal in the source region and the drain region to form a source metal electrode and a drain metal electrode.

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