Vertical conductive semiconductor device based on trench gate type and preparation method thereof

Abstract

The invention provides a vertical conductive semiconductor device based on a trench gate type and a preparation method thereof, when a trench gate structure is pressurized to invert a body region to form a channel, current in the channel region flows towards a drift region along the outer side wall surrounding the trench gate structure located in the body region; the doping layer with the doping concentration larger than that of the drift region is arranged and makes contact with the body region, that is, the current in the channel region enters the drift region through the doping layer, and under the pressurization of the groove type gate structure, due to the fact that the ion concentration of the region where the doping layer is located is larger than that of the drift region, the current flowing into the drift region in the channel region can pass through more easily; therefore, the accumulation resistance RACC is effectively reduced, the on resistance of the semiconductor device is reduced, and meanwhile, the doping layer surrounds the outer side wall and the outer bottom wall of the groove type gate structure, so that the current flow direction is more concentrated.

Description

Technical Field

[0001] The invention relates to a semiconductor device, in particular to a trench gate-based vertical conductive semiconductor device and a preparation method thereof. Background Art

[0002] Semiconductor power devices are basic electronic components for energy control and conversion in power electronics systems. For example, they are widely used in fields such as motor drive in power systems and frequency conversion in consumer electronics. The continuous development of power electronics technology has opened up a wide range of application fields for semiconductor power devices. Vertical conductive semiconductor power devices represented by IGBT and VDMOS are the mainstream devices in the field of power electronics today. IGBT and VDMOS are currently formed by planar gate or trench gate processes, especially trench gate primitive cell structures are widely used. The trench gate will cover the channel area from the side to form a longitudinal trench, while the existing surface gate structure will cover the channel area from the top surface to make the channel a lateral channel, that is, the trench gate semiconductor device can change the channel from lateral to longitudinal, which is more conducive to the improvement of primitive cell density.

[0003] However, as the pitch size of the trench gate cell becomes smaller and smaller, the on-resistance of the semiconductor device cannot be further reduced, thereby increasing the on-state energy consumption of the semiconductor device. Summary of the invention

[0004] In view of the shortcomings of the prior art described above, an object of the present invention is to provide a vertical conductive semiconductor device based on a trench gate type and a preparation method thereof, so as to solve the problem in the prior art that the on-resistance of the vertical conductive semiconductor device based on a trench gate type is large, making it impossible to further reduce the on-state energy consumption of the semiconductor device.

[0005] To achieve the above-mentioned object and other related objects, the present invention provides a trench gate-based vertical conductive semiconductor device, including a cell region, wherein the cell region includes:

[0006] A drift region of a first conductivity type and a body region of a second conductivity type stacked from bottom to top;

[0007] A trench gate structure extending inwardly from the surface of the body region into the drift region;

[0008] A source region of the first conductivity type is formed in the body region and extends inward from a surface of the body region, and the source region is formed at the periphery of the trench gate structure;

[0009] A doping layer of a first conductivity type, surrounding an outer sidewall and an outer bottom wall of the trench gate structure in the drift region and contacting the body region, wherein the doping concentration of the doping layer is greater than the doping concentration of the drift region;

[0010] The first conductivity type is opposite to the second conductivity type.

[0011] Optionally, the trench gate structure is a trench gate or a trench shield gate; wherein the trench gate includes a gate dielectric layer formed on the inner sidewall and bottom of the gate trench and a gate polycrystalline layer formed on the gate dielectric layer; the trench shield gate includes a gate dielectric layer formed on the inner sidewall and bottom of the gate trench and a control gate polycrystalline layer and a shield gate polycrystalline layer formed on the gate dielectric layer, and the control gate polycrystalline layer and the shield gate polycrystalline layer are isolated by a dielectric isolation layer.

[0012] Optionally, the vertical conductive semiconductor device is an IGBT, and the vertical conductive semiconductor device also includes a buffer region of the first conductive type, a collector region and a collector metal of the second conductive type, which are sequentially located below the drift region, and an emitter metal located above the source region; or the vertical conductive semiconductor device is a VDMOS, and the vertical conductive semiconductor device also includes a drain region of the first conductive type, a drain region metal, which are located below the drift region, and a source region metal, which are located above the source region.

[0013] The present invention also provides a method for preparing a trench gate-based vertical conductive semiconductor device, including a method for preparing the first conductive type doping layer as described above:

[0014] Providing a semiconductor substrate, the semiconductor substrate comprising, from bottom to top, a drift region of a first conductivity type and a body region of a second conductivity type;

[0015] Etching to form a gate trench extending inwardly from the surface of the body region into the drift region;

[0016] forming an insulating layer containing a first conductive type element on the inner sidewall and the inner bottom wall of the gate trench located in the drift region;

[0017] Using a thermal drive-in process to drive the first conductive type element in the insulating layer into the drift region, so as to form a doped layer of the first conductive type on the outer sidewall and the outer bottom wall of the gate trench located in the drift region;

[0018] The insulating layer is removed.

[0019] Optionally, the method of forming the insulating layer includes:

[0020] Sequentially forming the insulating layer and the photoresist layer on the exposed upper surface of the semiconductor substrate where the gate trench is formed;

[0021] removing the photoresist layer to a preset thickness;

[0022] removing the insulating layer based on the retained photoresist layer to retain the insulating layer in the inner sidewall and inner bottom wall of the gate trench in the drift region;

[0023] The remaining photoresist layer is removed.

[0024] Furthermore, after removing the remaining photoresist layer, before forming the doping layer by a thermal drive-in process, a step of forming a mask layer on the exposed upper surface of the structure is included; and when removing the insulating layer, a step of removing the mask layer is also included.

[0025] Optionally, the method of forming the insulating layer includes:

[0026] forming a first mask layer on the inner sidewall of the gate trench located only in the body region;

[0027] The gate trench is filled with an insulating layer containing a first conductive type element, so that the insulating layer is at least located in the inner sidewall and the inner bottom wall of the gate trench in the drift region.

[0028] Furthermore, before forming the doping layer, the method further includes forming a second mask layer on the exposed upper surface of the structure; and when removing the insulating layer, the method further includes removing the first mask layer and the second mask layer.

[0029] Optionally, the first conductivity type is N type, the second conductivity type is P type, and the material of the insulating layer is ASG or PSG; or the first conductivity type is P type, the second conductivity type is N type, and the material of the insulating layer is BSG.

[0030] Optionally, the doping layer is formed by a heat-driving process of annealing, the annealing temperature is 900° C. to 1200° C., and the annealing time is 10 min to 60 min, both inclusive.

[0031] Optionally, the doping concentration of the doping layer is 1E13 atom / cm 2 ~1E16 atom / cm 2 , including the endpoint values.

[0032] As described above, in the trench gate-based vertical conductive semiconductor device of the present invention, when the trench gate structure is pressurized to make the body region invert to form a channel, the current in the channel region will flow toward the drift region along the outer side wall of the trench gate structure surrounding the body region, and by providing the doping layer with a doping concentration greater than that of the drift region and the doping layer is in contact with the body region, that is, the current in the channel region enters the drift region through the doping layer. Under the pressure of the trench gate structure, since the ion concentration in the region where the doping layer is located is greater than that in the drift region, the current flowing from the channel region to the drift region can pass more easily, that is, the accumulation resistance R is effectively reduced. ACC , thereby reducing the on-resistance of the semiconductor device. At the same time, since the doped layer surrounds the outer side wall and the outer bottom wall of the trench gate structure, the current flow can be more concentrated. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It shows a schematic diagram of the structure of the on-resistance in a general IGBT semiconductor device structure.

[0034] Figure 2 Shown is a schematic cross-sectional structure diagram of an example of a trench-gate-based vertical conductive semiconductor device according to the first embodiment of the present invention, wherein the trench-type gate structure is a trench gate.

[0035] Figure 3 Shown is a schematic cross-sectional structure diagram of another example of a trench-gate-based vertical conductive semiconductor device according to the first embodiment of the present invention, wherein the trench-type gate structure is a trench shielding gate.

[0036] Figure 4 Shown is a schematic cross-sectional structure diagram of yet another example of a trench-gate-based vertical conductive semiconductor device according to the first embodiment of the present invention.

[0037] Figures 5 to 15 It is a schematic diagram of the cross-sectional structure presented after each step in the method for preparing a first conductive type doping layer in a trench gate-based vertical conductive semiconductor device according to the second embodiment of the present invention is completed.

[0038] Figures 16 to 24 It is a schematic diagram of the cross-sectional structure presented after each step in the method for preparing a first conductive type doping layer in a trench gate-based vertical conductive semiconductor device according to the third embodiment of the present invention is completed.

[0039] Component number description

[0040] 10 Semiconductor substrate

[0041] 101 Drift Zone

[0042] 102 Body Area

[0043] 103 Trench Gate Structure

[0044] 104 Source region

[0045] 105 doping layer

[0046] 106 Gate trench

[0047] 107 gate dielectric layer

[0048] 108 gate polycrystalline layer

[0049] 109 Control gate polycrystalline layer

[0050] 110 Shielding grid polycrystalline layer

[0051] 111 Buffer

[0052] 112 collector area

[0053] 113 Collector Metal

[0054] 114 emitter metal

[0055] 115 Drain region

[0056] 116 Drain metal

[0057] 117 Source metal

[0058] 118 Insulation layer

[0059] 119 photoresist layer

[0060] 120 Mask layer

[0061] 121 first mask layer

[0062] 122 second mask layer

[0063] 123 Dielectric Isolation Layer

[0064] 201 Launch Area

[0065] 202 Groove Area

[0066] 203 Base Area

[0067] 204 substrate area

[0068] 205 Buffer

[0069] 206 collector area DETAILED DESCRIPTION

[0070] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0071] See also Figures 1 to 24 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0072] Embodiment 1

[0073] For trench-gate vertical conductive semiconductor devices, the gate structure is built in the trench dug inside the structure, and its on-resistance is generally the total resistance of the area where the current path passes. Figure 1 The figure shows a schematic diagram of the cross-sectional structure of an insulated gate bipolar transistor (IGBT for short). The current path passes through all the resistors in the region including: the resistor R N+ , the resistance R of the channel region 202 CH , the accumulation resistance R formed by the outer wall and outer bottom wall area of ​​the gate structure located in the drift region ACC , the resistance R of the drift region 204 sub , the resistance R of buffer 205 buffer and the resistance R of the collector region 206 p , of course, also includes the emitter contact resistance and the collector contact resistance, the sum of these resistances constitutes the on-resistance of the IGBT. It is well known that the smaller the on-resistance of a semiconductor device, the smaller its power loss during operation, but this parameter needs to be compromised with other energy consumption parameters of the device to reduce the on-resistance as much as possible without aggravating the degradation of other energy consumption parameters. At present, as the pitch size of semiconductor device cells becomes smaller and smaller, the on-resistance of semiconductor devices cannot be further reduced.

[0074] Based on this, this embodiment provides a trench gate-based vertical conductive semiconductor device, including a cell region, such as Figures 2 to 4 As shown, the cell region includes:

[0075] A drift region 101 of the first conductivity type and a body region 102 of the second conductivity type stacked from bottom to top;

[0076] A trench gate structure 103 extending inwardly from the surface of the body region 102 into the drift region 101;

[0077] A source region 104 of the first conductivity type is formed in the body region 102 and extends inward from the surface of the body region 102 , and the source region 104 is formed at the periphery of the trench gate structure 103 ;

[0078] A doping layer 105 of a first conductivity type surrounds an outer sidewall and an outer bottom wall of the trench gate structure 103 in the drift region 101 and contacts the body region 102 , and a doping concentration of the doping layer 105 is greater than a doping concentration of the drift region 101 ;

[0079] The first conductivity type is opposite to the second conductivity type.

[0080] In the vertical conductive semiconductor device of this embodiment, when the trench gate structure 103 is pressurized to invert the body region 102 to form a channel, the current in the channel region will flow toward the drift region 101 along the outer sidewall of the trench gate structure 103 surrounding the body region 102. By providing the doping layer 105 with a doping concentration greater than that of the drift region 101 and the doping layer 105 being in contact with the body region 102, that is, the current in the channel region enters the drift region 101 through the doping layer 105. Under the pressure of the trench gate structure 103, since the ion concentration in the region where the doping layer 105 is located is greater than that in the drift region 101, the current flowing from the channel region into the drift region 101 can pass more easily, that is, the accumulation resistance R is effectively reduced. ACC , thereby reducing the on-resistance of the semiconductor device. At the same time, since the doped layer 105 surrounds the outer side wall and the outer bottom wall of the trench gate structure 103, the current flow can be more concentrated.

[0081] The thickness and doping concentration of the doping layer 105 are adjusted according to actual needs, as long as it surrounds the outer sidewall and outer bottom wall of the trench gate structure 103 located in the drift region 101, is located in the drift region 101, and contacts the body region 102. As a preferred example, the doping concentration of the doping layer 105 is 1E13 atom / cm 2 ~1E16atom / cm 2 , including the endpoint value, generally the doping concentration of the drift region 101 is low, less than 1E13 atom / cm 2 Therefore, the concentration of the doping layer 105 is selected to be no less than 1E13 atom / cm 2 , but the concentration of the doping layer 105 cannot be too high, for example, higher than 1E16 atom / cm 2 , there is a risk of causing depletion breakdown in the body region 102.

[0082] As an example, the trench gate structure 103 may be a conventional trench gate, such as Figure 2 and Figure 4 As shown, the trench gate includes a gate dielectric layer 107 formed on the inner sidewall and bottom of the gate trench and a gate polycrystalline layer 108 formed on the gate dielectric layer 107; the trench gate structure 103 can also be a trench shielded gate (SGT for short), such as Figure 3 As shown, the trench shield gate includes a gate dielectric layer 107 formed on the inner sidewall and bottom of the gate trench, and a control gate polycrystalline layer 109 and a shield gate polycrystalline layer 110 formed on the gate dielectric layer 107 , and the control gate polycrystalline layer 109 and the shield gate polycrystalline layer 110 are isolated by a dielectric isolation layer 123 .

[0083] The first conductivity type and the second conductivity type can be N-type or P-type, as long as the two satisfy the opposite conduction type, that is, if the first conductivity type is N-type, the second conductivity type is P-type; if the first conductivity type is P-type, the second conductivity type is N-type. Named after the conductivity type of the channel, when the first conductivity type is N-type, it is called an N-type semiconductor device; when the first conductivity type is P-type, it is called a P-type semiconductor device. N-type doping can be formed by doping with VA group elements, such as phosphorus, and P-type doping can be formed by doping with IIIA group elements, such as boron. However, it is not limited to this, and other N-type ions and P-type ions can also achieve the formation of corresponding doping types.

[0084] The trench gate-based vertical conductive semiconductor device of this embodiment is suitable for high-voltage power semiconductor devices, such as IGBT, VDMOS, etc., because it is provided with a drift region that can withstand high voltage. Figure 2 The figure shows a trench gate IGBT device, in which: Figure 2 The middle trench gate structure 103 is a trench gate. The IGBT device further includes a buffer region 111 of the first conductivity type, a collector region 112 of the second conductivity type and a collector metal 113 located sequentially below the drift region 101, and an emitter metal 114 located above the source region 104. Figure 4 The device shown is a trench gate VDMOS device, which further includes a drain region 115 of the first conductivity type located below the drift region 101 , a drain region metal 116 , and a source region metal 117 located above the source region 104 .

[0085] As an example, the semiconductor material used in the trench gate vertical conductive semiconductor device can be selected from conventional semiconductor materials in the art, such as silicon, silicon carbide, gallium arsenide or gallium nitride, etc. In this embodiment, the commonly used silicon material is selected.

[0086] Embodiment 2

[0087] The present embodiment provides a method for preparing a trench gate-based vertical conductive semiconductor device. The preparation method can be used to prepare a first conductive type doping layer in the trench gate-based vertical conductive semiconductor device as described in Example 1, but is not limited to this. Any other suitable preparation method can also be used to prepare the first conductive type doping layer in the trench gate-based vertical conductive semiconductor device as described in Example 1.

[0088] The method for preparing the first conductive type doping layer comprises:

[0089] S1, providing a semiconductor substrate, wherein the semiconductor substrate comprises, from bottom to top, a drift region of a first conductivity type and a body region of a second conductivity type;

[0090] S2, etching to form a gate trench extending inwardly from the surface of the body region to the drift region;

[0091] S3, forming an insulating layer containing a first conductive type element on the inner sidewall and inner bottom wall of the gate trench located in the drift region;

[0092] S4, driving the first conductive type element in the insulating layer into the drift region using a thermal drive-in process to form a doped layer of the first conductive type on the outer sidewall and the outer bottom wall of the gate trench in the drift region;

[0093] S5, removing the insulating layer.

[0094] The method for preparing the first conductivity type doping layer of this embodiment is described in detail below with reference to specific drawings.

[0095] like Figure 5 and Fig.16 As shown, step S1 is first performed to provide a semiconductor substrate 10 , wherein the semiconductor substrate 10 includes, from bottom to top, a drift region 101 of a first conductivity type and a body region 102 of a second conductivity type.

[0096] It should be noted here that Figure 5 and Fig.16 The semiconductor substrate 10 shown in the figure only shows some material layers involved in the subsequent preparation of the doping layer. In practice, according to different semiconductor devices, the semiconductor substrate 10 may also include other material layers.

[0097] The semiconductor substrate 10 may be made of conventional semiconductor materials in the art, such as silicon, silicon carbide, gallium arsenide or gallium nitride, etc. In this embodiment, commonly used silicon material is selected.

[0098] like Figure 6 and Fig.17As shown, step S2 is then performed to form a gate trench 106 extending from the surface of the body region 102 inwardly into the drift region 101 by etching.

[0099] As an example, the method for forming the gate trench 106 includes: coating photoresist, exposing and developing the photoresist through a photolithography process to pattern the photoresist; then wet or dry etching the semiconductor substrate based on the patterned photoresist to form the gate trench 106; and then removing the patterned photoresist layer.

[0100] For shallower gate trenches 106, the etching process can easily achieve a gate trench 106 with a relatively consistent diameter from top to bottom; while for deeper trenches, based on the existing etching process limitations, the shape of the gate trench 106 from top to bottom is generally a V-shape with a specific inclination angle, and the specific inclination angle is generally 88°±1°, where the inclination angle refers to the angle between the gate trench 106 and the horizontal direction.

[0101] like Fig.12 , Fig. 20 and Fig.21 As shown, step S3 is then performed to form an insulating layer 118 containing a first conductive type element on the inner sidewall and the inner bottom wall of the gate trench 106 located in the drift region 101 .

[0102] It should be noted that the thickness of the insulating layer 118 is set according to the doping concentration required by the doping layer to be formed subsequently. The thicker the insulating layer 118 is, the more ions are driven into the drift region 101 through a thermal drive-in process, and the higher the doping concentration is. Fig.12 and Fig. 20 The insulating layer 118 formed on the inner sidewall and the inner bottom wall of the gate trench 106 in the drift region 101 is relatively thin; and Fig.21 The inner sidewall and the inner bottom wall of the gate trench 106 in the drift region 101 are thicker and fill the entire interior of the gate trench 106 in the drift region 101. The thickness of the insulating layer 118 on the inner sidewall and the inner bottom wall of the gate trench 106 in the drift region 101 is set according to actual needs and is not excessively limited here.

[0103] Two methods of forming the insulating layer 118 on the inner sidewalls and the inner bottom wall of the gate trench 106 in the drift region 101 are shown below.

[0104] Method 1: If Figures 7 to 9 As shown, firstly, the insulating layer 118 and the photoresist layer 119 are sequentially formed on the exposed upper surface of the semiconductor substrate 10 where the gate trench 106 is formed.

[0105] It should be noted that the thickness of the insulating layer 118 can be thin or thick according to actual needs. Figure 7 The thickness of the insulating layer 118 is relatively thin and does not completely fill the gate trench 106 located in the drift region 101. Figure 8 The thickness of the insulating layer 118 is relatively thick and has filled the gate trench 106 located in the drift region 101. In addition, the thickness of the photoresist layer 119 is selected according to actual needs and can fill the gate trench 106 (such as Fig. 9 As shown in FIG. 1 , the gate trench 106 may not be completely filled, as long as it can play an effective etching barrier role when the insulating layer 118 is subsequently etched.

[0106] The insulating layer 118 may be formed by using conventional deposition processes, such as CVD, ALD, etc.

[0107] As an example, when the first conductive type element in the insulating layer 118 is N-type, the material of the insulating layer 118 is preferably ASG (arsenic silicon glass) or PSG (phosphorus silicon glass), and when a thermal drive-in process is performed later, the arsenic element in the ASG or the phosphorus element in the PSG can be diffused into the drift region 101; when the first conductive type element in the insulating layer 118 is P-type, the material of the insulating layer 118 is preferably BSG (borosilicate glass), and when a thermal drive-in process is performed later, the boron element in the BSG can be diffused into the drift region 101. Of course, the insulating layer 118 can also be other materials, as long as the first conductive type element contained therein can be diffused out in the thermal drive-in process.

[0108] like Fig.10 As shown, the photoresist layer 119 is then removed to a predetermined thickness.

[0109] The purpose of removing the photoresist layer 119 to a preset thickness is to etch the insulating layer 118 later so that the insulating layer 118 is formed only inside the gate trench 106 in the drift region 101 and used as an etching barrier. Because the photoresist layer 119 is inevitably damaged when etching the insulating layer 118, the preset thickness of the photoresist layer 119 is related to the material of the photoresist layer 119, the etching method used to etch the insulating layer 118, the thickness of the insulating layer 118, the material of the insulating layer 118 and other parameters. Fig.10 In the embodiment, the height of the photoresist layer 119 exceeds that of the drift region 101 .

[0110] like Fig.11As shown, the insulating layer 118 is then removed based on the retained photoresist layer 119 to retain the insulating layer 118 on the inner sidewalls and inner bottom wall of the gate trench 106 in the drift region 101 .

[0111] like Fig.12 As shown, the remaining photoresist layer 119 is finally removed to obtain the insulating layer 118 located only on the inner sidewall and inner bottom wall of the gate trench 106 in the drift region 101 .

[0112] Method 2: If Fig.19 As shown, firstly, a first mask layer 121 is formed on the inner sidewall of the gate trench 106 located in the body region 102. Specifically, as Fig.18 As shown, a first mask layer 121 can be first deposited on the entire exposed surface of the semiconductor substrate having the gate trench 106 (including the inner surface of the gate trench 106); then the first mask layer 121 is etched to remove all the first mask layer 121 except the first mask layer 121 on the inner side wall of the gate trench 106 in the body region 102.

[0113] like Fig. 20 and Fig.21 As shown, the gate trench 106 is then filled with an insulating layer 118 containing a first conductive type element, so that the insulating layer 118 is at least located in the inner sidewalls and the inner bottom wall of the gate trench 106 in the drift region 101 .

[0114] The thickness of the insulating layer 118 can be set according to actual needs, such as Fig. 20 As shown, the insulating layer 118 is relatively thin and does not completely fill the interior of the gate trench 106 in the drift region 101. Fig.21 As shown, the insulating layer 118 is relatively thick and has filled the inside of the gate trench 106 located in the drift region 101. It should be noted here that the insulating layer 118 formed by this method is not only formed in the gate trench 106 located in the drift region 101, but also formed in the gate trench 106 located in the body region 102. However, since the inner sidewall of the gate trench 106 located in the body region is formed with the first mask layer 121, the first conductive type element contained in the insulating layer 118 will be effectively blocked from diffusing into the body region 102 during the subsequent thermal drive-in process.

[0115] like Fig.14 , Fig. 22 and Fig.23As shown, step S4 is then performed, in which the first conductive type element in the insulating layer 118 is driven into the drift region 101 by a thermal drive-in process, so as to form a doped layer 105 of the first conductive type on the outer sidewall and the outer bottom wall of the gate trench 106 located in the drift region 101. Since the doped layer 105 is formed by diffusion of the first conductive type element in the insulating layer 119, the doped layer 105 can conform to the external morphology of the bottom of the gate trench 106.

[0116] As an example, the heat drive-in process may be an annealing process, and generally the annealing temperature is between 900° C. and 1200° C., and the annealing time of the annealing process is between 10 min and 60 min, including end values.

[0117] As a preferred example, the annealing temperature is 1150° C. and the annealing time is 30 minutes.

[0118] As a preferred example, the doping concentration of the doping layer 105 is 1E13 atom / cm 2 ~1E16 atom / cm 2 , including the endpoint value, generally the doping concentration of the drift region 101 is low, less than 1E13 atom / cm 2 Therefore, the concentration of the doping layer 105 is selected to be no less than 1E13 atom / cm 2 , but the concentration of the doping layer 105 cannot be too high, for example, higher than 1E16 atom / cm 2 , there is a risk of causing depletion breakdown in the body region 102.

[0119] As an example, if the insulating layer 118 is formed on the inner sidewalls and inner bottom walls of the gate trench 106 in the drift region 101 by method 1 in step S3, it is also necessary to form a mask layer 120 on the exposed upper surface of the entire obtained structure before forming the doping layer 105 by the thermal drive-in process in this step, that is, the mask layer 120 covers the surface of the body region 102, the sidewalls of the gate trench 106 in the body region 102, and the sidewalls and bottom of the insulating layer 118 in the drift region 101, as shown in FIG. Fig.13As shown, the mask layer 120 can effectively block the first conductive type elements contained in the insulating layer 118 from diffusing to other regions, while reducing the damage to the surface of the semiconductor substrate during the thermal drive-in process. If the insulating layer 118 formed on the inner sidewall and inner bottom wall of the gate trench 106 in the drift region 101 is obtained by the second method in step S3, it is also necessary to form a second mask layer 122 on the exposed upper surface of the entire resulting structure before the doping layer 105 is formed by the thermal drive-in process, that is, the second mask layer 122 covers the surface of the body region 102, the surface of the first mask layer 121 and the surface of the insulating layer 118, as shown in FIG. Fig. 22 and Fig.23 As shown, the second mask layer 122 combined with the first mask layer 121 can effectively block the first conductive type element contained in the insulating layer 118 from diffusing to other regions, while reducing damage to the surface of the semiconductor substrate during the heat drive-in process. Preferably, the mask layer 120, the first mask layer 121 and the second mask layer 122 are made of TEOS.

[0120] like Fig.15 and Fig.24 As shown, step S5 is finally performed to remove the insulating layer 118 , thereby forming the doping layer 105 on the outer sidewall and the outer bottom wall of the gate trench 106 in the drift region 101 .

[0121] As an example, corresponding to step S4, when the doping layer 105 is formed, a mask layer 120 is also formed on the exposed upper surface of the entire resulting structure, and the mask layer 120 also needs to be removed when the insulating layer 118 is removed in this step; when the doping layer 105 is formed, a second mask layer 122 is also formed on the exposed upper surface of the entire resulting structure, and the first mask layer 121 and the second mask layer 122 also need to be removed when the insulating layer 118 is removed in this step.

[0122] As described in the first embodiment, the trench gate-based vertical conductive semiconductor device of the present invention is suitable for high-voltage power semiconductor devices. Therefore, in the preparation method of this embodiment, after forming the doping layer 105, it also includes forming a corresponding structure of the semiconductor device, which is well known in the art and is not excessively limited here. For example, when it is an IGBT, Figure 2 As shown, it also includes: forming a trench gate structure 103 in the gate trench 106, forming a buffer zone 111 of the first conductivity type, a collector region 112 of the second conductivity type and a collector metal 113 located below the drift region 101, and an emitter metal 114 located above the source region 104; when it is a VDMOS, as Figure 4As shown, the method further includes: forming a trench gate structure 103 in the gate trench 106 , forming a drain region 115 of the first conductivity type located below the drift region 101 , a drain region metal 116 , and a source region metal 117 located above the source region 104 .

[0123] In summary, in the trench gate-based vertical conductive semiconductor device of the present invention, when the trench gate structure is pressurized to make the body region invert to form a channel, the current in the channel region will flow to the drift region along the outer side wall of the trench gate structure surrounding the body region, and by providing the doping layer with a doping concentration greater than that of the drift region and the doping layer is in contact with the body region, that is, the current in the channel region enters the drift region through the doping layer. Under the pressure of the trench gate structure, since the ion concentration in the region where the doping layer is located is greater than that in the drift region, the current flowing from the channel region to the drift region can pass more easily, that is, the accumulation resistance R is effectively reduced. ACC , thereby reducing the on-resistance of the semiconductor device, and at the same time, since the doped layer surrounds the outer side wall and the outer bottom wall of the trench gate structure, the current flow can be more concentrated. Therefore, the present invention effectively overcomes various shortcomings of the prior art and has a high industrial utilization value.

[0124] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A trench gate-based vertical conductive semiconductor device, comprising a cell region, characterized in that: The cell region comprises: A drift region of a first conductivity type and a body region of a second conductivity type stacked from bottom to top; A trench gate structure extending inwardly from the surface of the body region into the drift region; A source region of the first conductivity type is formed in the body region and extends inward from a surface of the body region, and the source region is formed at the periphery of the trench gate structure; A doping layer of a first conductivity type, surrounding an outer sidewall and an outer bottom wall of the trench gate structure in the drift region and contacting the body region, wherein the doping concentration of the doping layer is greater than the doping concentration of the drift region; The first conductivity type is opposite to the second conductivity type.

2. The trench gate-based vertical conductive semiconductor device according to claim 1, characterized in that: The trench gate structure is a trench gate or a trench shield gate; wherein the trench gate includes a gate dielectric layer formed on the inner sidewall and bottom of the gate trench and a gate polycrystalline layer formed on the gate dielectric layer; the trench shield gate includes a gate dielectric layer formed on the inner sidewall and bottom of the gate trench and a control gate polycrystalline layer and a shield gate polycrystalline layer formed on the gate dielectric layer, and the control gate polycrystalline layer and the shield gate polycrystalline layer are isolated by a dielectric isolation layer.

3. The trench gate-based vertical conductive semiconductor device according to claim 1, characterized in that: The vertical conductive semiconductor device is an IGBT, and the vertical conductive semiconductor device also includes a buffer region of the first conductive type, a collector region and a collector metal of the second conductive type, which are sequentially located below the drift region, and an emitter metal located above the source region; or the vertical conductive semiconductor device is a VDMOS, and the vertical conductive semiconductor device also includes a drain region of the first conductive type, a drain region metal, which are located below the drift region, and a source region metal, which are located above the source region.

4. A method for preparing a trench gate-based vertical conductive semiconductor device according to any one of claims 1 to 3, characterized in that: A method for preparing the first conductive type doped layer: Providing a semiconductor substrate, the semiconductor substrate comprising, from bottom to top, a drift region of a first conductivity type and a body region of a second conductivity type; Etching to form a gate trench extending inwardly from the surface of the body region into the drift region; forming an insulating layer containing a first conductive type element on the inner sidewall and the inner bottom wall of the gate trench located in the drift region; Using a thermal drive-in process to drive the first conductive type element in the insulating layer into the drift region, so as to form a doped layer of the first conductive type on the outer sidewall and the outer bottom wall of the gate trench located in the drift region; The insulating layer is removed.

5. The method for preparing a trench gate-based vertical conductive semiconductor device according to claim 4, characterized in that: The method of forming the insulating layer includes: Sequentially forming the insulating layer and the photoresist layer on the exposed upper surface of the semiconductor substrate where the gate trench is formed; removing the photoresist layer to a preset thickness; Removing the insulating layer based on the retained photoresist layer to retain the insulating layer only in the inner sidewall and inner bottom wall of the gate trench in the drift region; The remaining photoresist layer is removed.

6. The method for preparing a trench gate-based vertical conductive semiconductor device according to claim 5, characterized in that: After removing the remaining photoresist layer and before forming the doping layer by a thermal drive-in process, the method further includes forming a mask layer on the exposed upper surface of the structure; and when removing the insulating layer, the method further includes removing the mask layer.

7. The method for preparing a trench gate-based vertical conductive semiconductor device according to claim 4, characterized in that: The method of forming the insulating layer includes: forming a first mask layer on the inner sidewall of the gate trench located only in the body region; The gate trench is filled with an insulating layer containing a first conductive type element, so that the insulating layer is at least located in the inner sidewall and the inner bottom wall of the gate trench in the drift region.

8. The method for preparing a trench gate-based vertical conductive semiconductor device according to claim 7, characterized in that: Before forming the doping layer, the method further includes forming a second mask layer on the exposed upper surface of the structure; and when removing the insulating layer, the method further includes removing the first mask layer and the second mask layer.

9. The method for preparing a trench gate-based vertical conductive semiconductor device according to claim 4, characterized in that: The first conductivity type is N type, the second conductivity type is P type, and the material of the insulating layer is ASG or PSG; or the first conductivity type is P type, the second conductivity type is N type, and the material of the insulating layer is BSG.

10. The method for preparing a trench gate-based vertical conductive semiconductor device according to claim 4, characterized in that: The doping layer is formed by a heat-driven annealing process, the annealing temperature is 900° C. to 1200° C., and the annealing time is 10 min to 60 min, including end values.

11. The method for preparing a trench gate-based vertical conductive semiconductor device according to claim 4, characterized in that: The doping concentration of the doping layer is 1E13 atom / cm 2 ~1E16 atom / cm 2 , including the endpoint values.

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