Manufacturing method of semiconductor device
Through the common light mask technology, inject the Pip ion injection and N -type drain mixing ions into the common first photoresses, inject the N -trap ion injection and the P -type drain -mixed ion injection into the common second light hood, solve the solution Save the challenge of the cost of light hood on the low cost and cost -effective process platform, while ensuring the performance of the thermal carrier effect of the NMOS tube and reducing the leakage current.
Patent Information
- Application Number
- CN202411514517.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-28
- Publication Date
- 2025-01-28
AI Technical Summary
When ensuring that the gate size of 7V CMOS devices and 5V CMOS devices remains unchanged, how to save at least two optical masks on the basis of normal logic processes to solve the challenges of wafer factory logic processes.
By injecting the Pip ion injection and N -type drain mixing ions into the common first light hood, the N -trap ion is injected and the P -type drain -mixed ion is injected into the common second mask, which saves a separate form of N -trap and a separate formation Form the two -crafted mask of the two processes.
Under retaining the NMOS tube's thermal carrier effect performance of the NMOS tube, the leak leakage current is greatly reduced to ensure that the NMOS tubes are injected with two LDD ions injected by the NMOS tube. Essence
Smart Images
Figure CN119384032A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of integrated circuit manufacturing, and in particular relates to a method for manufacturing a semiconductor device. Background Art
[0002] For the production of CMOS devices (for example, with an operating voltage of 7V), the market requires a low-cost, cost-effective process platform. While ensuring that the gate size of 7V CMOS devices and 5V CMOS devices remain unchanged, at least two masks are required to be saved on the basis of the normal logic process, which poses a great challenge to the logic process of the wafer processing plant. Summary of the invention
[0003] The purpose of the present invention is to provide a method for manufacturing a semiconductor device, which is manufactured on a low-cost, high-cost-performance process platform, wherein the P-well ion implantation and the N-type drain lightly doped ion implantation share a first mask, and the N-well ion implantation and the P-type drain lightly doped ion implantation share a second mask, thereby saving the masks of the two processes of forming the N-well and forming the P-well separately. Under the process conditions of retaining the two LDD ion implantations of the N-type drain lightly doped and the P-type drain lightly doped, the hot carrier effect performance of the NMOS tube is guaranteed, the substrate leakage current is greatly reduced, and the reliability test is passed.
[0004] The present invention provides a method for manufacturing a semiconductor device, comprising:
[0005] Step S1, providing a substrate, and defining a first active area and a second active area on the substrate by shallow trench isolation;
[0006] Step S2, sequentially forming a first gate oxide layer and a first gate layer on the substrate of the first active region; sequentially forming a second gate oxide layer and a second gate layer on the substrate of the second active region;
[0007] Step S3, using the first photoresist layer formed by the first photomask as a mask, performing P-well ion implantation and N-type drain lightly doped ion implantation in the first active region;
[0008] Step S4, using the second photoresist layer formed by the second photomask as a mask, performing N-well ion implantation and P-type drain lightly doped ion implantation in the second active region;
[0009] Step S5, performing N-type ion heavy doping implantation on the first active region to form a source region and a drain region of the NMOS tube;
[0010] Step S6: perform P-type ion heavy doping implantation on the second active region to form a source region and a drain region of the PMOS tube.
[0011] Furthermore, step S2 specifically includes:
[0012] forming a gate oxide material layer and a gate material layer sequentially covering the substrate;
[0013] forming a patterned second photoresist layer on the surface of the gate material layer,
[0014] Using the imaged second photoresist layer as a mask, the gate material layer and the gate oxide layer material layer are sequentially etched to form the first gate layer and the first gate oxide layer located in the first active area, and the second gate layer and the second gate oxide layer located in the second active area.
[0015] Furthermore, step S3 specifically includes:
[0016] forming the first photoresist layer, wherein the first photoresist layer exposes the first active area and covers the second active area;
[0017] Using the first photoresist layer as a mask, the P-well ion implantation is first performed on the first active region to form a P-well; and then the N-type drain lightly doped ion implantation is performed on the first active region to form an N-type lightly doped region.
[0018] Furthermore, in step S3, in the first active region, the P-well ion implantation depth is greater than the N-type drain lightly doped ion implantation depth, and the P-well ion implantation energy is greater than the N-type drain lightly doped ion implantation energy.
[0019] Furthermore, step S4 specifically includes:
[0020] forming the second photoresist layer, wherein the second photoresist layer exposes the second active area and covers the first active area;
[0021] Using the second photoresist layer as a mask, the N-well ion implantation is first performed on the second active region to form an N-well; and then the P-type drain lightly doped ion implantation is performed on the second active region to form a P-type lightly doped region.
[0022] Furthermore, in step S4, in the second active region, the N-well ion implantation depth is greater than the P-type drain lightly doped ion implantation depth, and the N-well ion implantation energy is greater than the P-type drain lightly doped ion implantation energy.
[0023] Furthermore, in step S3, the P-well ion implantation also passes through the first gate layer and the first gate oxide layer to enter the substrate below; in step S4, the N-well ion implantation also passes through the second gate layer and the second gate oxide layer to enter the substrate below.
[0024] Furthermore, the operating voltage of the semiconductor device includes: 7V or 5V.
[0025] Furthermore, after step S4 and before step S5, the manufacturing method further includes:
[0026] A first sidewall is formed on the substrate of the first active region, and the first sidewall covers the sidewalls of the first gate oxide layer and the first gate layer; a second sidewall is formed on the substrate of the second active region, and the second sidewall covers the sidewalls of the second gate oxide layer and the second gate layer.
[0027] Furthermore, after step S6, the manufacturing method further includes:
[0028] Forming metal silicide, forming the metal silicide on the surfaces of the first gate layer and the second gate layer, and the surfaces of the substrate of the first active region and the second active region;
[0029] forming a dielectric layer, the dielectric layer covering the substrate, the first sidewall, the first gate layer, the second sidewall and the second gate layer; and forming a contact hole in the dielectric layer;
[0030] Metal interconnection is formed, metal is filled in the contact hole, and the gate, source region and drain region of the NMOS tube and the PMOS tube are led out.
[0031] Compared with the prior art, the present invention has the following beneficial effects:
[0032] The present invention provides a method for manufacturing a semiconductor device, comprising: step S1, providing a substrate, defining a first active area and a second active area on the substrate by shallow trench isolation; step S2, sequentially forming a first gate oxide layer and a first gate layer on the substrate of the first active area; and sequentially forming a second gate oxide layer and a second gate layer on the substrate of the second active area; step S3, using a first photoresist layer formed by a first photomask as a mask, performing P-well ion implantation and N-type drain lightly doped ion implantation in the first active area; step S4, using a second photoresist layer formed by a second photomask as a mask, performing N-well ion implantation and P-type drain lightly doped ion implantation in the second active area; step S5, performing N-type ion heavy doping implantation in the first active area to form a source area and a drain area of an NMOS tube; step S6, performing P-type ion heavy doping implantation in the second active area to form a source area and a drain area of a PMOS tube.
[0033] The manufacturing method of the semiconductor device provided by the present invention is manufactured on a low-cost, high-cost-performance process platform, and the P-well ion injection and the N-type drain lightly doped (LDD) ion injection share the first mask, and the N-well ion injection and the P-type drain lightly doped (LDD) ion injection share the second mask, thereby saving the masks (masks) of the two processes of forming the N-well and forming the P-well separately. Under the process conditions of retaining the two LDD ion injections of the N-type drain lightly doped (LDD) and the P-type drain lightly doped (LDD), the hot carrier effect performance of the NMOS tube is guaranteed, the substrate leakage current is greatly reduced, and the reliability test is passed. Not only the electrical performance of the semiconductor device is guaranteed, but also the purpose of saving the mask cost is achieved. BRIEF DESCRIPTION OF THE DRAWINGS
[0034] Figure 1 Normal logic process flow chart for 5V CMOS devices.
[0035] Figure 2 Mask-saving logic process flow diagram for 5V CMOS devices.
[0036] Figure 3 The present invention is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
[0037] Figure 4 It is a three-dimensional schematic diagram after forming a gate layer in the method for manufacturing a semiconductor device according to an embodiment of the present invention.
[0038] Figure 5 A schematic cross-sectional view of a method for manufacturing a semiconductor device according to an embodiment of the present invention after a gate layer is formed in a first active region.
[0039] Figure 6 Schematic diagram of performing P-well ion implantation and N-type drain lightly doped ion implantation in a first active region in a method for manufacturing a semiconductor device according to an embodiment of the present invention.
[0040] Figure 7 A schematic diagram of performing N-type ion heavy doping implantation in a first active region in a method for manufacturing a semiconductor device according to an embodiment of the present invention.
[0041] Figure 8 The present invention is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
[0042] The reference numerals are as follows:
[0043] 10-substrate; 11-STI; 12-first gate oxide layer; 13-first gate layer; 14-first photoresist layer; 15-N-type lightly doped region; 16-P well; 17-first sidewall; 18-third photoresist layer; 19-source region. DETAILED DESCRIPTION
[0044] As described in the background art, the market requires a low-cost, cost-effective process platform for the manufacture of CMOS devices.
[0045] Figure 1 The following is a normal logic process flow chart of a 5V CMOS device. The inventor has found that in order to save masks, Figure 1 Based on the process, directly omitting the two process steps of N-type drain light doping (LDD) and P-type drain light doping (LDD) and the corresponding two masks will result in a very poor hot carrier effect of the CMOS device and a very high substrate leakage current Isub, which cannot pass the reliability evaluation.
[0046] Figure 2 The following is a process flow chart of mask-saving logic for 5V CMOS devices. Figure 2 The same process, Figure 1 Based on the normal logic process of 5V CMOS devices, the N-type drain light doping (LDD) and the N-type ion heavy doping share the same mask, and the P-type drain light doping (LDD) and the P-type ion heavy doping share the same mask; in this way, two masks of N-type drain light doping (LDD) and P-type drain light doping (LDD) can be saved; but in actual tests, it is found that under the application voltage of 7VCMOS devices, the substrate leakage current Isub is still very high and cannot pass the reliability test. Therefore, for the low-cost and cost-effective process platform of 7V CMOS devices, a new process method is urgently needed to save mask costs and ensure device performance, especially the electrical performance of NMOS tubes.
[0047] Based on the above research, the present invention provides a method for manufacturing a semiconductor device. The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will become clearer. It should be noted that the drawings are all in a very simplified form and use an inaccurate scale, which is only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.
[0048] For ease of description, some embodiments of the present application may use spatially relative terms such as "above", "below", "top", "below", etc. to describe the relationship between one element or component and another (or other) elements or components as shown in the various figures of the embodiments. It should be understood that in addition to the orientations described in the drawings, the spatially relative terms are also intended to include different orientations of the device in use or operation. For example, if the device in the drawings is turned over, the elements or components described as being "below" or "below" other elements or components will subsequently be positioned as being "above" or "above" other elements or components. The terms "first", "second", etc. below are used to distinguish between similar elements and are not necessarily used to describe a specific order or time sequence. It is to be understood that these terms used in this way are interchangeable where appropriate.
[0049] The embodiment of the present invention provides a method for manufacturing a semiconductor device, such as Figure 3 As shown, including:
[0050] Step S1, providing a substrate, and defining a first active area and a second active area on the substrate by shallow trench isolation;
[0051] Step S2, sequentially forming a first gate oxide layer and a first gate layer on the substrate of the first active region; and sequentially forming a second gate oxide layer and a second gate layer on the substrate of the second active region;
[0052] Step S3, using the first photoresist layer formed by the first photomask as a mask, performing P-well ion implantation and N-type drain lightly doped ion implantation in the first active region;
[0053] Step S4, using the second photoresist layer formed by the second photomask as a mask, performing N-well ion implantation and P-type drain lightly doped ion implantation in the second active region;
[0054] Step S5, performing N-type ion heavy doping implantation on the first active region to form a source region and a drain region of the NMOS tube;
[0055] Step S6: perform P-type ion heavy doping implantation on the second active region to form a source region and a drain region of the PMOS tube.
[0056] Combine the following Figures 4 to 8 Each step of the method for manufacturing a semiconductor device according to an embodiment of the present invention is described in detail.
[0057] Step S1: Figure 4As shown, a substrate 10 is provided, and a first active region I and a second active region II are defined on the substrate 10 by shallow trench isolation (STI) 11. The substrate 10 may include a semiconductor material, and may be a single-layer structure or a multi-layer structure. The substrate 10 may be a semiconductor material such as Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and other III / V or II / VI compound semiconductors; it may also include a layered substrate such as silicon on insulator (SOI) or silicon germanium on insulator. This embodiment is described by taking the first active region I being used to form NMOS and the second active region II being used to form PMOS as an example. In other embodiments, the first active region I may be used to form PMOS, and the second active region II may be used to form NMOS.
[0058] Figure 4 It is a three-dimensional schematic diagram of the semiconductor device after forming a gate layer according to an embodiment of the present invention. Figure 5 FIG. 1 is a schematic cross-sectional view of a semiconductor device after a gate layer is formed in a first active region I according to an embodiment of the present invention.
[0059] Step S2: Figure 4 and Figure 5 As shown, a first gate oxide layer 12 and a first gate layer 13 are sequentially formed on the substrate of the first active region I; a second gate oxide layer (not shown) and a second gate layer are sequentially formed on the substrate of the second active region II. Specifically: a gate oxide layer material layer and a gate material layer are sequentially formed to cover the substrate 10; a patterned second photoresist layer is formed on the surface of the gate material layer, and the patterned second photoresist layer is used as a mask to sequentially etch the gate material layer and the gate oxide layer material layer to form a first gate layer 12 and a first gate oxide layer 13 located in the first active region I, and a second gate layer and a second gate oxide layer located in the second active region. The first gate oxide layer 12 and the second gate oxide layer can be formed in the same process, and the first gate oxide layer 12 and the second gate oxide layer can be grown by a thermal oxidation growth process, and the temperature of the thermal oxidation growth process is, for example, 900°C to 1150°C; the tail end of the first gate oxide layer 12 and the tail end of the second gate oxide layer can be connected together. The first gate layer 13 and the second gate layer can be formed in the same process; the tail end of the first gate layer 13 and the tail end of the second gate layer can be connected together.
[0060] Step S3: Figure 6As shown, the first photoresist layer 14 formed by the first photomask is used as a mask to perform P-well ion implantation and N-type drain lightly doped (LDD) ion implantation in the first active region I. Specifically, a first photoresist layer 14 is formed, the first photoresist layer 14 has an opening in the first active region I, the first photoresist layer 14 exposes the first active region I, and the first photoresist layer 14 covers the second active region II. Using the first photoresist layer 14 as a mask, the first active region I is first implanted with P-well (Well) ions to form a P-well 16; the P-well ion implantation also passes through the first gate layer and the first gate oxide layer into the substrate below. Then, the first active region I is implanted with N-type drain lightly doped (LDD) ions to form an N-type lightly doped region 15. In the first active region I, the P-well ion implantation depth is greater than the N-type drain lightly doped ion implantation depth, and the P-well ion implantation energy is greater than the N-type drain lightly doped ion implantation energy.
[0061] Step S4, then, similarly, using the second photoresist layer (not shown) formed by the second photomask as a mask, perform N-well ion implantation and P-type drain lightly doped (LDD) ion implantation in the second active area II. Specifically, a second photoresist layer is formed, the second photoresist layer has an opening in the second active area II, the second photoresist layer exposes the second active area II, and the second photoresist layer covers the first active area I. Using the second photoresist layer as a mask, first perform N-well (Well) ion implantation in the second active area II to form an N-well. The N-well ion implantation also passes through the second gate layer and the second gate oxide layer into the substrate below. Using the second photoresist layer as a mask, perform P-type drain lightly doped (LDD) ion implantation in the second active area II to form a P-type lightly doped area. In the second active area II, the N-well ion implantation depth is greater than the P-type drain lightly doped ion implantation depth, and the N-well ion implantation energy is greater than the P-type drain lightly doped ion implantation energy.
[0062] By performing light drain doping (LDD), the short channel effect and hot carrier effect are suppressed, the concentration gradient at the junction of the channel, drain and source is reduced, and the electric field strength of the source and drain is reduced to a certain extent. By performing light drain doping (LDD), the lightly doped drain region has a lighter doping in the overlapping area with the gate layer, which can increase the penetration voltage of the LDD junction, improve the channel penetration characteristics of the device, reduce the hot carrier effect, and improve the reliability of the device.
[0063] The order of step S3 and step S4 can be swapped; step S3 can be performed first and then step S4; or step S4 can be performed first and then step S3.
[0064] Then, if Figure 7As shown, a first sidewall spacer 17 is formed on the substrate of the first active area I, and the first sidewall spacer 17 covers the sidewalls of the first gate oxide layer 12 and the first gate layer 13; a second sidewall spacer is formed on the substrate of the second active area II, and the second sidewall spacer covers the sidewalls of the second gate oxide layer and the second gate layer.
[0065] Step S5: Figure 7 As shown, N-type ion heavy doping implantation is performed in the first active region I. Specifically, a third photoresist layer 18 is formed, the third photoresist layer 18 has an opening in the first active region I, the third photoresist layer 18 exposes the first active region I, and the third photoresist layer 18 covers the second active region II. Using the third photoresist layer 18 as a mask, N-type ion heavy doping implantation is performed in the first active region I. A source region 19 and a drain region are respectively formed in the substrate on both sides of the first sidewall 17, and an NMOS is formed in the first active region I.
[0066] Step S6, performing P-type ion heavy doping implantation in the second active region II. Specifically, a fourth photoresist layer (not shown) is formed, the fourth photoresist layer has an opening in the second active region II, the fourth photoresist layer exposes the second active region II, and the fourth photoresist layer covers the first active region I. Using the fourth photoresist layer as a mask, P-type ion heavy doping implantation is performed in the second active region II, a source region and a drain region are respectively formed in the substrate on both sides of the second sidewall, and a PMOS is formed in the second active region II.
[0067] The order of step S5 and step S6 can be swapped; step S5 can be performed first and then step S6; or step S6 can be performed first and then step S5.
[0068] Next, metal silicide is formed. A layer of metal (such as Ti, Co, NiPt, etc.) can be deposited on the first gate layer 13, the second gate layer, and the first active region I and the second active region II by physical vapor deposition. Then, rapid thermal annealing and selective wet etching are performed to finally form metal silicide on the surface of the first gate layer 13 and the second gate layer, and the substrate surface of the first active region I and the second active region II. Metal silicide includes TiSi 2 , CoSi 2 Metal Ti, Co or NiPt will not react with dielectric materials to form metal silicides, but will only react with polysilicon in direct contact and substrate silicon in the active area to form metal silicides to reduce sheet resistance and contact resistance, resulting in smaller series resistance, reduced RC delay, and increased circuit speed.
[0069] Next, metal interconnection is formed; specifically, a dielectric layer is deposited, the dielectric layer covers the substrate, the first sidewall, the first gate layer, the second sidewall and the second gate layer, etc., a chemical mechanical polishing (CMP) process is used to complete the dielectric layer flattening process, and then a dry etching process is used to complete the device contact hole processing. The device contact hole filling process is completed by a tungsten sputtering process and a tungsten chemical mechanical flattening process. The gate, source region and drain region can be led out through the contact hole. A metal film layer is sputtered and a metal wiring etching process is completed.
[0070] Combination Figure 8 As shown, the method for manufacturing a semiconductor device provided by the present invention is manufactured on a low-cost, cost-effective process platform, and the P-well ion implantation and the N-type drain lightly doped (LDD) ion implantation share a first mask, and the N-well ion implantation and the P-type drain lightly doped (LDD) ion implantation share a second mask, saving two masks for the two processes of forming the N-well and forming the P-well separately. Under the process conditions of retaining the two LDD ion implantations of the N-type drain lightly doped and the P-type drain lightly doped, the hot carrier effect performance of the NMOS tube is guaranteed, the substrate leakage current is greatly reduced, and the reliability test is passed. Not only the hot carrier effect performance of the semiconductor device is guaranteed, but also the purpose of saving the mask cost is achieved.
[0071] The hot carrier injection of high-voltage NMOS tubes is worse than that of PMOS tubes. The majority carriers of NMOS tubes are electrons, and the electron mobility is higher than the majority carrier holes of PMOS tubes. Therefore, under the same electric field, the hot carrier effect injection of NMOS tubes will be worse. The present invention retains the process conditions of two LDD ion implantations of N-type drain light doping and P-type drain light doping, ensures the hot carrier effect performance of NMOS tubes, and greatly reduces substrate leakage current.
[0072] For example, the semiconductor device of this embodiment may be a CMOS device, and the operating voltage is, for example, 7V, that is, when the gate voltage and the drain voltage are 7V, the transistor is fully turned on. According to actual tests, the substrate leakage current Isub performance of the NMOS tube of the 7V CMOS device formed by the method for manufacturing the semiconductor device of the present invention is better than that of the NMOS tube formed by the method for manufacturing the semiconductor device of the present invention. Figure 2 The mask-saving logic process of the 5V CMOS device has been significantly improved, and the substrate leakage current Isub has been reduced to 1 / 3 of the original state, which is only 1.7% of the saturation current Idsat.
[0073] In summary, the present invention provides a method for manufacturing a semiconductor device, comprising: step S1, providing a substrate, and defining a first active area and a second active area on the substrate by shallow trench isolation; step S2, sequentially forming a first gate oxide layer and a first gate layer on the substrate of the first active area; and sequentially forming a second gate oxide layer and a second gate layer on the substrate of the second active area; step S3, using a first photoresist layer formed by a first mask as a mask, performing P-well ion implantation and N-type drain lightly doped ion implantation in the first active area; step S4, using a second photoresist layer formed by a second mask as a mask, performing N-well ion implantation and P-type drain lightly doped ion implantation in the second active area; step S5, performing N-type ion heavy doping implantation in the first active area to form a source area and a drain area of an NMOS tube; step S6, performing P-type ion heavy doping implantation in the second active area to form a source area and a drain area of a PMOS tube.
[0074] The manufacturing method of the semiconductor device provided by the present invention is manufactured on a low-cost, high-cost-performance process platform, and the P-well ion injection and the N-type drain lightly doped (LDD) ion injection share the first mask, and the N-well ion injection and the P-type drain lightly doped (LDD) ion injection share the second mask, thereby saving the masks (masks) of the two processes of forming the N-well and forming the P-well separately. Under the process conditions of retaining the two LDD ion injections of the N-type drain lightly doped (LDD) and the P-type drain lightly doped (LDD), the hot carrier effect performance of the NMOS tube is guaranteed, the substrate leakage current is greatly reduced, and the reliability test is passed. Not only the electrical performance of the semiconductor device is guaranteed, but also the purpose of saving the mask cost is achieved.
[0075] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the method disclosed in the embodiment, since it corresponds to the device disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.
[0076] The above description is only a description of the preferred embodiment of the present invention, and is not any limitation on the scope of rights of the present invention. Any technical personnel in this field can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.
Claims
1. A method for manufacturing a semiconductor device, characterized in that: include: Step S1, providing a substrate, and defining a first active area and a second active area on the substrate by shallow trench isolation; Step S2, sequentially forming a first gate oxide layer and a first gate layer on the substrate of the first active region; sequentially forming a second gate oxide layer and a second gate layer on the substrate of the second active region; Step S3, using the first photoresist layer formed by the first photomask as a mask, performing P-well ion implantation and N-type drain lightly doped ion implantation in the first active region; Step S4, using the second photoresist layer formed by the second photomask as a mask, performing N-well ion implantation and P-type drain lightly doped ion implantation in the second active region; Step S5, performing N-type ion heavy doping implantation on the first active region to form a source region and a drain region of the NMOS tube; Step S6: perform P-type ion heavy doping implantation on the second active region to form a source region and a drain region of the PMOS tube.
2. The method for manufacturing a semiconductor device according to claim 1, wherein: Step S2 specifically includes: forming a gate oxide material layer and a gate material layer sequentially covering the substrate; A second imaged photoresist layer is formed on the surface of the gate material layer, and the gate material layer and the gate oxide layer material layer are sequentially etched using the imaged second photoresist layer as a mask to form the first gate layer and the first gate oxide layer located in the first active area, and the second gate layer and the second gate oxide layer located in the second active area.
3. The method for manufacturing a semiconductor device according to claim 1, wherein: Step S3 specifically includes: forming the first photoresist layer, wherein the first photoresist layer exposes the first active area and covers the second active area; Using the first photoresist layer as a mask, the P-well ion implantation is first performed on the first active region to form a P-well; and then the N-type drain lightly doped ion implantation is performed on the first active region to form an N-type lightly doped region.
4. The method for manufacturing a semiconductor device according to claim 3, wherein: In step S3, in the first active region, the P-well ion implantation depth is greater than the N-type drain lightly doped ion implantation depth, and the P-well ion implantation energy is greater than the N-type drain lightly doped ion implantation energy.
5. The method for manufacturing a semiconductor device according to claim 1, wherein: Step S4 specifically includes: forming the second photoresist layer, wherein the second photoresist layer exposes the second active area and covers the first active area; Using the second photoresist layer as a mask, the N-well ion implantation is first performed on the second active region to form an N-well; and then the P-type drain lightly doped ion implantation is performed on the second active region to form a P-type lightly doped region.
6. The method for manufacturing a semiconductor device according to claim 5, wherein: In step S4, in the second active region, the N-well ion implantation depth is greater than the P-type drain lightly doped ion implantation depth, and the N-well ion implantation energy is greater than the P-type drain lightly doped ion implantation energy.
7. The method for manufacturing a semiconductor device according to claim 1, wherein: In step S3, the P-well ion implantation also passes through the first gate layer and the first gate oxide layer and enters the substrate below; In step S4, the N-well ion implantation also passes through the second gate layer and the second gate oxide layer and enters the substrate below.
8. The method for manufacturing a semiconductor device according to claim 1, wherein: The operating voltage of the semiconductor device includes: 7V or 5V.
9. The method for manufacturing a semiconductor device according to claim 1, wherein: After step S4 and before step S5, the manufacturing method further includes: A first sidewall is formed on the substrate of the first active region, and the first sidewall covers the sidewalls of the first gate oxide layer and the first gate layer; a second sidewall is formed on the substrate of the second active region, and the second sidewall covers the sidewalls of the second gate oxide layer and the second gate layer.
10. The method for manufacturing a semiconductor device according to claim 9, wherein: After step S6, the manufacturing method further includes: Forming metal silicide, forming the metal silicide on the surfaces of the first gate layer and the second gate layer, and the surfaces of the substrate of the first active region and the second active region; forming a dielectric layer, the dielectric layer covering the substrate, the first sidewall, the first gate layer, the second sidewall and the second gate layer; and forming a contact hole in the dielectric layer; Metal interconnection is formed, metal is filled in the contact hole, and the gate, source region and drain region of the NMOS tube and the PMOS tube are led out.