Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. Embodiments of the present disclosure relate to forming isolation structures in gate structures to prevent current leakage through source / drain regions (EPIs), transistors, and silicon substrates. An isolation structure may be formed in the gate structure before or after replacing the gate sequence.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same. Background Art

[0002] As the semiconductor industry has advanced to nanometer technology process nodes in pursuit of higher device density, higher performance and lower cost, challenges from both manufacturing issues and design issues have led to the development of multi-gate devices, such as fin field effect transistors (FinFETs) and gate all around (GAA) transistors. In order to continue to provide the required size and increased density for multi-gate devices in advanced technology nodes, the gate pitch needs to continue to decrease.

[0003] The device layout may employ polysilicon (poly) sections that are formed as diffusion edges (PODE) or continuous polysilicon on diffusion edges (COPED) to avoid leakage between adjacent devices. A PODE pattern or a CPODE pattern is used to form the polysilicon sections. As device dimensions (e.g., gate pitch) shrink, design schemes (e.g., PODE and CPODE schemes) may face the following difficulties: it is difficult to provide the levels of device density, cell isolation, and device performance required for aggressively scaling circuits and devices. Summary of the invention

[0004] According to one embodiment of the present disclosure, a semiconductor device is provided, including: a semiconductor substrate; a fin structure located on the semiconductor substrate and extending along a first direction; a plurality of gate structures crossing the fin structure along a second direction; a plurality of source / drain regions located above the fin structure and between the plurality of gate structures; a first isolation structure formed in a first gate structure among the plurality of gate structures, wherein the first isolation structure has a first width along the first direction; and a second isolation structure formed in a second gate structure among the plurality of gate structures, wherein the second isolation structure has a second width along the first direction, the first gate structure is positioned adjacent to the second gate structure, and the first width is greater than the second width.

[0005] According to one embodiment of the present disclosure, a semiconductor device is provided, comprising: a semiconductor substrate; a plurality of fin structures located on the semiconductor substrate and extending along a first direction; a gate structure arranged across the plurality of fin structures and extending along a second direction; and an isolation structure arranged in the gate structure, wherein the isolation structure comprises: a first segment having a first width; and a second segment having a second width, wherein the first width is greater than the second width.

[0006] According to one embodiment of the present disclosure, a method for forming a semiconductor device is provided, comprising: forming a plurality of fin structures on a substrate along a first direction; forming a plurality of gate structures across the plurality of fin structures; depositing a mask layer over the plurality of gate structures; forming a pattern in the mask layer, wherein the pattern comprises: a first opening aligned with a first gate structure among the plurality of gate structures; and a second opening aligned with a second gate structure among the plurality of gate structures, wherein the first gate structure and the second gate structure are adjacent to each other, the first opening having a first width along the first direction, the second opening having a second width along the first direction, and the first width being greater than the second width; forming a first isolation opening and a second isolation opening using the pattern in the mask layer; and depositing a dielectric layer to fill the first isolation opening and the second isolation opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read together with the accompanying drawings, various aspects of the present disclosure can be best understood through the following detailed description. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for clarity of discussion, the size of various features may be arbitrarily increased or reduced.

[0008] Figures 1A-1I The pattern design of the isolation structure according to an embodiment of the present disclosure is schematically shown.

[0009] Figure 2A-2R Variations of the pattern design of the isolation structure according to an embodiment of the present disclosure are schematically shown.

[0010] Figure 3 is a flow chart of a method for manufacturing a semiconductor substrate according to an embodiment of the present disclosure.

[0011] Figures 4A-4C , Figures 5A-5D , Figures 6A-6C , Figures 7A-7C , Figures 8A-8C , Figures 9A-9F , Figures 10A-10D , Figures 11A-11D , Figures 12A-12E Various stages of manufacturing a semiconductor device according to an embodiment of the present disclosure are schematically illustrated.

[0012] Figures 13A-13B and Figures 14A-14C Various stages of manufacturing a semiconductor device according to an embodiment of the present disclosure are schematically illustrated.

[0013] Fig.15 is a flow chart of a method for manufacturing a semiconductor substrate according to an embodiment of the present disclosure.

[0014] Figures 16A-16C , Figures 17A-17C , Figures 18A-18C , Figures 19A-19C , Figures 20A-20F , Figures 21A-21C and Figures 22A-22C Various stages of manufacturing a semiconductor device according to an embodiment of the present disclosure are schematically illustrated.

[0015] Figures 23A-23B , Figures 24A-24B , Figures 25A-25B and Figures 26A-26B Various stages of manufacturing a semiconductor device according to an embodiment of the present disclosure are schematically illustrated. DETAILED DESCRIPTION

[0016] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or above a second feature may include an embodiment in which the first feature and the second feature are directly in contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself dictate the relationship between the various embodiments and / or configurations discussed.

[0017] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "down," "above," "above," "top," "up," and the like may be used herein to describe the relationship of one element or feature relative to another (one or more) elements or (one or more) features as shown in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0018] The foregoing generally summarizes some aspects of the embodiments described in the present disclosure. Although some embodiments described herein are described in the context of nanosheet channel FETs, implementations of some aspects of the present disclosure may be used in other processes and / or other devices, such as planar FETs, Fin-FETs, horizontal gate all around (HGAA) FETs, vertical gate all around (VGAA) FETs, and other suitable devices. It will be readily understood by those of ordinary skill in the art that other modifications that may be made are contemplated to be within the scope of the present disclosure. In addition, although method embodiments may be described in a particular order, various other method embodiments may be performed in any logical order and may include fewer or more steps than described herein. In the present disclosure, source / drain regions refer to source and / or drain. Source and drain may be used interchangeably.

[0019] The fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. In general, double patterning or multiple patterning processes combine a photolithography process with a self-aligned process, thereby allowing patterns to be created with, for example, a smaller pitch than can be obtained using a single direct photolithography process.

[0020] Embodiments of the present disclosure relate to forming an isolation structure in a gate structure to prevent current leakage through a source / drain region (EPI), a transistor, and a silicon substrate. The isolation structure may be formed in the gate structure before or after a replacement gate sequence. A continuous polysilicon on diffusion edge (CPODE) process (involving a silicon gate etching process) may be performed before the replacement gate sequence. A continuous metal on diffusion edge (CMODE) process (involving a metal gate etching process) may be performed after the replacement gate sequence.

[0021] Embodiments of the present disclosure relate to a method for patterning a CPODE or CMODE to avoid photoresist stripping or pattern merging. First, a plurality of fin structures are formed along the x direction. Each fin structure may include a type of epitaxial semiconductor material for a FinFET structure or a multilayer epitaxial semiconductor layer of a GAA structure. Then, a plurality of gate structures are formed on the fin structure along the y direction. The gate structure has a gate pitch along the x direction. Then, a source / drain region is formed along the fin structure and between the gate structures. First, a CPODE or CMODE opening pattern is formed in a hard mask layer. The CPODE or CMODE pattern includes a group of isolation openings along a group of adjacent gate structures (i.e., along the y direction). According to an embodiment of the present disclosure, the CPODE or CMODE pattern includes isolation openings having uneven widths along the x direction. Specifically, the group of isolation openings includes at least one wide opening and one narrow opening. Each wide opening is located next to a narrow opening. The width of the wide opening along the x direction is at least about 50% of the gate pitch. Then, multiple etching processes are performed to remove the exposed portions of the gate structure, the fin structure, and the substrate. Isolation material is then filled in to replace the removed portions of the substrate, fin structure, and gate structure.

[0022] As the gate pitch decreases, the variation in the width of the isolation opening avoids photoresist stripping, pattern merging, and pattern loading in subsequent processes. The wide opening results in a greater etching depth of the substrate, thereby ensuring isolation between the source / drain region and the transistor.

[0023] Figures 1A-1G The pattern design of the isolation structure according to an embodiment of the present disclosure is schematically shown. Figure 1A is a schematic top view of a semiconductor device 10 according to the present disclosure. Figure 1B-1C It is along Figure 1A Schematic cross-sectional view of the semiconductor device 10 along lines 1B- 1B, 1C- 1C, which are along fin structures in the semiconductor device 10 . Figure 1D , Figure 1E and Figure 1F It is along Figure 1A Schematic cross-sectional view of the semiconductor device 10 along lines 1D-1D, 1E-1E, and 1F-1F in FIG. 1 , which are along gate structures in the semiconductor device 10 . Figure 1G is a schematic plan view of the semiconductor device 10 , which shows an isolation structure for preventing leakage current.

[0024] The semiconductor device 10 includes a plurality of transistors formed in and on a semiconductor substrate 12. Specifically, the semiconductor device 10 includes a plurality of fin structures 14 formed on the semiconductor substrate 12 along the x direction. The fin structure 14 may include a single channel (for FinFET devices) or multiple channels (for GAA devices). A plurality of gate structures 16 (16a, 16b, 16c, collectively referred to as 16) are formed on the fin structure 14 along the y direction. The source / drain region 18 is formed by the fin structure 14 between the gate structures 16. The gate structure 16 has a gate pitch GP. In some embodiments, the gate pitch GP is less than 50nm, for example, the gate pitch is between about 20nm and about 30nm. The gate structure 20 may have a gate width GW along the x direction. The source / drain region 18 and the gate structure 16 therebetween form a transistor. Isolation structures 20 are formed in portions of gate structures 16 and extend into semiconductor substrate 12, thereby electrically isolating source / drain regions 18 on opposite sides of isolation structures 20 (isolation structures 20a, 20b, 20c are shown, collectively referred to as isolation structures 20). Isolation structures 20 may be formed by a CPODE process or a CMODE process.

[0025] like Figure 1A As shown, the isolation structures 20a, 20b, 20c are formed side by side in the continuously adjacent gate structures 16a, 16b, 16c. Figure 1B-1E As shown, the isolation structures 20a, 20b, 20c replace a portion of the gate structures 16a, 16b, 16c, cut the fin structure 14 below, and extend into the semiconductor substrate 12. The isolation structures 20a, 20b, 20c cut the fin structure 14 and electrically isolate the source / drain region 18l on the left from the isolation region 18r on the right. The source / drain region 18 between the isolation structures 20 becomes a dummy source / drain region 18d.

[0026] During the formation of the isolation structure 20 by the CPODE process or the CMODE process, a hard mask is first formed over the gate structure 16, and then a photolithography process is performed to form a mask opening in the hard mask. It has been observed that a mask opening having a wider width along the x-direction results in a greater etching depth in the semiconductor substrate 12, while a mask opening having a narrower width along the x-direction results in a smaller etching depth in the semiconductor substrate 12.

[0027] As the gate pitch decreases, it becomes increasingly challenging to form mask openings side by side. For example, photoresist defects such as stripping and scum may occur. The gate pattern may include a 1D gate pitch and a 2D gate pitch. The 1D gate pitch refers to the pitch along the direction of the fin structure (ie, the x direction). The 2D gate pitch refers to the pitch along the direction perpendicular to the fin structure (ie, the y direction). The gate pitch discussed below refers to the 1D gate pitch. It is also observed that the mask spacing needs to be less than about 50% of the gate pitch to avoid stripping. When the gate pitch decreases, the mask spacing width may need to be greater than 50% of the gate pitch to achieve sufficient etching depth in the semiconductor substrate 12 to provide isolation. Embodiments of the present disclosure provide mask opening designs that avoid photoresist defects without compromising isolation function.

[0028] In some embodiments, the isolation structure 20 is formed in two or more adjacent gate structures 16. In some embodiments, the isolation structures 20 formed in two or more adjacent gate structures 16 have staggered widths along the x-direction. For example, a wide isolation structure 20 is positioned parallel to one or two narrow isolation structures 20. In other words, the two wide isolation structures 20 are not positioned adjacent to each other. By positioning the narrow isolation structure 20 next to the wide isolation structure 20, the isolation structure 20 can be formed without causing photoresist defects.

[0029] In some embodiments, the isolation structure 20 within one gate structure 16 may include a single segment having one width in the x-direction, such as the isolation structure 20c. Alternatively, the isolation structure 20 in one gate structure 16 may include two or more segments having different widths, such as the isolation structures 20a and 20b. The segments of the isolation structure 20 have different widths.

[0030] For example, the isolation structure 20 may include a wide section 20w having a width W1 along the x-direction and a narrow section having a width W2. The width W1 is greater than about 50% of the gate pitch GP. For example, the width W1 is in a range between about 0.5 GP and about 0.6 GP. The width W2 is in a range between about 0.25 GP and 0.5 GP. In some embodiments, the width W1 and the width W2 are selected so that the average width of the isolation structure 20 is less than 0.5 GP, for example, the average width of the isolation structure 20 is between about 0.4 GP and 0.45 GP.

[0031] In some embodiments, adjacent sections of the isolation structure 20 in adjacent gate structures 16 may have different widths. For example, along the same fin structure 14, a wide section 20w of the isolation structure 20 is located adjacent to one or two narrow sections 20n. The wide section 20w of the isolation structure 20 has a sufficient depth to provide isolation on the fin structure 14, while the adjacent narrow sections 20n of the isolation structure 20 avoid photoresist defects during manufacturing.

[0032] In some embodiments, a single isolation structure 20 (eg, isolation structures 20a, 20b) may include a wide segment 20w and a narrow segment 20n. By connecting the wide segment 20w and the narrow segment 20n, the length of the isolation structure 20 along the y direction increases, facilitating a greater etching depth during fabrication.

[0033] Figure 1H 2 is a schematic top view of an isolation structure 20 according to the present disclosure, the isolation structure 20 having one narrow section 20n connected to two wide sections 20w. The isolation structure 20 is symmetrical about a central axis 21. Fig. 1I 2 is a schematic diagram of an isolation structure 20 ′ according to another embodiment. The isolation structure 20 ′ is similar to the isolation structure 20 , except that the narrow section 20 n is disposed off-center, so that the isolation structure 20 ′ has a straight line along the y direction on one side.

[0034] In some embodiments, the isolation structures 20 in adjacent gate structures 16 also vary in length along the y direction. Figure 1A As shown, adjacent isolation structures 20a, 20b, 20c have reduced lengths. By reducing the lengths of the isolation structures 20a, 20b, 20c, the number of dummy source / drain regions 18d is also reduced, thereby increasing the effective device density.

[0035] exist Figure 1A In the design of FIG. 1 , the isolation structure 20c includes a wide section 20w having a length L1 and a width W1. The length L1 of the isolation structure 20c may be in a range between about 2 times and 10 times of W1. The length L1 may be selected based on the circuit design. In some embodiments, the length L1 may be selected to ensure that the isolation structure reaches a sufficient depth in the semiconductor substrate 12. The isolation structure 20c may extend over one or more fin structures 14. Figure 1D As shown, the fin structure 14 is formed on the semiconductor substrate 12. The lower portion of the fin structure 14 is surrounded by a shallow trench isolation (STI) layer 22. The isolation structure 20c cuts the two fin structures 14 below and extends into the semiconductor substrate 14. In some embodiments, the isolation structure 20c extends into the semiconductor substrate 14 to have a depth D1 along the z-direction. The depth D1 is selected to ensure that the isolation structure 20c electrically isolates the source / drain region 18l from the source / drain region 18r, as shown in FIG. Figure 1B In some embodiments, the depth D1 is in a range from about 20 nm to about 90 nm.

[0036] Isolation structure 20b is adjacent to isolation structure 20c. Isolation structure 20b includes two wide segments 20w connected by narrow segment 20n. Narrow segment 20n has a length L1 or substantially equal to the length of isolation structure 20c, thereby providing a spacing 24bc wider than about 50% of the gate pitch GP. Wide segment 20w is formed from both ends of narrow segment 20n. For example, isolation structure 20b may be similar to Figure 1H and Fig. 1I Alternatively, the isolation structure 20b may include only one wide section 20w and one narrow section 20n. The wide section 20w may have a length L2. The length L2 may be long enough to cover one or more fin structures 14. The isolation structure 20b has a total length L3, which is equal to L1 plus twice L2. Figure 1E As shown, the isolation structure 20b cuts the four fin structures 14 below and extends into the semiconductor substrate 14. In some embodiments, the narrow section 20n of the isolation structure 20b extends into the semiconductor substrate 14 to have a depth D2 along the z direction, while the wide section 20w of the isolation structure 20b extends into the semiconductor substrate to have a depth D1. The depth D2 is less than the depth D1. In some embodiments, the depth D2 is in a range between about 0nm and about 70nm. In some embodiments, the difference between D1 and D2 is less than about 60nm. In some embodiments, the ratio of D1:D2 is in a range between about 1.2 and about 3.0, for example, between about 1.5 and about 2.0. In some embodiments, at the depth D2, the isolation structure 20b may not be sufficient to isolate the source / drain region 18 on the opposite side of the isolation structure 20b. Therefore, the wide section 20w of the isolation structure 20b provides electrical isolation on the fin structure 14 below. The narrow section 20n of the isolation structure 20b does not provide electrical isolation on the fin structure 14 below. The fin structure 14 below the narrow section 20 n of the isolation structure 20 b is electrically isolated by the isolation structure 20 c .

[0037] Isolation structure 20a is adjacent to isolation structure 20b. Similar to isolation structure 20b, isolation structure 20a includes two wide segments 20w connected by a narrow segment 20n. Narrow segment 20n has a length L3 or substantially equal to the length of isolation structure 20b, thereby providing a spacing 24ab wider than about 50% of the gate pitch GP. Wide segment 20w is formed from both ends of narrow segment 20n. Wide segment 20w may have a length L4. Length L4 may be long enough to cover one or more fin structures 14. Figure 1FAs shown, the isolation structure 20c cuts through the six fin structures 14 below and extends into the semiconductor substrate 14. In some embodiments, the narrow section 20n of the isolation structure 20a extends into the semiconductor substrate 14 to have a depth D2 along the z-direction, while the wide section 20w of the isolation structure 20a extends into the semiconductor substrate to have a depth D1. Therefore, the wide section 20w of the isolation structure 20a provides electrical isolation on the fin structure 14 below. The narrow section 20n of the isolation structure 20a does not provide electrical isolation on the fin structure 14 below. The fin structure 14 below the narrow section 20n of the isolation structure 20a relies on the isolation structures 20c and 20b for electrical isolation.

[0038] Figure 1G The galvanic isolation across the fin structure 14 is schematically illustrated. Figure 1G The X marks in represent the electrical isolation on both sides of the fin structure 14. Figure 1G As shown, the wide sections 20w of the isolation structures 20a, 20b, 20c provide electrical isolation on the fin structure 14. Although each fin structure 14 may be segmented by one or more isolation structures 20, not every isolation structure 20 intersecting a fin structure 14 functions to provide electrical isolation to the fin structure 14.

[0039] As described above, embodiments of the present disclosure arrange narrow and wide sections of an isolation structure to achieve effective isolation while avoiding photoresist defects. The wide and narrow sections may be arranged in various designs. Figure 2A-2Q Variations of the pattern design of the isolation structure according to an embodiment of the present disclosure are schematically shown.

[0040] Figure 2A-2B 1 is a schematic top view of a semiconductor device 10a according to an embodiment of the present disclosure. The semiconductor device 10a is similar to the semiconductor device 10, but the arrangement of the narrow segments and the wide segments in the isolation structure is different. In the semiconductor device 10a, the isolation structure 20a on the left includes a single wide segment 20w, the isolation structure 20c on the right includes a single narrow segment 20n, and the isolation structure 20b in the middle includes a narrow segment 20n connecting the two wide segments 20w. Figure 2B As shown, the isolation structure 20 a on the left provides electrical isolation to the source / drain region 18 l in the fin structure 14 from the rest of the source / drain region 18 , and the wide section of the isolation structure 20 b provides additional electrical isolation to the source / drain region 18 r in the fin structure 14 .

[0041] Figure 2C-2D1 is a schematic top view of a semiconductor device 10b according to an embodiment of the present disclosure. The semiconductor device 10b is similar to the semiconductor device 10a, but the arrangement of the narrow segments and the wide segments in the isolation structure is different. In the semiconductor device 10b, the isolation structure 20a on the left includes a single wide segment 20w, the isolation structure 20c on the right includes a wide segment 20w, and the isolation structure 20b in the middle includes a narrow segment 20n connecting the two wide segments 20w. Figure 2D As shown, the isolation structure 20a on the left provides electrical isolation to the source / drain region 18l in the fin structure 14 from the rest of the source / drain region 18, and the isolation structure 20c on the right and the wide section of the isolation structure 20b provide additional electrical isolation to the source / drain region 18r in the fin structure 14 from the rest of the source / drain region 18.

[0042] Figure 2E , Figure 2F and Figure 2G A semiconductor device 10 c according to an embodiment of the present disclosure is schematically illustrated. Figure 2E-2F is a schematic top view of a semiconductor device 10 c according to an embodiment of the present disclosure. Figure 2G 1 is a schematic cross-sectional view of a semiconductor device 10c along a fin structure 14. The semiconductor device 10c is similar to the semiconductor device 10, but the arrangement of the narrow segments and the wide segments in the isolation structure is different. In the semiconductor device 10c, each of the isolation structures 20a, 20b, 20c includes a single segment. The wide segments and the narrow segments are alternately arranged above the gate structure 16. Figure 2E The semiconductor device 10c is schematically shown at a stage when mask openings 24a, 24b, 24c are formed through the mask layer 24. Figure 2F As shown, each of the isolation structure 20a on the left and the isolation structure 20c on the right includes a single wide section 20w, and the isolation structure 20b in the middle includes a single narrow section 20n. Figure 2F and Figure 2G As shown, the isolation structure 20 a on the left and the isolation structure 20 c on the right provide electrical isolation between the source / drain region 18 l and the source / drain region 18 r in the fin structure 14 .

[0043] Figure 2H , Fig.2I and Figure 2J A semiconductor device 10 d according to an embodiment of the present disclosure is schematically illustrated. Figure 2H-2I is a schematic top view of a semiconductor device 10 d according to an embodiment of the present disclosure. Figure 2J1 is a schematic cross-sectional view of a semiconductor device 10d along a fin structure 14. The semiconductor device 10d is similar to the semiconductor device 10c, but the arrangement of the narrow segments and the wide segments in the isolation structure is different. In the semiconductor device 10d, each of the isolation structures 20a, 20b, and 20c includes a single segment. The isolation structure 20c on the right includes a single wide segment 20w, and each of the isolation structure 20b in the middle and the isolation structure 20a on the left includes a single narrow segment 20n. Fig.2I and Figure 2J As shown, the isolation structure 20 c on the right provides electrical isolation between the source / drain region 18 l and the source / drain region 18 r in the fin structure 14 .

[0044] Figure 2K 1 is a schematic top view of a semiconductor device 10e according to an embodiment of the present disclosure. The semiconductor device 10e includes a design of an isolation structure. The semiconductor device 10e includes an isolation structure 20 above a set of gate structures 16. The semiconductor device 10e includes two wide isolation structures 20w formed above an external gate structure 16 in the set of gate structures 16 and a narrow isolation structure 20n formed above an internal gate structure 16 in the set of gate structures 16. In some embodiments, the wide isolation structure 20w is a long segment and the narrow isolation structure 20n is a short segment. In some embodiments, a plurality of short narrow segments 20n may be formed above each internal gate structure 16.

[0045] Figure 2L 1 is a schematic top view of a semiconductor device 10f according to an embodiment of the present disclosure. The semiconductor device 10f includes a design of an isolation structure. The semiconductor device 10f includes an isolation structure 20 on a set of gate structures 16. The semiconductor device 10e includes a wide isolation structure 20w formed on one side of the set of gate structures 16, and a narrow isolation structure 20n formed on the rest of the set of gate structures 16. In some embodiments, the wide isolation structure 20w is a long segment and the narrow isolation structure 20n is a short segment. Alternatively, one or more narrow isolation structures 20n may be arranged with a wide segment.

[0046] Figure 2M 1 is a schematic top view of a semiconductor device 10g according to an embodiment of the present disclosure. The semiconductor device 10g includes a design of an isolation structure. The semiconductor device 10g includes two wide isolation structures 20w formed on the external gate structure 16 and a narrow isolation structure 20n formed between the two wide isolation structures 20w. In some embodiments, the middle narrow isolation structure 20n can be connected to the wide isolation structure 20w.

[0047] Figure 2N1 is a schematic top view of a semiconductor device 10h according to an embodiment of the present disclosure. The semiconductor device 10h includes a design of an isolation structure. The semiconductor device 10h is similar to Figure 2M 1. Referring to the semiconductor device 10g in FIG. 10, the semiconductor device 10h includes a wide isolation structure 20w and a narrow isolation structure 20n formed on the external gate structure 16.

[0048] Fig.2O 1 is a schematic top view of a semiconductor device 10i according to an embodiment of the present disclosure. The semiconductor device 10i includes a design of an isolation structure. The semiconductor device 10i includes an isolation structure 20 above a set of gate structures 16. The semiconductor device 10i is similar to the semiconductor device 10e, except that the isolation structure 20 in the semiconductor device 10i is a short segment. The semiconductor device 10i includes two wide isolation segments 20w formed above an outer gate structure 16 in the set of gate structures 16 and a narrow isolation segment 20n formed above an inner gate structure 16 in the set of gate structures 16.

[0049] Figure 2P 1 is a schematic top view of a semiconductor device 10j according to an embodiment of the present disclosure. The semiconductor device 10j includes a design of an isolation structure. The semiconductor device 10j includes an isolation structure 20 above a set of gate structures 16. The semiconductor device 10j is similar to Fig.2O The semiconductor device 10i is different in that the semiconductor device 10j only includes one wide isolation structure 20w located above the outer gate structure 16.

[0050] Figure 2Q 1 is a schematic top view of a semiconductor device 10k according to an embodiment of the present disclosure. The semiconductor device 10k includes a design of an isolation structure. The semiconductor device 10k is similar to Figure 2M The semiconductor device 10g in FIG. 1 is different in that the semiconductor device 10k includes short and wide isolation structures 20w and long isolation structures with short sections 20n that are alternately arranged.

[0051] Figure 2R 1 is a schematic top view of a semiconductor device 101 according to an embodiment of the present disclosure. The semiconductor device 101 includes a design of an isolation structure. The semiconductor device 101 is similar to Figure 2Q In the semiconductor device 10k, the semiconductor device 101 includes short and narrow isolation structures 20n and long and wide isolation structures 20w that are alternately arranged.

[0052] Figure 3 is a flow chart of a method 100 for manufacturing a semiconductor device according to an embodiment of the present disclosure. Figures 4A-4C and Figures 12A-12CVarious stages of manufacturing a semiconductor device 200 according to an embodiment of the present disclosure are schematically illustrated.The semiconductor device 200 may include an isolation structure similar to the semiconductor devices 10, 10a-101.

[0053] The method 100 begins at operation 102, in which a plurality of semiconductor fins 220 are formed on a substrate 210, such as Figure 4A , Figure 4B and Figure 4C as shown in . Figure 4A is a schematic perspective view of a semiconductor device 200 . Figure 4B is a cross-sectional view of the semiconductor device 200 along the x-direction. Figure 4C is a schematic cross-sectional view of the semiconductor device 200 along the y direction.

[0054] The substrate 210 may include a single crystal semiconductor material, such as but not limited to Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. Depending on the circuit design, the substrate 210 may include various doping configurations. For example, different doping profiles (e.g., n-well, p-well) may be formed in the substrate 210 in regions designed for different device types (e.g., n-type field effect transistors (NFETs) and p-type field effect transistors (PFETs)). In some embodiments, the substrate 210 may be a silicon-on-insulator (SOI) substrate including an insulator structure for enhancement.

[0055] The semiconductor fin 220 is formed on and in the substrate 210. The semiconductor fin 220 may be formed by patterning a hard mask deposited on the semiconductor stack and one or more etching processes. The semiconductor fin 220 is formed along the x-direction.

[0056] Then, an isolation layer 222 is formed in the trenches between the semiconductor fins 220. The isolation layer 222 may be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD), or other suitable deposition processes. In some embodiments, the isolation layer 222 may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics, or combinations thereof. In some embodiments, the isolation layer is formed to cover the semiconductor fins 220 by a suitable deposition process (e.g., atomic layer deposition (ALD)), and then recessed etching is performed using a suitable anisotropic etching process to expose the channel portion 218 of the semiconductor fin 220.

[0057] In some embodiments, dielectric fins 221 may be formed between semiconductor fins 220. Dielectric fins 221 may be formed during deposition and etching back of isolation layer 222.

[0058] In operation 104, a sacrificial gate structure 228 and a spacer layer 230 are then formed over the semiconductor fin 220, such as Figures 4A-4C As shown. A sacrificial gate dielectric layer 224 is deposited on the exposed surface of the semiconductor device 200. The sacrificial gate dielectric layer 224 may be conformally formed on the semiconductor fins 220 and the isolation layer 222. In some embodiments, the sacrificial gate dielectric layer 224 may be deposited by a CVD process, a sub-atmospheric pressure CVD (SACVD) process, a FCVD process, an ALD process, a PVD process, or other suitable processes. The sacrificial gate dielectric layer 224 may include one or more layers of dielectric material, such as SiO2, SiN, a high-K dielectric material, and / or other suitable dielectric materials.

[0059] A sacrificial gate electrode layer 226 is deposited over the sacrificial gate dielectric layer 224. The sacrificial gate electrode layer 226 may be blanket deposited over the sacrificial gate dielectric layer 224. The sacrificial gate electrode layer 226 includes silicon, such as polysilicon or amorphous silicon. In some embodiments, a planarization operation is performed on the sacrificial gate electrode layer 226. The sacrificial gate electrode layer 226 may be deposited using CVD (including LPCVD and PECVD), PVD, ALD, or other suitable processes. A patterning operation is performed over the sacrificial gate dielectric layer 224 and the sacrificial gate electrode layer 226 to form a sacrificial gate structure 228 that covers a portion of the semiconductor fin 220 designed as a channel region.

[0060] Then, a gate sidewall spacer 230 is formed on the sidewall of each sacrificial gate structure 228. After forming the sacrificial gate structure 228, the gate sidewall spacer 230 can be formed by blanket deposition of an insulating material followed by anisotropic etching to remove the insulating material from the horizontal surface. The gate sidewall spacer 230 can have a thickness in a range between about 3 nm and about 8 nm. In some embodiments, the insulating material of the gate sidewall spacer 230 is a silicon nitride-based material such as SiN, SiON, SiOCN, or SiCN, and combinations thereof. Figure 4A In the embodiment, the gate sidewall spacer 230 includes two layers. In other embodiments, the gate sidewall spacer 230 can be formed of fewer or more layers of dielectric material.

[0061] In operation 106, the semiconductor fins 220 are etched back and source / drain regions 240 are grown from the exposed semiconductor fins 220, such as Figures 4A-4CAs shown. The source / drain region 240 is formed by an epitaxial growth method using CVD, ALD, or molecular beam epitaxy (MBE). For NFET, the source / drain region 240 may include one or more layers of Si, SiP, SiC, and SiCP, or for PFET, the source / drain region 240 may include Si, SiGe, Ge. For PFET, a p-type dopant (e.g., boron (B)) may also be included in the source / drain region 240.

[0062] A contact etch stop layer (CESL) 242 and an interlayer dielectric (ILD) layer 244 are formed over the exposed surface. The CESL 242 is formed over the epitaxial source / drain regions 240 and the gate sidewall spacers 230. The CESL 242 may include Si3N4, SiON, SiCN, or any other suitable material, and may be formed by CVD, PVD, or ALD. The interlayer dielectric (ILD) layer 244 is formed over the contact etch stop layer (CESL) 242. The material of the ILD layer 244 includes compounds containing Si, O, C, and / or H, such as silicon oxide, SiCOH, and SiOC. Organic materials such as polymers may be used for the ILD layer 244. After the ILD layer 244 is formed, a planarization operation (e.g., CMP) is performed to expose the sacrificial gate electrode layer 226 for subsequent removal of the sacrificial gate structure 228. The ILD layer 244 protects the epitaxial source / drain regions 240 during the removal of the sacrificial gate structure 228.

[0063] In operation 108, a mask layer 248 is deposited on the semiconductor device 200, such as Figures 4A-4C As shown. Mask layer 248 may include one or more dielectric layers. Mask layer 248 may be deposited over sacrificial gate structure 228, gate spacer 230, CESL 242, and ILD layer 244. In some examples, one or more mask layers may include or be silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, or the like, or a combination thereof, and may be deposited by CVD, PVD, ALD, or another deposition technique. In some embodiments, mask layer 248 may be a film having compressive stress because the opening formed in the compressive stress film may be gapless. In some embodiments, mask layer 248 may be silicon nitride having a thickness in a range between about 650 angstroms and 850 angstroms, such as in a range between about 730 angstroms and about 750 angstroms.

[0064] In operation 110, a photolithography process is performed to form a CPODE pattern in a photoresist layer, such as Figures 5A-5C shown. Figure 5A is a schematic perspective view of a semiconductor device 200 . Figure 5B is a cross-sectional view of the semiconductor device 200 along the x-direction. Figure 5Cis a schematic cross-sectional view of the semiconductor device 200 along the y direction. Figure 5D is a schematic top view of a semiconductor device 200. In some embodiments, a three-layer photoresist stack including an underlayer 250, a backside anti-reflective coating (BARC) 252, and a photoresist (PR) layer 254 is deposited. A photolithography process is performed to form a CPODE pattern.

[0065] In some embodiments, the CPODE pattern may include a wide opening 256 and a narrow opening 258 aligned with the sacrificial gate structure 230. The wide opening 256 is shaped to form a wide section of the isolation structure 20 described above. The narrow opening 258 is shaped to form a narrow section of the isolation structure 20. The wide opening 256 and the narrow opening 258 may be arranged in a pattern to achieve isolation on the semiconductor fin 220. The wide opening 256 and the narrow opening 258 may be arranged in any pattern in the semiconductor device 10, 10a-10l. In some embodiments, the wide opening 256 may have a width W1 along the x-direction, and the narrow opening 458 may have a width W2 along the x-direction.

[0066] like Figure 5D As shown, wide openings 256 and narrow openings 258 are positioned along two adjacent sacrificial structures 228. By positioning wide openings 256 adjacent narrow openings 258, a spacing 260 between openings 256, 258 may be maintained at a size to avoid photoresist defects, such as peeling.

[0067] In operation 112, the CPODE pattern is transferred to the mask layer 248, as shown in FIG. Figures 6A-6C shown. Fig. 6A is a schematic perspective view of a semiconductor device 200 . Figure 6B is a cross-sectional view of the semiconductor device 200 along the x-direction. Figure 6C 2 is a schematic cross-sectional view of the semiconductor device 200 along the y direction. In some embodiments, the CPODE pattern may be transferred to the mask layer 248 by a suitable etching process. After operation 112, a portion of the sacrificial gate structure 228 is exposed. Figure 6B As shown, the wide opening 256 in the mask layer 248 may be wider than the sacrificial gate electrode layer 226 along the x-direction, while the narrow opening 258 in the mask layer 248 may expose a portion of the sacrificial gate electrode layer 226 .

[0068] In operation 114, an etching process is performed to selectively remove the sacrificial gate electrode layer 226, such as Figures 7A-7CIn some embodiments, when the sacrificial gate electrode layer 226 is polysilicon, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution may be used to selectively remove the sacrificial gate electrode layer 226 without removing the dielectric material of the ILD layer 242, the CESL 244, and the sidewall spacer 230. Figure 7B As shown, under the wide openings 256 in the mask layer 248, the sacrificial gate electrode layer 226 can be substantially removed, thereby exposing the gate spacers 230. Under the narrow openings 258 in the mask layer 248, the sacrificial gate electrode layer 226 can be partially removed without exposing the gate spacers 230.

[0069] In operation 116, an etching process is performed to remove the sacrificial gate dielectric layer 224, such as Figures 8A-8C As shown. The sacrificial gate dielectric layer 224 may be removed by any suitable etching process, such as plasma dry etching and / or wet etching. After operation 116, the semiconductor fins 220 exposed by the openings 256, 258 are exposed. Figure 8B As shown, sacrificial gate dielectric layer 224 can be substantially removed beneath wide openings 256 in mask layer 248. Sacrificial gate dielectric layer 224 can be partially removed beneath narrow openings 258 in mask layer 248, and a portion of sacrificial gate dielectric layer 224 remains on semiconductor fin 220.

[0070] In operation 118, an etching process is performed to remove the semiconductor fins 220 and to enter the semiconductor substrate 210 and form isolation openings 262, 264, as shown in FIG. Figures 9A-9C The etching process may include one or more plasma etching operations configured to selectively remove semiconductor material to form a self-aligned CPODE opening in the semiconductor substrate 210. In some embodiments, the self-aligned etching process may be performed by one or more plasma etching operations.

[0071] In some embodiments, the etching process can be achieved by plasma etching based on HBr. In some embodiments, O2 or CO2 can be added to HBr. In some embodiments, a polymer protective layer can be deposited on top of the hard mask layer 248 at the beginning of the etching process to increase the etching selectivity of the semiconductor material (e.g., silicon) relative to the material (e.g., SiN) in the hard mask layer 248. In addition, a passivation layer can be formed during the etching process to facilitate a self-aligned etching process. In some embodiments, the passivation layer can be based on silicon oxide. In some embodiments, a precursor containing SiCl4, O2, and HBr can be used to form a passivation process. In some embodiments, a breakthrough operation can be performed to remove excess passivation layer. In some embodiments, the breakthrough operation can be an etching process based on a fluorine-containing etchant (e.g., CF4, CHF3, CH2F2, CHF3, C4F6, or a combination thereof).

[0072] In some embodiments, the plasma etching process may be a high-density plasma process. The etching process may be performed using a processing chamber with an ICP (inductively coupled plasma) or a resonant antenna plasma source. The plasma may be driven by an RF power generator using an AC current operating at a multiple frequency of 13.56 MHz and 27 MHz. The processing chamber may operate at a pressure in the range of about 1 mTorr to about 200 mTorr. The etching process may be performed at a temperature range between about 10 degrees Celsius and about 200 degrees Celsius. The RF power generator may operate at a power level between about 0 W and about 2500 W. In some embodiments, an RF bias power may be applied to a substrate pedestal in the processing chamber. The RF bias power may be in the range of about 0 W to about 2000 W. In some etching operations, the etching plasma may be pulsed with a duty cycle in the range of about 5% to 95%. In some embodiments, the plasma operation may be performed using only the bias power (i.e., using zero plasma power) to enhance etching directionality.

[0073] After operation 118, isolation openings 262, 264 are formed through wide opening 256 and narrow opening 258 in mask layer 248, respectively. Fig. 9B , Fig. 9C and Fig.9D As shown, isolation opening 262 extends deeper into semiconductor substrate 210 than isolation opening 264, which is caused by the difference in width between openings 256 and 258. Opening 262 may have a depth D1 below isolation layer 222 along the z-direction. Opening 264 may have a depth D2 below isolation layer 222 along the z-direction. Depth D1 is greater than depth D2.

[0074] The opening 262 may have a width W3 along the x-direction below the top of the semiconductor fin 220. The width W3 is substantially similar to the width W1. The opening 262 may have a width W4 along the x-direction below the top of the semiconductor fin 220 and a width W5 above the top of the semiconductor fin 220. The width W3 is greater than the width W4. In some embodiments, the width W5 is greater than W4 because the sacrificial gate electrode layer 224 over the top of the semiconductor fin 220 may be removed during operation 118.

[0075] In some embodiments, when the mask opening includes a wide section and a narrow section, the depth of the CPODE opening into the semiconductor substrate may vary, such as Fig.9E and Fig.9F shown. Fig.9E is a schematic top view of a CPODE pattern having a combined opening with two wide sections 256w connected by a narrow section 256n. Fig.9F is a schematic cross-sectional view of the fin structure 220 below the combined openings 262n and 262w. The opening 262n below the narrow section 256n is shallower than the opening 262w below the wide section 256w.

[0076] In operation 120, openings 262 and 264 are filled with an isolation material to form isolation structures 266, 268, such as Figures 10A-10D and Figures 11A-11D As shown. In some embodiments, a filling material is deposited in the openings 262, 264 to replace the removed sections of the semiconductor substrate 210, the semiconductor fins 220, and the sacrificial gate structure 230. The filling material may be an insulating material. In some examples, the filling material may be a single insulating material, and in other examples, the filling material may include a variety of different insulating materials, such as in a multilayer configuration. The filling material may include or may be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, or the like, or a combination thereof, and may be deposited by CVD, PVD, ALD, or another deposition technique. In some embodiments, a liner layer 265 may be formed before depositing the filling material. After depositing the liner layer 265 and the filling material, a CMP process may be performed to expose the sacrificial gate structure 228 for subsequent processes.

[0077] The isolation structure 266 extends sufficiently deep into the semiconductor substrate 210 and provides electrical isolation between the source / drain regions 240 at opposite sides.

[0078] In operation 122, as Figures 12A-12DThe replacement gate process is performed as shown. First, the sacrificial gate structure 228 is removed. Specifically, the sacrificial gate electrode layer 226 and the sacrificial gate dielectric layer 224 are sequentially removed to expose the semiconductor fin 220. Then a replacement gate structure 274 is formed around the semiconductor fin 220. The gate dielectric layer 270 is formed on the semiconductor fin 220, and the gate electrode layer 272 is formed on the gate dielectric layer 270. The gate dielectric layer 270 and the gate electrode layer 272 can be referred to as a replacement gate structure 274.

[0079] The gate dielectric layer 270 may be formed by CVD, ALD, or any suitable method. In one embodiment, the gate dielectric layer 246 is formed using a highly conformal deposition process such as ALD to ensure the formation of the gate dielectric layer 270. The gate dielectric layer 270 includes one or more layers of dielectric materials, such as silicon oxide, silicon nitride, or high-k dielectric materials, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloys, other suitable high-k dielectric materials, and / or combinations thereof.

[0080] The gate electrode layer 272 is formed on the gate dielectric layer 270. The gate electrode layer 272 includes one or more layers of conductive materials, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials and / or combinations thereof. The gate electrode layer 272 can be formed by CVD, ALD, electroplating or other suitable methods.

[0081] Fig.12E is a schematic cross-sectional view of an example device according to the present disclosure. Fig.12E In the device, there are two isolation structures 266 and 268. Isolation structure 266 is formed by a wider mask opening, and isolation structure 268 is formed by a narrow mask opening. Isolation structure 268 has an average mask opening width a of about 28.1 nm, an average fin top width b of about 18.7 nm, an average bending width (maximum width) c of about 28.7 nm, an average bending depth d of about 75.3 nm, and an average depth e of about 147.3 nm. Isolation structure 266 has an average mask opening width a' of about 31.5 nm, an average fin top width b' of about 18.4 nm, an average bending width (maximum width) c' of about 31.5 nm, an average bending depth d' of about 75.3 nm, and an average depth e' of about 169.1 nm.

[0082] The semiconductor device 200 is a FinFET device. The method 100 can also be used to manufacture a GAA device. Figures 13A-13B and Figures 14A-14C A GAA device 300 manufactured using the method 100 is schematically illustrated.

[0083] Figures 13A-13B The GAA device 300 is schematically shown after operation 108. Fig.13A and Fig. 13B As shown, the GAA device 300 includes a plurality of semiconductor fins 320 formed on a semiconductor substrate 310. Each semiconductor fin 320 includes a well portion 312 formed by the semiconductor substrate 310 and a semiconductor stack including alternating stacked sacrificial semiconductor layers 314 and semiconductor channel layers 316. A sacrificial gate structure 328 is formed on the semiconductor fin 320. The sacrificial gate structure 328 includes a sacrificial gate dielectric layer 324 and a sacrificial gate electrode layer 326. Sidewall spacers 330 are formed on the sidewalls of the sacrificial gate structure 328. Internal spacers 332 are formed on the ends of the sacrificial semiconductor layers 314. Epitaxial source / drain regions 340 are formed between the semiconductor channel layers 316. CESL 342 is formed on the epitaxial source / drain regions 340, and an ILD layer 346 is formed on the CESL 342. A mask layer 348 is deposited on the sacrificial gate structure 328 and the ILD layer 346. The mask layer 348 is used to form a CPODE pattern.

[0084] Figures 14A-14C The GAA device 300 is schematically shown after operation 122. Figures 14A-14C As shown, deep isolation structures 366 and shallow isolation structures 368 are formed in sections of sacrificial gate structure 328 and into semiconductor substrate 310. A replacement gate structure 374 (including a gate dielectric layer 370 and a gate electrode layer 372) is formed around semiconductor channel layer 316. Deep isolation structures 366 formed by wide openings through mask layer 348 provide electrical isolation between source / drain regions 340. Shallow isolation structures 368 provide pattern balancing and prevent pattern loading during manufacturing.

[0085] The embodiments of the present disclosure may also be used to form an isolation structure in a CMODE process. Fig.15 4 is a flow chart of a method 400 for manufacturing a semiconductor substrate according to an embodiment of the present disclosure. The method 400 involves forming an isolation structure using a CMODE process. The method 400 is similar to the method 100, except that a replacement gate process is performed before the CMODE process.

[0086] Figures 16A-16C , Figures 17A-17C , Figures 18A-18C , Figures 19A-19C , Figures 20A-20F, Figures 21A-21C and Figures 22A-22C Various stages of manufacturing a semiconductor device 500 according to an embodiment of the present disclosure are schematically illustrated.

[0087] Figures 16A-16C The semiconductor device 500 is schematically shown after operation 108 of the method 400. Figures 16A-16C As shown, the semiconductor device 500 includes a plurality of semiconductor fins 220 formed on a semiconductor substrate 210. A gate structure 274 is formed on the semiconductor fins 220. The gate structure 274 includes a gate dielectric layer 270 and a gate electrode layer 272. Sidewall spacers 230 are formed on sidewalls of the gate structure 274. Epitaxial source / drain regions 240 are formed between segments of the semiconductor fins 220. A CESL 242 is formed on the epitaxial source / drain regions 240, and an ILD layer 246 is formed on the CESL 242. A cap layer 280 may be disposed on the ILD layer 246. In some embodiments, a self-aligned contact (SAC) layer 276 is disposed on the gate structure 274.

[0088] A mask layer 348 is deposited on the SAC layer 280. The mask layer 248 is used to form a CMODE pattern. In some embodiments, a dielectric fin 221 may be formed between the semiconductor fins 220. In some embodiments, a cut gate opening may be formed above the dielectric fin 221, and the mask layer 248 may be filled in the cut gate opening and contact the dielectric fin 221.

[0089] In operation 110, a photolithography process is performed and the photoresist layer 254 is patterned using a CMODE pattern, such as Figures 17A-17C In some embodiments, the CMODE pattern can be similar to any of the patterns discussed in semiconductor devices 10 and 10 a - 10 l. In some embodiments, the CMODE pattern can include a wide opening 256 and a narrow opening 258 aligned over a gate structure 274 .

[0090] In operation 112, openings 256 and 258 are transferred to mask layer 248, such as Figures 18A-18C In some embodiments, the SAC layer 276 may be removed during the pattern transfer process.

[0091] In operation 414, the gate electrode layer 272 is removed by a suitable etching process to expose the gate dielectric layer 270. In operation 416, the gate dielectric layer 270 is removed by a suitable etching process to expose the semiconductor fin 210 below. Figures 19A-19C shown.

[0092] In operation 118, one or more etching processes may be performed to remove the exposed semiconductor fins 220 and semiconductor substrate 210 and form isolation openings 262 and 264. Figures 20A-20C As shown, deeper isolation openings 262 may be formed through wide openings 256 , and shallower isolation openings 264 may be formed through narrow openings 258 .

[0093] In addition, if Fig.20D As shown, the shallower isolation opening 264 may be formed by a narrow section in a mask opening having a wide section and a narrow section.

[0094] like Fig.20E As shown, the dielectric fin 221 can be implanted into the isolation layer 222 according to the circuit design. Fig.20F As shown, a cut metal gate fill 249 may be formed over the dielectric fin 221. The cut metal gate fill 249 may be formed during the deposition of the mask layer 248.

[0095] In operation 120, openings 262 and 264 are filled with an isolation material to form isolation structures 266, 268, such as Figures 21A-21C The CMP process may be performed to perform further processes such as Figures 22A-22C shown.

[0096] The semiconductor device 500 is a FinFET device. The method 400 can also be used to manufacture a GAA device. Figures 23A-23B , Figures 24A-24B , Figures 25A-25B and Figures 26A-26B Various stages of manufacturing a semiconductor device according to an embodiment of the present disclosure are schematically illustrated.

[0097] Figures 23A-23B The GAA device 600 after operation 108 is schematically illustrated. The GAA device 600 includes a plurality of semiconductor fins 320 formed over a semiconductor substrate 310. Each semiconductor fin 320 includes a well portion 312 formed by the semiconductor substrate 310 and two or more semiconductor channel layers 316. A gate structure 374 is formed around the two or more semiconductor channel layers 316. The gate structure 374 includes a gate dielectric layer 370 and a gate electrode layer 372. Sidewall spacers 330 are formed on sidewalls of the gate structure 374. Epitaxial source / drain regions 340 are formed between the semiconductor channel layers 316. Internal spacers 332 are formed between the epitaxial source / drain regions 340 and the gate structure 374. A CESL 342 is formed over the epitaxial source / drain regions 340, and an ILD layer 346 is formed over the CESL 342. A mask layer 348 is deposited on the sacrificial gate structure 328 and the ILD layer 346. The mask layer 348 is used to form a CMODE pattern.

[0098] Figures 24A-24B The GAA device 600 is schematically shown after operation 112. A photolithography process is performed and then the photoresist layer is transferred to the mask layer 348. In some embodiments, the CMODE pattern can be similar to any of the patterns discussed in the semiconductor devices 10 and 10a-10l. In some embodiments, the CMODE pattern can include a wide opening 356 and a narrow opening 358 aligned over the gate structure 374.

[0099] Figures 25A-25B The GAA device 600 is schematically shown after operation 118. A plurality of etching processes may be performed to remove the gate electrode layer 372, the gate dielectric layer 370, the semiconductor channel layer 316 and the semiconductor substrate 310 and to form the isolation openings 362 and 364. Figures 25A-25B As shown, a deeper isolation opening 362 may be formed through the wide opening 356 , and a shallower isolation opening 364 may be formed through the narrow opening 358 .

[0100] Figures 26A-26B The GAA device 600 after operation 122 is schematically shown. Deep isolation structures 366 and shallow isolation structures 368 are formed in sections of the gate structure 374 and into the semiconductor substrate 310. The deep isolation structures 366 formed by the wide opening through the mask layer 348 provide electrical isolation between the source / drain regions 340. The shallow isolation structures 368 provide pattern balance and prevent pattern loading during manufacturing. In some embodiments, the gate structure 374 and the semiconductor channel layer 316 can contact the shallow isolation structures 368 in the yz plane.

[0101] Various embodiments or examples described herein provide several advantages over the prior art. Methods according to the present disclosure enable scaling of gate pitch in CPODE or CMODE processes without photoresist defects or performance loss.

[0102] It should be understood that not all advantages are necessarily discussed herein, that all embodiments or examples do not require a particular advantage, and that other embodiments or examples may provide different advantages.

[0103] Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes: a semiconductor substrate; a fin structure located on the semiconductor substrate and extending along a first direction; a plurality of gate structures crossing the fin structure along a second direction; a plurality of source / drain regions located above the fin structure and between the plurality of gate structures; a first isolation structure formed in a first gate structure among the plurality of gate structures, wherein the first isolation structure has a first width along the first direction; and a second isolation structure formed in a second gate structure among the plurality of gate structures, wherein the second isolation structure has a second width along the first direction, the first gate structure is positioned adjacent to the second gate structure, and the first width is greater than the second width.

[0104] Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes: a semiconductor substrate; a plurality of fin structures located on the semiconductor substrate and extending along a first direction; a gate structure arranged across the plurality of fin structures and extending along a second direction; and an isolation structure arranged in the gate structure, wherein the isolation structure includes: a first section having a first width; and a second section having a second width, wherein the first width is greater than the second width.

[0105] Some embodiments provide a method for forming a semiconductor device. The method includes: forming a plurality of fin structures on a substrate along a first direction; forming a plurality of gate structures across the plurality of fin structures; depositing a mask layer on the plurality of gate structures; forming a pattern in the mask layer, wherein the pattern includes: a first opening aligned with a first gate structure among the plurality of gate structures; and a second opening aligned with a second gate structure among the plurality of gate structures, wherein the first gate structure and the second gate structure are adjacent to each other, the first opening has a first width along the first direction, the second opening has a second width along the first direction, and the first width is greater than the second width; forming a first isolation opening and a second isolation opening using the pattern in the mask layer; and depositing a dielectric layer to fill the first isolation opening and the second isolation opening.

[0106] The features of several embodiments have been summarized above so that those skilled in the art can better understand the detailed description that follows. Those skilled in the art should understand that they can easily use this disclosure as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also be aware that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that they can make various modifications, substitutions, and changes to this document without departing from the spirit and scope of the present disclosure.

[0107] Example 1 is a semiconductor device, comprising: a semiconductor substrate; a fin structure located on the semiconductor substrate and extending along a first direction; a plurality of gate structures crossing the fin structure along a second direction; a plurality of source / drain regions located above the fin structure and between the plurality of gate structures; a first isolation structure formed in a first gate structure among the plurality of gate structures, wherein the first isolation structure has a first width along the first direction; and a second isolation structure formed in a second gate structure among the plurality of gate structures, wherein the second isolation structure has a second width along the first direction, the first gate structure is positioned adjacent to the second gate structure, and the first width is greater than the second width.

[0108] Example 2 is the semiconductor device described in Example 1, wherein the plurality of gate structures are uniformly distributed along the first direction with a gate pitch.

[0109] Example 3 is the semiconductor device of Example 2, wherein the first width is greater than 0.5 times the gate pitch.

[0110] Example 4 is the semiconductor device of Example 3, wherein the first isolation structure is a first distance from the second isolation structure along the first direction, and the first distance is greater than 0.5 times the gate pitch.

[0111] Example 5 is a semiconductor device as described in Example 1, wherein the first isolation structure cuts through the fin structure and extends to a first depth in the semiconductor substrate, the second isolation structure cuts through the fin structure and extends to a second depth in the semiconductor substrate, and the first depth is greater than the second depth.

[0112] Example 6 is the semiconductor device of Example 1, wherein the fin structure includes a single channel.

[0113] Example 7 is the semiconductor device of Example 1, wherein the fin structure includes two or more channels.

[0114] Example 8 is the semiconductor device described in Example 1, further comprising: a third isolation structure, disposed in a third gate structure among the multiple gate structures, wherein the third gate structure is disposed adjacent to the first gate structure, and the third isolation structure has a third width that is smaller than the first width.

[0115] Example 9 is the semiconductor device described in Example 1, further comprising: a third isolation structure, disposed in a third gate structure among the multiple gate structures, wherein the third gate structure is disposed adjacent to the second gate structure, and the third isolation structure has a third width greater than the second width.

[0116] Example 10 is a semiconductor device comprising: a semiconductor substrate; a plurality of fin structures located on the semiconductor substrate and extending along a first direction; a gate structure arranged across the plurality of fin structures and extending along a second direction; and an isolation structure arranged in the gate structure, wherein the isolation structure comprises: a first segment having a first width; and a second segment having a second width, wherein the first width is greater than the second width.

[0117] Example 11 is the semiconductor device of Example 10, wherein the first section cuts into a first fin structure of the plurality of fin structures, and the second section cuts into a second fin structure of the plurality of fin structures.

[0118] Example 12 is the semiconductor device of Example 11, wherein the first segment is connected to the second segment.

[0119] Example 13 is the semiconductor device of Example 12, wherein the first segment extends to a first depth in the semiconductor substrate, the second segment extends to a second depth in the semiconductor substrate, and the first depth is greater than the second depth.

[0120] Example 14 is the semiconductor device described in Example 11, further including: a second gate structure, arranged adjacent to the gate structure; a second isolation structure, arranged in the second gate structure, wherein the second isolation structure cuts into the second fin structure, the second isolation structure has a third width, and the third width is greater than the second width.

[0121] Example 15 is a semiconductor device described in Example 14, wherein the first isolation structure further includes: a third segment, a third fin structure cut into the multiple fin structures, wherein the third segment and the first segment are connected to both ends of the second segment, the third segment has a fourth width, and the fourth width is greater than the second width.

[0122] Example 16 is a method for forming a semiconductor device, comprising: forming a plurality of fin structures on a substrate along a first direction; forming a plurality of gate structures across the plurality of fin structures; depositing a mask layer over the plurality of gate structures; forming a pattern in the mask layer, wherein the pattern comprises: a first opening aligned with a first gate structure among the plurality of gate structures; and a second opening aligned with a second gate structure among the plurality of gate structures, wherein the first gate structure and the second gate structure are adjacent to each other, the first opening having a first width along the first direction, the second opening having a second width along the first direction, and the first width being greater than the second width; forming a first isolation opening and a second isolation opening using the pattern in the mask layer; and depositing a dielectric layer to fill the first isolation opening and the second isolation opening.

[0123] Example 17 is the method described in Example 16, wherein forming the first isolation opening and the second isolation opening includes: etching the first gate structure and the second gate structure to expose the fin structure; etching through the fin structure and into the substrate, wherein the first isolation opening extends to a first depth in the substrate, the second isolation opening extends to a second depth in the substrate, and the first depth is greater than the second depth.

[0124] Example 18 is the method of Example 17, wherein forming the plurality of gate structures includes forming a plurality of sacrificial gate structures, and the method further includes: performing a replacement process after depositing the dielectric layer.

[0125] Example 19 is the method described in Example 16, wherein the pattern further includes: a third opening, aligned with a third gate structure among the multiple gate structures, wherein the first gate structure and the third gate structure are adjacent to each other, and the third opening has a third width along the first direction, and the first width is greater than the third width.

[0126] Example 20 is the method described in Example 16, wherein the second opening includes: a first segment; a second segment connected to the first segment; and a third segment connected to the second segment, wherein the first segment and the third segment are wider than the second segment.

Claims

1. A semiconductor device, comprising: Semiconductor substrate; A fin structure, located on the semiconductor substrate and extending along a first direction; A plurality of gate structures straddling the fin structure along a second direction; a plurality of source / drain regions located above the fin structure and between the plurality of gate structures; a first isolation structure formed in a first gate structure among the plurality of gate structures, wherein the first isolation structure has a first width along the first direction; and A second isolation structure is formed in a second gate structure among the plurality of gate structures, wherein the second isolation structure has a second width along the first direction, the first gate structure is positioned adjacent to the second gate structure, and the first width is greater than the second width.

2. The semiconductor device according to claim 1, wherein The plurality of gate structures are uniformly distributed along the first direction with a gate pitch.

3. The semiconductor device according to claim 2, wherein: The first width is greater than 0.5 times the gate pitch.

4. The semiconductor device according to claim 3, wherein: The first isolation structure is a first distance away from the second isolation structure along the first direction, and the first distance is greater than 0.5 times the gate pitch.

5. The semiconductor device according to claim 1, wherein The first isolation structure cuts through the fin structure and extends to a first depth in the semiconductor substrate, and the second isolation structure cuts through the fin structure and extends to a second depth in the semiconductor substrate, wherein the first depth is greater than the second depth.

6. The semiconductor device according to claim 1, wherein The fin structure includes a single channel.

7. The semiconductor device according to claim 1, wherein The fin structure includes two or more channels.

8. The semiconductor device according to claim 1, further comprising: A third isolation structure is disposed in a third gate structure among the plurality of gate structures, wherein the third gate structure is disposed adjacent to the first gate structure and has a third width that is smaller than the first width.

9. A semiconductor device comprising: Semiconductor substrate; A plurality of fin structures are located on the semiconductor substrate and extend along a first direction; a gate structure, disposed across the plurality of fin structures and extending along a second direction; as well as An isolation structure is provided in the gate structure, wherein the isolation structure comprises: a first segment having a first width; and The second section has a second width, wherein the first width is greater than the second width.

10. A method of forming a semiconductor device, comprising: forming a plurality of fin structures on the substrate along a first direction; forming a plurality of gate structures across the plurality of fin structures; depositing a mask layer over the plurality of gate structures; A pattern is formed in the mask layer, wherein the pattern comprises: a first opening aligned with a first gate structure of the plurality of gate structures; and a second opening aligned with a second gate structure among the plurality of gate structures, wherein the first gate structure and the second gate structure are adjacent to each other, the first opening has a first width along the first direction, the second opening has a second width along the first direction, and the first width is greater than the second width; forming a first isolation opening and a second isolation opening using the pattern in the mask layer; and A dielectric layer is deposited to fill the first isolation opening and the second isolation opening.

Images