Semiconductor device with dielectric fin structure

Abstract

The invention discloses a semiconductor device with a dielectric fin structure. The semiconductor device includes a channel structure on a substrate and a dielectric fin structure on the substrate and adjacent to the channel structure. The channel structure extends in a first direction. The dielectric fin structure includes a hard dielectric material and extends in a second direction parallel to the first direction. The semiconductor device also includes an isolation structure extending through the channel structure. The isolation structure is in contact with the dielectric fin structure.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor devices, and more particularly to a semiconductor device having a dielectric fin structure. Background Art

[0002] As semiconductor technology advances, there is an increasing demand for higher storage capacity, faster processing systems, higher performance, and lower costs. To meet these demands, the semiconductor industry continues to shrink the size of semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs), including planar MOSFETs and fin field effect transistors (finFETs). This scaling down increases the complexity of semiconductor manufacturing processes and increases the difficulty of process control in semiconductor devices. Summary of the invention

[0003] In one aspect, a semiconductor structure is provided according to an embodiment of the present application, comprising: a channel structure on a substrate, wherein the channel structure extends along a first direction; a dielectric fin structure on the substrate and adjacent to the channel structure, wherein the dielectric fin structure comprises a hard dielectric material and extends along a second direction parallel to the first direction; and an isolation structure extending through the channel structure, wherein the isolation structure is in contact with the dielectric fin structure.

[0004] In some implementations, the dielectric fin structure is on a top surface of the isolation layer, and the hard dielectric material has a Young's modulus greater than 75 GPa.

[0005] In some implementations, the semiconductor structure further includes: a gate structure surrounding the channel structure, wherein the gate structure is between the channel structure and the dielectric fin structure.

[0006] In some implementations, a top surface of the dielectric fin structure is below a top surface of the gate structure.

[0007] In some implementations, a ratio of a height of the dielectric fin structure to a height of the gate structure is in a range from 0.15 to 0.3.

[0008] In some implementations, a top surface of the dielectric fin structure is below a top surface of the isolation structure.

[0009] In some implementations, a bottom surface of the dielectric fin structure is at the same level or higher than a top surface of the channel structure.

[0010] In some implementations, the isolation structure extends into the substrate, and the dielectric fin structure is surrounded by the isolation structure.

[0011] In some implementations, the isolation structure includes a liner in contact with the dielectric fin structure and a dielectric filler on the liner.

[0012] In one aspect, a semiconductor device is provided according to an embodiment of the present application, comprising: a plurality of channel structures on a substrate; a plurality of dielectric fin structures on the substrate, the dielectric fin structures comprising a hard dielectric material, wherein the plurality of channel structures and the plurality of dielectric fin structures are arranged in an alternating configuration; a gate structure surrounding the plurality of channel structures and the plurality of dielectric fin structures; and an isolation structure extending through the gate structure and at least one of the plurality of channel structures, wherein the isolation structure contacts at least one of the plurality of dielectric fin structures.

[0013] In some implementations, the plurality of dielectric fin structures are located on a top surface of the isolation layer, and the hard dielectric material has a Young's modulus greater than 75 GPa.

[0014] In some implementations, a top surface of the plurality of dielectric fin structures is below a top surface of the gate structure.

[0015] In some implementations, top surfaces of the gate structure and the isolation structure are coplanar.

[0016] In some implementations, bottom surfaces of the plurality of dielectric fin structures are at the same level or higher than top surfaces of the plurality of channel structures.

[0017] In some implementations, the isolation structure extends through the plurality of trench structures into the substrate.

[0018] In one aspect, a method is provided according to an embodiment of the present application, comprising: forming a channel structure on a substrate, wherein the channel structure extends along a first direction; forming a dielectric fin structure adjacent to the channel structure on the substrate, wherein the dielectric fin structure comprises a hard dielectric material and extends along a second direction parallel to the first direction; and forming an isolation structure extending through the channel structure, wherein the isolation structure contacts the dielectric fin structure.

[0019] In some implementations, the method further includes forming a gate structure surrounding the channel structure, wherein the gate structure is between the channel structure and the dielectric fin structure.

[0020] In some implementations, forming a dielectric fin structure includes: forming an isolation layer on a channel structure and an adjacent channel structure; etching the isolation layer to form an opening between the channel structure and the adjacent channel structure, wherein a bottom surface of the opening is at the same level as or higher than a top surface of the channel structure; and filling the opening with a hard dielectric material, wherein the hard dielectric material has a Young's modulus greater than 75 GPa.

[0021] In some implementations, forming the isolation structure includes: forming a sacrificial gate structure on the channel structure and the dielectric fin structure; etching through the sacrificial gate structure and the channel structure to form an opening; depositing a dielectric material in the opening, wherein the dielectric material contacts the dielectric fin structure; and replacing the sacrificial gate structure with a metal gate structure.

[0022] In some implementations, forming the isolation structure includes: forming a metal gate structure on the channel structure and the dielectric fin structure; etching through the metal gate structure and the channel structure to form an opening; and depositing a dielectric material in the opening, wherein the dielectric material contacts the dielectric fin structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures.

[0024] Figure 1 A top view of a semiconductor device having a dielectric fin structure according to some embodiments is shown.

[0025] Figure 2 An isometric view of a semiconductor device having a dielectric fin structure is shown in accordance with some embodiments.

[0026] Figures 3 to 5 A cross-sectional view of a semiconductor device having a dielectric fin structure in accordance with some embodiments is shown.

[0027] Figure 6 is a flow chart of a method for fabricating a semiconductor device having a dielectric fin structure according to some embodiments.

[0028] Figures 7 to 68 Top view, isometric view, and cross-sectional views of a semiconductor device having a dielectric fin structure at various stages of its fabrication are shown in accordance with some embodiments.

[0029] Fig.69 is a flow chart of another method for fabricating a semiconductor device having a dielectric fin structure according to some embodiments.

[0030] Figures 70 to 85 Cross-sectional views of a semiconductor device having a dielectric fin structure at various stages of its fabrication by another method are shown in accordance with some embodiments.

[0031] Illustrative embodiments will now be described with reference to the drawings.In the drawings, like reference numbers generally indicate identical, functionally similar, and / or structurally similar elements. DETAILED DESCRIPTION

[0032] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first feature on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. As used herein, forming a first feature on a second feature means that the first feature and the second feature are formed in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. The repetition itself does not indicate the relationship between the various embodiments and / or configurations discussed.

[0033] Additionally, spatially relative terms (e.g., "below," "below," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature shown in the figures relative to another element(s) or feature(s). These spatially relative terms are also intended to encompass different orientations of the device in use or operation other than the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be similarly interpreted accordingly.

[0034] It should be noted that references in the specification to "one embodiment," "an embodiment," "an example embodiment," "exemplary," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but not every embodiment may include the particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. In addition, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, whether or not explicitly described, it is within the knowledge of those skilled in the art to implement such feature, structure, or characteristic in conjunction with other embodiments.

[0035] It should be understood that the phraseology or terminology herein is for the purpose of description rather than limitation, so that the phraseology or terminology of the specification is interpreted by persons skilled in the relevant art(s) based on the teachings herein.

[0036] In some embodiments, the terms "about" and "substantially" may indicate that the value of a given amount varies within 20% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%, ±10%, ±20% of the value). These values ​​are examples only and are not intended to be limiting. The terms "about" and "substantially" may refer to a percentage of a value as interpreted by one or more persons skilled in the relevant art(s) in accordance with the teachings herein.

[0037] As the demand for lower power consumption, higher performance and smaller semiconductor devices increases, the size of semiconductor devices is continuously scaled down. The continuous scaling down of device size and the growing demand for device performance may require various process and material improvements, which may have multiple challenges. For example, continuous polysilicon on diffusion edge (CPODE) or continuous metal on diffusion edge (CMODE) processes can be used to pattern nanostructure transistors with trench isolation structures. The trench isolation structure can reduce the leakage current through the source / drain (S / D) epitaxial structure, the transistor channel and the substrate. Nanostructure transistors may include finFETs, gate all-around field effect transistors (GAA FETs), nanosheet transistors, nanowire transistors, multi-bridge channel transistors, nanoribbon transistors, and other transistors of similar structures. However, CPODE and CMODE processes may generate tensile and / or compressive forces on the surface of the substrate, resulting in deformation of the substrate and causing layout-related effects (LDE) of nanostructure transistors on the substrate. The iso-dense depth loading effect of LDE may increase the leakage current of nanostructure transistors. The iso-dense critical dimension loading effect of LDE may cause damage to the S / D epitaxial structure. Gate deformation from LDE may cause the threshold voltage (V t )drift.

[0038] Various embodiments of the present disclosure provide methods for forming a dielectric fin structure in a semiconductor device (e.g., a nanostructure transistor) and / or other semiconductor device in an integrated circuit (IC). In some embodiments, a channel structure extending in a first direction may be formed on a substrate. A dielectric fin structure adjacent to the channel structure may be formed on the substrate. In some embodiments, the dielectric fin structure may include a hard dielectric material and extend in a second direction parallel to the first direction. In some embodiments, the hard dielectric material may have a Young's modulus greater than that of silicon oxide. In some embodiments, the hard dielectric material may have a Young's modulus greater than about 75 GPa. A gate structure may be formed on the channel structure and the dielectric fin structure. An isolation structure may be formed on the gate structure, and the isolation structure may extend through the gate structure and the channel structure. In some embodiments, the isolation structure may contact the dielectric fin structure. In some embodiments, the isolation structure may be formed by a CPODE or CMODE process. In some embodiments, the dielectric fin structure may reduce deformation of the substrate and minimize the LDE effect of the semiconductor device on the substrate. Therefore, the dielectric fin structure may reduce device leakage current, minimize damage to the S / D epitaxial structure, and reduce the V t drift.

[0039] Figure 1A top view of a semiconductor device 100 having a dielectric fin structure is shown in accordance with some embodiments. Figure 2 A partial isometric view of a semiconductor device 100 having a dielectric fin structure is shown in accordance with some embodiments. Figures 3 to 5 The semiconductor device 100 having a dielectric fin structure according to some embodiments is shown in FIG. Figure 2 A partial cross-sectional view of lines AA, BB and CC shown in FIG.

[0040] In some embodiments, the semiconductor device 100 may include transistors 102A to 102C, such as Figure 2 As shown. In some embodiments, transistors 102A to 102C may include nanostructure transistors. Nanostructure transistors may include finFETs, GAA FETs, nanosheet transistors, nanowire transistors, multi-bridge channel transistors, nanoribbon transistors, and other transistors of similar structures. Nanostructure transistors may provide channels in a stacked nanosheet / nanowire configuration. In some embodiments, transistors 102A to 102C may be n-type field effect transistors (NFETs). In some embodiments, transistors 102A to 102C may be p-type field effect transistors (PFETs). In some embodiments, any of transistors 102A to 102C may be an NFET or a PFET. Although Figure 2 Three transistors are shown, but semiconductor device 100 can have any number of transistors. In addition, semiconductor device 100 can be incorporated into an IC by using other structural components (e.g., conductive vias, wires, dielectric layers, passivation layers, and interconnects, which are not shown for simplicity). Unless otherwise noted, the discussion of transistors 102A to 102C with the same reference numerals applies to each other. In addition, the same reference numerals generally represent the same, functionally similar, and / or structurally similar elements.

[0041] refer to Figures 1 to 5, a semiconductor device 100 having transistors 102A to 102C may be formed on a substrate 104, and the semiconductor device 100 may be isolated by a shallow trench isolation (STI) region 106. Each of the transistors 102A to 102C may include a fin structure 108, nanostructures 122-1, 122-2, and 122-3 (collectively referred to as “nanostructures 122”), a gate dielectric layer 124, a gate structure 112, a gate spacer 114, an inner spacer 121, and an S / D structure 110. In some embodiments, the semiconductor device may further include trench isolation structures 113-1 and 113-2 (collectively referred to as “trench isolation structures 113”), a protective layer 115, an etch stop layer (ESL) 116, an isolation layer 117, an interlayer dielectric (ILD) layer 118, a dielectric fin structure 119, and a gate isolation structure 120.

[0042] refer to Figures 1 to 5 , the substrate 104 may include a semiconductor material, such as silicon. In some embodiments, the substrate 104 includes a crystalline silicon substrate (e.g., a silicon wafer). In some embodiments, the substrate 104 includes (i) an elemental semiconductor, such as germanium; (ii) a compound semiconductor, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; (iii) an alloy semiconductor, including silicon germanium carbide, silicon germanium, gallium arsenic phosphide, and / or aluminum gallium arsenide; or (iv) a combination of the foregoing. In addition, the substrate 104 may be doped, depending on the design requirements (e.g., a p-type substrate or an n-type substrate). In some embodiments, the substrate 104 may be doped with a p-type dopant (e.g., boron, indium, aluminum, or gallium) or an n-type dopant (e.g., phosphorus or arsenic).

[0043] STI regions 106 may provide electrical isolation between transistors 102A- 102C, as well as electrical isolation from adjacent transistors (not shown) on substrate 104 and / or adjacent active and passive components (not shown) integrated with or deposited on substrate 104. Figure 5 As shown, an oxide liner 105 may be provided between the STI region 106 and the substrate 104 to protect the fin structure 108 and the nanostructure 122 during the formation of the STI region 106. In some embodiments, the oxide liner 105 may include silicon oxide or other suitable dielectric materials. The STI region 106 may be made of a dielectric material. In some embodiments, the STI region 106 may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric material, and / or other suitable insulating materials. In some embodiments, the STI region 106 may include a multilayer structure.

[0044] refer to Figures 1 to 5, the nanostructure 122 and the fin structure 108 can be formed on the patterned portion of the substrate 104. The embodiments of the nanostructure and the fin structure disclosed herein can be patterned by any suitable method. For example, one or more photolithography processes (including double patterning processes or multi-patterning processes) can be used to pattern to obtain the nanostructure and the fin structure. The double patterning process or the multi-patterning process can combine the photolithography process and the self-alignment process to form, for example, a pattern with a spacing smaller than the spacing obtainable using a single direct photolithography process. For example, a sacrificial layer is formed on the substrate, and the sacrificial layer is patterned using a photolithography process. A self-alignment process can be used to form spacers along the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the nanostructure and the fin structure.

[0045] like Figures 1 to 5 As shown, the nanostructure 122 and the fin structure 108 may extend along the X-axis. In some embodiments, the nanostructure 122 and the fin structure 108 may be disposed on the substrate 104. The nanostructure 122 may include a stack of nanostructures 122-1, 122-2, and 122-3, which may be in the form of nanosheets, nanowires, or nanoribbons. Each nanostructure 122 may serve as a channel structure and form a channel region below the gate structure 112 of the transistors 102A to 102C. In some embodiments, the nanostructure 122 and the fin structure 108 may include a semiconductor material similar to or different from the substrate 104. In some embodiments, the nanostructure 122 and the fin structure 108 may include silicon. In some embodiments, the nanostructure 122 and the fin structure 108 may include silicon germanium. The semiconductor material of the nanostructure 122 and the fin structure 108 may be undoped or may be in-situ doped during the formation process thereof. In some embodiments, as Figures 2 to 5 As shown, the nanostructure 122 under the gate structure 112 can form a channel region of the semiconductor device 100 and represents a current-carrying channel structure of the semiconductor device 100. In some embodiments, the nanostructure 122 can have a thickness in the range of about 5 nm to about 8 nm along the Z axis. In some embodiments, the nanostructure 122 can have a width in the range of about 15 nm to about 50 nm along the Y axis. In some embodiments, the nanostructure 122 can have a width in the range of about 15 nm to about 25 nm along the X axis. In some embodiments, the spacing between adjacent nanostructures 122 along the Z axis can be in the range of about 8 nm to about 12 nm. Although in Figures 2 to 5 Three layers of nanostructures 122 are shown in FIG. 1 , but transistors 102A to 102C may have any number of nanostructures 122 .

[0046] refer to Figures 2 to 5, the gate dielectric layer 124 may be disposed on the nanostructure 122, the fin structure 108, the STI region 106, the isolation layer 117, and the dielectric fin structure 119. In some embodiments, the gate dielectric layer 124 may be a multilayer structure and may include an interface layer and a high-k dielectric layer. In some embodiments, the gate dielectric layer 124 may not include an interface layer, but may include a high-k dielectric layer in direct contact with the nanostructure 122. In some embodiments, the interface layer may include silicon oxide formed by a deposition process or an oxidation process. In some embodiments, the interface layer may have a thickness ranging from about 0.1 nm to about 1.5 nm. In some embodiments, the high-k dielectric layer may include hafnium oxide, zirconium oxide, or other suitable high-k dielectric materials.

[0047] In some embodiments, Figures 2 to 5 As shown, the gate structure 112 may be disposed on the gate dielectric layer 124. In some embodiments, the gate structure 112 may include one or more work function metal layers and metal fillers. The one or more work function metal layers may include work function metals to tune the threshold voltage V of the transistors 102A to 102C. t In some embodiments, the gate structures 112 of the NFET and PFET devices may have substantially the same work function metal. In some embodiments, the gate structures 112 of the NFET and PFET devices may have different work function metals. Figures 2 to 5 As shown, each nanostructure 122 may be surrounded by a gate structure 112, and thus, the gate structure 112 may be referred to as a "gate all around (GAA) structure", and the transistors 102A to 102C may also be referred to as "GAA FETs 102A to 102C". The one or more work function metal layers may surround the nanostructure 122, and may include work function metal to tune the V t In some embodiments, transistors 102A to 102C may include any number of work function metal layers for V t Tuning (e.g., ultra-low V t , Low V t , and standard V t ). In some embodiments, Figure 5 As shown, the gate structure 112 may have a height 112h along the Z-axis from the top surface of the STI region 106. The height 112h may be in the range of about 80 nm to about 120 nm. Figure 5 As shown, a distance 112d between a top surface of the gate structure 112 and a top surface of the top nanostructure 122 - 3 along the Z-axis may be in a range of about 30 nm to about 40 nm.

[0048] In some embodiments, the NFETs 102A to 102C may include an n-type work function metal layer. The n-type work function metal layer may include aluminum, titanium aluminum, titanium aluminum carbon, tantalum aluminum, tantalum aluminum carbon, tantalum silicon carbide, hafnium carbide, silicon, titanium nitride, titanium silicon nitride, or other suitable work function metals. In some embodiments, the PFETs 102A to 102C may include a p-type work function metal layer. The p-type work function metal layer may include titanium nitride, titanium silicon nitride, tantalum nitride, tungsten carbon nitride, tungsten, molybdenum, or other suitable work function metals. In some embodiments, the work function metal layer may include a single metal layer or a metal layer stack. The metal layer stack may include work function metals having work function values ​​that are equal to or different from each other. In some embodiments, the metal filler may include titanium, tantalum, aluminum, cobalt, tungsten, nickel, ruthenium, or other suitable conductive materials.

[0049] refer to Figure 2 and Figure 3 According to some embodiments, the gate spacer 114 may be disposed on the sidewall of the gate structure 112 and in contact with the gate dielectric layer 124. The internal spacer 121 may be disposed adjacent to the end of the nanostructure 122 and between the S / D structure 110 and the gate structure 112. The gate spacer 114 and the internal spacer 121 may include an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, low-k material, and a combination of the foregoing. In some embodiments, the gate spacer 114 and the internal spacer 121 may include the same insulating material. In some embodiments, the gate spacer 114 and the internal spacer 121 may include different insulating materials. In some embodiments, the gate spacer 114 and the internal spacer 121 may include a single insulating layer or an insulating layer stack. In some embodiments, the gate spacer 114 and the internal spacer 121 may have a low-k dielectric material having a dielectric constant less than about 3.9 (e.g., about 3.5, about 3.0, or about 2.8).

[0050] The S / D structure 110 may be disposed on the fin structure 108 and on the opposite side of the gate structure 112. The S / D structure 110 may be used as an S / D region of the transistors 102A to 102C. In some embodiments, the S / D structure 110 may have any geometric shape, such as a polygon, a cone, a rhombus, an ellipse, and a circle. In some embodiments, the S / D structure 110 may include an epitaxially grown semiconductor material, such as silicon (e.g., the same material as the substrate 104). In some embodiments, the S / D structure 110 may include an epitaxially grown semiconductor material (e.g., silicon germanium) different from the material of the substrate 104, and stress may be applied to the channel region under the gate structure 112. Since the lattice constant of such epitaxially grown semiconductor material is different from the material of the substrate 104, the channel region is stressed to increase the carrier mobility in the channel region of the semiconductor device 100. The epitaxially grown semiconductor material may include: (i) semiconductor materials such as germanium and silicon; (ii) compound semiconductor materials such as gallium arsenide and aluminum gallium arsenide; or (iii) semiconductor alloys such as silicon germanium and gallium arsenide phosphide.

[0051] In some embodiments, the S / D structure 110 may include silicon and may be in-situ doped using n-type dopants (e.g., phosphorus and arsenic) during the epitaxial growth process. For n-type in-situ doping, n-type doping precursors may be used, such as phosphine, arsine, and other n-type doping precursors. In some embodiments, the S / D structure 110 may include silicon, silicon germanium, germanium, or III-V materials (e.g., indium antimonide, gallium antimonide, or indium gallium antimonide), and may be in-situ doped using p-type dopants (e.g., boron, indium, and gallium) during the epitaxial growth process. For p-type in-situ doping, p-type doping precursors may be used, such as diborane (B2H6), boron trifluoride (BF3), and other p-type doping precursors.

[0052] In some embodiments, the S / D structure 110 may include one or more epitaxial layers, wherein each epitaxial layer may have a different composition. In some embodiments, each of the one or more epitaxial layers may include Si and may differ from one another based on, for example, doping concentration and / or epitaxial growth process conditions. In some embodiments, each of the one or more epitaxial layers may include silicon germanium and may differ from one another based on, for example, doping concentration, epitaxial growth process conditions, and / or a relative concentration of germanium relative to silicon.

[0053] refer to Figures 1 to 5, the trench isolation structure 113 may be disposed on the substrate 104 and on the edge between different diffusion regions (e.g., n and p regions). In some embodiments, the trench isolation structure 113 may include a liner 113A and a dielectric filler 113B. In some embodiments, the liner 113A may include silicon nitride, silicon carbonitride, or other suitable dielectric materials. The dielectric filler 113B may include silicon oxide, silicon oxynitride, silicon oxycarbonitride, or other suitable dielectric materials. In some embodiments, the liner 113A may protect the nanostructure 122, the fin structure 108, and the substrate 104 (e.g., to prevent oxidation) during the formation of the dielectric filler 113B. In some embodiments, the trench isolation structure 113 may extend through the gate structure 112, the nanostructure 122, the STI region 106, and the fin structure 108 until it is in the substrate 104. In some embodiments, the trench isolation structure 113 may be formed by a CPODE and / or CMODE process to reduce leakage current flowing through the S / D structure 110, the nanostructure 122, and the substrate 104. In some embodiments, Figures 1 to 5 As shown, the trench isolation structure 113 may include a short trench isolation structure extending over about 1 to about 3 fin structures 108. In some embodiments, the trench isolation structure 113 may include a long trench isolation structure extending over more than about 3 fin structures 108. Figure 3 As shown, the trench isolation structure 113 may have a height 113h from the bottom surface of the trench isolation structure 113 to the top surface of the top nanostructure 122-3 along the Z axis. The height 113h may be in a range from about 120nm to about 250nm. If the height 113h is less than about 120nm, the trench isolation structure 113 may not extend through the STI region 106 and may not reduce leakage current. If the height 113h is greater than about 250nm, the well structure of the transistors 102A to 102C may be damaged and the device performance may be reduced. In addition, the leakage current may not be further reduced, but the manufacturing cost may increase.

[0054] In some embodiments, Figures 2 to 5 As shown, the protection layer 115 can be disposed on the STI region 106 and between the gate dielectric layer 124 and the isolation layer 117. In some embodiments, the protection layer 115 can include silicon carbon nitride or other suitable materials to protect adjacent structures during the formation of the isolation layer 117. In some embodiments, the isolation layer 117 can be disposed on the protection layer 115, and the isolation layer 117 can include silicon oxide or other suitable materials.

[0055] refer to Figures 1 to 5 , the dielectric fin structure 119 may be disposed on the isolation layer 117 and between adjacent nanostructures 122. In some embodiments, as Figure 1 As shown, the dielectric fin structure 119 and the nanostructure 122 may be arranged in an alternating configuration on the substrate 104. In some embodiments, the dielectric fin structure 119 may include a hard dielectric material. In some embodiments, the hard dielectric material may have a Young's modulus greater than that of silicon oxide. In some embodiments, the hard dielectric material may have a Young's modulus greater than about 75 GPa. In some embodiments, the hard dielectric material may include hafnium oxide, zirconium oxide, or other suitable high-k dielectric materials. In some embodiments, the hard dielectric material may include silicon, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbon nitride, aluminum oxide, or other suitable low-k dielectric materials. In some embodiments, the dielectric fin structure 119 may have one or more layers of different hard dielectric materials. In some embodiments, the dielectric fin structure 119 may have a higher etch resistance to be retained after various etching processes. In some embodiments, the bottom surface of the dielectric fin structure 119 may be above the top surface of the top nanostructure 122-3. If the bottom surface of the dielectric fin structure 119 is below the top surface of the top nanostructure 122-3, the parasitic capacitance between adjacent nanostructure transistors may increase. In some embodiments, the dielectric fin structure 119 can reduce the deformation of the substrate 104 and minimize the LDE effect of the semiconductor device 100 on the substrate 104. Figure 3 As shown, the gate structure 112 can be substantially vertical relative to the X-axis and the Y-axis (e.g., the top surface of the nanostructure 122). In some embodiments, the gate structure 112 adjacent to the trench isolation structure 113 can be bent less than about 2 degrees. In some embodiments, with the dielectric fin structure 119, the width difference of the nanostructure 122 along the X-axis between the isolated area and the dense area can be less than about 1.5nm, and the height difference of the trench isolation structure 113 can be less than about 15nm. Therefore, the dielectric fin structure 119 can reduce the leakage current caused by the sparse depth loading effect, minimize the damage to the S / D epitaxial structure caused by the sparse critical dimension loading effect, and reduce the V of the semiconductor device 100 caused by gate deformation. t drift.

[0056] In some embodiments, Figure 4 As shown, the dielectric fin structure 119 may have a width 119w along the Y-axis in a range from about 15 nm to about 20 nm. Figure 4As shown, the dielectric fin structure 119 may have a height 119h in the range from about 20nm to about 30nm along the Z axis. In some embodiments, a first ratio of the height 119h to the distance 112d may be in the range from about 0.6 to about 0.8. A second ratio of the height 119h to the height 112h of the gate structure may be in the range from about 0.15 to about 0.3. If the height 119h is less than about 20nm, the first ratio is less than about 0.6, or the second ratio is less than about 0.15, the dielectric fin structure 119 may not be retained after the CPODE or CMODE process. If the height 119h is greater than about 30nm, the first ratio is greater than about 0.8, or the second ratio is greater than about 0.3, the parasitic capacitance between adjacent nanostructure transistors may increase. In some embodiments, the width 119w, the height 119h, and the first ratio and the second ratio may depend on the hard dielectric material of the dielectric fin structure 119. In some embodiments, the bottom surface of the dielectric fin structure 119 and the top surface of the top nanostructure 122-3 can be substantially at the same level. Figure 4 As shown, the dielectric fin structure 119 may be surrounded by the trench isolation structure 113 .

[0057] refer to Figures 2 to 5 , the ESL 116 may be disposed on sidewalls of the S / D structure 110, the dielectric fin structure 119, and the gate spacer 114. The ESL 116 may be configured to protect the S / D structure 110, the dielectric fin structure 119, and the gate structure 112 during formation of an S / D contact structure on the S / D structure 110. In some embodiments, the ESL 116 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride, silicon boron nitride, silicon carbon boron nitride, or a combination of the foregoing.

[0058] The ILD layer 118 may be disposed on the ESL 116 above the S / D structure 110 and the dielectric fin structure 119. The ILD layer 118 may include a dielectric material deposited using a deposition method suitable for a flowable dielectric material. For example, flowable silicon oxide may be deposited using flowable chemical vapor deposition (FCVD). In some embodiments, the dielectric material may include silicon oxide.

[0059] In some embodiments, Figure 2 and Figure 5As shown, the gate isolation structure 120 can be disposed on the trench isolation structure 113. In some embodiments, the gate isolation structure 120, the dielectric fin structure 119, the isolation layer 117 and the trench isolation structure 113 can electrically isolate the gate structure 112 into two parts. In some embodiments, the gate isolation structure 120 may include silicon nitride, silicon oxide, and / or other suitable dielectric materials. In some embodiments, the gate isolation structure 120 may include a single dielectric layer or a dielectric layer stack. In some embodiments, the gate isolation structure 120, the dielectric fin structure 119 and the isolation layer 117 may extend vertically through the gate structure 112.

[0060] In some embodiments, the semiconductor device 100 may further include an S / D contact structure, a gate contact structure, metal lines, metal vias, interconnects, and additional ILD layers, which are not described in detail for clarity.

[0061] Figure 6 is a flow chart of a method 600 for manufacturing a semiconductor device 100 having a dielectric fin structure according to some embodiments. The method 600 may not be limited to nanostructured transistor devices and may be applied to other devices that benefit from dielectric fin structures. Additional manufacturing operations may be performed between various operations of the method 600 and may be omitted, such omissions being for clarity and ease of description only. Additional processes may be provided before, during, and / or after the method 600; one or more of these additional processes are briefly described herein. Furthermore, not all operations may be required to perform the disclosure provided herein. Additionally, some operations may be performed simultaneously or in parallel. Figure 6 In some embodiments, one or more other operations may be performed in addition to or in place of the operations currently described.

[0062] For the purpose of illustration, reference will be made to Figures 7 to 68 An example manufacturing process for manufacturing the semiconductor device 100 is shown to describe Figure 6 The operation shown. Figure 7 A top view of a semiconductor device 100 having a dielectric fin structure at various stages of its fabrication is shown in accordance with some embodiments. Figures 8 to 68 Partial isometric views and partial cross-sectional views of a semiconductor device 100 having a dielectric fin structure at various stages of its fabrication are shown in accordance with some embodiments. Fig.11 , Fig.14 , Fig.17 , Fig. 20 , Fig.23 , Fig.26 , Fig.29 , Fig.32 , Fig.35 , Fig.37 , Fig.40 , Fig.43 , Fig.46 , Fig.49 and Fig.52 Shown are partial isometric views of a semiconductor device 100 at various stages of its fabrication in accordance with some embodiments. Figure 8 , Fig.12 , Fig.15 , Fig.18 , Fig.21 , Fig.24 , Fig. 27 , Fig.30 , Fig.33 , Fig.36 , Fig.38 , Fig.41 , Fig.44 , Fig.47 , Fig.50 , Fig.53 , Fig.55 , Fig.57 , Fig.59 , Fig.61 , Fig.63 , Fig.65 and Fig.67 FIG. 1 shows a semiconductor device 100 according to some embodiments at various stages of its manufacture along an X-axis (eg, Figure 2 A partial cross-sectional view of the line AA) shown in FIG. Fig. 9 , Fig.10 , Fig.13 , Fig.16 , Fig.19 , Fig. 22 , Fig.25 , Fig.28 , Fig.31 , Fig.34 , Fig.39 , Fig.42 , Fig.45 , Fig.48 , Fig.51 , Fig.54 , Fig.56 , Fig.58 , Fig.60 , Fig.62 , Fig.64 , Fig.66 and Fig.68 FIG. 1 shows a semiconductor device 100 according to some embodiments at various stages of its manufacture along the Y-axis (eg, Figure 2 A partial cross-sectional view of line BB) shown in FIG. Figures 7 to 68 With Figures 1 to 5 Elements with the same reference numerals as those in the description above.

[0063] refer to Figure 6The method 600 begins at operation 610 and forms a channel structure extending along a first direction on a substrate. Figures 7 to 9 As shown, nanostructures 122 and nanostructures 820 along the X-axis can be formed on substrate 104. In some embodiments, nanostructures 122 and nanostructures 820 can be stacked in an alternating configuration. Sacrificial nanostructures 823 can be formed on nanostructures 122-3, and sacrificial nanostructures 823 are protected by hard mask layer 722. In some embodiments, nanostructures 122 and nanostructures 820 and sacrificial nanostructures 823 can be epitaxially grown on substrate 104, and then patterned with hard mask layer 722 to form a stack of nanostructures 122 and nanostructures 820. In some embodiments, nanostructures 122 and nanostructures 820 and sacrificial nanostructures 823 can be in the form of nanosheets, nanowires, or nanobelts. In some embodiments, nanostructures 122 and nanostructures 820 and sacrificial nanostructures 823 can include semiconductor materials similar to or different from substrate 104. In some embodiments, nanostructures 122 and nanostructures 820 and sacrificial nanostructures 823 can include different semiconductor materials. In some embodiments, nanostructure 820 may include a semiconductor material having an etch rate and / or etch selectivity higher than nanostructure 122 but lower than sacrificial nanostructure 823. For example, nanostructure 122 may include silicon, and nanostructure 820 may include silicon germanium having a germanium atomic percentage from about 10% to about 40%. Sacrificial nanostructure 823 may include silicon germanium having a germanium atomic percentage from about 25% to about 60%. In some embodiments, nanostructure 122 and nanostructure 820 may include silicon doped with different dopants to have different etch rates and / or etch selectivities and minimize the loss of nanostructure 122 during the sheet formation process of nanostructure 122.

[0064] The embodiments of the nanostructures 122 and nanostructures 820 and sacrificial nanostructures 823 disclosed herein can be patterned by any suitable method. For example, one or more photolithography processes (including double patterning or multi-patterning processes) can be used to pattern to obtain the nanostructure. The double patterning process or the multi-patterning process can combine the photolithography process with the self-alignment process to form, for example, a pattern with a spacing smaller than the spacing obtainable using a single direct photolithography process. For example, a sacrificial layer is formed on the substrate, and the sacrificial layer is patterned using a photolithography process. A self-alignment process can be used to form spacers along the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the nanostructure.

[0065] After forming the nanostructures 122 and 820 and the sacrificial nanostructures 823, an STI region 106 may be formed between the stacks of adjacent nanostructures 122 and 820. Figures 9 to 16 In some embodiments, Fig. 9 As shown, an oxide liner 105 may be conformally deposited on the substrate 104, the nanostructures 122 and the nanostructures 820, and the sacrificial nanostructures 823 to provide protection during the subsequent formation of the STI region 106. In some embodiments, the oxide liner 105 may include silicon oxide or other suitable dielectric materials. Fig.10 As shown, dielectric material 1006 may be deposited on oxide liner 105 over substrate 104, nanostructures 122 and nanostructures 820, and sacrificial nanostructures 823. In some embodiments, as shown in FIG. Figures 11 to 13 As shown, dielectric material 1006 can be polished by a chemical mechanical polishing (CMP) process to form STI regions 106 between adjacent nanostructures 122 and the stack of nanostructures 820. The CMP process can remove hard mask layer 722 and planarize the top surface of STI regions 106 and sacrificial nanostructures 823. In some embodiments, as shown in FIG. Figures 14 to 16 As shown, STI regions 106 may be recessed, and a top surface of STI regions 106 may be below nanostructures 122 and nanostructures 820 .

[0066] After forming the STI region 106, a cladding layer 1725 may be formed. Figures 17 to 19 As shown, a cladding layer 1725 can be conformally deposited on the STI region 106, the nanostructure 122 and the nanostructure 820, and the sacrificial nanostructure 823. In some embodiments, the cladding layer 1725 can include a semiconductor material having an etch rate and / or etch selectivity similar to that of the nanostructure 820 and lower than that of the sacrificial nanostructure 823. In some embodiments, the cladding layer 1725 can include silicon germanium having a germanium atomic percentage from about 10% to about 40%. In some embodiments, the cladding layer 1725 on the top surface of the STI region 106 and the sacrificial nanostructure 823 can be removed by a directional etching process, such as Figure 20 to Figure 22 After the directional etching process, the capping layer 1725 may remain on the sidewalls of the nanostructures 122 and 820 and the sacrificial nanostructures 823 .

[0067] After forming the cladding layer 1725, the isolation layer 117 may be formed. Figure 23 to Figure 28 As shown, an isolation layer 117 may be formed on the STI region 106 between the stack of nanostructures 122 and nanostructures 820. In some embodiments, as shown in FIG. Figure 23 to Figure 25As shown, a protective layer 115 may be conformally deposited on the top surface of the STI region 106 and the sacrificial nanostructure 823 and the sidewall surface of the cladding layer 1725. In some embodiments, the protective layer 115 may include silicon carbonitride or other suitable dielectric materials to protect the cladding layer 1725 and the sacrificial nanostructure 823 in subsequent processes. In some embodiments, an oxide material 2317 may be deposited on the protective layer 115 to fill the openings between the stacks of the nanostructures 122 and the nanostructures 820. In some embodiments, the oxide material 2317 may include silicon oxide or other suitable oxide materials. In some embodiments, as Figure 26 to Figure 28 As shown, the oxide material 2317 may be planarized by a CMP process and recessed by an etching process to form the isolation layer 117. In some embodiments, the top surface of the isolation layer 117 may be above the top surface of the top nanostructure 122-3 for lower device parasitic capacitance.

[0068] refer to Figure 6 In operation 620, a dielectric fin structure is formed on the substrate adjacent to the channel structure. The dielectric fin structure includes a hard dielectric material and extends along a second direction parallel to the first direction. For example, Figure 29 to Figure 31 As shown, a dielectric fin structure 119 may be formed on the isolation layer 117 above the STI region 106 and between the stacks of adjacent nanostructures 122 and nanostructures 820. In some embodiments, the dielectric fin structure 119 may include a hard dielectric material. In some embodiments, the hard dielectric material may have a Young's modulus greater than that of silicon oxide. In some embodiments, the hard dielectric material may have a Young's modulus greater than about 75 GPa. In some embodiments, the hard dielectric material may include hafnium oxide, zirconium oxide, or other suitable high-k dielectric materials. In some embodiments, the hard dielectric material may include silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon, aluminum oxide, or other suitable low-k dielectric materials. In some embodiments, the dielectric fin structure 119 may have a higher etch resistance to be retained after various etching processes. In some embodiments, the hard dielectric material in the dielectric fin structure 119 may have a lower etch rate than the semiconductor material in the nanostructure 122. Therefore, the dielectric fin structure 119 may be retained after etching by the CPODE and CMODE processes. In some embodiments, the dielectric fin structure 119 may extend along an X-axis parallel to the nanostructure 122. In some embodiments, as shown in FIG. Fig.29As shown, the dielectric fin structure 119 and the nanostructure 122 may be arranged in an alternating configuration on the substrate 104. In some embodiments, the bottom surface of the dielectric fin structure 119 may be higher than the top surface of the top nanostructure 122-3. In some embodiments, the dielectric fin structure 119 may reduce the deformation of the substrate 104 and minimize the LDE effect of the semiconductor device 100 on the substrate 104. Therefore, the dielectric fin structure 119 may reduce the leakage current caused by the sparse depth loading effect, minimize the damage to the S / D epitaxial structure caused by the sparse critical dimension loading effect, and reduce the V of the semiconductor device 100 caused by the gate deformation. t drift.

[0069] refer to Figure 6 In operation 630, a sacrificial gate structure may be formed on the channel structure and the dielectric fin structure. Figure 32 to Figure 42 As shown, a sacrificial gate structure 3712 can be formed on the nanostructure 122 and the dielectric fin structure 119. In some embodiments, forming the sacrificial gate structure 3712 can include removing the sacrificial nanostructure 823, conformally depositing the liner 3524, and depositing the sacrificial gate structure 3712. In some embodiments, the etching process can remove the sacrificial nanostructure 823. Due to the etching selectivity between the dielectric fin structure 119 and the sacrificial nanostructure 823, the etching process may not remove the dielectric fin structure 119. In some embodiments, the liner 3524 can be conformally deposited on the nanostructure 122 and the dielectric fin structure 119. The liner 3524 can include silicon oxide or other suitable dielectric materials. In some embodiments, the sacrificial gate structure 3712 can be deposited on the liner 3524 above the nanostructure 122 and the dielectric fin structure 119. In some embodiments, as Figure 40 to Figure 42 As shown, the sacrificial gate structure 3712 may be patterned with a nitride hard mask layer 4032 and an oxide hard mask layer 4034. A spacer layer 4014 may be conformally deposited over the sacrificial gate structure 3712, the nitride hard mask layer 4032, the oxide hard mask layer 4034, the nanostructures 122, and the dielectric fin structure 119.

[0070] After forming the sacrificial gate structure 3712, the S / D structure 110 may be formed, such as Figures 43 to 51 Forming the S / D structure 110 may include removing a portion of the nanostructure 122 and the nanostructure 820, forming the internal spacer 121, and epitaxially growing the S / D structure 110. In some embodiments, as Figure 43 to Figure 45As shown, the directional etching process can remove a portion of nanostructure 122 and nanostructure 820 to form recess 4510 on each side of sacrificial gate structure 3712. The lateral etching process can remove the ends of nanostructure 820 to form recess 4521 between nanostructures 122. In some embodiments, as shown in FIG. Figure 46 to Figure 48 As shown, internal spacer 121 may be formed in recess 4521. In some embodiments, forming internal spacer 121 may include blanket depositing a spacer layer followed by an etching process to remove the spacer layer on the sidewalls and top surfaces of sacrificial gate structure 3712 and nanostructure 122 and nanostructure 820. Figures 49 to 51 As shown, the S / D structure 110 may be epitaxially grown on the fin structure 108, and the S / D structure 110 is in contact with the nanostructure 122. In some embodiments, the S / D structure 110 may be formed between stacks of adjacent protective layers 115, isolation layers 117, and dielectric fin structures 119. In some embodiments, the S / D structure 110 may be in contact with the protective layer 115. In some embodiments, the S / D structure 110 may be in-situ doped with an n-type or p-type dopant during epitaxial growth.

[0071] like Figure 52 to Figure 56 As shown, after forming the S / D structure 110, an ESL 116 and an ILD layer 118 may be formed on the S / D structure 110, the dielectric fin structure 119, and the gate spacer 114. In some embodiments, the ESL 116 may be conformally deposited on the S / D structure 110, the dielectric fin structure 119, and the gate spacer 114. In some embodiments, the ILD layer 118 may be blanket deposited on the ESL 116. A subsequent CMP process may planarize the top surfaces of the gate spacers 114, the ESL 116, the ILD layer 118, and the sacrificial gate structure 3712. In some embodiments, the ILD layer 118 may be recessed between the sacrificial gate structures 3712. A hard mask layer 5236 may be deposited in the recesses and on the sacrificial gate structure 3712, as shown in FIG. Figure 52 to Figure 56 In some embodiments, the hard mask layer 5236 may include silicon nitride or other suitable dielectric materials. Fig.53 and Fig.54 As shown, the S / D structure 110 may include multiple epitaxial layers having different material compositions and doping concentrations. Fig.55 and Fig.56 As shown, the S / D structure 110 may extend further into the substrate 104 .

[0072] refer to Figure 6In operation 640, an isolation structure is formed that extends through the sacrificial gate structure and the channel structure and contacts the dielectric fin structure. Figures 58 to 68 As shown, a trench isolation structure 113-2 extending through the sacrificial gate structure 3712 and the nanostructure 122 can be formed on the substrate 104. The trench isolation structure 113-2 can contact the dielectric fin structure 119. In some embodiments, a stack of a bottom layer 5738, an intermediate layer 5740, and a photoresist 5742 can be deposited on the hard mask layer 5236. In some embodiments, the photoresist 5742 above the sacrificial gate structure 3712 can be patterned to obtain an opening 5713, such as Fig.57 and Fig.58 After the patterning process, an opening 5713 may be formed in the hard mask layer 5236 by a dry etching process, as shown in FIG. Fig.59 and Fig.60 shown.

[0073] In some embodiments, Fig.61 and 62 As shown, the dry etching process can remove the sacrificial gate structure 3712 and extend the opening 5713 through the sacrificial gate structure 3712. In some embodiments, the etching of the sacrificial gate structure 3712 can be directional and self-aligned. The etchant can include a hydrogen bromide-based plasma with an additive of oxygen or carbon dioxide. In some embodiments, the hydrogen bromide-based plasma can be a high-density plasma generated by an inductively coupled plasma or a resonant antenna plasma source with a radio frequency (RF) power generator. In some embodiments, the RF power generator can use an alternating current (AC) operating at a frequency of multiples of about 13.56 MHz. In some embodiments, the RF power generator can provide a source power from about 0 W to about 2500 W to generate plasma. In some embodiments, the RF bias power can be in the range of from about 0 W to about 2000 W. In some embodiments, pulsed plasma etching with a duty cycle from about 5% to about 95% can be used in the etching process. In some embodiments, the plasma etching process can use a bias power with zero source power to increase the directionality of the etching process. In some embodiments, the etch process chamber may be operated at a temperature from about 10° C. to about 200° C. at a pressure ranging from about 1 mTorr to about 200 mTorr.

[0074] In some embodiments, to increase the etching selectivity between the sacrificial gate structure 3712 and the hard mask layer 5236, a polymer layer can be formed on the hard mask layer 5236 using a methane-based deposition process. In some embodiments, an oxide (e.g., silicon oxide) can be formed during the dry etching process to improve the self-aligned etching process. In some embodiments, these oxides can be formed from silicon tetrachloride, oxygen, and hydrogen bromide. In some embodiments, a wet cleaning process can be performed to remove oxides formed on the nanostructures 122 and the dielectric fin structure 119 during the dry etching process. In some embodiments, the wet cleaning process can include etchants such as carbon tetrafluoride (CF4), trifluoromethane (CHF3), difluoromethane (CH2F2), methane (CH3F), and hexafluorobutadiene (C4F6). In some embodiments, such as Fig.63 and Fig.64 As shown, an additional dry etching process may extend the opening 5713 through the nanostructure 122 into the substrate 104 .

[0075] In some embodiments, Figure 65 to Figure 68 As shown, a trench isolation structure 113-2 may be formed in the opening 5713. In some embodiments, the trench isolation structure 113-2 may include a liner 113A and a dielectric filler 113B. The liner 113A may be conformally deposited on the hard mask layer 5236, the substrate 104, and on the sidewalls of the STI region 106, the isolation layer 117, the dielectric fin structure 119, the gate spacer 114, and the sacrificial gate structure 3712. The dielectric filler 113B may be blanket deposited on the liner 113A, and the dielectric filler 113B may fill the opening 5713, as shown. Fig.65 and Fig.66 In some embodiments, the CMP process may planarize the top surfaces of the gate spacers 114 , the ESL 116 , the hard mask layer 5236 , the trench isolation structure 113 - 2 , and the sacrificial gate structure 3712 .

[0076] In some embodiments, the trench isolation structure 113-2 may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbon nitride or other suitable dielectric materials. In some embodiments, the trench isolation structure 113-2 may extend through the sacrificial gate structure 3712, the nanostructure 122, the STI region 106 and the fin structure 108 until it reaches the substrate 104. In some embodiments, the trench isolation structure 113-2 may be formed by a CPODE process to reduce leakage current flowing through the S / D structure 110, the nanostructure 122 and the substrate 104.

[0077] refer to Figure 6 In operation 650, the sacrificial gate structure may be replaced with a metal gate structure. Figures 2 to 5As shown, the sacrificial gate structure 3712 may be replaced with a metal gate structure 112. In some embodiments, the replacement of the gate structure 112 may include removing the sacrificial gate structure 3712, removing the nanostructure 820, and depositing the gate structure 112, and for the sake of clarity, these processes are not described in detail. In some embodiments, the trench isolation structure 113 may be formed after the replacement of the gate structure 112, such as Figure 69 to Figure 85 described.

[0078] Fig.69 is a flow chart of another method 6900 for manufacturing a semiconductor device 100 having a dielectric fin structure according to some embodiments. Method 6900 may not be limited to nanostructured transistor devices and may be applied to other devices that benefit from dielectric fin structures. Additional manufacturing operations may be performed between various operations of method 6900 and may be omitted, such omission being for clarity and ease of description only. Additional processes may be provided before, during, and / or after method 6900; one or more of these additional processes are briefly described herein. Furthermore, not all operations may be required to perform the disclosure provided herein. Additionally, some operations may be performed simultaneously or in conjunction with Fig.69 In some embodiments, one or more other operations may be performed in addition to or in place of the operations currently described.

[0079] For the purpose of illustration, reference will be made to Figures 7 to 56 as well as Figures 70 to 85 An example manufacturing process for manufacturing the semiconductor device 100 is shown to describe Fig.69 The operation shown. Figures 7 to 56 Described above. Figures 70 to 85 A partial cross-sectional view of a semiconductor device 100 having a dielectric fin structure at various stages of its fabrication by another method is shown in accordance with some embodiments. Fig.70 , Fig.72 , Fig.74 , Fig.76 , Fig.78 , Fig.80 , Fig.82 and Fig.84 FIG. 1 shows a semiconductor device 100 according to some embodiments at various stages of its manufacture by another method along an X-axis (eg, Figure 2 A partial cross-sectional view along line AA) is shown. Fig.71 , Fig.73 , Fig.75 , Fig.77 , Fig.79 , Fig.81 , Fig.83 and Fig.85FIG. 1 shows a semiconductor device 100 according to some embodiments at various stages of its manufacture by another method along the Y-axis (eg, Figure 2 A partial cross-sectional view of line CC) shown. Figures 70 to 85 With Figures 1 to 5 Elements with the same reference numerals as those in the description above.

[0080] refer to Fig.69 , method 6900 begins with operation 6910 and a process of forming a channel structure extending along a first direction on a substrate. In some embodiments, operation 6910 may be similar to operation 610 as described above. For example, Figures 7 to 9 As shown, nanostructures 122 and nanostructures 820 along the X-axis may be formed on substrate 104. In some embodiments, after nanostructures 122 and nanostructures 820 are formed, STI regions 106 may be formed between adjacent stacks of nanostructures 122 and nanostructures 820, such as Figures 9 to 16 In some embodiments, after forming the STI region 106, a cladding layer 1725 may be formed, such as Figures 17 to 19 In some embodiments, after forming the coating layer 1725, an isolation layer 117 may be formed. Figure 23 to Figure 28 shown.

[0081] refer to Fig.69 In operation 6920, a dielectric fin structure is formed on the substrate adjacent to the channel structure. The dielectric fin structure includes a hard dielectric material and extends along a second direction parallel to the first direction. In some embodiments, operation 6920 can be similar to operation 620 as described above. For example, Figure 29 to Figure 31 As shown, dielectric fin structures 119 may be formed on isolation layer 117 over STI regions 106 and between adjacent stacks of nanostructures 122 and nanostructures 820. In some embodiments, dielectric fin structures 119 may extend parallel to nanostructures 122 along the X-axis.

[0082] refer to Fig.69 In operation 6930, a metal gate structure is formed on the channel structure and the dielectric fin structure. Fig.70 and Fig.71 As shown, a gate structure 112 may be formed on the nanostructure 122 and the dielectric fin structure 119. In some embodiments, forming the gate structure 112 may include removing Fig.52 The sacrificial gate structure 3712 shown in FIG. Fig.52The nanostructure 820 is shown, and one or more work function metal layers and metal fillers are deposited around the nanostructure 122. In some embodiments, a gate isolation structure 120 can be formed in the gate structure 112 and on the dielectric fin structure 119 to divide the gate structure 112 into multiple parts. In some embodiments, a hard mask layer 7036 can be deposited on the gate structure 112, the gate spacer 114, the ESL 116, the ILD layer 118, and the gate isolation structure 120.

[0083] refer to Fig.69 In operation 6940, an isolation structure is formed that extends through the metal gate structure and the channel structure and contacts the dielectric fin structure. Figure 72 to Figure 85 As shown, trench isolation structures 113-1 and 113-2 extending through the gate structure 112 and the nanostructure 122 and contacting the dielectric fin structure 119 can be formed on the substrate 104. In some embodiments, a stack of a bottom layer 7238, an intermediate layer 7240, and a photoresist 7242 can be deposited on the hard mask layer 7036. In some embodiments, patterning can be performed in the photoresist 7242 above the gate structure 112 to obtain an opening 7213, such as Fig.72 and Fig.73 After the patterning process, an opening 7213 may be formed in the hard mask layer 7036 by a dry etching process, as shown in FIG. Fig.74 and Fig.75 In some embodiments, the highly selective etching process can remove the gate structure 112 and extend the opening 7213 through the gate structure 112, as shown in FIG. Fig.76 and Fig.77 As shown. In some embodiments, the highly selective etching process may include a dry etching process or a wet etching process. After the selective etching process, the gate structure 112 may be removed, and the gate dielectric layer 124 may remain on the nanostructure 122. In some embodiments, a wet cleaning process after each of the dry etching process or the wet etching process may remove any residues formed during the etching process. In some embodiments, as Fig.78 and Fig.79 As shown, another selective etching process can remove the gate dielectric layer 124 from the nanostructure 122. In some embodiments, the selective etching process can include a dry etching process or a wet etching process. Fig.80 and Fig.81 As shown, an additional dry etching process may remove the nanostructure 122 and extend the opening 7213 through the nanostructure 122 into the substrate 104 .

[0084] In some embodiments, Figure 82 to Figure 85As shown, trench isolation structures 113-1 and 113-2 may be formed in openings 7213. In some embodiments, trench isolation structures 113-1 and 113-2 may include liner 113A and dielectric filler 113B. Liner 113A may be conformally deposited on hard mask layer 7036, substrate 104, and on sidewalls of STI region 106, isolation layer 117, dielectric fin structure 119, gate spacer 114, and gate isolation structure 120. Dielectric filler 113B may be blanket deposited on liner 113A, and dielectric filler 113B may fill openings 7213, as shown. Fig.82 and Fig.83 In some embodiments, the CMP process may planarize the top surfaces of the gate spacers 114 , the ESL 116 , the ILD layer 118 , the trench isolation structures 113 - 1 and 113 - 2 , the gate isolation structure 120 , and the gate structure 112 .

[0085] In some embodiments, the trench isolation structures 113-1 and 113-2 may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbon nitride or other suitable dielectric materials. In some embodiments, the trench isolation structures 113-1 and 113-2 may extend through the gate structure 112, the nanostructure 122, the STI region 106 and the fin structure 108 until the substrate 104. In some embodiments, the trench isolation structures 113-1 and 113-2 may be formed by a CMODE process to reduce leakage current flowing through the S / D structure 110, the nanostructure 122 and the substrate 104.

[0086] Various embodiments of the present disclosure provide methods for forming a dielectric fin structure 119 in a semiconductor device 100. In some embodiments, a nanostructure 122 extending in a first direction may be formed on a substrate 104. A dielectric fin structure 119 adjacent to the nanostructure 122 may be formed on the substrate 104. In some embodiments, the dielectric fin structure 119 may include a hard dielectric material and extend in a second direction parallel to the first direction. In some embodiments, the hard dielectric material may have a Young's modulus greater than that of silicon oxide. In some embodiments, the hard dielectric material may have a Young's modulus greater than about 75 GPa. A gate structure 112 may be formed on the nanostructure 122 and the dielectric fin structure 119. A trench isolation structure 113 may be formed on the gate structure 112, and the trench isolation structure 113 may extend through the gate structure 112 and the nanostructure 122. In some embodiments, the trench isolation structure 113 may contact the dielectric fin structure 119. In some embodiments, the trench isolation structure 113 may be formed by a CPODE or CMODE process. In some embodiments, the dielectric fin structure 119 can reduce deformation of the substrate 104 and minimize the LDE effect of the semiconductor device on the substrate 104. Therefore, the dielectric fin structure 119 can reduce device leakage current, minimize damage to the S / D structure 110, and reduce the V t drift.

[0087] In some embodiments, the semiconductor structure includes a channel structure on a substrate. The channel structure extends along a first direction. The semiconductor structure also includes a dielectric fin structure on the substrate and adjacent to the channel structure. The dielectric fin structure includes a hard dielectric material and extends along a second direction parallel to the first direction. The semiconductor structure also includes an isolation structure extending through the channel structure. The isolation structure contacts the dielectric fin structure.

[0088] In some embodiments, a semiconductor device includes a plurality of channel structures on a substrate and a plurality of dielectric fin structures on the substrate including a hard dielectric material. The plurality of channel structures and the plurality of dielectric fin structures are arranged in an alternating configuration. The semiconductor device also includes a gate structure surrounding the plurality of channel structures and the plurality of dielectric fin structures, and an isolation structure extending through the gate structure and at least one of the plurality of channel structures. The isolation structure contacts at least one of the plurality of dielectric fin structures.

[0089] In some embodiments, a method includes: forming a channel structure on a substrate, and forming a dielectric fin structure adjacent to the channel structure on the substrate. The channel structure extends along a first direction. The dielectric fin structure includes a hard dielectric material and extends along a second direction parallel to the first direction. The method also includes forming an isolation structure extending through the channel structure. The isolation structure contacts the dielectric fin structure.

[0090] It should be understood that the detailed description section (rather than the abstract section of the present disclosure) is intended to be used to interpret the claims. The abstract section of the present disclosure may set forth one or more embodiments, rather than all possible embodiments of the present disclosure contemplated by the inventor(s), and is therefore not intended to limit the appended claims in any way.

[0091] The foregoing disclosure summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same purpose and / or achieving the same advantages of the embodiments described herein. Those skilled in the art will also appreciate that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure comprising: A channel structure on a substrate, wherein the channel structure extends along a first direction; a dielectric fin structure on the substrate and adjacent to the channel structure, wherein the dielectric fin structure comprises a hard dielectric material and extends in a second direction parallel to the first direction; and An isolation structure extends through the channel structure, wherein the isolation structure contacts the dielectric fin structure.

2. The semiconductor structure according to claim 1, wherein: The dielectric fin structure is located on a top surface of the isolation layer, and the hard dielectric material has a Young's modulus greater than 75 GPa.

3. The semiconductor structure according to claim 1, further comprising: A gate structure surrounds the channel structure, wherein the gate structure is between the channel structure and the dielectric fin structure.

4. The semiconductor structure according to claim 3, wherein: A top surface of the dielectric fin structure is below a top surface of the gate structure.

5. The semiconductor structure according to claim 3, wherein: A ratio of a height of the dielectric fin structure to a height of the gate structure ranges from 0.15 to 0.

3.

6. The semiconductor structure according to claim 1, wherein: A top surface of the dielectric fin structure is below a top surface of the isolation structure.

7. The semiconductor structure according to claim 1, wherein: A bottom surface of the dielectric fin structure is at the same level as or higher than a top surface of the channel structure.

8. The semiconductor structure according to claim 1, wherein: The isolation structure extends into the substrate, and the dielectric fin structure is surrounded by the isolation structure.

9. A semiconductor device comprising: a plurality of channel structures on a substrate; a plurality of dielectric fin structures on the substrate, the dielectric fin structures comprising a hard dielectric material, wherein the plurality of channel structures and the plurality of dielectric fin structures are arranged in an alternating configuration; a gate structure surrounding the plurality of channel structures and the plurality of dielectric fin structures; and An isolation structure extends through the gate structure and at least one of the plurality of channel structures, wherein the isolation structure contacts the at least one of the plurality of dielectric fin structures.

10. A method comprising: forming a channel structure on a substrate, wherein the channel structure extends along a first direction; forming a dielectric fin structure on the substrate adjacent to the channel structure, wherein the dielectric fin structure comprises a hard dielectric material and extends in a second direction parallel to the first direction; and An isolation structure is formed extending through the trench structure, wherein the isolation structure contacts the dielectric fin structure.

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