Transistor manufacturing method for inhibiting array carbon nanotube stacking through anchoring process

Abstract

The invention relates to a transistor manufacturing method for inhibiting array carbon nanotube stacking through an anchoring process, which comprises the following steps of: firstly, providing a silicon substrate with an oxide layer, and forming an array carbon nanotube film material on the silicon substrate; then, depositing a metal yttrium layer on the substrate, and converting the metal yttrium layer into an yttrium oxide layer after being heated by a hot plate to form a first anchor point; then, preparing a source-drain window on the yttrium oxide layer by using a photoetching process, and selectively removing the yttrium oxide layer in the source-drain window by using a pickling solution; then, source-drain electrode metal is deposited in the window to form a second anchor point, and the yttrium oxide layer in the area outside the window is removed; further, determining an active region through an etching process, and depositing a hafnium oxide dielectric layer as a gate isolation layer; and finally, constructing a top gate on the gate isolation layer to form a top gate field effect transistor. Binding and stacking of the carbon nanotubes are effectively inhibited, fixation and higher ordered arrangement of materials are achieved, and therefore the overall performance of a carbon nanotube device is improved.

Description

Technical Field

[0001] The invention relates to the field of semiconductor device manufacturing, and in particular to a transistor manufacturing method for suppressing array carbon nanotube stacking through an anchoring process. Background Art

[0002] With the rapid development of microelectronics technology, the size of semiconductor devices has been continuously reduced, which has put forward more stringent requirements on material performance. Carbon nanotubes (CNTs) are considered to be one of the potential candidates to replace traditional silicon materials in the future due to their unique physical and electrical properties. The diameter of carbon nanotubes is as low as 1 nm, which can meet the demand for small-size, high-performance devices in future advanced technology nodes. Its excellent conductivity, high carrier mobility and good thermal stability provide great possibilities for realizing high-performance, low-power and highly integrated electronic devices.

[0003] In recent years, the preparation technology of carbon nanotube films has made important progress. Studies have shown that through precision processes, array carbon nanotube (A-CNT) films with high density (>200 / μm), high semiconductor tube purity (>99.9999%) and perfect arrangement can be prepared. These films show extremely excellent electrical properties in theoretical calculations, such as high switching ratio and low power consumption. However, in practical applications, the performance of transistors based on A-CNT films has failed to achieve the expected results, especially showing obvious performance degradation under small size conditions.

[0004] When the transistor gate length (L g ) is reduced to less than 100 nm, the off-state performance of the A-CNT transistor decreases significantly. Studies have shown that the main reason for this performance degradation is that carbon nanotubes are prone to bundling and stacking due to the van der Waals force during the manufacturing process. The stacking effect caused by the van der Waals force not only destroys the orderly arrangement of carbon nanotubes, but also causes the electrical performance of the constructed carbon nanotube transistor to deviate significantly from the theoretical prediction value, thereby limiting the overall performance of the device.

[0005] In addition, many links in the conventional transistor manufacturing process, such as material cleaning, metal film deposition and high-temperature heating and baking, further aggravate the accumulation effect of carbon nanotubes. These process processes destroy the original arrangement structure of the array carbon nanotube film, making its material intrinsic properties and the electrical performance of the constructed transistor far lower than the theoretical value. This series of problems seriously hinders the promotion and development of carbon-based integrated circuits in high-density, small-size applications.

[0006] Therefore, it is urgent to develop new manufacturing technologies to effectively alleviate and suppress these inter-tube stacking effects in order to improve the performance of array carbon nanotube transistors under small-size conditions. Summary of the invention

[0007] The present invention is intended to provide a method for preparing a transistor by suppressing the stacking of array carbon nanotubes through an anchoring process to solve the deficiencies in the prior art. The technical problem to be solved by the present invention is achieved through the following technical solutions, including: Providing a silicon-based substrate with an oxide layer, and forming an array carbon nanotube thin film material with directional and orderly arrangement on the substrate; Depositing a metal yttrium layer on the array carbon nanotube film material to form a first anchor point, and then heating with a hot plate to form an yttrium oxide layer; Forming a source-drain window on the yttrium oxide layer by a photolithography process, and selectively removing the yttrium oxide layer in the source-drain window by using an acid wash solution; Depositing a source-drain metal in the source-drain window to form a second anchor point, and removing the yttrium oxide layer outside the source-drain window; The active area is determined by etching, and a hafnium oxide dielectric layer is deposited to form a gate isolation layer, and then a top gate is formed on the gate isolation layer to realize a top gate field effect transistor structure.

[0008] In an optional embodiment, the carbon nanotube film material is a semiconductor-type, directional array carbon nanotube film.

[0009] In an optional embodiment, the metal yttrium layer is formed by electron beam evaporation and has a thickness of 3 nm.

[0010] In an optional embodiment, the hot plate heating is performed in an atmosphere at 270° C. for 1 hour to oxidize the metal yttrium layer to form YO x layer.

[0011] In an optional embodiment, the photolithography process is to coat polymethyl methacrylate (PMMA) electron beam glue on the yttrium oxide layer, determine the window positions of the source and drain by electron beam lithography, and form the source-drain window.

[0012] In an optional embodiment, the pickling solution is dilute hydrochloric acid with a concentration of 0.5%.

[0013] In an optional embodiment, the source-drain metal is a palladium (Pd) layer with a thickness of 20 nm.

[0014] Compared with the related art, the technical solution of the present application has at least the following advantages: This application is made by YO x The anchoring effect of the layer effectively suppresses the accumulation and disorder of carbon nanotubes caused by the interaction of van der Waals forces, and improves the alignment accuracy of the material. The combination of photolithography and selective etching processes ensures the electrode contact stability in the source-drain region and the cleanliness of the channel region. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a flow chart of a method for manufacturing a transistor by suppressing stacking of array carbon nanotubes through an anchoring process of the present invention; Figure 2 It is a schematic diagram of a transistor manufacturing method for suppressing stacking of array carbon nanotubes through an anchoring process of the present invention; Figure 3 is a transmission electron microscope (TEM) characterization image of the array carbon nanotube film material of the present application; Figure 4 is the electrical performance test result of the carbon nanotube transistor of the present application; Figure 5 This is a transmission electron microscope (TEM) characterization of carbon nanotube materials in transistors made using conventional processes; Figure 6 These are the electrical performance test results of carbon nanotube transistors made using conventional processes. DETAILED DESCRIPTION

[0016] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. Figure 1-Figure 6 The present application is described in detail with reference to embodiments.

[0017] Figure 1 and Figure 2 They are respectively a flow chart and a detailed step diagram of the transistor manufacturing method of the present invention that suppresses the stacking of array carbon nanotubes through an anchoring process. First, a surface-treated substrate is provided. The substrate material can be selected according to application requirements, such as a silicon wafer with an oxide layer, quartz or glass. An array carbon nanotube film material is formed on the surface of the substrate. The carbon nanotube material is an array film that is directional and orderly arranged. The high density and high purity of the array carbon nanotubes are the basis for realizing high-performance transistors. By optimizing the growth conditions of the array, it can be ensured that the number of carbon nanotubes per unit length (per micron) exceeds 200 and the purity of the semiconductor tube reaches more than 99.9999%.

[0018] Subsequently, a 3nm thick yttrium (Y) layer is deposited on the carbon nanotube array by electron beam evaporation technology. The yttrium layer is the basis for the subsequent oxidation process, and its deposition quality has an important impact on the subsequent process and the final device performance. Therefore, it is necessary to deposit the yttrium layer under high vacuum conditions (10 -8 Torr or less) to avoid the introduction of impurities or uneven film thickness.

[0019] Then, the yttrium metal layer reacts with oxygen to form yttrium oxide (YO x) layer. The heating baking time is 1 hour, and the baking temperature needs to be strictly controlled to ensure uniform oxidation and not produce too many defects. The formed YO x As the first anchor point, the unique wettability and anchoring effect of the layer with carbon nanotubes effectively inhibits the bundling and accumulation of carbon nanotubes caused by the interaction of van der Waals forces, while enhancing the arrangement effect of carbon nanotubes, providing a stable material structure foundation for subsequent processes.

[0020] YO x After the layer is formed, the source and drain window positions are defined by photolithography. x A layer of PMMA electron beam glue is spin-coated on the surface of the layer with a thickness of about 70 nm. Subsequently, the window positions of the source and drain are accurately determined by electron beam lithography, and developed to form the required pattern. The photolithography process needs to ensure the position accuracy of the window and the clarity of the edge to avoid electrical performance deviations in the subsequent metallization process.

[0021] After photolithography, selective etching is performed to remove the YO in the source-drain window. x During this process, a 0.5% concentration of dilute hydrochloric acid solution was used to selectively remove the YO layer through a wet etching process. x Etching requires strict control of time and solution concentration to ensure that only YO in the window area x Removed, while YO in other areas x The layer remains intact. The process provides clean surface conditions for subsequent metallization while avoiding structural damage in the channel area.

[0022] Then, after removing YO x The source-drain metal is deposited in the source-drain window area. A 20 nm thick palladium (Pd) layer is deposited by electron beam evaporation technology to form the metal second anchor point of the source and drain. The palladium layer has excellent contact performance with carbon nanotubes and can provide good electrical performance and mechanical stability. The excess metal layer is removed by a standardized lift-off process to ensure that the shape and position of the metal anchor point meet the design requirements.

[0023] After that, the channel area is cleaned and defined. The YO in the area outside the source-drain window is removed by acid cleaning process. x The carbon nanotube array is then cleaned and the electrical performance is guaranteed by removing the carbon nanotube layer and other possible residual materials. Subsequently, the active area is precisely defined using inductively coupled plasma (ICP) etching technology. During the etching process, the gas flow, power and time need to be optimized to avoid damage to the carbon nanotube array while ensuring the clarity of the active area boundary.

[0024] After the channel definition is completed, a hafnium oxide (HfO2) dielectric layer is deposited in the active area with a thickness controlled within 5nm. The atomic layer deposition (ALD) process is used to ensure the uniformity and high quality of the dielectric layer. This dielectric layer acts as a gate isolation layer, providing excellent insulation performance and structural stability for achieving high-performance gate control characteristics.

[0025] Finally, a top gate is fabricated on the gate isolation layer. The top gate position is defined by electron beam lithography, and the top gate material (titanium / gold composite layer) is deposited by metallization process. The deposition thickness and position of the top gate must be strictly controlled to ensure uniform distribution of the electric field between the gate and the carbon nanotubes. The metal in the non-patterned area is removed by a standardized lift-off process to complete the fabrication of the top gate.

[0026] In the present application, the process of depositing metal yttrium to form the first anchor point and the process of depositing the metal second anchor point of the source and drain are complementary. First, by utilizing the good wettability of metal yttrium with carbon nanotubes, by depositing metal yttrium on the array carbon nanotube material, the bundling and accumulation of carbon nanotubes caused by the interaction of van der Waals forces can be suppressed, and the arrangement effect of carbon nanotubes can be enhanced. In the hot plate heating process, yttrium oxide is formed as the first anchor point to fix the carbon nanotubes. Then, the source and drain window areas are defined, and the YO in the window area is selectively washed away only in the specific source and drain areas. x , the carbon tubes in other areas are still covered with yttrium oxide YO x (First anchor point) is firmly fixed; then the source and drain metal as the second anchor point is covered in the window area, the carbon tube is continued to be fixed, and the yttrium oxide YO in other areas is removed. x , these two steps fix each other to ensure that the carbon nanotubes are firmly fixed during the preparation process.

[0027] Figure 3 and Figure 4 The transmission electron microscope (TEM) characterization images of the carbon nanotube material of the carbon nanotube transistor made by the process of this application and the device electrical performance test results are respectively shown. After the electrical performance test of the top gate field effect transistor (TG-FETs) prepared by the above method, the subthreshold swing (SS) of the device is 81 mV / dec, showing extremely low power consumption characteristics. This indicator fully proves the ability of the device to achieve fast current switching in the subthreshold range, which helps to reduce energy consumption and improve energy efficiency. At the same time, the peak transconductance (G m ) reaches 1.8 mS / μm, showing good gain performance and current driving capability. This high sensitivity and high gain characteristics give the device significant advantages in areas such as analog signal processing and high-speed communication. In addition, the current switching ratio of the device is greater than 10 6 , showing a significant gap between the on-state current and the off-state current.

[0028] Figure 5 and Figure 6 The transmission electron microscope (TEM) characterization images of carbon nanotube materials of carbon nanotube transistors made by conventional processes and the test results of device electrical properties are respectively shown. Compared with the performance of top gate field effect transistors (TG-FETs) prepared by conventional processes, the devices prepared by the present invention show significant advantages in various key electrical indicators. The test results show that the subthreshold swing (SS) of the device prepared by conventional processes is 149 mV / dec, which is much higher than 81 mV / dec of the device of the present invention. This shows that the off-state control ability of conventional process devices is poor and cannot achieve fast shutdown. The present invention effectively suppresses the accumulation and disorder of carbon nanotubes by optimizing the process, thereby significantly reducing power consumption and improving the off-state characteristics.

[0029] At the same time, the peak transconductance (G m ) is only 1.2 mS / μm, while the device prepared by the present invention reaches 1.8mS / μm, and the gain performance is improved by 50%. This improvement shows that the present invention enhances the current driving ability and signal amplification ability of the device by improving the arrangement accuracy of carbon nanotubes, making it more suitable for high-gain and high-sensitivity application scenarios. In addition, in terms of current switching ratio, the value of conventional process devices is only about 10 3 , the switching performance is poor and it is difficult to meet the needs of high-performance digital circuits. The switching ratio of the device of the present invention is greater than 10 6 , indicating that it has extremely low leakage current and significant on-state current, which significantly improves the switching characteristics and energy efficiency.

[0030] The above process steps combine advanced material deposition, oxidation, lithography and etching technologies to achieve the preparation of high-precision, high-performance array carbon nanotube transistors. x The anchoring effect of the layer effectively suppresses the accumulation and disorder of carbon nanotubes, improves the alignment accuracy of carbon nanotube materials and the electrical performance of transistors, and ensures the electrical contact stability of the source-drain region and the cleanliness of the channel region. Compared with traditional technologies, it overcomes the accumulation and disorder problems of carbon nanotube materials caused by van der Waals force interactions, greatly improving the performance of the device and the alignment accuracy of the material.

[0031] It should be noted that the above detailed descriptions are exemplary and are intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present application belongs.

[0032] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should also be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0033] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein.

[0034] In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or inherent to these processes, methods, products, or apparatuses.

[0035] For ease of description, spatially relative terms, such as "above", "above", "on the upper surface of", "above", etc., may be used herein to describe the spatial positional relationship between a device or feature and other devices or features as shown in the figure. It should be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation described in the figure. For example, if the device in the accompanying drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Thus, the exemplary term "above" may include both "above" and "below". The device may also be positioned in other different ways, such as rotated 90 degrees or in other orientations, and the spatially relative descriptions used herein are interpreted accordingly.

[0036] In the above detailed description, reference is made to the accompanying drawings, which form a part of this document. In the accompanying drawings, similar symbols typically identify similar components unless the context indicates otherwise. The illustrated embodiments described in the detailed description, drawings, and claims are not meant to be limiting. Other embodiments may be used, and other changes may be made, without departing from the spirit or scope of the subject matter presented herein.

[0037] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for manufacturing a transistor by suppressing the stacking of array carbon nanotubes through an anchoring process, characterized in that: The method comprises the following steps: Providing a silicon-based substrate with an oxide layer, and forming an array carbon nanotube thin film material with directional and orderly arrangement on the substrate; Depositing a metal yttrium layer on the array carbon nanotube film material to form a first anchor point, and then heating with a hot plate to form an yttrium oxide layer; Forming a source-drain window on the yttrium oxide layer by a photolithography process, and selectively removing the yttrium oxide layer in the source-drain window by using an acid wash solution; Depositing a source-drain metal in the source-drain window to form a second anchor point, and removing the yttrium oxide layer outside the source-drain window; The active area is determined by an etching process, and a hafnium oxide dielectric layer is deposited to form a gate isolation layer, and then a top gate is formed on the gate isolation layer to realize a top gate field effect transistor structure.

2. The method for manufacturing a transistor by suppressing stacking of array carbon nanotubes through an anchoring process according to claim 1, characterized in that: The carbon nanotube film material is a semiconductor-type, directional carbon nanotube array film.

3. The method for manufacturing a transistor by suppressing stacking of array carbon nanotubes through an anchoring process according to claim 1, characterized in that: The metal yttrium layer is formed by electron beam evaporation and has a thickness of 3 nm.

4. The method for manufacturing a transistor by suppressing stacking of array carbon nanotubes through an anchoring process according to claim 1, characterized in that: The hot plate heating is carried out in an atmosphere at 270° C. for 1 hour to oxidize the metal yttrium layer to form YO x layer.

5. The method for manufacturing a transistor by suppressing stacking of array carbon nanotubes through an anchoring process according to claim 1, characterized in that: The photolithography process is to coat polymethyl methacrylate electron beam glue on the yttrium oxide layer, determine the window positions of the source and drain electrodes by electron beam photolithography, and form the source-drain window.

6. The method for manufacturing a transistor by suppressing stacking of array carbon nanotubes through an anchoring process according to claim 1, characterized in that: The concentration of the pickling solution is 0.5% dilute hydrochloric acid.

7. The method for manufacturing a transistor by suppressing stacking of array carbon nanotubes through an anchoring process according to claim 1, characterized in that: The source-drain metal is a palladium layer with a thickness of 20 nm.

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