Tracking contamination propagation in integrated circuit design

Abstract

Operation of an integrated circuit is simulated. The simulation includes tracking the propagation of contamination from source data (e.g., sensitive information or fault) by using contamination indicators. The source data is marked as "contaminated" by setting a value of a corresponding contamination indicator to a contamination value. Propagation of the source data along a signal path in the integrated circuit is simulated. The signal path contains elements through which the source data propagates. Propagation of the contamination from the source data is simulated by calculating a value of a contamination indicator corresponding to a signal along the signal path. These contamination indicators indicate whether the contamination of the source data has propagated to the corresponding signal. The values of the contamination indicators are calculated based on the elements and input and / or output signals of the elements in the signal path.

Description

[0001] Related Applications

[0002] This application claims priority to the following U.S. Provisional Patent Applications: Serial No. 63 / 352,999, filed on June 16, 2022, for "Tracking Taint Propagation in Integrated Circuit Designs," and Serial No. 63 / 353,000, filed on June 16, 2022, for "Tracking Taint Propagation in Integrated Circuit Designs, with T-Prop System Example." The subject matter of all of the foregoing U.S. Provisional Patent Applications is incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to functional verification of electronic circuits. In particular, the present disclosure relates to tracking contamination propagation stored in an integrated circuit during functional verification of the integrated circuit. Background Art

[0004] With regard to sensitive or important data, vulnerabilities in the design of integrated circuits can be exploited to expose or leak such data. By accessing sensitive data (such as passwords or encryption keys), an attacker can defeat the system's protection mechanisms and compromise its functionality. Therefore, an important hardware security issue is confidentiality: the degree to which a hardware device can prevent sensitive data from being leaked.

[0005] Regarding malicious data, hardware designs are also susceptible to fault injection attacks, in which an attacker manipulates the environment in which the design operates. Examples of such attacks include inserting voltage, timing, or temperature glitches at certain points in time. Such environmental faults allow an attacker to subvert the correct operation of the system by causing the processor to skip instructions, temporarily disable security features, allow unauthorized access, or behave in a way that allows the attacker to sneak in malicious instructions or otherwise deviate from its intended behavior. Summary of the invention

[0006] In one aspect, the functionality of an integrated circuit is verified. The functional verification can track the propagation of contamination from source data (e.g., sensitive information or induced faults) during operation of the circuit by using contamination indicators. The source data is marked as "contaminated" by setting the value of the corresponding contamination indicator to a Boolean contamination value. The functional verification includes the propagation of the source data along a signal path in the integrated circuit. The signal path contains elements through which the source data propagates. The propagation of the contamination from the source data is performed by calculating the values ​​of contamination indicators corresponding to signals along the signal path. These contamination indicators indicate whether the contamination at the source data has propagated to the corresponding signal. The values ​​of these contamination indicators are calculated using a set of functions based on the values ​​of the contamination indicators of the elements in the signal path and the input signals of these elements.

[0007] In another aspect, a design of the integrated circuit is accessed. Contamination configuration data is also accessed. The contamination configuration data specifies instrumentation of the design for tracking contamination propagation through the design. The design is compiled for functional verification according to the contamination configuration data. Next, the functionality of the compiled design is verified. This includes propagation of the source data through a signal path of the integrated circuit. It also includes tracking contamination propagation from the source data during the functional verification of the integrated circuit by setting and calculating values ​​of contamination indicators for signals along the signal path according to the contamination configuration data.

[0008] In yet another aspect, traces of contamination propagation can be examined, analyzed, and / or used in the development of a circuit design. For example, metrics indicative of contamination propagation can be calculated. A log of contamination information and waveforms of contaminated signals can also be generated for immediate or later review.

[0009] Other aspects include components, devices, systems, improvements, methods, processes, applications, computer-readable media, and other techniques related to any of the above. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The present disclosure will be more fully understood from the detailed description given below and from the drawings of embodiments of the present disclosure. The drawings are used to provide an understanding and understanding of the embodiments of the present disclosure and will not limit the scope of the present disclosure to these specific embodiments. In addition, the drawings are not necessarily drawn to scale.

[0011] Figure 1 is a signal diagram of a circuit design depicting contamination propagation from source data according to an embodiment of the present disclosure.

[0012] Figure 2 is a diagram depicting the propagation of a contamination indicator through an element according to an embodiment of the present disclosure.

[0013] Figure 3A and 3B is a graph depicting pollution generations for two different pollution strategies according to an embodiment of the present disclosure.

[0014] Figure 4 is a diagram depicting the number of pollution generations of a memory index according to an embodiment of the present disclosure.

[0015] Figure 5A and 5B is a graph depicting two different pollution generations for polluted conditions according to an embodiment of the present disclosure.

[0016] Figure 6 A flow chart depicting the inspection process accompanying the tracking of contamination propagation according to an embodiment of the present disclosure.

[0017] Figure 7 is a screenshot of a preferences screen according to an embodiment of the present disclosure.

[0018] Figure 8 A flow chart depicting verification and tracking of contamination propagation using a separate test platform according to an embodiment of the present disclosure.

[0019] Fig. 9 Flowcharts depicting various processes used during the design and fabrication of integrated circuits according to embodiments of the present disclosure.

[0020] Fig.10 A diagram depicting an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0021] Aspects of the present disclosure relate to tracking contamination propagation in integrated circuit designs. Contamination refers to the propagation of data through a circuit design. This data may be sensitive or important data. Alternatively, it may be malicious data or a fault.

[0022] There are many situations where it is useful to track the propagation of taint within an integrated circuit. For example, nondestructive probing attacks can be used to learn the contents of memory cells within an integrated circuit during operation of the circuit. If those memory cells contain sensitive data, then the data may be compromised. In many designs, sensitive data is initially stored in a secure location. However, sensitive data (or derivatives from which sensitive data can be recovered) may propagate to vulnerable locations during operation of the integrated circuit. Therefore, it may be useful to track the propagation of such data through the integrated circuit during operation of the circuit. In this case, taint propagation is used to model information leakage.

[0023] As another example, a fault in the form of malicious data may be injected into an integrated circuit to disrupt its operation. If the fault is localized to its original injection site, its impact may be small. However, if the fault is widely propagated throughout the integrated circuit or propagates to sensitive parts of the integrated circuit, it may be problematic. Therefore, it would be useful to track the propagation of the fault through the integrated circuit during the operation of the circuit. In this case, contamination propagation is used to model the fault data.

[0024] In both of the above examples, the resilience of the hardware design to such vulnerabilities can be assessed and improved by analyzing the propagation of data (whether sensitive data or faults or the effects of their generation) through the circuit design. One propagation metric is permeability: the extent to which data is able to propagate to other areas of the design. Another metric is persistence: the duration that data exists in the integrated circuit. Quantifying permeability and persistence can be used by the design team to assess and improve resistance to vulnerabilities.

[0025] In various aspects, a contamination indicator is used as a mechanism for tracking data propagation during register transfer level (RTL) inspection or other types of inspection (including simulation). The original data being tracked is called source data. During RTL inspection of an integrated circuit, the source data will propagate along a signal path in the integrated circuit. The source data and other signals along the signal path are marked by a contamination indicator, which can be set to a contamination value or a non-contamination value. For example, a contamination indicator can be a bit, where a value of 1 indicates contamination (the contamination value is 1), and a value of 0 indicates no contamination (the non-contamination value is 0). The contamination indicator corresponding to the source data is initially set to a contamination value. Then, the contamination propagation from the source data is tracked by calculating the value of the contamination indicator of the signal downstream of the source data. The values ​​of these contamination indicators depend on the elements in the signal path. The value of the contamination indicator also depends on the value of the contamination indicator of the input signal of the element and may also depend on the input or output signal of the element.

[0026] In one approach, a set of functions (e.g., algebraic) are used to calculate the value of a contamination indicator as a signal propagates through an integrated circuit. For different types of components, the function describes the contamination indicator at the output of the component as a function of the contamination indicator at the input of the component, and may also describe it as a function of the corresponding signal at the input (and / or output) of the component.

[0027] In one aspect, the functionality of an integrated circuit is verified. Functional verification can track the propagation of contamination from source data (e.g., sensitive information or induced faults) during operation of the circuit by using contamination indicators. The source data is marked as "contaminated" by setting the value of the corresponding contamination indicator to a Boolean contamination value. Functional verification includes the propagation of source data along a signal path in the integrated circuit. The signal path contains elements through which the source data propagates. The propagation of contamination from the source data is performed by calculating the values ​​of contamination indicators corresponding to signals along the signal path. These contamination indicators indicate whether contamination at the source data has propagated to the corresponding signal. The values ​​of these contamination indicators are calculated using a set of functions based on the values ​​of the contamination indicators of the elements in the signal path and the input signals of these elements.

[0028] In various embodiments, the set of functions may include the following. For different component types, the set of functions defines the value of the pollution indicator of the output signal of the component type as a function of the pollution indicator of the input signal of the component type. For at least one component type, the value of the pollution indicator of the output signal is also a function of the value of the input signal of the component type. The set of functions can be expressed as a truth table. The set of functions supports four-state encoding of the input signal, and the four-state encoding includes 1, 0, X and Z.

[0029] In addition, the following functions may also be included in the set of functions of at least one element type. If an input signal of the element type is passed to an output signal of the element type, the value of the pollution indicator of the input signal is propagated to the pollution indicator of the output signal. If any data input signal of the element type has a pollution indicator with a pollution value, the pollution indicator of the data output signal of the element type is set to the pollution value. If the data input signal of the element type has a pollution indicator with a pollution value and the data output signal of the element type changes value when the data input signal changes value, the pollution indicator of the data output signal is set to the pollution value. For an element type that is a memory, if an index of the memory has a pollution indicator with a pollution value, the pollution indicator of the output data of the memory read at the index is set to the pollution value. If the only pollution indicator with a pollution value is used for an input signal of the element type with a value of X or Z, the pollution indicator of the output signal of the element type is set to a non-polluted value.

[0030] In various embodiments, different component types may include Boolean operators, arithmetic operators, relational operators, logical operators, conditional operators, control operators, memory access and behavior control constructs, function calls, loops, and / or assertions. In some embodiments, different component types include only synthesizable component types.

[0031] Different element types may also include conditional operators. The conditional operator has a data input signal and a condition input signal. The function of the conditional operator on the data input signal depends on the condition input signal. The set of functions includes the case where the pollution indicator of the condition input signal has a pollution value. Examples of conditional operators include behavioral control structures, if statements, and case statements.

[0032] The following functions may also be included in the set of functions of at least one conditional operator. If the pollution indicator of the conditional input signal has a pollution value, then the pollution indicator of the output data signal will have a non-pollution value only if (x) the pollution indicators of all data input signals have non-pollution values ​​and (y) all data input signals have the same value. If the pollution indicator of the conditional input signal has a pollution value, then the pollution indicator of the output data signal is set to the pollution value.

[0033] The different element types may also include a timing element type. The timing element type has a data input signal and a clock signal. The set of functions includes a case where a contamination indicator of the clock signal has a contamination value. In some cases, the contamination indicator of the clock signal is propagated through the timing element type via a contaminated active clock transition.

[0034] In another aspect, a design of an integrated circuit is accessed. Contamination configuration data is also accessed. The contamination configuration data specifies instrumentation of the design for tracking contamination propagation through the design. The design is compiled for functional verification according to the contamination configuration data. The functionality of the compiled design is then verified. This includes propagation of source data through a signal path of the integrated circuit. It also includes tracking contamination propagation from source data during functional verification of the integrated circuit by setting and calculating values ​​of contamination indicators of signals along the signal path according to the contamination configuration data.

[0035] Examples of taint configuration data include the following. For a signal path including a memory, the taint configuration data may specify a taint indicator for a bit of the memory, a taint indicator for a block of the memory, or a single taint indicator for the entire memory. The taint configuration data may specify a taint indicator for a signal in the design. The taint configuration data may specify the set of functions for tracking taint propagation. The set of functions may be selected from different sets of functions with different levels of pessimism depending on the taint configuration date.

[0036] In some embodiments, verifying functionality of the compiled design includes receiving runtime contamination data further specifying tracking of contamination propagation during functional verification of the integrated circuit. The runtime contamination data may be received via an API. The runtime contamination data may specify a contamination value of at least one contamination indicator of the functional verification of the integrated circuit, a non-contamination value of at least one contamination indicator of the functional verification of the integrated circuit, a start time for tracking contamination propagation, and / or a start condition for tracking contamination propagation. The runtime contamination data may specify that the value of at least one contamination indicator is preserved through power down of the integrated circuit, that contamination propagation is blocked at a specified boundary within the integrated circuit, and / or that a contamination indicator of a signal crossing a specified boundary within the integrated circuit is set to a non-contamination value after the boundary is crossed.

[0037] In some embodiments, compiling the design may include disabling tracking X-propagation when tracking taint propagation is enabled and / or disabling tracking taint propagation when tracking X-propagation is enabled. Compiling the design may also include setting any of the following as default: tracking taint propagation through all behavioral control structures when possible, tracking taint propagation through all conditional controls when possible, tracking taint propagation through all clocks when possible. Compiling the design may also include generating a log file of elements in the design that are blocking tracking taint propagation.

[0038] In some embodiments, a first test platform performs functional verification of the integrated circuit, and a separate safety test platform tracks contamination propagation without modifying the first test platform.

[0039] In some embodiments, the design is compiled for hardware emulation, and verifying the functionality of the integrated circuit is performed together with tracking contamination propagation through hardware emulation.

[0040] In yet another aspect, tracking of contamination propagation may be examined, analyzed, and / or used in the development of a circuit design. For example, a metric indicative of contamination propagation may be calculated. The metric may be a standardized metric. It may indicate the permeability of an integrated circuit to contamination propagation or indicate the persistence of contamination in an integrated circuit. The metric may be ratio-based. The metric may be calculated within a test bench that performs functional verification of the integrated circuit. Alternatively, it may be calculated outside of such a test bench.

[0041] A log of contamination information and waveforms of contaminated signals may also be generated for immediate or later review. The log may collect contamination status of signals based on corresponding contamination indicators, changes in contamination status of signals based on corresponding contamination indicators, contamination status of signals stored only in memory, and / or contamination status of memory clusters.

[0042] In some aspects, the source data may include sensitive data or faults. The traced contamination propagation may be used to estimate the propagation of sensitive data stored on the integrated circuit, the propagation of control signals throughout the integrated circuit, the diffusion of clock signals throughout the integrated circuit, the permeability of the source data throughout the integrated circuit, and / or the persistence of the source data on the integrated circuit.

[0043] Examples of functional verification include simulation of an RTL description of an integrated circuit, simulation of a description of the integrated circuit in a hardware description language, and simulation of a behavioral description of the integrated circuit. In addition, as the design of the integrated circuit evolves, functional verification may be performed multiple times, and tracking contamination propagation for a later functional verification may be based on the results of tracking contamination propagation for a previous functional verification.

[0044] This approach has many technical advantages. It allows designers to assess the vulnerabilities of hardware designs at a relatively early RTL stage. Assessing vulnerabilities early in the design flow enables the design team to develop countermeasures and measure their effectiveness under real workloads. It also reduces the need to mitigate vulnerabilities as the design nears completion, which can result in increased costs and delays.

[0045] It also allows for analysis of interactions between components and identification of where sensitive data is stored (even temporarily). Good alternatives for tracking data propagation are not readily available. For example, searching for a sensitive data value to see if it exists in various memories yields limited useful information. Additionally, during chip operation, data may be transformed through various encodings and operations that make simple identification based on the original form insufficient.

[0046] Furthermore, because this method can be used to trace data at the RTL level, it can be used without boundary (source or destination) markings that allow or do not allow sensitive data to cross. The dynamic nature of this taint tracing also allows it to handle real workloads without special environmental conditions. It can be implemented using RTL descriptions and testbenches, and can also be implemented using system firmware. Since functional defects can also lead to safety issues, taint tracing can also enhance functional verification.

[0047] Taint tracing can be applied to many use cases such as sensitive data tracing, control tracing, and clock diffusion. Data integrity can explore how sensitive data moves in a design, such as from an electrically passive fuse through a bus (data path) and potentially stored in cache or system memory. It can also be used to analyze the effectiveness of system / firmware countermeasures such as cache clearing or memory zeroing. Control tracing can explore the integrity of computations, hidden features (such as chicken bits), or the effectiveness of domain separation (such as secure vs. unsecure). Finally, clock diffusion can explore the creation of passive side channels and the impact of timing or voltage attacks and the effectiveness of deployed mitigation techniques.

[0048] In more detail, Figure 1 is a signal diagram of a circuit design depicting contamination propagation from source data according to an embodiment of the present disclosure. Figure 1 The circuit 100 in FIG. 1 includes sequential logic 110 (e.g., memory, flip-flops, registers, and other elements that store data) and combinatorial logic 112 (e.g., logic gates, multiplexers / demultiplexers, and other elements that process data without storing it). Signals propagate from left to right. For convenience, sequential logic 110 will be referred to as flops, and combinatorial logic 112 will be referred to as gates.

[0049] Figure 1 The propagation of data originally stored in flop 110A is tracked. For convenience, this data is referred to as source data. During functional verification of circuit 100, source data follows a signal path from flop 110A through gate 112X to flops 110B, C, D. From flop 110C, the signal path flows through gate 112Y to flops 110E, F, G. This simulation of circuit 100 computes the values ​​of the signals along these different signal paths. Figure 1 , different signals are labeled according to the suffix of the corresponding component: signal X for gate 112X, signal B for flop 110B, and so on. Figure 1 A single element and signal is shown, but it should be understood that there may be many elements and signals. For example, the combinational logic 112X may include many different gates connected in different ways to many intermediate signals X. In addition, Figure 1 Elements are described using hardware elements flops and gates, but the description of the circuit can be behavioral. Elements can be operators that perform some function regardless of the hardware implementation, rather than specific hardware elements.

[0050] As the functional verification of circuit 100 proceeds, the influence of the source data will propagate to different signals along the signal path. The contamination indicator is used to track this propagation. Figure 1 In , the pollution indicator is a bit, and each signal has a corresponding pollution bit. The pollution bit is set to the pollution value "T", which means that the corresponding signal is polluted, or is set to the non-pollution value "-", which means that the corresponding signal is not polluted.

[0051] Taint tracking begins by marking the source data as tainted. This is done by setting the taint bit of the source data to the taint value T, as Figure 1As the trace proceeds, not only are different signal values ​​calculated, but also the values ​​of their corresponding tainted bits are calculated. For example, during the first clock cycle of the simulation, source data may propagate through gate 112X to flops 110B, C, D. The simulation calculates the values ​​of signals X, B, C, D. To track the propagation of taint, the values ​​of the tainted bits corresponding to signals X, B, C, D are also calculated. The simulation continues, and new values ​​of the signals and corresponding tainted bits are calculated in the next cycle of the simulation.

[0052] The value of the signal is calculated based on the functionality of the elements along the signal path. The value of the contamination bit is calculated based on the element type and the value of the contamination indicator of the element's input signal. In one approach, these calculations are based on the algebra of contamination indicators propagated through different element types.

[0053] Figure 2 is a diagram depicting the propagation of a contamination indicator through an element according to an embodiment of the present disclosure. Element 200 may be combinatorial or sequential. It may also be an RTL operator. Instances of element 200 include Boolean operators, conditional operators, control operators, and behavioral control constructs. More powerful instances of element 200 include function calls including function calls with no return value, loops, and assertions. If the task is to verify the resilience and / or confidentiality of the hardware itself, then the RTL operators may be limited to those that can be synthesized into the hardware.

[0054] Component 200 generates a data output signal Data Out as a function of a data input signal Data In. The function applied by the component may vary depending on a control signal Cntl. The component may be time-controlled by a clock signal Clk. Figure 2 In , each of the signals Input, Output, Cntl, Clk is shown as a single line, but it may include multiple signals. [] is the pollution indicator of the signal. For example, Input[T] indicates that the input is polluted, and Input[-] indicates that the input is not polluted. The pollution indicator of a signal captures the pollution status of the signal.

[0055] In the general model, the pollution indicator of the output signal is a function of the input signals - data input, control and clock - and their corresponding input indicators. The function also depends on the type of element 200. In one approach, the pollution algebra is defined by different functions for different types of elements. Each function defines the value of the pollution indicator of the output signal of the element type as a function of the pollution indicator of the input signal. In some cases, the function may also depend on the input signal of the element.

[0056] The propagation of pollution through any particular component can be modeled in more than one way. Therefore, different functions can be used for the same component. For example, a more conservative (pessimistic) approach can result in more pollution propagation from input to output than a less pessimistic approach. The set of strategies that determine how pollution propagates through various components defines the pollution algebra.

[0057] In the case where data is only copied or moved across the data path, the taint state may only be copied. For example, when moving data from register S to register D, if S is tainted, then D is also tainted, and if S is not tainted, then D is also not tainted.

[0058] When the operation of an element produces a new output value from a set of inputs, there are more possibilities. In such cases, the pollution algebra defines whether the result (the output of the operation) is polluted given the values ​​of its inputs and the pollution state. The choice of pollution algebra balances the desire to retain every pollution possibility with the desire to reduce false or uninteresting pollution. This is a trade-off between pessimism or false negatives and optimism or false positives. It is difficult to achieve perfect accuracy in both aspects, so the choice of algebra will make some compromises. In some embodiments, the system of the present invention allows a choice between different strategy types and their corresponding transformation operations: for example, more pessimistic and more optimistic.

[0059] For example, Figure 3A and 3B are diagrams depicting pollution generations for two different pollution strategies according to an embodiment of the present disclosure. In these diagrams, it is assumed that control and clock signals are not polluted and only data signals are shown. Figure 3A Depicts a conservative strategy where if any of the inputs to operation 300 are contaminated then its output is contaminated. The contamination state of the output is only a function of the contamination state of the inputs, rather than depending on the values ​​of the inputs. This simplifies the algebra. The guiding principle here is that if a contaminated input could change the outcome of an operation, then it should propagate to the output. For convenience, this approach will be referred to as a conservative strategy.

[0060] Under the conservative strategy, there are situations where more contamination can be caused than the actual hardware can cause, or contamination may not be propagated. For example, consider the bitwise (Boolean) AND (&) operation x=a&b. Assume b=0 and also assume b is not contaminated. In this case, x=0, regardless of the value of a. The value of x does not reveal any information about a, so if a is contaminated, then the contamination should not be propagated to the output a. However, under the conservative strategy, x will be contaminated because one of the inputs (a) is contaminated.

[0061] As another example, consider an element that is an encryption block. The input to the encryption block is secret data. Assume that the secret data is contaminated. The purpose of the encryption block is to encrypt the secret data so that it is no longer accessible to the first party. Because the encryption prevents the reconstruction of the secret data from the encrypted output, the output should not be marked as contaminated. However, a conservative strategy will mark the encrypted output as contaminated because it was generated from a contaminated input.

[0062] Figure 3B A less pessimistic strategy is depicted in which the output of operation 300 is tainted only when the tainted input can affect the value of the output. That is, the output is tainted only when the output is actually a function of the tainted input. Consider again the Boolean & example x = a & b, where a is tainted and b is not tainted. Under this less pessimistic strategy, if b = 0, then x = 0, regardless of the value of a, so x is not tainted. However, if b = 1, then the value of x depends on the value of a, so x is tainted.

[0063] Tables 1A and 1B below are Figure 3A Conservative strategies and Figure 3B Truth tables for the less pessimistic strategy. In these tables, the left column is the value of the input a (0 or 1) and the value of its tainted bit (T or -), the top row is the value of the input b and its tainted bit, and each cell is the value of the tainted bit of the output x = a & b. Note that in Table 1A, the tainted bit of the output is only a function of the tainted bit of the input, while in Table 1B, it is also a function of the value of the input. Table 1B is more accurate than Table 1A, but Table 1A is simpler and easier to implement.

[0064] Table 1A: Truth table of the & gate using the conservative strategy

[0065] & 0[-] 1[-] 0[T] 1[T] 0[-] - - T T 1[-] - - T T 0[T] T T T T 1[T] T T T T

[0066] Table 1B: Truth table of the & gate using the less pessimistic strategy

[0067]

[0068]

[0069] Truth tables can also be constructed for other types of elements. In addition, the pollution algebra can be extended to support four-state encoding of input signals. The four-state encoding includes additional states of X (random or unknown) and Z (three-state or high impedance). Table 2 below is an example of the extension of Table 1B to four-state encoding.

[0070] Table 2: Truth table of the & gate using four-state encoding of the input

[0071] & 0[-] 1[-] X[-] Z[-] 0[T] 1[T] X[T] Z[T] 0[-] - - - - - - - - 1[-] - - - - T T T T X[-] - - - - T T T T Z[-] - - - - T T T T 0[T] - T T T T T T T 1[T] - T T T T T T T X[T] - T T T T T T T Z[T] - T T T T T T T

[0072] In some cases, propagation of X and Z values ​​is undesirable or results in excessive noise. The pollution algebra can be modified to prevent the propagation of pollution of such values. Table 3 below shows this alternative propagation model for the & operator. The modified results (compared to Table 2 above, the modified results with propagation disabled) are marked with *. The case where the pollution state switches from T to - is the case where all polluted inputs have only values ​​of X or Z. In these cases, the output is considered unpolluted rather than polluted.

[0073] Table 3: Truth table of the & gate that suppresses the propagation of X and Z values

[0074] & 0[-] 1[-] X[-] Z[-] 0[T] 1[T] X[T] Z[T] 0[-] - - - - - - - - 1[-] - - - - T T * * X[-] - - - - T T * * Z[-] - - - - T T * * 0[T] - T T T T T T T 1[T] - T T T T T T T X[T] - * * * T T * * Z[T] - * * * T T * *

[0075] Similar methods can be used to develop contamination algebras for other types of elements, including assignment operators, bitwise (Boolean) operators, contraction operators, arithmetic and relational operators, logical operators, shift operators, concatenation and flow operators, conditional operators, behavioral control constructs, and networks.

[0076] One type of assignment operator moves or copies data from an input to an output or from a source to a destination. In such cases, the taint state is also copied. A tainted input produces a tainted output, and an untainted input produces an untainted output. More complex assignment operators can be decomposed into sequences of operators. For example, the addition assignment operator a+=b can be viewed as an addition operator (a+b) followed by an assignment operator. Propagation of taint through a join or stream operation can follow assignment (data-path) semantics. In one approach, taint of individual bits participating in a join or stream operation is propagated with those bits.

[0077] Bitwise (Boolean) operators include NOT, AND, OR, XOR, and combinations of these, such as NAND, NOR, XOR. The pollution algebras for these elements can be developed as described above for the bitwise & (AND) operator. The pollution algebras for the abbreviation operators AND, OR, XOR, NAND, NOR, XNOR, etc. can be developed based on their bitwise counterparts. The pollution algebras for logical operators such as conjunction (&&), disjunction (||), implication (->), and equivalence (<->) can be developed in a similar manner.

[0078] Arithmetic operators include addition (+), subtraction (-), multiplication (*), division ( / ), modulus (%), and power (**) operators. Relational operators include less than (<), greater than (>), less than or equal to (<=), greater than or equal to (>=), equal to (==), not equal to (!=), wildcard equal to (==?), and wildcard not equal to (!=?) operators. The pollution algebra of these elements can be followed Figure 3AThe conservative strategy shown in becomes extremely complex, especially if different input values ​​are taken into account. In addition, the circuit design can be described by these operators at the RTL level, but these operators can have multiple different hardware implementations, and the taint propagation can be different depending on which hardware implementation is used.

[0079] The pollution propagation of logical and arithmetic shift operators can be asymmetric about their operands. The first operand (the data being shifted) has a bit granularity. The pollution state of each bit is shifted along with the data. The second operand (the shift amount) treats the polluted state of the operand as a whole. If any part or bit of the operand is polluted, then the entire operand is considered polluted. Therefore, if the second operand is polluted, then the result as a whole (all bits) is polluted. Otherwise, the first operand is considered part of the data-path, and the pollution is propagated bit by bit.

[0080] Now consider the propagation of pollution through storage. Figure 4 is a diagram depicting the number of pollution generations of a memory index according to an embodiment of the present disclosure. Figure 4 The block 400 in FIG. 4 includes a memory array storing data at different addresses and a memory controller executing commands for accessing the memory. The input of the memory 400 includes an index and a command, which in the following example will be a read command. The functional check includes reading data stored at a memory location defined by the index from the memory 400.

[0081] For taint propagation, if the index is not tainted, then the output will have the same taint state as the data. If the stored data is tainted, then the output will also be tainted. If the stored data is not tainted, then the output is also not tainted.

[0082] If the index is contaminated, then applying a conservative strategy results in an output that is also contaminated, regardless of the contamination state of the data. This conservative strategy is embodied in Table 4A below. In some cases, this may be too pessimistic. In a less pessimistic strategy, contaminated indexes are not propagated. Only contaminated data is propagated. However, contaminated index operations can be recorded as built-in assertions. This relaxed mode is described by Table 4B below, where * marks relaxed contamination propagation.

[0083] Table 4A: Truth table for memory access using conservative strategy

[0084] Data[-] Data[T] Index[-] - T Index[T] T T

[0085] Table 4B: Truth table for memory access using a less pessimistic strategy

[0086] Data[-] Data[T] Index[-] - T Index[T] * T

[0087] The algebra presented above can also be used for write commands, where data represents the data to be written to the memory at location Index.

[0088] Now consider the conditional operator. A conditional operator is one in which the function of an element depends on some condition. A simple conditional operator is a 2-to-1 1-bit multiplexer that can be represented by the expression v=s?a:b, where a and b are data inputs, s is a selector, and v is an output. If s=1, then v=a. If s=0, then v=b. ? indicates that s is a selector, and : indicates that a and b are selection options. The input s may be referred to as a control input or a conditional input. If the conditional input s is not contaminated, the operator may be simplified to an operator that expresses v as a function of only a and b, and the contamination propagation from the data inputs a and b to the data output v may be determined as described above for other operators without conditions.

[0089] However, if the conditional input s is contaminated, then the situation is more complicated. This conditional operator can be implemented in hardware in different ways, such as using NAND gates or using NOR gates. However, the propagation of contamination through the hardware implementation will be different depending on the specific gate-level implementation. If the design specifies the operator at the behavioral level without a hardware implementation, then the number of contamination generations should be selected based on the different possible hardware implementations.

[0090] Figure 5A and 5B is a diagram depicting two different pollution algebras for pollution conditions according to an embodiment of the present disclosure. These algebras will be explained using the multiplexer described above. The conditional input s selects between two possible data inputs a and b. Therefore, if the output v is associated with a polluted selector s representing confidential data, then the selector s can cause its data to be exposed. However, if the inputs a and b are the same, then the polluted selector will not expose any data (unless the inputs themselves are polluted). Similarly, if the pollution represents a fault-inducing value, then the fact that the fault does not cause a functional change means that the fault will not cause a failure to occur. This behavior is summarized by the following Table 5 and in Figure 5A and can be called a precise strategy.

[0091] Table 5: Truth table for contaminated condition input using the exact strategy

[0092]

[0093] An alternative, more pessimistic approach considers only the taint status of the conditional inputs. If the conditional input is tainted, then the output is tainted, regardless of the value and taint status of the inputs, e.g. Figure 5BThis approach can be called a composite strategy because it can be thought of as a projection of all possible gate-level implementations of the conditional operator and merging all possible contamination results from these implementations. Although the composite strategy is pessimistic, it may be good enough. One advantage is that it requires much less instrumentation, so it can be compiled and executed faster than the exact strategy.

[0094] Examples of conditional operators include behavioral control constructs, such as IF statements and CASE statements. Consider first an IF statement. An IF statement contains a condition and then various branches that depend on the evaluation of the condition. An IF statement has two branches: one branch when the condition is true and another branch when the condition is false. If this type of IF statement has a contaminated condition, the precise strategy described above can be applied by considering both branches. If any output is contaminated or if all outputs are not the same, then the contamination is propagated. In contrast, if the contamination of the data input does not produce a contaminated output and all outputs of the different branches are the same (making the output independent of the condition), then the contamination is not propagated.

[0095] Another type of IF statement has only one branch, which is executed when the condition is true. This can be modeled as a two-branch IF statement, where the second branch is to do nothing when the condition is false. The pollution strategy described above can then be applied.

[0096] IF statements can also have more than two branches, where the selected branch depends on the value of a condition. These can be evaluated by expanding them into nested two-branch IF statements. CASE statements are a form of multi-branch IF statements, and contamination algebra can be developed on this basis.

[0097] Now consider the case where the clock is contaminated and when that contamination should propagate through to the output of the component. The clock is used to trigger the operation. The behavior of a sequential process triggered by a contaminated clock can be derived by comparing the output of the process when triggered by the clock with the output of the process when not triggered by the clock. In other words, the new value of the output is compared to the previous value. If the output is the same, then the clock has no effect on the output and the contamination on the clock is not propagated through to the output. If the output is different, then the contamination on the clock is propagated through to the output. If the input signal is contaminated, then the output may also be contaminated. This method can be used for both edge-sensitive and level-sensitive components.

[0098] Figure 6A flow chart depicting an inspection flow for tracing accompanying taint propagation according to an embodiment of the present disclosure. The circuit is described at a register transfer level (RTL) 610. This is a behavioral description of the behavior of the hardware and it typically involves a hardware description language, such as Verilog. At the RTL level, the hardware behavior is defined in terms of registers that store signal values ​​and combinatorial logic that performs logical operations on the signal values. In normal flow, the RTL circuit design 610 is compiled into a form that can be executed by a simulator or emulator. Here, taint configuration data 620 specifies instrumentation that is added at compile time to enable tracing of taint propagation. The taint configuration data 620 may take the form of an option on the command line of the compiler, or it may be specified in a generated file for the compiler or in a separate configuration file.

[0099] The taint configuration data 620 may specify which taint indicators should be instantiated in the compiled design 640. It may also specify the granularity of the taint indicators. For example, for different memories in the design, the taint configuration data may specify whether to use one taint bit per memory bit, one taint bit per memory word or block, or one taint bit to represent the entire memory. In one variation, the amount of memory corresponding to one taint bit is set by the user in the taint configuration data 620.

[0100] The taint configuration data 620 may also turn various compiler options on or off. For example, the compiler may default to tracing taint propagation through all behavioral control constructs when possible, tracing taint propagation through all conditional controls when possible, and / or tracing taint propagation through all clocks when possible. The configuration data 620 may allow the user to turn off these defaults, or exclude them for certain modules or blocks within the circuit design. Other options include whether to enable taint propagation through memory indexes and whether to enable taint propagation of X and Z values. The configuration data 620 may also be used to select different taint strategies: for example, conservative versus less pessimistic, or precise versus complex.

[0101] exist Figure 6 6, compiler 630 compiles circuit design 610 according to pollution configuration data 620. The resulting compiled design 640 is in a form suitable for verifying the functionality of the integrated circuit and includes instrumentation that allows tracking pollution propagation. For example, the compiled design may include pollution indicators and implementations that describe the number of pollution generations that propagate through the elements of the design. In some cases, compiler 630 may also generate a log file of elements in the design for which pollution propagation is not enabled or for which it is not possible to enable pollution propagation.

[0102] The compiled design 640 is run on a testbench 660. The testbench includes a simulator. The compiled design 640 can also be targeted to a hardware emulator. Different simulations can be run on the compiled design 640 by specifying different values ​​of signals in the circuit (different test stimuli) and / or by monitoring different signals during simulation. In a similar manner, different pollution scenarios can be run on the compiled design 640 by specifying different values ​​of pollution indicators (different source data) and / or by monitoring different pollution indicators during simulation. These runtime controls are specified by runtime pollution data 650.

[0103] The test bench 660 simulates the operation of compiling the design. This includes the propagation of source data through the signal paths of the integrated circuit. It also includes tracking the propagation of contamination from the source data during simulation. This is done by setting and calculating the value of contamination indicators for signals along the signal paths, as previously described.

[0104] Runtime pollution data 650 allows the user to specify different pollution scenarios for the test platform. For example, various pollution indicators can be set to specific values ​​during simulation. Setting the pollution indicator to a pollution value can be the beginning of a scenario for investigating the propagation of that signal. Setting the pollution indicator to a non-polluted value can be to reset the pollution propagation at that moment in the simulation. Some use cases require pollution to start at a specific time or when a specific enabling condition occurs. For example, secret keys are usually randomly generated, and the runtime mechanism allows the user to specify those values ​​as secret pollution. Other use cases may require pollution ROM, some ROM locations, or possibly fuses. These can be specified at runtime. Similarly, it is sometimes desirable to cancel the pollution of a signal once data reaches a pre-specified area of ​​the design. For example, secret pollution can reach a secure location or may enter a block that may be difficult to analyze or has been thoroughly tested.

[0105] More complex runtime controls may also be implemented. For example, runtime controls may specify that certain contamination indicators retain their values ​​through power down of the integrated circuit. Alternatively, runtime controls may specify that contamination propagation is blocked at certain boundaries within the integrated circuit or that the contamination state is reset to uncontaminated after a boundary is crossed.

[0106] The results 690 (eg, the value of the contamination indicator over time during a simulation) may be used for various purposes. Figure 6 Some examples are shown. Various metrics 691 indicative of contamination spread may be calculated. Examples include metrics of permeability (area extent) and / or persistence (time extent) of contamination spread. If the metrics are standardized, this allows for comparison of different designs. Metrics 691 may be calculated by the test platform 660 or by a program outside the test platform based on data generated by the simulation.

[0107] The results may also include various reports and logs 692. The logging mechanism enables the user to construct a compressed system-level representation of the contamination at a given point in the simulation. In one approach, changes in the contamination state of data stored in the design's memories and registers are tracked. By examining these contamination change logs, the user can identify where and when the contamination propagated. The compressed information can be used to record more detailed information, such as waveforms, to analyze the contamination propagation path in more detail.

[0108] For log files, there are tradeoffs. Recording all changes in individual contamination states will create a complete log of the integrated circuit. In one approach, memories are divided into two categories: discrete and clustered. Discrete memories are tracked and recorded individually, and large memories can be labeled as discrete memories. Cluster memories are grouped together and recorded as a single item. Small memories can be grouped into cluster memories. Both discrete and cluster memories can be tracked and recorded per design example. That is, for each example in the design, the log contains discrete and cluster entries. The memory size that characterizes a memory as large or small can be a user-specified parameter in the configuration file. In one approach, all memories default to clusters, resulting in only a single (cluster) contamination indicator per example.

[0109] The taint-log provides a compressed snapshot of the taint state stored in the design's memory. It can be compressed by computing the taint disjunction over the entire memory: one taint indicator per discrete memory and one taint indicator per instance of all clustered memories. The taint-log thus provides a compact representation of the design's memory taint state.

[0110] In some embodiments, the pollution state of both discrete and clustered memories is pollution monotonic. That is, once a memory has been polluted, its polluted state will persist. Once polluted, the pollution state of the memory can only be cleared via explicit commands.

[0111] By using pollution-log information of different granularities, the preliminary analysis can be subsequently refined to assess overall security. For example, the initial test may use only cluster memory and generate a single pollution-log at the end of the test. The pollution-log generated subsequently will indicate all examples to which the pollution has spread. Any uncontaminated examples do not require further analysis and can be ignored. Subsequent test runs can be used to periodically generate pollution-logs to create an image of the pollution propagation through the system memory over time. Further tests can be used to subdivide the pollution propagation by clearing the pollution state of specific memories to narrow the time window in which the pollution propagates. All this analysis can be automated. Finally, once the problematic examples are identified, the final test can dump detailed waveform information to thoroughly explore how the pollution is propagated through the system.

[0112] In a multi-pass flow, the first run determines where the tainted data has propagated, and possibly identifies specific blocks it shouldn't have reached. Successful runs track how the tainted data got to where it shouldn't have. After the problem has been identified and fixed with some countermeasure, only a single test with a single taint-log may be needed to verify its correctness.

[0113] Users often use waveforms to perform detailed analysis and visualize design data. Therefore, in addition to the contamination log 692, the debugging tool can enable the designer to visualize contamination and track the flow of contaminated data through various types of displays 693. One option is to allow the user to select the waveform dump of signals so that it also contains the contamination status of those signals.

[0114] When displaying the dumped signal waveform, the pollution status of the signal waveform may also be displayed, for example using a user-specified color and / or pattern. Figure 7 is a screenshot of a preferences screen that allows a user to design the display of different signal values ​​1, 0, X, Z and contamination T, -. In this example, the user interface receives one or more configurations, such as color, width, style, stippling, shape, and height of different values ​​of the signal and contamination.

[0115] In addition to user tracking and debugging of contamination propagation, the system can automate or semi-automate the design cycle 694. For example, the user or the system can generate scripts to automate the correction of common contamination propagation patterns. Once the contamination problem is corrected, contamination propagation can be used to verify 695 the solution.

[0116] Figure 8 Flowchart depicting verification and tracking of contamination propagation using a separate test platform according to an embodiment of the present disclosure. In some embodiments, the design itself does not need to be modified in order to contaminate or decontaminate data or check the contamination state of a signal. Instead, the supplemental safety test platform 855 handles all contamination, decontamination, contamination monitoring and checking during test execution. The safety test platform 855 receives runtime contamination data 650. The safety test platform 855 can communicate with the test platform 850 via the API 860. The test platform 850 generates simulation test results 890, such as waveforms of dump signals. The safety test platform 855 generates results 895 related to contamination propagation.

[0117] Fig. 9An example set of processes 900 for transforming and verifying design data and instructions representing an integrated circuit during the design, verification, and fabrication of an article of manufacture (e.g., an integrated circuit) is illustrated. Each of these processes may be constructed and implemented as multiple modules or operations. The term 'EDA' represents the term 'electronic design automation'. These processes begin with creating a product concept 910 using information supplied by a designer, which is transformed to create an article of manufacture using a set of EDA processes 912. When the design is complete, the design is tape-out 934, at which time the artwork (e.g., geometric pattern) of the integrated circuit is sent to a fabrication facility to manufacture a mask set, which is then used to fabricate the integrated circuit. After tape-out, semiconductor die are fabricated 936, and packaging and assembly processes 938 are performed to produce a finished integrated circuit 940.

[0118] The specification of a circuit or electronic structure can range from low-level transistor material layout to high-level description languages. High representation levels can be used to design circuits and systems using hardware description languages ​​('HDL'), such as VHDL, Verilog, SystemVerilog, SystemC, MyHDL, or OpenVera. The HDL description can be transformed into a logic-level register transfer level ('RTL') description, a gate-level description, a layout-level description, or a mask-level description. Each lower level of representation, as a more detailed description, adds more useful details to the design description, for example, more details of the modules that contain the description. The lower level of representation, as a more detailed description, can be computer-generated, derived from a design library, or created by another design automation process. An example of a specification language at a lower level of representation language for specifying a more detailed description is SPICE, which is used to describe in detail circuits with many analog components. The description at each level of representation is enabled for use by a corresponding system (e.g., a formal verification system) at that layer. The design process can use Fig. 9 The described process is enabled by an EDA product (or EDA system).

[0119] During system design 914, the functionality of the integrated circuit to be manufactured is specified. The design may be optimized for desired characteristics such as power consumption, performance, area (physical and / or lines of code), and cost reduction, etc. Separation of the design into different types of modules or components may occur at this stage.

[0120] During logic design and functional verification 916, modules or components in a circuit are specified in one or more description languages, and the functional accuracy of the specifications is checked. For example, the components of the circuit may be verified to generate outputs that match the requirements of the specifications of the circuit or system being designed. Functional verification may use simulators and other programs (such as test bench generators, static HDL checkers, and formal checkers). In some embodiments, special component systems called 'emulators' or 'prototype systems' are used to accelerate functional verification.

[0121] During synthesis and test design 918, the HDL code is transformed into a netlist. In some embodiments, the netlist may be a graph structure where the edges of the graph structure represent components of the circuit and where the nodes of the graph structure represent how the components are interconnected. Both the HDL code and the netlist are hierarchical artifacts that can be used by EDA products to verify that the integrated circuit operates according to the specified design when manufactured. The netlist can be optimized for the target semiconductor manufacturing technology. In addition, the finished integrated circuit can be tested to verify that the integrated circuit meets the requirements of the specification.

[0122] During netlist verification 920, the netlist is checked for compliance with timing constraints and correspondence with the HDL code. During design planning 922, an overall floor plan of the integrated circuit is constructed and analyzed for timing and top-level routing.

[0123] During layout or physical implementation 924, physical placement (positioning of circuit components such as transistors or capacitors) and routing (connection of circuit components through multiple conductors) occur, and selection of cells from a library to implement a specific logic function may be performed. As used herein, the term "cell" may specify a group of transistors, other components, and interconnections that provide a Boolean logic function (such as AND, OR, NOT, XOR) or a storage function (such as a flip-flop or latch). As used herein, a circuit "block" may refer to two or more cells. Both cells and circuit blocks may be referred to as modules or components and are enabled as two physical structures and enabled in simulation. Parameters such as size are selected for the selected cell (based on 'standard cells') and made accessible in a database for use by the EDA product.

[0124] During analysis and extraction 926, circuit functionality is verified at the layout level, which allows the layout design to be improved. During physical verification 928, the layout design is checked to ensure that manufacturing constraints are correct, such as DRC constraints, electrical constraints, lithography constraints, and to ensure that the circuit system functionality matches the HDL design specifications. During resolution enhancement 930, the geometry of the layout is transformed to improve the manufacturing of the circuit design.

[0125] During tape-out, data is created for producing lithographic masks (after applying lithographic enhancements where appropriate).During mask data preparation 932, the 'tape-out' data is used to produce lithographic masks for producing finished integrated circuits.

[0126] Computer systems (e.g. Fig.10 The storage subsystem of the computer system 1000 may be used to store programs and data structures used by some or all of the EDA products described herein, and products for developing units for libraries and physical and logical designs using the libraries.

[0127] Fig.10 An example machine is illustrated of a computer system 1000 within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In alternative embodiments, the machine may be connected (e.g., connected to a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0128] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Furthermore, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0129] The example computer system 1000 includes a processing device 1002, a main memory 1004 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM)), a static memory 1006 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device 1018 that communicate with each other via a bus 1030.

[0130] The processing device 1002 represents a processor, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets or multiple processors implementing a combination of instruction sets. The processing device 1002 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 1002 is configured to execute instructions 1026 for performing the operations and steps described herein.

[0131] The computer system 1000 may further include a network interface device 1008 to communicate over a network 1020. The computer system 1000 may also include a video display unit 1010 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 1012 (e.g., a keyboard), a cursor control device 1014 (e.g., a mouse), a graphics processing unit 1022, a signal generating device 1016 (e.g., a speaker), a graphics processing unit 1022, a video processing unit 1028, and an audio processing unit 1032.

[0132] The data storage device 1018 may include a machine-readable storage medium 1024 (also referred to as a non-transitory computer-readable medium) on which is stored one or more sets of instructions 1026 or software embodying any one or more of the methodologies or functions described herein. The instructions 1026 may also reside, completely or at least partially, within the main memory 1004 and / or within the processing device 1002 during execution thereof by the computer system 1000, the main memory 1004 and the processing device 1002 also constituting machine-readable storage media.

[0133] In some embodiments, the instructions 1026 include instructions for implementing functionality corresponding to the present disclosure. Although the machine-readable storage medium 1024 is shown as a single medium in the example embodiments, the term "machine-readable storage medium" should be considered to include a single medium or multiple media (such as a centralized or distributed database and / or associated caches and servers) that store one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium that can store or encode a set of instructions for machine execution and cause the machine and processing device 1002 to perform any one or more of the methodology of the present disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but not limited to, solid-state memory, optical media, and magnetic media.

[0134] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm may be a sequence of operations leading to a desired result. Operations are those requiring physical manipulation of physical quantities. Such quantities may take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient to refer to such signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0135] It should be remembered, however, that all of these and similar terms should be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless otherwise expressly indicated as apparent from the present disclosure, it should be understood that throughout the description certain terms refer to actions and processes of computer systems or similar electronic computing devices that manipulate and transform data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage devices.

[0136] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may include a computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0137] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various other systems may be used with the program according to the teachings herein, or it may prove convenient to construct more specialized equipment to perform the methods. In addition, the present disclosure is not described with reference to any particular programming language. It should be appreciated that various programming languages ​​may be used to implement the teachings of the present disclosure described herein.

[0138] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form that can be read by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory device, etc.

[0139] In the foregoing disclosure, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It should be understood that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure set forth in the appended claims. Where the present disclosure refers to some elements in the singular, more than one element may be depicted in the drawings, and similar elements are marked with similar numbers. Therefore, the present disclosure and drawings should be viewed in an illustrative sense rather than a restrictive sense.

Claims

1. A method comprising: verifying functionality of an integrated circuit design, including propagation of source data along signal paths of said integrated circuit design; setting a contamination indicator of the source data to a contamination value; and tracking, by a processor, propagation of contamination from the source data during the functional verification of the integrated circuit by calculating a value of a contamination indicator for a signal along the signal path, the calculated value being based on values ​​of contamination indicators for (a) elements comprising the signal path and (b) input signals from the elements being verified for the functional verification of the integrated circuit; Wherein calculating the value of the contamination indicator is based on a set of functions of the contamination indicator propagated through a plurality of different component types.

2. The method of claim 1, wherein the set of functions comprises: For each of the plurality of different element types: defining a value of a contamination indicator for an output signal of the element type as a function of the contamination indicator for the input signal of the element type. 3 . The method of claim 2 , wherein for at least one component type, the value of the contamination indicator of the output signal is also a function of the value of the input signal of the component type. The method of claim 2 , wherein the set of functions can be expressed as a truth table.

5. The method of claim 2, wherein the set of functions supports four-state encoding of the input signal, the four-state encoding comprising 1, 0, X, and Z.

6. The method of claim 2, wherein the different element types include Boolean operators, arithmetic operators, relational operators, logical operators, conditional operators, control operators, memory access, and behavioral control constructs. The method of claim 2 , wherein the different element types comprise function calls. The method of claim 2 , wherein the different element types comprise cycles.

9. The method of claim 2, wherein the different element types include assertions.

10. The method of claim 2, wherein the different component types comprise only synthesizable component types.

11. The method of claim 1 , wherein the set of functions comprises: For at least one component type: if an input signal of the component type is passed to an output signal of that component type, then the value of the contamination indicator of the input signal is propagated to the contamination indicator of the output signal.

12. The method of claim 1, wherein the set of functions comprises: For at least one component type: if any data input signal of the component type has a contamination indicator with the contamination value, then the contamination indicator of the data output signal of the component type is set to the contamination value.

13. The method of claim 1, wherein the set of functions comprises: For at least one component type: if a data input signal of the component type has a contamination indicator with the contamination value and a data output signal of the component type changes value if the data input signal changes value, then the contamination indicator of the data output signal is set to the contamination value.

14. The method of claim 1, wherein the set of functions comprises: For at least one element type that is a memory: if an index of the memory has a taint indicator with the taint value, then the taint indicator of the output data of the memory read at the index is set to the taint value.

15. The method of claim 1, wherein the set of functions supports four-state encoding of the input signal, the four-state encoding including 1, 0, X, and Z, and the set of functions comprises: For at least one component type: if the unique contamination indicator with the contamination value is used for an input signal of the component type with a value of X or Z, then the contamination indicator of an output signal of the component type is set to a non-contamination value.

16. The method of claim 1 , wherein the different element types include a conditional operator; wherein the conditional operator comprises a data input signal and a conditional input signal, a function of the conditional operator on the data input signal depends on the conditional input signal, and the set of functions includes a case where a contamination indicator of the conditional input signal has the contamination value. The method of claim 16 , wherein the conditional operator is a behavioral control construct.

18. The method of claim 16, wherein the conditional operator is one of an if statement and a case statement.

19. The method of claim 16, wherein the set of functions of at least one conditional operator comprises: If the pollution indicator of the conditional input signal has the pollution value, then the pollution indicator of the output data signal will have a non-pollution value only if (x) the pollution indicators of all the data input signals have the non-pollution value and (y) all the data input signals have the same value.

20. The method of claim 16, wherein the set of functions of at least one conditional operator comprises: If the contamination indicator of the conditional input signal has the contamination value, then the contamination indicator of the output data signal is set to the contamination value.

21. The method of claim 1, wherein the different component types include a clocked component type; wherein the clocked component type includes a data input signal and a clock signal, and the set of functions includes a case where the contamination indicator of the clock signal has the contamination value.

22. The method of claim 21, wherein the contamination indicator of the clock signal is propagated through the clocked element type via a contaminated active clock transition.

23. A method comprising: accessing designs of integrated circuits including multiple signal paths; accessing instrumented contamination configuration data of the design specified for tracking contamination propagation through the design; compiling the design according to the contamination configuration data; and Verifying, by a processor, functionality of the compiled design, comprising: (a) propagation of source data through a signal path of the integrated circuit; and (b) tracking contamination propagation from the source data during the functional verification of the integrated circuit, including setting and calculating values ​​of contamination indicators for signals along the signal path according to the contamination configuration data.

24. The method of claim 23, wherein the signal path includes a memory and the pollution configuration data specifies pollution indicators for bits of the memory.

25. The method of claim 23, wherein the signal path includes a memory and the pollution configuration data specifies pollution indicators for blocks of the memory.

26. The method of claim 23, wherein the signal path includes a memory and the pollution configuration data specifies a single pollution indicator for the entire memory.

27. The method of claim 23, wherein the pollution configuration data specifies pollution indicators for signals in the design.

28. The method of claim 23, wherein the taint configuration data specifies a set of functions for tracking taint propagation.

29. The method of claim 28, wherein the pollution configuration data selects the set of functions from different sets of functions having different levels of pessimism.

30. The method of claim 23, wherein verifying functionality of the compiled design comprises: Run-time contamination data further specifying tracking contamination propagation is received during the functional verification of the integrated circuit.

31. The method of claim 30, wherein the runtime contamination data is received via an API.

32. The method of claim 30, wherein the runtime contamination data specifies a contamination value of at least one contamination indicator of the functional verification of the integrated circuit.

33. The method of claim 30, wherein the runtime contamination data specifies a non-contamination value for at least one contamination indicator of the functional verification of the integrated circuit.

34. The method of claim 30, wherein the runtime taint data specifies a start time for tracking the taint propagation.

35. The method of claim 30, wherein the runtime taint data specifies a start condition for tracking the taint propagation.

36. The method of claim 30, wherein the runtime contamination data specifies that a value of at least one contamination indicator is to be persisted through a power shutdown of the integrated circuit.

37. The method of claim 30, wherein the runtime tainted data specific taint propagation is blocked at a designated boundary within the integrated circuit.

38. The method of claim 30, wherein a taint indicator of a signal whose runtime taint data specifically crosses a specified boundary within the integrated circuit is set to a non-taint value after the boundary crossing.

39. The method of claim 23, wherein compiling the design comprises disabling tracking X-propagation when tracking taint propagation is enabled.

40. The method of claim 23, wherein compiling the design comprises disabling trace taint propagation when trace X-propagation is enabled.

41. The method of claim 23, wherein compiling the design includes tracing taint propagation through all behavioral control structures by default where possible.

42. The method of claim 23, wherein compiling the design includes defaulting to tracing contamination propagation through all conditional controls where possible.

43. The method of claim 23, wherein compiling the design includes defaulting to tracing contamination propagation through all clocks when possible.

44. The method of claim 23, wherein compiling the design includes generating a log file of elements in the design that hinder tracking of contamination propagation.

45. The method of claim 23, wherein a first test platform performs the functional verification of the integrated circuit and a separate safety test platform tracks contamination propagation without modifying the first test platform.

46. ​​The method of claim 23, wherein compiling the design comprises compiling the design for hardware emulation, and verifying functionality of the integrated circuit and tracking contamination propagation are performed together with the hardware emulation.

47. A method comprising: Verifying the functionality of an integrated circuit, comprising: (a) propagation of source data through a signal path of the integrated circuit; and (b) tracking the propagation of contamination from the source data, including setting and calculating the value of a contamination indicator for a signal along the signal path; and Information related to pollution propagation is generated by a processor based on the value of the pollution indicator.

48. The method of claim 47, wherein generating information comprises calculating a metric indicative of the contamination propagation from the source data.

49. The method of claim 48, wherein the metric is a normalized metric.

50. The method of claim 48, wherein the metric indicates permeability of the integrated circuit to contamination propagation.

51. The method of claim 48, wherein the metric indicates persistence of contamination in the integrated circuit.

52. The method of claim 48, wherein the metric is based on a ratio.

53. The method of claim 48, wherein a test platform performs the functional verification of the integrated circuit and also calculates the metric.

54. The method of claim 48, wherein a test platform performs the functional verification of the integrated circuit and calculating the metric occurs outside of the test platform.

55. The method of claim 47, wherein generating information comprises: A waveform of a signal is displayed based on the value of the corresponding contamination indicator.

56. The method of claim 47, wherein generating information comprises recording a contamination status of a signal based on the corresponding contamination indicator.

57. The method of claim 56, wherein recording a contamination status of a signal comprises recording a change in the contamination status of a signal based on the corresponding contamination indicator.

58. The method of claim 56, wherein recording the contamination status of the signal comprises recording the contamination status of only the signal stored in the memory.

59. The method of claim 56, wherein recording a contamination status of a signal comprises recording a contamination status of a memory cluster.

60. A method comprising: Verifying the functionality of an integrated circuit, including the propagation of source data through a signal path of said integrated circuit; The pollution indicator of the source data is set to a pollution value; and The processor tracks contamination propagation from the source data during operation of the integrated circuit by calculating a contamination indicator value for a signal along the signal path, the calculated value being based on (a) contamination indicator values ​​for elements comprising the signal path and (b) input signals from the elements under functional verification of the integrated circuit.

61. The method of any one of claims 1-60, wherein the source data comprises sensitive data.

62. The method of any one of claims 1-60, wherein the source data comprises faults.

63. The method of any one of claims 1 to 60, further comprising: Propagation of sensitive data stored on the integrated circuit is estimated based on the tracked contamination propagation.

64. The method of any one of claims 1 to 60, further comprising: Propagation of a control signal throughout the integrated circuit is estimated based on the tracked contamination propagation.

65. The method of any one of claims 1 to 60, further comprising: A spread of a clock signal throughout the integrated circuit is estimated based on the tracked contamination propagation.

66. The method of any one of claims 1 to 60, further comprising: Permeability of the source data throughout the integrated circuit is estimated based on the tracked contamination propagation.

67. The method of any one of claims 1 to 60, further comprising: Persistence of the source data on the integrated circuit is estimated based on the tracked contamination propagation.

68. The method of any one of claims 1-60, wherein the functional verification of the integrated circuit comprises simulation of an RTL description of the integrated circuit.

69. The method of any one of claims 1 to 60, wherein the functional verification of the integrated circuit comprises simulation of a description of the integrated circuit in a hardware description language.

70. The method of any one of claims 1-60, wherein the functional verification of the integrated circuit comprises simulation of a behavioral description of the integrated circuit.

71. A method according to any one of claims 1 to 60, wherein as the design of the integrated circuit evolves, multiple executions are performed to verify the functionality of the integrated circuit, and tracking contamination propagation for a later functional verification is based on the results of tracking contamination propagation for a previous functional verification.

72. A system comprising: a memory storing instructions; and A processor coupled to the memory and configured to execute the instructions, which when executed cause the processor to perform any of the processes of claims 1 to 71.

73. A non-transitory computer-readable medium comprising stored instructions that, when executed by a processor, cause the processor to perform any of the processes of claims 1-71.

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