Semiconductor device manufacturing method and structure

Abstract

In this method for manufacturing a semiconductor device, a structure (200) is prepared, the structure (200) having an interposer (60) in which a trench section (61) divided into a plurality of installation regions (65) is formed, and semiconductor elements (202a, 202b) disposed on each of the installation regions (65). The semiconductor element (202a) is a processor, and the semiconductor element (202a) is a memory. Each groove portion (61) includes two grooves (61a) arranged side by side. In this structure (200), semiconductor elements (202a, 202b) are sealed so that a sealing material (80b) is inserted into each of the trenches (61a). Then, the back surface of the interposer (60) is polished so that the sealing material (80b) inserted into each of the trenches (61a) is exposed. Thereafter, the sealing material (80b) is cut along the trench portion (61) to obtain a plurality of semiconductor devices (201). According to this method, only the sealing material (80b) is cut during singulation, so that blade change can be omitted and manufacturing efficiency can be improved.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor device and a structure. Background Art

[0002] Due to the demand for high functionality, various semiconductor device mounting methods have been developed. As an example, 2.5D mounting is known in which a plurality of semiconductor devices are arranged close to a silicon interposer and the semiconductor devices are connected to each other via wiring formed on the silicon interposer (for example, refer to Patent Document 1).

[0003] A semiconductor device using such an interposer mounting method is manufactured through the following process. As an example, first, a plurality of semiconductor elements are arranged on the interposer, and each semiconductor element is connected to a wiring formed on the interposer. Next, a sealing material is arranged in the interposer to cover the semiconductor element. Then, the sealing material and the interposer are cut and separated into pieces, thereby obtaining a plurality of semiconductor devices.

[0004] Previous technical literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2018-037465 Summary of the invention

[0007] Technical issues to be solved by the invention

[0008] In the above process, for example, a high-speed rotating blade is used to sequentially cut the interposer and the sealing material and separate them into pieces. The material of the interposer and the sealing material are different from each other, so it is necessary to cut the interposer and the sealing material with different blades suitable for their respective materials. Therefore, for example, after cutting the interposer using a blade for the interposer, it is necessary to change the blade to a blade for the sealing material and then cut the sealing material. This operation of changing the blade during separation has become a cause that hinders the improvement of the manufacturing efficiency of semiconductor devices.

[0009] An object of the present invention is to provide a method and a structure for manufacturing a semiconductor device that can improve the manufacturing efficiency of the semiconductor device.

[0010] Means for solving technical problems

[0011] [1] As one aspect of the present invention, a method for manufacturing a semiconductor device is provided. The method for manufacturing a semiconductor device includes: a step of preparing a structure having an interposer including a first main surface and a second main surface opposite to the first main surface and having a plurality of groove portions formed thereon to divide the first main surface into a plurality of setting regions, and a plurality of semiconductor elements each having at least one arranged in each setting region, wherein each groove portion includes at least two grooves arranged side by side; a step of sealing at least a portion of each of the plurality of semiconductor elements with a sealing material so that the sealing material is arranged at least in the plurality of groove portions; a step of grinding the interposer from the second main surface toward the first main surface so that the sealing material arranged in the plurality of groove portions is exposed; and a step of cutting the sealing material along each groove portion to separate the structure into a plurality of regions to obtain a plurality of semiconductor devices.

[0012] In the manufacturing method, the sealing material is arranged in a plurality of groove portions that divide the first main surface of the interposer into a plurality of setting areas, and the interposer is polished from the second main surface toward the first main surface to expose the sealing material arranged in each groove portion. Then, the structure is singulated (chipped) by cutting off the area including the sealing material arranged in each groove portion, thereby obtaining a plurality of semiconductor devices. In this case, the structure can be singulated by cutting off the area including the sealing material arranged in the groove portion. Therefore, when the structure is singulated, it is not necessary to use a blade for cutting the interposer other than a blade for cutting the sealing material, for example. Thus, the manufacturing efficiency of the semiconductor device can be improved. In addition, in the manufacturing method, a portion of the interposer remains between at least two parallel grooves, but a portion of the interposer is not a part of the manufactured semiconductor device, so there is no problem even if a blade for cutting the interposer is not used. In addition, when a groove portion is formed on the interposer, if a groove with a width corresponding to the cutting width (blade width) during singulation is to be formed, the formation of the groove portion sometimes takes time. However, according to the above-mentioned manufacturing method, the width of each groove in the groove portion is narrowed, and the time required to form the groove portion can be shortened. Therefore, according to this manufacturing method, the manufacturing efficiency of the semiconductor device can be improved in this regard as well.

[0013] [2] In the method for manufacturing a semiconductor device of the above-mentioned [1], the step of preparing a structure may include the step of forming a plurality of groove portions, wherein the plurality of groove portions have a depth of 10% to 60% relative to the thickness of the interlayer before grinding. In the case where the depth of the formed groove portion is less than 10% relative to the thickness of the interlayer before grinding, it is not easy to expose the sealing material in the step of grinding the interlayer. In addition, in the case where the depth of the formed groove portion is greater than 60% relative to the thickness of the interlayer before grinding, the strength of the interlayer is reduced, and cracks may be generated on the interlayer in the manufacturing process of the semiconductor device. In order to avoid the generation of such cracks, there is a risk of reduced manufacturing efficiency. In contrast, according to the above-mentioned manufacturing method, the sealing material can be easily exposed in the step of grinding the interlayer, and cracks are not easily generated on the interlayer in the manufacturing process of the semiconductor device, and the manufacturing efficiency will not be reduced. As a result, the manufacturing efficiency of the semiconductor device can be improved.

[0014] [3] In the method for manufacturing a semiconductor device of [1] or [2] above, the step of preparing a structure may include the step of forming a plurality of groove portions having a depth of 70 μm to 470 μm. When the depth of the groove portion formed is less than 70 μm, it is not easy to expose the sealing material in the step of grinding the intermediate layer. Furthermore, when the depth of the groove portion formed is greater than 470 μm, the strength of the intermediate layer is reduced, and cracks may be generated on the intermediate layer in the manufacturing process of the semiconductor device. In order to avoid the generation of such cracks, there is a risk of reduced manufacturing efficiency. In contrast, according to the above-mentioned manufacturing method, the sealing material can be easily exposed in the step of grinding the intermediate layer, and cracks are not easily generated on the intermediate layer in the manufacturing process of the semiconductor device, and the manufacturing efficiency will not be reduced. As a result, the manufacturing efficiency of the semiconductor device can be improved.

[0015] [4] In any one of the semiconductor device manufacturing methods of [1] to [3] above, the width of each of the parallel grooves can be 20 μm to 50 μm. In this case, the amount of chips generated when forming the groove portion is reduced, and contaminants can be prevented from adhering to the semiconductor device including the semiconductor element. As a result, the defect rate in the monolithic semiconductor device can be reduced, and the manufacturing efficiency of the semiconductor device can be further improved. In addition, by keeping the width of the parallel grooves within the above range, even if the interposer is a silicon interposer, for example, the parallel grooves can be quickly formed using a blade for cutting the interposer.

[0016] [5] In the method for manufacturing a semiconductor device of any one of [1] to [4] above, the step of preparing the structure may include a step of forming each groove portion so that a convex portion remains between the parallel grooves, and in the step of obtaining a plurality of semiconductor devices, the sealing material arranged in each groove portion and the convex portion can be cut together. In this case, the step of forming the groove portion can be performed quickly, and the cutting during singulation can also be performed quickly, so that the manufacturing efficiency of the semiconductor device can be further improved. In addition, in this case, the width of the convex portion can be 100μm to 200μm. In this case, the cutting during singulation can be performed more reliably.

[0017] [6] In the method for manufacturing a semiconductor device of any one of [1] to [5] above, the step of preparing the structure may include: a step of forming a redistribution layer on the first main surface before forming a plurality of groove portions; a step of removing a portion of the redistribution layer that overlaps with a portion of the plurality of groove portions that is predetermined to be formed; and a step of forming a plurality of groove portions on an interposer. In this case, a portion of the redistribution layer that overlaps with a portion of the plurality of groove portions that is predetermined to be formed is removed. Thus, for example, when a blade is used to form a plurality of groove portions on the interposer, the blade is less likely to come into contact with the redistribution layer. Thus, peeling and cracking (micro defects) of the redistribution layer can be suppressed.

[0018] [7] In the method for manufacturing a semiconductor device of [6], the material forming the redistribution layer includes a photosensitive material. In the step of removing the overlapping portion, the overlapping portion can be removed by exposing and developing the redistribution layer. In this case, even if the overlapping portion in the redistribution layer has a complex shape or a fine shape, the overlapping portion can be easily removed.

[0019] [8] In the method for manufacturing a semiconductor device according to any one of [1] to [7] above, before the step of disposing the sealing material, a step of disposing an underfill between the plurality of semiconductor elements and the first main surface may be further included. In this case, for example, the semiconductor elements are more stably fixed to the interposer by the underfill.

[0020] [9] In the method for manufacturing a semiconductor device of any one of [1] to [8] above, a sealing material is arranged in the sealing process to cover the side and upper surface of each semiconductor element, and the method for manufacturing a semiconductor device also includes a process of grinding the sealing material to expose the upper surface of the semiconductor element from the sealing material. In this case, the side of the semiconductor element is covered by the sealing material, so the semiconductor element can be protected. In addition, the upper surface of the semiconductor element is exposed from the sealing material, so the heat dissipation of the semiconductor element can be improved. In addition, in this case, in the sealing process, a sealing material is also arranged in the multiple groove portions of the interlayer, so the side of each part of the monolithic interlayer is also covered by the sealing material. In this way, each part of the interlayer constituting the semiconductor device can also be protected.

[0021]

[10] In any one of the semiconductor device manufacturing methods of [1] to [9] above, the step of preparing the structure may include the step of cutting the interposer using at least two first blades to simultaneously form at least two side-by-side grooves. In this case, the step of forming the side-by-side grooves on the interposer can be performed more quickly, and the manufacturing efficiency of the semiconductor device can be further improved. In addition, in the above-mentioned semiconductor device manufacturing method, the step of preparing the structure may include the step of cutting the interposer using one first blade to sequentially form at least two side-by-side grooves. In this case, the structure of the blade device used in forming the grooves can be simplified.

[0022]

[11] In the method for manufacturing a semiconductor device according to any one of [1] to

[10] , in the step of obtaining a plurality of semiconductor devices, the sealing material may be cut along the groove portion using a second blade. In this case, the sealing material can be cut more reliably.

[0023]

[12] In the method for manufacturing a semiconductor device of the above-mentioned

[11] , the step of preparing the structure may include the step of forming a plurality of groove portions by cutting an intermediate layer using a first blade. The particle size of the abrasive grains possessed by the first blade is larger than the particle size of the abrasive grains possessed by the second blade. In this case, the groove portion can be more reliably formed relative to the intermediate layer using the first blade. Furthermore, the groove portion forming the intermediate layer can be set as a groove having a fine cutting surface. In addition, the intermediate layer and the sealing material can be cut or cut by the first blade and the second blade having abrasive grains suitable for their respective materials.

[0024]

[13] In the method for manufacturing a semiconductor device of

[12] , the particle size of the abrasive grains of the first blade may be #2000 to #4000. The particle size of the abrasive grains of the second blade may be #320 to #600. In this case, the interposer and the sealing material can be cut or cut by the first blade and the second blade having abrasive grains suitable for their respective materials.

[0025]

[14] Another aspect of the present invention relates to a structure. The structure comprises an intermediate layer including a first main surface and a second main surface opposite to the first main surface, and a plurality of semiconductor elements arranged on the first main surface. On the intermediate layer, a plurality of groove portions are formed to divide the first main surface into a plurality of setting areas. Each groove portion comprises at least two grooves arranged side by side. At least one of the plurality of semiconductor elements is arranged on each setting area. In addition, in the structure, more than two semiconductor elements may be arranged on each setting area.

[0026] In the structure, a plurality of groove portions that divide the first main surface into a plurality of setting areas are formed on the interposer. When the semiconductor device is manufactured by the above-mentioned manufacturing method using the structure, the structure can be monolithicized by cutting the sealing material arranged in the groove portion, as described above. Therefore, when the structure is monolithicized, it is not necessary to use a blade for cutting the interposer other than a blade for cutting the sealing material, for example. Thus, the manufacturing efficiency of the semiconductor device can be improved. In addition, in the structure, a portion of the interposer remains between at least two parallel grooves, but the portion of the interposer is not a part of the manufactured semiconductor device, so there is no problem even if a blade for cutting the interposer is not used. In addition, when the groove portion is formed on the interposer, if a groove with a width corresponding to the cutting width during monolithicization is to be formed, the formation of the groove portion sometimes takes time. However, according to the above-mentioned structure, the width of each groove in the groove portion is narrowed, and the time required to form the groove portion can be shortened. Therefore, according to the structure, the manufacturing efficiency of the semiconductor device can also be improved in this regard.

[0027]

[15] In the structure of

[14] , the plurality of grooves have a depth of 10% to 60% relative to the thickness of the interposer. When the semiconductor device is manufactured by the manufacturing method using the structure, the sealing material can be easily exposed in the step of grinding the interposer, and cracks are less likely to occur in the interposer during the manufacturing process of the semiconductor device. Thus, the manufacturing efficiency of the semiconductor device can be improved.

[0028]

[16] In the structure of

[14] or

[15] , the plurality of grooves may have a depth of 70 μm to 470 μm. When the semiconductor device is manufactured by the manufacturing method using the structure, the sealing material can be easily exposed in the step of grinding the intermediate layer, and cracks are less likely to occur in the intermediate layer during the manufacturing process of the semiconductor device. Thus, the manufacturing efficiency of the semiconductor device can be improved.

[0029]

[17] In any one of the structures of

[14] to

[16] above, the width of each of the parallel grooves may be 20 μm to 50 μm. In this case, as described above, the amount of chips generated when forming the groove portion is reduced, and contaminants can be prevented from adhering to the semiconductor device. As a result, the defect rate in the semiconductor device can be reduced, and the manufacturing efficiency of the semiconductor device can be further improved.

[0030]

[18] In any one of the structures of

[14] to

[17] above, a convex portion may be provided between the parallel grooves, and the width of the convex portion may be 100 μm to 200 μm. In this case, as in the above, the cutting during singulation can be performed quickly, thereby further improving the manufacturing efficiency of the semiconductor device.

[0031]

[19] In the structure of

[14] to

[18] above, the plurality of groove portions may be formed in a lattice shape including a plurality of first groove portions along a first direction and a plurality of second groove portions along a second direction intersecting the first direction. The plurality of first groove portions may each have at least two grooves arranged side by side, and the plurality of second groove portions may each have at least two grooves arranged side by side. The interval between adjacent first groove portions may be 10 mm to 100 mm. The interval between adjacent second groove portions may be 20 mm to 100 mm. When a semiconductor device is manufactured using the structure by the above manufacturing method, a semiconductor device with high versatility having a size that can be mounted on a general electronic component can be manufactured. In addition, the interval between the groove portions mentioned here refers to the interval between adjacent grooves in a groove constituting one groove portion and a groove constituting another groove portion.

[0032] Effects of the Invention

[0033] According to an aspect of the present invention, it is possible to improve the manufacturing efficiency of a semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a cross-sectional view schematically showing an example of a semiconductor device manufactured by the manufacturing method according to the first embodiment.

[0035] Figure 2 It is a schematic cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0036] Figure 3 It is a schematic cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0037] Figure 4 It is a schematic cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0038] Figure 5 FIG. 1 is a plan view showing an interposer having a groove portion formed therein.

[0039] Figure 6 It is a magnified representation Figure 5 A top view of a trench portion of an interposer is shown.

[0040] Figure 7 It is a schematic cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0041] Figure 8 It is a schematic cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0042] Fig. 9 It is a diagram showing the structure of an underfill material.

[0043] Fig.10 It is a schematic cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0044] Fig.11 It is a schematic cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0045] Fig.12 It is a schematic cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0046] Fig.13 It is a schematic cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0047] Fig.14 It is a cross-sectional view schematically showing an example of a semiconductor device manufactured by the manufacturing method according to the second embodiment.

[0048] Fig.15 (a) to (c) are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to the second embodiment.

[0049] Fig.16 (a) to (c) are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to the second embodiment.

[0050] Fig.17 (a) to (c) are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to the second embodiment. DETAILED DESCRIPTION

[0051] Hereinafter, several embodiments of the present invention will be described in detail with reference to the accompanying drawings as needed. In the following description, the same symbols are added to the same or corresponding parts, and repeated descriptions are omitted. In addition, the positional relationship such as up, down, left, and right shall follow the positional relationship shown in the accompanying drawings unless otherwise specified. In addition, the dimensional ratios of the accompanying drawings are not limited to the ratios shown in the drawings.

[0052] In this specification, the numerical range indicated by "~" includes the numerical values ​​before and after "~" as the minimum value and the maximum value, respectively. In the numerical ranges recorded in stages in this specification, the upper limit value or the lower limit value recorded in one numerical range can be replaced by the upper limit value or the lower limit value of the numerical range recorded in other stages. Furthermore, in the numerical ranges recorded in this specification, the upper limit value or the lower limit value of the numerical range can be replaced by the value shown in the embodiments.

[0053] [First embodiment]

[0054] (Structure of Semiconductor Device)

[0055] Figure 1 1 is a cross-sectional view schematically showing an example of a semiconductor device 1 manufactured by the manufacturing method involved in the present embodiment. The semiconductor device 1 is, for example, a semiconductor package having a CoWoS (Chip on Wafer on Substrate) structure. The semiconductor device 1 includes a semiconductor element 2, a bump 3, an underfill 4, a redistribution layer 5, an interposer 6, a bump 7, and a sealing material 8. In CoWoS, a semiconductor device 1 of such a structure is mounted on an organic substrate (not shown).

[0056] The semiconductor element 2 is, for example, a semiconductor chip such as a processor or a memory. The processor may be, for example, a processor unit such as a GPU (Graphics Processing Unit) or a CPU (Central Processing Unit). The memory may be, for example, a memory unit such as an HBM (High Bandwidth Memory). In this embodiment, for ease of description, the case where the semiconductor device 1 has one semiconductor element 2 is used as an example for description, but the semiconductor device 1 may not have multiple semiconductor elements 2 (for example, refer to the second embodiment), and may also have one processor and multiple memory units.

[0057] Semiconductor element 2 is disposed on interposer 6 via redistribution layer 5. Semiconductor element 2 has upper surface 2a, lower surface 2b, and side surface 2c connecting upper surface 2a and lower surface 2b. Upper surface 2a is located farther from interposer 6 than lower surface 2b.

[0058] The bump 3 is arranged between the semiconductor element 2 and the redistribution layer 5 (RDL). The bump 3 is arranged between the lower surface 2b of the semiconductor element 2 and the main surface 5a of the redistribution layer 5 described later. The bump 3 is formed of a metal material such as solder. The bump 3 electrically connects the semiconductor element 2 and the redistribution layer 5.

[0059] The underfill 4 is disposed between the semiconductor element 2 and the rewiring layer 5 so as to cover the bump 3. The underfill 4 is bonded to the semiconductor element 2 and the rewiring layer 5. The underfill 4 seals and protects the bump 3.

[0060] The rewiring layer 5 is arranged between the bump 3 and the interposer 6. The rewiring layer 5 has main surfaces 5a and 5b facing each other and a side surface 5c connecting the main surface 5a and the main surface 5b. The main surface 5a is located at a position farther away from the interposer 6 than the main surface 5b. The bump 3 and the bottom filler 4 are arranged on the main surface 5a. The rewiring layer 5 is directly arranged on the interposer 6. The main surface 5b is in contact with the interposer 6. The rewiring layer 5 has a layered insulating portion 15 and wiring (not shown) formed in the insulating portion 15. The wiring electrically connects the bump 3 and the interposer 6.

[0061] The interposer 6 is a substrate supporting the semiconductor element 2. In the present embodiment, the interposer 6 is formed into a rectangular plate shape. The shape of the interposer 6 is not limited, and the interposer 6 can be formed into a circular plate shape or a polygonal plate shape other than a rectangle. The interposer 6 has main surfaces 6a and 6b facing each other and a side surface 6c connecting the main surface 6a and the main surface 6b. The main surface 6a is in contact with the main surface 5b of the redistribution layer 5. Wiring is formed on the interposer 6. The wiring can be a through electrode that passes through from the main surface 6a toward the main surface 6b. The wiring possessed by the interposer 6 electrically connects the wiring possessed by the redistribution layer 5 to the bump 7 described later. In addition, the side surface 6c of the interposer 6 is covered with a sealing material 8.

[0062] Bumps 7 are arranged on the main surface 6b of the interposer 6. Bumps 7 are formed of a metal material such as solder. When the semiconductor device 1 is mounted on another electronic component, the bumps 7 electrically connect the interposer 6 and the electronic component.

[0063] The sealing material 8 seals the semiconductor element 2 and the interposer 6. When viewed from the thickness direction of the interposer 6, the sealing material 8 is formed in a ring shape around the semiconductor element 2. The sealing material 8 covers the side 2c of the semiconductor element 2, the surface of the bottom filler 4, the side 5c of the redistribution layer 5, and the side 6c of the interposer 6. In this way, by being covered by the sealing material 8, the durability of the semiconductor device 1 can be improved. In particular, sometimes the interposer 6 is formed of a material having relatively hard and brittle properties (for example, silicon, etc.). Even in this case, the interposer 6 can be more reliably protected by being covered by the sealing material 8. In addition, the sealing material 8 does not cover the upper surface 2a of the semiconductor element 2 and the main surface 6b of the interposer 6. That is, the upper surface 2a and the main surface 6b are exposed from the sealing material 8. In this embodiment, the entire upper surface 2a and the main surface 6b are exposed from the sealing material 8.

[0064] (Method for manufacturing semiconductor device)

[0065] refer to Figure 2 to Figure 13 , a method for manufacturing the semiconductor device 1 is described. Figures 2 to 4 , Figure 7 , Figure 8 and Figures 10 to 13 It is a schematic cross-sectional view showing a method for manufacturing the semiconductor device 1 . Figure 5 1 is a plan view showing an interposer 60 in which a plurality of grooves 61 are formed. Figure 6 It is a magnified representation Figure 5 FIG. 1 is a plan view of a groove portion 61 (a first groove portion 62 and a second groove portion 63 ) of an interposer 60 . Fig. 9 1 is a diagram showing the structure of the underfill material 4. The semiconductor device 1 is manufactured through, for example, the following steps (a) to (f).

[0066] (a) A process for preparing a structure 100, wherein the structure 100 has an interposer 60 including a main surface 60a (first main surface) and a main surface 60b (second main surface) opposite to the main surface 60a, and having a plurality of groove portions 61 for dividing the main surface 60a into a plurality of setting areas 65, and a plurality of semiconductor elements 2, at least one of which is arranged on each setting area 65, wherein each groove portion 61 includes at least two grooves 61a arranged side by side.

[0067] (b) A step of disposing an underfill material 4 between the plurality of semiconductor elements 2 and the main surface 60 a .

[0068] (c) A step of sealing at least a portion of each of the plurality of semiconductor elements 2 with the sealing material 80 so that the sealing material 80 b is disposed at least in the groove portion 61 (the groove 61 a ).

[0069] (d) A step of polishing the sealing material 80 so that the upper surface 2 a of each semiconductor element 2 is exposed from the sealing material 80 .

[0070] (e) A step of polishing the interposer 60 from the main surface 60 b toward the main surface 60 a to expose the sealing material 80 b arranged in the plurality of groove portions 61 .

[0071] (f) A step of cutting the sealing material 80 b along the groove portion 61 to separate the structure 100 into pieces for each of the plurality of installation regions 65 , thereby obtaining a plurality of semiconductor devices 1 .

[0072] [Step (a)]

[0073] refer to Figure 2 to Figure 7 Step (a) is to prepare Figure 7 In step (a), first, as shown in FIG. Figure 2 As shown, prepare the interposer 60. The interposer 60 is singulated in a subsequent process to become the interposer 6 of the semiconductor device 1. The interposer 60 has a main surface 60a and a main surface 60b opposite to the main surface 60a. The direction in which the main surface 60a and the main surface 60b are opposite is the thickness direction of the interposer 60. In the present embodiment, the interposer 60 is formed of silicon (Si). The interposer 60 is in the shape of a circular plate. The interposer 60 can be formed of glass or an organic material, or it can be an organic substrate formed using an organic material including an inorganic filler. These organic substrates can, for example, be formed by using a copper-clad laminate (for example, MCL series (product name, manufactured by Resonac Holdings Corporation)) as a multilayer material as a core material, and an interlayer insulating material (for example, ABF film, etc.) is stacked thereon. In the case where the interposer 60 is formed of glass or an organic material, the interposer 60 can be in a shape other than a circular plate (for example, a rectangular plate). The thickness T1 of the interposer 60 may be, for example, 500 μm to 1000 μm, or 700 μm to 800 μm. Wiring is formed on the interposer 60. The wiring may be a through-silicon via (TSV) penetrating from the main surface 60a toward the main surface 60b.

[0074] Next, a redistribution layer 50 is formed on the main surface 60a of the interposer 60. The redistribution layer 50 is singulated in a subsequent process to become the redistribution layer 5 of the semiconductor device 1. The redistribution layer 50 is formed over the entire main surface 60a. The redistribution layer 50 has a layered insulating portion 51 and wiring (not shown) formed in the insulating portion 51. In this embodiment, the insulating portion 51 is formed of an organic material. The organic material forming the insulating portion 51 may be a polyimide resin, a maleimide resin, an epoxy resin, a phenoxy resin, a polybenzoxazole resin, an acrylic resin, or an acrylate resin. In addition, the insulating portion 51 of the redistribution layer 50 may be formed, for example, using a photosensitive insulating material (e.g., AH series (product name, manufactured by Resonac Holdings Corporation)).

[0075] Generally, the elastic modulus of organic materials is lower than that of inorganic materials. In other words, generally, organic materials are softer than inorganic materials. The elastic modulus of the organic material forming the insulating portion 51 may be, for example, 1 GPa to 10 GPa. The elastic modulus described here refers to Young's modulus.

[0076] The wiring of the redistribution layer 50 is formed of a metal material such as copper. The material forming the insulating portion 51 may be photosensitive. In the case where the material forming the insulating portion 51 is photosensitive, a portion of the insulating portion 51 may be removed by exposure and development, and wiring may be formed in the removed portion using an electrolytic plating method or the like. The removal of the insulating portion 51 may be performed by laser irradiation. In the case of laser irradiation, the material forming the insulating portion 51 may not be photosensitive. The wiring of the redistribution layer 50 is electrically connected to the wiring of the intermediate layer 60.

[0077] Then, if Figure 3 As shown in FIG. 1 , a portion of the redistribution layer 50 is removed. By removing a portion of the redistribution layer 50, a plurality of openings 52 are formed on the redistribution layer 50. In the present embodiment, after a portion of the redistribution layer 50 is removed, a plurality of groove portions 61 are formed on the interposer 60 (see FIG. 1 ). Figure 4 For the detailed structure of the groove portion 61, please refer to Figure 4 This will be described later. Figure 3 In the process of removing a portion of the redistribution layer 50 shown in FIG. 1 , portions of the redistribution layer 50 corresponding to the plurality of groove portions 61 are removed. Each groove portion 61 is configured to have at least two grooves 61a. Specifically, in Figure 3 In FIG. 1 , the portion where the groove portion 61 (groove 61a) in the interposer 60 is to be formed is indicated by a two-dot chain line as a portion 61A. Figure 3In the step of removing a portion of the redistribution layer 50 shown in , the portion overlapping with the portion 61A in the redistribution layer 50 is removed. The portion overlapping with the portion 61A in the redistribution layer 50 may be removed by exposing and developing the redistribution layer 50, or may be removed by laser irradiation.

[0078] Then, if Figure 4 As shown in FIG. 1 , a plurality of grooves 61 are formed in the interposer 60. The width W of each groove 61 corresponds to the width of the cut (the width of the blade 75) when the structure 100 is singulated in the step (f) described later, and is preferably 100 μm to 500 μm (see FIG. 1 ). Figure 6 ). However, the width W of each groove portion does not need to be consistent with the cutting width (i.e., the blade width of the blade 75) when performing singulation. The width W of each groove portion 61 is more preferably 150 μm to 400 μm, and more preferably 200 μm to 300 μm. If the width W of each groove portion 61 is narrower than 100 μm, it becomes difficult to maintain the blade 75 (refer to FIG. 1 ) for cutting the sealing resin in step (f). Fig.12 ) strength. On the other hand, if the width W of each groove portion 61 is wider than 500μm, the cut area becomes wider, resulting in a decrease in the number of semiconductor devices 1 that can be obtained from one interposer. In addition, each groove portion 61 has two grooves 61a extending from the main surface 60a of the interposer 60 toward the main surface 60b. The two grooves 61a extend side by side with each other, and a convex portion 61b is formed between the two grooves 61a. Each groove 61a constituting each groove portion 61 is formed in a slit shape and opens on the main surface 60a. The depth A1 of the groove portion 61 (groove 61a) can be, for example, 70μm to 470μm, 100μm to 400μm, or 200μm to 300μm. The depth A1 of the groove portion 61 (groove 61a) relative to the thickness T1 of the interposer 60 may be, for example, 10% to 60%, 20% to 50%, or 30% to 40%. The depth A1 of the groove portion 61 may be greater than the thickness T2 of the interposer 6 of the semiconductor device 1 obtained in the end (refer to Figure 1 ) is large, for example, 30 μm to 50 μm. Also, the width W1 of each groove 61a (refer to Figure 6 ) can be arbitrarily selected within the range of width W, for example, it can be 20μm to 40μm, or 40μm to 50μm. The width W2 of the convex portion 61b located between each groove 61a can be, for example, 100μm to 150μm, or 150μm to 200μm. In addition, the aspect ratio of the width W1 of the groove 61a relative to the depth A1 of the groove 61a (depth A1: width W1) can be, for example, 3.5:1 to 8:1.

[0079] Here, also refer to Figure 5 and Figure 6 The structure of the groove portion 61 will be described in more detail. Figure 5 and Figure 6 In the figure, for the convenience of explanation, the redistribution layer 50 is omitted and only the interposer 60 is shown. Figure 5 and Figure 6 As shown, the groove portion 61 has a plurality of first groove portions 62 along the first direction D1 and a plurality of second groove portions 63 along the second direction D2 intersecting the first direction D1. That is, the groove portion 61 is formed in a lattice shape including a plurality of first groove portions 62 and a plurality of second groove portions 63. In the present embodiment, the second direction D2 is perpendicular to the first direction D1. The first groove portion 62 has two grooves 62a arranged side by side, and the second groove portion 63 has two grooves 63a arranged side by side. A convex portion 62b is formed between the two grooves 62a arranged side by side, and a convex portion 63b is formed between the two grooves 63a arranged side by side. In addition, the interval P1 between the adjacent first groove portions 62 can be, for example, 10 mm to 100 mm, or 25 mm to 60 mm. The interval P2 between the adjacent second groove portions 63 may be, for example, 20 mm to 100 mm, or 30 mm to 60 mm. The interval P2 may be larger than the interval P1.

[0080] The plurality of grooves 61 divide the main surface 60a into a plurality of setting areas 65. In the present embodiment, when viewed from the thickness direction of the interposer 60, each setting area 65 is rectangular. The width of the setting area 65 along the first direction D1 is equal to the spacing P2 between the adjacent second grooves 63. The width of the setting area 65 along the second direction D2 is equal to the spacing P1 between the adjacent first grooves 62. The shape of each setting area 65 is not limited, and each setting area 65 may be, for example, a polygonal shape other than a rectangular shape. Figure 4 As shown, the interposer 60 having the groove portion 61 formed therein has a plate-shaped first portion 66 and a plurality of second portions 67 formed on the first portion 66. The second portion 67 is in a mesa shape. The top surface of the second portion 67 corresponds to the installation region 65.

[0081] Each groove 61a (grooves 62a, 63a) of the groove portion 61 is formed by using, for example, two blades 70 (first blade, see Figure 3) is formed. As an example, by moving two blades 70 rotating at high speed from the main surface 60a of the intermediary layer 60 toward the main surface 60b, and cutting the intermediary layer 60, two grooves 61a in each groove portion 61 are formed simultaneously. During this formation, a convex portion 61b remains between the two grooves 61a. The two grooves 61a in each groove portion 61 can be formed sequentially using one blade 70. Regarding the blade 70 for cutting the intermediary layer 60, for example, it is a dicing blade for silicon cutting, and it is a blade for forming the groove 61a, so it has a blade width equivalent to the width W1 of the groove 61a. The blade width of the blade 70 is, for example, 20μm to 50μm. In addition, the particle size (particle size number) of the abrasive grains possessed by the blade 70 for cutting the intermediary layer 60 can be, for example, #2000 to #4000. The larger the # value showing the particle size, the smaller the particle size of the abrasive grains becomes. The abrasive grains can be diamond abrasive grains (SD). The method for forming each groove 61 a of the groove portion 61 is not limited, and the groove portion 61 may be formed by, for example, laser irradiation.

[0082] Then, if Figure 7 As shown, a semiconductor element 2 is set on each setting area 65. In the present embodiment, a semiconductor element 2 is set on each setting area 65. It is sufficient that at least one semiconductor element 2 is set on each setting area 65. Therefore, a plurality of semiconductor elements 2 may also be set on each setting area 65. As an example, a processor (e.g., a GPU) and a plurality of memories (e.g., an HBM) may be set on each setting area 65 as a plurality of semiconductor elements 2. In this case, in each setting area 65, a plurality of memories may be arranged close to the periphery of the processor. The processor and the memory may be arranged two-dimensionally, rather than stacked on each other. A plurality of memories may be stacked on each other and arranged three-dimensionally.

[0083] In the present embodiment, the redistribution layer 50 is arranged on the interposer 60, and the semiconductor element 2 is arranged on the redistribution layer 50 via the bump 3. That is, the semiconductor element 2 is arranged on the setting area 65 via the redistribution layer 50 and the bump 3. The semiconductor element 2 is electrically connected to the wiring portion of the redistribution layer 50 through the bump 3. Through the above process (a), the structure 100 is prepared. The prepared structure 100 has an interposer 60 and a plurality of semiconductor elements 2. The interposer 60 includes a main surface 60a and a main surface 60b opposite to the main surface 60a. A plurality of groove portions 61 are formed on the interposer 60 to divide the main surface 60a into a plurality of setting areas 65. Each groove portion 61 includes at least two grooves 61a arranged side by side. At least one of the plurality of semiconductor elements 2 is arranged on each setting area 65. In the present embodiment, one of the plurality of semiconductor elements 2 is arranged on each setting area 65.

[0084] [Step (b)]

[0085] Step (b) is a step of disposing the bottom filler 4 between the plurality of semiconductor elements 2 and the main surface 60a of the interposer 60. Figure 8 As shown, the bottom filler 4 is arranged between each semiconductor element 2 and the main surface 60a. In this embodiment, the bottom filler 4 is arranged between the redistribution layer 50 and the semiconductor element 2, and the redistribution layer 50 is arranged on the main surface 60a. Fig. 9 As shown, the bottom filler 4 is arranged to cover the bump 3 between the semiconductor element 2 and the redistribution layer 50. The bottom filler 4 is filled in the gap between the bumps 3. The bottom filler 4 is bonded to the semiconductor element 2 and the redistribution layer 50. The bottom filler 4 seals and protects the bump 3. The bottom filler 4 can be formed of a material including epoxy resin, for example. In addition, as the bottom filler 4, not only a single bottom filler material can be used to form it, but also a part of the sealing material 80 can be used as the bottom filler when sealing with the sealing material 80 described later.

[0086] [Step (c)]

[0087] Step (c) is a step of sealing each of the plurality of semiconductor elements 2 with the sealing material 80 and disposing the sealing material 80b at least in the groove portion 61 (groove 61a). Fig.10 As shown, the plurality of semiconductor elements 2 are sealed with a sealing material 80 so that the sealing material 80b is arranged (filled) in the entire groove portion 61. The sealing material 80 is also arranged inside the opening 52 of the redistribution layer 50 and between the plurality of semiconductor elements 2. The sealing material 80 is arranged throughout the entire interposer 60 to cover the semiconductor elements 2, the underfill 4 and the redistribution layer 50. The sealing material 80 is arranged to cover the upper surface 2a and the side surface 2c of each semiconductor element 2. The sealing material 80 can be formed of a material including epoxy resin, for example. The sealing material 80 can be an epoxy molding compound (EMC).

[0088] [Step (d)]

[0089] Step (d) is a step of polishing the sealing material 80 so that the upper surface 2a of each semiconductor element 2 is exposed from the sealing material 80. Fig.10 As shown in FIG. 1 , the sealing material 80 has a surface 80a on the side opposite to the interposer 60. In step (d), the sealing material 80 is thinned by grinding the sealing material 80 from the surface 80a toward the interposer 60. Fig.11 As shown in FIG. 1 , the sealing material 80 is polished until the surface 80 a and the upper surface 2 a are flush with each other. Thus, the upper surface 2 a is exposed from the sealing material 80 .

[0090] In this embodiment, after step (d) is completed, the orientation of the interposer 60 is reversed. In the steps up to step (d), the main surface 60a of the interposer 60 is located above the main surface 60b in the vertical direction (see Fig.11 ). In contrast, in the steps after step (e), the interposer 60 is arranged so that the main surface 60a is located below the main surface 60b in the vertical direction.

[0091] [Step (e)]

[0092] Step (e) is a step of grinding the interposer 60 to expose the sealing material 80b disposed in the two grooves 61a constituting each groove portion 61. In step (e), the interposer 60 is thinned by grinding the interposer 60 from the main surface 60b toward the main surface 60a. If the interposer 60 is ground until the sealing material 80b disposed in the groove portion 61 is exposed, Fig.11 and Fig.12 As shown, the first portion 66 of the interposer 60 is removed, and a plurality of second portions 67 remain. When viewed in the thickness direction of the interposer 60, only the convex portion 61b between the sealing material 80 and the groove 61a exists between adjacent second portions 67.

[0093] Then, if Fig.13 As shown, the bumps 7 are arranged on the interposer 60. In the present embodiment, the bumps 7 are arranged on the surface of each second portion 67 on the side opposite to the redistribution layer 50. The bumps 7 are electrically connected to the wiring of the interposer 60.

[0094] [Step (f)]

[0095] Step (f) is a step of cutting the sealing material 80b in the two grooves 61a and the convex portion 61b between the grooves 61a along each groove portion 61, so as to separate the structure 100 into a plurality of setting areas 65, thereby obtaining a plurality of semiconductor devices 1. Fig.12 and Fig.13As shown, in step (f), the sealing material 80b and the convex portion 61b are cut in the thickness direction of the interposer 60. Specifically, the sealing material 80b arranged in the groove 61a, the convex portion 61b between the grooves 61a, the sealing material 80 arranged in the opening 52 of the redistribution layer 50, and the portion of the sealing material 80 arranged between the plurality of semiconductor elements 2 are cut together. Thus, the structure 100 is singulated according to the plurality of setting regions 65. As described above, when viewed from the thickness direction of the interposer 60, the sealing materials 80 and 80b exist between the adjacent second portions 67. Therefore, when the sealing materials 80 and 80b are cut in step (f), the main body of the interposer 60 (except the portion of the convex portion 61b) is not cut. In the present embodiment, when viewed from the thickness direction of the interposer 60, the groove portion 61 is formed in a lattice shape. Therefore, the interposer 60 is cut in a lattice shape along the groove portion 61.

[0096] The sealing material 80b and the convex portion 61b in the groove 61a are cut using, for example, a blade 75 (a second blade). As an example, the sealing material 80b and the convex portion 61b are cut by the blade 75 rotating at high speed. The blade 75 used to cut the sealing material 80b is, for example, a cutting blade for cutting the sealing material (resin material). Since it is necessary to cut at least the convex portion 61b, it is preferred to have a blade width greater than the width W2 of the convex portion 61b and less than the width W of the groove portion 61. The blade width of such a blade 75 is, for example, 100μm to 200μm. That is, the blade width of the blade 75 during singulation can be greater than that of the blade 70 (refer to Figure 3 ) has a wider blade width. When using a blade 75 whose blade width is close to the width W2 of the convex portion 61b, the thickness of the sealing material 80 in the side of the singulated semiconductor device 1 can be sufficiently ensured, thereby improving the protection function of the package. In addition, the particle size (unit number) of the abrasive grains possessed by the blade 75 used to cut the sealing material 80b during singulation can be, for example, #320 to #600. The abrasive grains can be diamond abrasive grains (SD). The particle size of the abrasive grains possessed by the blade 70 (the blade used to form the groove portion 61) used to cut the interposer 60 in step (a) can be larger than the particle size of the abrasive grains possessed by the blade 75 used to cut the sealing material 80b in step (f).

[0097] The structure 100 is singulated in step (f) to obtain a plurality of semiconductor devices 1 (see Figure 1 The individualized interposer 60 corresponds to the interposer 6 of the semiconductor device 1, and the individualized redistribution layer 50 corresponds to the redistribution layer 5 of the semiconductor device 1. The above-described manufacturing process of the semiconductor device 1 is completed.

[0098] As described above, according to the manufacturing method of the semiconductor device 1 involved in the present embodiment, the sealing material 80b is arranged in the plurality of groove portions 61 that divide the main surface 60a of the interposer 60 into the plurality of setting areas 65, and the interposer 60 is polished from the main surface 60b toward the main surface 60a so that the sealing material 80b arranged in each groove portion 61 is exposed. Then, the region including the sealing material 80b arranged in each groove portion 61 is cut to separate the structure 100, thereby obtaining a plurality of semiconductor devices 1. In this case, it is not necessary to cut the main body of the interposer 60, but it is possible to separate the structure 100 by cutting the region including the sealing material 80b arranged in each groove portion 61. Therefore, when the structure 100 is separated into pieces, it is not necessary to use a blade for cutting the interposer 60, for example, in addition to the blade 75 for cutting the sealing material 80b. As a result, for example, it is not necessary to replace the blade, and the manufacturing efficiency of the semiconductor device 1 can be improved. Furthermore, in the conventional manufacturing method in which both the interposer and the sealing material need to be cut sequentially when the structure is singulated, in order to reliably cut the interposer, the interposer is sometimes cut in such a way that the blade reaches the sealing material. In this case, the blade used to cut the interposer contacts the sealing material. In this way, when an object of a material different from the original object is cut, abnormal wear may occur in the blade. In contrast, in the manufacturing method of the semiconductor device 1 of the present embodiment, when the structure 100 is singulated, it is not necessary to make the blade 75 used to cut the area including the sealing material 80b contact the main part of the interposer 60, so abnormal wear is not easy to occur in the blade. Thus, the life of the blade is extended and the replacement frequency of the blade is reduced, so the manufacturing efficiency of the semiconductor device 1 can be improved. In addition, in the semiconductor device 1 manufactured by the manufacturing method involved in the present embodiment, the side 6c of the interposer 6 is covered with the sealing material 8, so the interposer 6 can be protected. According to the above-mentioned structure in which the side of the interposer 6 is covered with the sealing material 8, even if the interposer 6 is formed by silicon having relatively hard and brittle properties, the interposer 6 can be more reliably protected. Furthermore, in the above-mentioned manufacturing method, a part of the interposer remains between the two parallel grooves 61a, but the part of the interposer (convex part 61b) does not constitute the part of the manufactured semiconductor device 1, so there is no problem even if a blade for cutting the interposer 60 is not used (that is, there is no problem even if the blade 75 is used to cut it together). Furthermore, when the groove portion 61 is formed in the interposer 60, if a groove with a width corresponding to the cutting width during singulation is to be formed, it sometimes takes time to form the groove portion. However, according to the above-mentioned manufacturing method, the time required to form the groove portion 61 can also be shortened by narrowing the width of each groove 61a in the groove portion. Therefore, according to this manufacturing method, the manufacturing efficiency of the semiconductor device can also be improved in this regard.

[0099] In the manufacturing method of the semiconductor device 1 of the present embodiment, the step of preparing the structure 100 may include the step of forming the groove portion 61 (groove 61a), the groove portion 61 having a depth A1 of 10% to 60% relative to the thickness T1 of the interposer 60. When the depth A1 of the groove portion 61 is less than 10% relative to the thickness T1 of the interposer 60, it is difficult to expose the sealing material 80b in the step of grinding the interposer 60. In addition, when the depth A1 of the groove portion 61 is greater than 60% relative to the thickness T1 of the interposer 60, the strength of the interposer 60 is reduced, and cracks may be generated in the interposer 60 in the manufacturing process of the semiconductor device 1. In order to avoid the generation of such cracks, there is a risk of reducing the manufacturing efficiency. In contrast, according to the above-mentioned manufacturing method, in the step of grinding the interposer 60, the sealing material 80b can be easily exposed, and cracks are not easily generated in the interposer 60 in the manufacturing process of the semiconductor device 1, and the manufacturing efficiency will not be reduced. As a result, the manufacturing efficiency of the semiconductor device 1 can be improved.

[0100] In the manufacturing method of the semiconductor device 1 of the present embodiment, the step of preparing the structure 100 may include the step of forming a groove portion 61 (groove 61a) having a depth A1 of 70 μm to 470 μm. When the depth A1 of the groove portion 61 is less than 70 μm, it is not easy to expose the sealing material 80b in the step of grinding the interposer 60. In addition, when the depth A1 of the groove portion 61 is greater than 470 μm, the strength of the interposer 60 is reduced, and cracks may be generated on the interposer 60 in the manufacturing process of the semiconductor device 1. In order to avoid the generation of such cracks, there is a risk of reduced manufacturing efficiency. In contrast, according to the above-mentioned manufacturing method, in the step of grinding the interposer 60, the sealing material 80b can be easily exposed, and cracks are not easily generated in the interposer 60 in the manufacturing process of the semiconductor device 1, and the manufacturing efficiency will not be reduced. As a result, the manufacturing efficiency of the semiconductor device 1 can be improved.

[0101] In the manufacturing method of the semiconductor device 1 of the present embodiment, the width of each of the parallel grooves 61a can be 20μm to 50μm. In this case, the amount of chips generated when forming the groove portion 61 is reduced, and contaminants can be prevented from adhering to the semiconductor device 1 including the semiconductor element 2. As a result, the defect rate in the singulated semiconductor device 1 can be reduced, and the manufacturing efficiency of the semiconductor device 1 can be further improved. In addition, by making the width of the parallel grooves 61a within the above range, even if, for example, the interposer 60 is a silicon interposer, the parallel grooves 61a can be quickly formed using a blade 70 or the like.

[0102] In the manufacturing method of the semiconductor device 1 of the present embodiment, the process of preparing the structure 100 includes the process of forming each groove portion 61 so that the convex portion 61b remains between the parallel grooves 61a. In addition, in the process of obtaining a plurality of semiconductor devices 1, the sealing material 80b and the convex portion 61b arranged in the groove 61a of each groove portion 61 are cut together. In this case, the process of forming the groove portion 61 can be performed quickly, and the cutting during singulation can also be performed quickly, so the manufacturing efficiency of the semiconductor device 1 can be further improved. In addition, in this case, the width of the convex portion 61b can be 100μm to 200μm. In this case, the cutting during singulation can be performed more reliably.

[0103] In the method for manufacturing the semiconductor device 1 of the present embodiment, the interposer 60 is formed of silicon (Si). In this case, the wiring formed in the interposer 60 can be miniaturized.

[0104] In the manufacturing method of the semiconductor device 1 of the present embodiment, the process of preparing the structure 100 may include: a process of forming the redistribution layer 50 on the main surface 60a before forming the plurality of groove portions 61; a process of removing the overlapping portion of the redistribution layer 50 with the portion (portion 61A) where the plurality of groove portions 61 are to be formed; and a process of forming the plurality of groove portions 61 on the interposer 60. In this case, the overlapping portion of the redistribution layer 50 with the portion where the plurality of groove portions 61 are to be formed is removed. Thus, for example, when the groove portion 61 is formed on the interposer 60 using a blade, the blade is less likely to come into contact with the redistribution layer 50. Thus, peeling and cracking (micro defects) of the redistribution layer 50 can be suppressed.

[0105] In the method for manufacturing the semiconductor device 1 of the present embodiment, the material forming the redistribution layer 50 may include a photosensitive material. In the step of removing the overlapping portion, the overlapping portion may be removed by exposing and developing the redistribution layer 50. In this case, even if the overlapping portion in the redistribution layer 50 has a complex shape or a fine shape, the overlapping portion can be easily removed.

[0106] The method for manufacturing the semiconductor device 1 of this embodiment further includes a step of disposing an underfill 4 between the plurality of semiconductor elements 2 and the main surface 60a before disposing the sealing material 80. In this case, the semiconductor elements 2 are more stably fixed to the interposer 60 by the underfill 4.

[0107] In the method for manufacturing the semiconductor device 1 of the present embodiment, in the step of disposing the sealing material 80, the sealing material 80 is disposed so as to cover the side surface 2c and the upper surface 2a of each semiconductor element 2, and the method for manufacturing the semiconductor device 1 further includes a step of grinding the sealing material 80 so that the upper surface 2a of each semiconductor element 2 is exposed from the sealing material 80. In this case, the side surface 2c of the semiconductor element 2 is covered by the sealing material 80, so that the semiconductor element 2 can be protected. In addition, the upper surface 2a of the semiconductor element 2 is exposed from the sealing material 8, so that the heat dissipation of the semiconductor element 2 can be improved.

[0108] In the method for manufacturing the semiconductor device 1 of the present embodiment, the step of preparing the structure 100 may include a step of forming at least two parallel grooves 61a by cutting the interposer 60 using at least two blades 70. In this case, the step of forming the parallel grooves 61a in the interposer can be performed more quickly, and the manufacturing efficiency of the semiconductor device 1 can be further improved.

[0109] In the method for manufacturing the semiconductor device 1 of the present embodiment, in the step of obtaining a plurality of semiconductor devices 1, the region including the sealing material 80b is cut along the groove portion 61 using the blade 75. In this case, the region including the sealing material 80b can be cut more reliably.

[0110] In the manufacturing method of the semiconductor device 1 of the present embodiment, the process of preparing the structure 100 includes the process of forming a plurality of groove portions 61 by cutting the interposer 60 using a blade 70. In addition, the particle size of the abrasive grains of the blade 70 used for cutting the interposer 60 in the process of forming the groove portions 61 is larger than the particle size of the abrasive grains of the blade 75 used for cutting the region including the sealing material 80b in the process of obtaining a plurality of semiconductor devices 1. In this case, the groove portion 61 can be formed more reliably with respect to the interposer 60 using the blade 70. In addition, the groove portion 61 formed in the interposer 60 can be set as a groove having a fine cutting surface. In addition, the interposer 60 and the sealing material 80 can be cut or cut by a blade having abrasive grains suitable for their respective materials.

[0111] In the method for manufacturing the semiconductor device 1 of the present embodiment, the particle size of the abrasive grains of the blade 70 for cutting the interposer 60 in the step of forming the groove portion 61 may be #2000 to #4000. The particle size of the abrasive grains of the blade 75 for cutting the sealing material 80b and the like in the step of obtaining a plurality of semiconductor devices 1 may be #320 to #600. In this case, the interposer 60 and the sealing material 80 can be cut or cut by a blade having abrasive grains suitable for the respective materials.

[0112] In the structure 100 according to the present embodiment, a plurality of grooves 61 are formed in the interposer 60 to divide the main surface 60a into a plurality of setting areas 65. When the semiconductor device 1 is manufactured by the above-mentioned manufacturing method using the structure 100, the structure 100 can be singulated by cutting the sealing material 80b and the like arranged in the grooves 61 without cutting the main body of the interposer 60 as described above. Therefore, when the structure 100 is singulated, for example, a blade for cutting the interposer 60 is not required except for the blade 75 for cutting the sealing material 80. Thus, the manufacturing efficiency of the semiconductor device 1 can be improved. In addition, in the structure 100, a portion of the interposer 60 (convex portion 61b) remains between the two parallel grooves 61a, but the portion of the interposer does not constitute the semiconductor device 1 to be manufactured, so there is no problem even if the blade for cutting the interposer 60 is not used during singulation. Furthermore, when the groove portion 61 is formed in the interposer 60, if a groove having a width corresponding to the cutting width during singulation is formed, it may take time to form the groove portion 61. However, according to the structure 100, the time required to form the groove portion 61 can be shortened by narrowing the width W1 of each groove 61a in the groove portion 61. Therefore, according to the structure 100, the manufacturing efficiency of the semiconductor device 1 can be improved in this regard as well.

[0113] In the structure 100 of the present embodiment, each groove 61a of the plurality of groove portions 61 may have a depth A1 of 10% to 60% of the thickness T1 of the interposer 60. When the semiconductor device 1 is manufactured by the above-mentioned manufacturing method using the structure 100, the sealing material 80 can be easily exposed in the step of grinding the interposer 60, and cracks are not easily generated in the interposer 60 in the manufacturing step of the semiconductor device 1. Thus, the manufacturing efficiency of the semiconductor device 1 can be improved.

[0114] In the structure 100 of the present embodiment, each groove 61a of the plurality of groove portions 61 may have a depth A1 of 70 μm to 470 μm. When the semiconductor device 1 is manufactured by the above-mentioned manufacturing method using the structure 100, the sealing material 80 can be easily exposed in the step of grinding the intermediate layer 60, and cracks are not easily generated in the intermediate layer 60 in the manufacturing step of the semiconductor device 1. Thus, the manufacturing efficiency of the semiconductor device 1 can be improved.

[0115] In the structure 100 of the present embodiment, the width of each of the parallel grooves 61a can be 20 μm to 50 μm. In this case, as described above, the amount of chips generated when forming the groove portion 61 is reduced, and contaminants can be prevented from adhering to the semiconductor device 1. As a result, the defect rate in the semiconductor device 1 can be reduced, and the manufacturing efficiency of the semiconductor device 1 can be further improved.

[0116] In the structure 100 of this embodiment, convex portions 61b may be provided between the parallel grooves 61a, and the width of the convex portions 61b may be 100 μm to 200 μm. In this case, as described above, the cutting during singulation can be performed quickly, thereby further improving the manufacturing efficiency of the semiconductor device.

[0117] In the structure 100 of the present embodiment, the plurality of groove portions 61 are formed in a lattice shape including a plurality of first groove portions 62 along a first direction D1 and a plurality of second groove portions 63 along a second direction D2 perpendicular to the first direction. The plurality of first groove portions 62 may each have two grooves 62a arranged side by side, and the plurality of second groove portions 63 may each have two grooves 63a arranged side by side. The interval between the first groove portions 62 adjacent to each other may be 10 mm to 100 mm. The interval between the second groove portions 63 adjacent to each other may be 20 mm to 100 mm. When the semiconductor device 1 is manufactured by the above-mentioned manufacturing method using the structure 100, a semiconductor device 1 with high versatility having a size that can be mounted on a general electronic component can be manufactured.

[0118] [Second embodiment]

[0119] Next, refer to Figure 14 to Figure 17 , a semiconductor device and a method for manufacturing the same according to a second embodiment are described. Fig.14 It is a cross-sectional view schematically showing an example of a semiconductor device 201 manufactured by the manufacturing method according to the second embodiment. Figure 15 to Figure 17 2 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to the second embodiment. The semiconductor device 201 according to the second embodiment is, for example, a semiconductor package having a CoWoS (Chip on Wafer on Substrate) structure, and is different from the first embodiment in that a plurality of semiconductor elements are mounted on each semiconductor device. Since other structures are the same, the description is sometimes omitted below. Fig.14 As shown, the semiconductor device 201 includes a plurality of semiconductor elements 202 ( 202 a , 202 b ), bumps 3 , underfills 4 , a redistribution layer 5 , an interposer 6 , bumps 7 , and a sealing material 8 .

[0120] The semiconductor element 202 is, for example, a semiconductor chip such as a processor or a memory. The processor may be, for example, a processor unit such as a GPU (Graphics Processing Unit) or a CPU (Central Processing Unit). The memory may be, for example, a memory unit such as an HBM (High Bandwidth Memory). Fig.14 In the example shown, for example, one semiconductor element 202a is a processor unit, and another semiconductor element 202b is a memory. The semiconductor element 202b may be a memory unit in which a plurality of memories are stacked. In the semiconductor device 201 according to the second embodiment, since a plurality of semiconductor elements 202 are provided, a sealing material 8 is also inserted between each semiconductor element 202. Furthermore, each semiconductor element 202a, 202b may be electrically connected to each other through a built-in chip or the like disposed in the redistribution layer 5 or in the redistribution layer 5.

[0121] Next, refer to Figure 15 to Figure 17 , a method for manufacturing the semiconductor device 201 is described. Step (a) is to prepare Fig.16 In step (a), first, as shown in FIG. Fig.15 As shown in (a), an interposer 60 is prepared. The interposer 60 is singulated in a subsequent process to become the interposer 6 of the semiconductor device 201. A redistribution layer 50 is formed on the main surface 60a of the interposer 60. The redistribution layer 50 is singulated in a subsequent process to become the redistribution layer 5 of the semiconductor device 201. The redistribution layer 50 is formed over the entire main surface 60a. The redistribution layer 50 has a layered insulating portion 51 and wiring (not shown) formed in the insulating portion 51.

[0122] Then, if Fig.15 As shown in (b), a portion of the redistribution layer 50 is removed. By removing a portion of the redistribution layer 50, a plurality of openings 52 are formed on the redistribution layer 50. In this embodiment, after a portion of the redistribution layer 50 is removed, a plurality of groove portions 61 (at least two grooves 61a) are formed on the interposer 60 (see Fig.15 (c)). The method of removing a portion of the redistribution layer 50 is the same as that of the first embodiment.

[0123] Then, if Fig.15As shown in (c) of the embodiment, a plurality of groove portions 61 are formed on the interposer 60. Also, similarly to the first embodiment, each groove portion 61 has two grooves 61a extending from the main surface 60a of the interposer 60 toward the main surface 60b, and the two grooves 61a extend side by side with each other, and a convex portion 61b is formed between the two grooves 61a. Each groove 61a constituting each groove portion 61 is formed in a slit shape and opens on the main surface 60a. Similar to the first embodiment, the depth of the groove portion 61 (groove 61a) may be, for example, 70 μm to 470 μm, 100 μm to 400 μm, or 200 μm to 300 μm. The depth of the groove portion 61 (groove 61a) relative to the thickness of the interposer 60 may be, for example, 10% to 60%, 20% to 50%, or 30% to 40%. The depth of the groove portion 61 may be greater than the thickness of the interposer 6 of the semiconductor device 201 finally obtained, for example, 30 μm to 50 μm. The aspect ratio of the width of the groove 61 a to the depth of the groove 61 a (depth:width) may be, for example, 3.5:1 to 8:1.

[0124] Also, similarly to the first embodiment, the plurality of grooves 61 divide the main surface 60a into a plurality of arrangement regions 65. When viewed from the thickness direction of the interposer 60, each arrangement region 65 has a rectangular shape. Fig.15 As shown in (c), the interposer 60 having the groove portion 61 formed therein has a plate-shaped first portion 66 and a plurality of second portions 67 formed on the first portion 66. The second portion 67 is in a table shape. The top surface of the second portion 67 corresponds to the setting area 65. In addition, similarly to the first embodiment, each groove 61a of the groove portion 61 is formed using, for example, two blades 70.

[0125] Then, if Fig.16 As shown in (a), a plurality of semiconductor elements 202 are provided on each setting area 65. In the second embodiment, two semiconductor elements 202 are provided on each setting area 65. As an example, a semiconductor element 202a as a processor (e.g., a GPU) and a semiconductor element 202b as a memory (e.g., an HBM) are provided on each setting area 65. When a plurality of memories are provided, the memories may be stacked and arranged three-dimensionally.

[0126] [Step (b)]

[0127] like Fig.16 As shown in (b) of FIG. 8 , step (b) is a step of disposing an underfill 4 between each of the semiconductor elements 202 a and 202 b and the redistribution layer 50 .

[0128] [Step (c)]

[0129] Step (c) is a step of sealing each semiconductor element 202a, 202b with a sealing material 80, and placing the sealing material 80b at least in the groove portion 61 (each groove 61a). Fig.16 As shown in (c), the plurality of semiconductor elements 202a, 202b are sealed with a sealing material 80 so that the sealing material 80b is arranged (filled) in the entire groove portion 61. The sealing material 80 is also arranged inside the opening 52 of the redistribution layer 50 and between the semiconductor elements 202a, 202b. The sealing material 80 is arranged throughout the entire interposer 60 to cover the semiconductor elements 202a, 202b, the bottom filler 4 and the redistribution layer 50. The sealing material 80 is arranged to cover the upper surface and side surfaces of each semiconductor element 202a, 202b.

[0130] [Step (d)]

[0131] Step (d) is a step of polishing the sealing material 80 so that the upper surfaces of the semiconductor elements 202a and 202b are exposed from the sealing material 80. Fig.17 As shown in (a), the sealing material 80 has a surface 80a on the side opposite to the interposer 60. In step (d), the sealing material 80 is thinned by grinding the sealing material 80 from the surface 80a toward the interposer 60. In this embodiment, as shown in FIG. Fig.17 As shown in (a) of FIG. 8 , the sealing material 80 is polished until the surface 80 a and the upper surfaces of the semiconductor elements 202 a and 202 b are flush with each other. As a result, the upper surfaces of the semiconductor elements 202 a and 202 b are exposed from the sealing material 80 .

[0132] In this embodiment, after step (d) is completed, the orientation of the interposer 60 is reversed. In the steps up to step (d), the main surface 60a of the interposer 60 is located above the main surface 60b in the vertical direction (see Fig.17 (a)). On the other hand, in the steps after step (e), the interposer 60 is arranged so that the main surface 60a is located below the main surface 60b in the vertical direction.

[0133] [Step (e)]

[0134] Step (e) is a step of grinding the interposer 60 to expose the sealing material 80b disposed in the two grooves 61a constituting each groove portion 61. In step (e), the interposer 60 is thinned by grinding the interposer 60 from the main surface 60b toward the main surface 60a. If the interposer 60 is ground until the sealing material 80b disposed in the groove portion 61 is exposed, Fig.17As shown in (b), the first portion 66 of the interposer 60 is removed, and a plurality of second portions 67 remain. When viewed from the thickness direction of the interposer 60, only the convex portion 61b between the sealing material 80 (80b) and the groove 61a exists between adjacent second portions 67.

[0135] Then, if Fig.17 As shown in (c) of FIG. 1 , bumps 7 are arranged on the interposer 60 . In the present embodiment, the bumps 7 are arranged on the surface of each second portion 67 on the opposite side to the redistribution layer 50 . The bumps 7 are electrically connected to the wiring of the interposer 60 .

[0136] [Step (f)]

[0137] Similar to the first embodiment, step (f) is a step of cutting the sealing material 80b in the two grooves 61a and the convex portion 61b between the grooves 61a along each groove portion 61, so that the structure 200 is singulated into a plurality of setting areas 65, thereby obtaining a plurality of semiconductor devices 201. Fig.17 As shown in (b) and (c) of FIG. 1 , in step (f), the sealing material 80b and the convex portion 61b are cut in the thickness direction of the interposer 60 by the blade 75. Specifically, the sealing material 80b arranged in the groove 61a, the convex portion 61b between the grooves 61a, the sealing material 80 arranged in the opening 52 of the redistribution layer 50, and the portion of the sealing material 80 arranged between the plurality of semiconductor elements 2 are cut together. Thus, the structure 200 is singulated according to the plurality of setting areas 65. As described above, when viewed from the thickness direction of the interposer 60, the sealing materials 80 and 80b exist between the adjacent second portions 67. Therefore, when the sealing materials 80 and 80b are cut in step (f), the main body of the interposer 60 (except the portion of the convex portion 61b) is not cut. In addition, the sealing material 80b and the convex portion 61b in the groove 61a are cut, for example, using a cutting blade rotating at a high speed. Thus, the structure 200 is singulated to obtain a plurality of semiconductor devices 201 (see Fig.14 The interposer 60 after singulation corresponds to the interposer 6 of the semiconductor device 201, and the redistribution layer 50 after singulation corresponds to the redistribution layer 5 of the semiconductor device 201. The manufacturing process of the semiconductor device 201 is completed as described above.

[0138] As described above, similarly to the first embodiment, according to the method for manufacturing the semiconductor device 201 according to the second embodiment, the structure 200 can be singulated by cutting the region including the sealing material 80b arranged in each groove portion 61 without cutting the main body of the interposer 60. Therefore, when the structure 200 is singulated, for example, a blade for cutting the interposer 60 is not required in addition to a blade for cutting the sealing material 80b. Thus, for example, the labor of replacing the blade is not required, and the manufacturing efficiency of the semiconductor device 201 can be improved. As for other effects, the same effects as those of the first embodiment can also be exerted.

[0139] As mentioned above, although embodiment of this invention is described in detail, this invention is not limited to the said embodiment.

[0140] The insulating portion 51 of the redistribution layer 50 may be formed of an inorganic material. The inorganic material forming the insulating portion 51 may be silicon dioxide (SiO 2 ), silicon nitride (SiN) or silicon oxynitride (SiON). In the case where the insulating portion 51 is formed of an inorganic material, when the overlapping portion of the redistribution layer 50 with the portion 61A is removed in step (a) (refer to Figure 3 ), the overlapping portion can be removed by cutting the redistribution layer 50 with a blade. The overlapping portion in the redistribution layer 50 is removed and the groove portion 61 is formed (refer to Figure 4 ) means that the same blade can be used to perform both operations.

[0141] In the step (a) of preparing the structure 100 or 200 , each groove portion 61 may be formed of more than two parallel grooves 61 a , for example, three parallel grooves 61 a .

[0142] In the manufacturing process of the semiconductor device 1 , 201 , the step (b) may be omitted. That is, the underfill material 4 may not be disposed between the plurality of semiconductor elements 2 , 202 and the main surface 60 a .

[0143] In the manufacturing process of the semiconductor device 1, 201, step (d) may be omitted. That is, the sealing material 80 may be polished without being thinned so that the upper surface 2a of each semiconductor element 2, 202 is exposed from the sealing material 80. Specifically, the sealing material 80 may not be polished at all, or may be polished to such an extent that the upper surface 2a of the semiconductor element 2, 202 is not exposed from the sealing material 80.

[0144] The depth A1 of the groove portion 61 (groove 61a) formed on the interposer 60 is not limited. The depth A1 may be less than 10% or greater than 60% of the thickness T1 of the interposer 60. The depth A1 may be less than 70 μm or greater than 470 μm.

[0145] There is no limitation on the orientation of semiconductor devices 1 and 201 when they are mounted on other electronic components. That is, semiconductor device 1 can be mounted so that upper surface 2a of semiconductor element 2 and 202 is located above lower surface 2b in the vertical direction, and semiconductor device 1 and 201 can be mounted so that upper surface 2a is located below lower surface 2b in the vertical direction.

[0146] Explanation of symbols

[0147] 1. 201-semiconductor device, 2. 202, 202a, 202b-semiconductor element, 2a-upper surface, 2c-side surface, 3-bump, 4-bottom filler, 5. 50-rewiring layer, 6. 60-intermediate layer, 8. 80, 80b-sealing material, 60a-main surface (first main surface), 60b-main surface (second main surface), 61-groove portion, 61A-portion (forming a predetermined portion), 61a-groove, 61b-convex portion, 62-first groove portion, 62a-groove, 62b-convex portion, 63-second groove portion, 63a-groove, 63b-convex portion, 65-setting area, 70-blade (first blade), 75-blade (second blade), 100, 200-structure.

Claims

1. A method for manufacturing a semiconductor device, comprising: A step of preparing a structure having an interposer including a first main surface and a second main surface opposite to the first main surface and having a plurality of groove portions for dividing the first main surface into a plurality of setting regions, and a plurality of semiconductor elements at least one each being provided on each of the setting regions, wherein each of the groove portions includes at least two grooves arranged side by side; A step of sealing at least a portion of each of the plurality of semiconductor elements with a sealing material so that the sealing material is disposed at least in the plurality of groove portions; a step of grinding the interposer from the second main surface toward the first main surface so as to expose the sealing material disposed in the plurality of groove portions; and The step of cutting the sealing material along the groove portions to separate the structure into pieces for each of the plurality of installation regions, thereby obtaining a plurality of semiconductor devices.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The step of preparing the structure includes the step of forming the plurality of grooves, wherein the plurality of grooves have a depth of 10% to 60% of a thickness of the interposer before grinding.

3. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein: The step of preparing the structure includes the step of forming the plurality of groove portions having a depth of 70 μm to 470 μm.

4. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein: The width of each of the parallel grooves is 20 μm to 50 μm.

5. The method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein: The step of preparing the structure includes forming each of the groove portions so that a convex portion remains between the parallel grooves. In the step of obtaining a plurality of semiconductor devices, the sealing material disposed in each of the groove portions is cut together with the convex portion.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: The width of the convex portion is 100 μm to 200 μm.

7. The method for manufacturing a semiconductor device according to any one of claims 1 to 6, wherein: The step of preparing the structure comprises: forming a redistribution layer on the first main surface before forming the plurality of groove portions; a step of removing a portion of the redistribution layer that overlaps with a portion where the plurality of grooves are to be formed; and A step of forming the plurality of grooves on the interposer.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: The material forming the rewiring layer includes a photosensitive material. In the step of removing the overlapping portion, the overlapping portion is removed by exposing and developing the redistribution layer.

9. The method for manufacturing a semiconductor device according to any one of claims 1 to 8, wherein: Before the step of disposing the sealing material, the method further includes the step of disposing an underfill between the plurality of semiconductor elements and the first main surface.

10. The method for manufacturing a semiconductor device according to any one of claims 1 to 9, wherein: In the sealing step, the sealing material is arranged to cover the side surfaces and the upper surface of each of the semiconductor elements. The method for manufacturing a semiconductor device further includes a step of grinding the sealing material so that the upper surface of each of the semiconductor elements is exposed from the sealing material.

11. The method for manufacturing a semiconductor device according to any one of claims 1 to 10, wherein: The step of preparing the structure includes: a step of simultaneously forming the at least two parallel grooves by cutting the intermediate layer using at least two first blades; or a step of sequentially forming the at least two parallel grooves by cutting the intermediate layer using one first blade.

12. The method for manufacturing a semiconductor device according to any one of claims 1 to 11, wherein: In the step of obtaining a plurality of semiconductor devices, the sealing material is cut along the groove portion using a second blade.

13. The method for manufacturing a semiconductor device according to claim 12, wherein: The step of preparing the structure includes the step of cutting the interposer using a first blade to form the plurality of grooves. The particle size of the abrasive grains of the first blade is larger than the particle size of the abrasive grains of the second blade.

14. The method for manufacturing a semiconductor device according to claim 13, wherein: The abrasive grains of the first blade have a particle size of #2000 to #4000. The abrasive grains of the second blade have a grain size of #320 to #600.

15. A structure comprising: an interposer layer, comprising a first main surface and a second main surface opposite to the first main surface; and A plurality of semiconductor elements are arranged on the first main surface, A plurality of grooves are formed on the interposer to divide the first main surface into a plurality of setting areas. Each of the groove portions comprises at least two grooves arranged side by side, At least one of the plurality of semiconductor elements is disposed on each of the installation regions.

16. The structure according to claim 15, wherein: The plurality of groove portions have a depth of 10% to 60% with respect to a thickness of the interposer.

17. The structure according to claim 15 or 16, wherein: The plurality of groove portions have a depth of 70 μm to 470 μm.

18. A structure according to any one of claims 15 to 17, wherein The width of each of the parallel grooves is 20 μm to 50 μm.

19. A structure according to any one of claims 15 to 18, wherein A convex portion is provided between the parallel grooves, The width of the convex portion is 100 μm to 200 μm.

20. A structure according to any one of claims 15 to 19, wherein The plurality of grooves are formed in a lattice shape including a plurality of first grooves along a first direction and a plurality of second grooves along a second direction intersecting the first direction. The plurality of first groove portions each have at least two grooves arranged side by side, and the plurality of second groove portions each have at least two grooves arranged side by side, The interval between the adjacent first groove portions is 10 mm to 100 mm. The interval between the adjacent second groove portions is 20 mm to 100 mm.

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