Semiconductor device, power conversion device, and method for manufacturing semiconductor device

Abstract

The technology disclosed in the present specification is a technology for improving the reliability of a semiconductor device. A semiconductor device according to the technology disclosed in the specification of the present application is provided with: a semiconductor layer; a first electrode layer covering a portion of an upper surface of the semiconductor layer; and an insulating film covering another part of the upper surface of the semiconductor layer and a part of the upper surface of the first electrode layer. The arithmetic mean roughness of the upper surface of the insulating film is smaller than the arithmetic mean roughness of the interface between the insulating film and the first electrode layer.

Description

Technical Field

[0001] The technology disclosed in this application specification relates to a technology for improving the reliability of a semiconductor device. Background Art

[0002] For example, the semiconductor devices shown in Patent Document 1, especially the insulated gate bipolar transistor (IGBT), metal-oxide-semiconductor field-effect transistor (MOSFET), or Schottky barrier diode (SBD) and other power semiconductor devices are widely used as inverter circuits of industrial motors or automotive motors, power supply devices of large-capacity servers, or semiconductor switches such as uninterruptible power supply devices. In recent years, the miniaturization of semiconductor devices has been achieved by increasing the current density of semiconductor devices, thereby promoting the reduction of the manufacturing cost of semiconductor devices.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2017-50358 Summary of the invention

[0006] Problems to be solved by the invention

[0007] If the current density of the semiconductor device increases, the temperature of the components when in operation also increases, so the temperature difference with the non-operation increases. Therefore, due to the stress received from the electrode layer or the molded resin surrounding the protective insulating film constituting the semiconductor device during thermal expansion and thermal contraction due to the difference in linear expansion coefficients of the various components, peeling or cracks may occur on the protective insulating film for ensuring insulation performance from the outside of the semiconductor device. In this case, the insulation performance of the semiconductor device becomes insufficient, and there is a problem that the reliability of the semiconductor device is impaired.

[0008] The technology disclosed in this application specification has been accomplished in view of the above-described problems, and is a technology for improving the reliability of a semiconductor device.

[0009] Means for solving problems

[0010] A semiconductor device as the first mode of the technology disclosed in the present application specification comprises: a semiconductor layer; a first electrode layer, which covers a portion of the upper surface of the semiconductor layer; and an insulating film, which covers another portion of the upper surface of the semiconductor layer and a portion of the upper surface of the first electrode layer, and the arithmetic mean roughness of the upper surface of the insulating film is smaller than the arithmetic mean roughness of the interface between the insulating film and the first electrode layer.

[0011] Effects of the Invention

[0012] According to at least the first aspect of the technology disclosed in the present specification, the connection between the lower portion of the protective insulating film and the constituent element can be made stronger than the connection between the upper portion of the protective insulating film and the constituent element, thereby suppressing the peeling of the protective insulating film during operation, etc. According to such a structure, the reliability of the semiconductor device can be improved.

[0013] In addition, the objects, features, aspects, and advantages associated with the technology disclosed in the present application specification will become more apparent from the following detailed description and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 A diagram schematically showing an example of the structure of a semiconductor device manufactured by the manufacturing method described in the embodiment.

[0015] Figure 2 A diagram schematically showing an example of the structure of a semiconductor device manufactured by the manufacturing method described in the embodiment.

[0016] Figure 3 A diagram schematically showing an example of the structure of a semiconductor device manufactured by the manufacturing method described in the embodiment.

[0017] Figure 4 1 is a flowchart showing an example of a manufacturing process of a SiC-SBD according to the embodiment.

[0018] Figure 5 It is a cross-sectional view showing an example of a manufacturing process of the SiC-SBD according to the embodiment.

[0019] Figure 6 It is a cross-sectional view showing an example of a manufacturing process of the SiC-SBD according to the embodiment.

[0020] Figure 7 It is a cross-sectional view showing an example of a manufacturing process of the SiC-SBD according to the embodiment.

[0021] Figure 8 It is a cross-sectional view showing an example of a manufacturing process of the SiC-SBD according to the embodiment.

[0022] Fig. 9 It is a cross-sectional view showing an example of a manufacturing process of the SiC-SBD according to the embodiment.

[0023] Fig.10 It is a cross-sectional view showing an example of a manufacturing process of the SiC-SBD according to the embodiment.

[0024] Fig.11 It is a cross-sectional view showing an example of a manufacturing process of the SiC-SBD according to the embodiment.

[0025] Fig.12 It is a cross-sectional view showing an example of a manufacturing process of the SiC-SBD according to the embodiment.

[0026] Fig.13 This is a diagram showing an enlarged structure of a front electrode and a protective insulating film in the semiconductor device according to the embodiment.

[0027] Fig.14 This is a diagram showing the definition of arithmetic mean roughness.

[0028] Fig.15 This is a graph showing the relationship between the ratio of the arithmetic mean roughness of the upper and lower surfaces of the protective insulating film and the peeling rate of the protective insulating film after performing a power cycle test 100,000 times.

[0029] Fig.16 This is a graph showing the relationship between the vertex angle and the crack generation rate when the ratio of the arithmetic mean roughness of the upper and lower surfaces of the protective insulating film is set to 0.7, focusing on the vertex having the smallest angle among the vertices formed at the end of the upper surface of the protective insulating film.

[0030] Fig.17 A diagram schematically showing an example of the structure of a semiconductor device manufactured by the manufacturing method described in the embodiment.

[0031] Fig.18 A diagram schematically showing an example of the structure of a semiconductor device manufactured by the manufacturing method described in the embodiment.

[0032] Fig.19 A diagram schematically showing an example of the structure of a semiconductor device manufactured by the manufacturing method described in the embodiment.

[0033] Fig. 20 1 is a flowchart showing an example of a manufacturing process of a SiC-SBD according to the embodiment.

[0034] Fig.21 It means it is completed Fig. 20 A cross-sectional view of an example of the structure of a semiconductor device in step ST06 in FIG.

[0035] Fig. 22 This is a flowchart showing an example of a plating pretreatment and a plating treatment.

[0036] Fig.23 : is a flowchart showing a modification of the zincate treatment.

[0037] Fig.24 : is a flowchart showing a modification of the zincate treatment.

[0038] Fig.25 A diagram showing an example of the structure of a semiconductor device.

[0039] Fig.26 A diagram showing an example of the structure of a semiconductor device.

[0040] Fig. 27 A diagram showing an example of the structure of a semiconductor device.

[0041] Fig.28 A diagram showing an example of the structure of a semiconductor device.

[0042] Fig.29 This is a diagram showing the relationship between the difference between the interface between the front electrode and the front electrode and the interface between the front electrode and the protective insulating film, and the defective rate after the assembly test.

[0043] Fig.30 It is a diagram schematically showing the configuration of a power conversion system to which the power conversion device according to the embodiment is applied.

[0044] Fig.31 A diagram schematically showing an example of the structure of a semiconductor device manufactured by the manufacturing method described in the embodiment.

[0045] Fig.32 A diagram schematically showing an example of the structure of a semiconductor device manufactured by the manufacturing method described in the embodiment.

[0046] Fig.33 A diagram schematically showing an example of the structure of a semiconductor device manufactured by the manufacturing method described in the embodiment. DETAILED DESCRIPTION

[0047] Hereinafter, the embodiments will be described with reference to the drawings. In the following embodiments, detailed features and the like are shown for the purpose of explaining the technology, but these are exemplifications and are not essential features as long as the embodiments can be implemented.

[0048] In addition, the drawings are schematically shown, and for the sake of convenience of explanation, the structure is appropriately omitted or simplified in the drawings. In addition, the mutual relationship between the size and position of the structures shown in different drawings is not necessarily accurately recorded and can be appropriately changed. In addition, in drawings such as top views that are not sectional views, shadows are sometimes marked to facilitate understanding of the contents of the embodiments.

[0049] In the following description, the same components are denoted by the same reference numerals and are illustrated, and their names and functions are also the same, so their detailed description may be omitted to avoid duplication.

[0050] In addition, in the description described in the specification of the present application, when a certain component is described as “having”, “including” or “having”, it is not an exclusive expression that excludes the existence of other components unless otherwise specified.

[0051] In the descriptions recorded in the specification of the present application, even when ordinal numbers such as "first" or "second" are used, these terms are used flexibly to facilitate understanding of the contents of the implementation methods, and the contents of the implementation methods are not limited to the order that can be generated by these ordinal numbers.

[0052] In addition, in the descriptions recorded in the specification of the present application, expressions such as “positive direction of the axis…” or “negative direction of the axis…” refer to the direction of the arrow along the axis… shown in the figure as the positive direction, and the direction on the side opposite to the arrow of the axis… shown in the figure as the negative direction.

[0053] In addition, in the descriptions recorded in the specification of the present application, expressions indicating an equal state, such as "same", "equal", "uniform" or "homogeneous", etc., unless otherwise specified, include situations where a state is strictly equal and situations where a difference occurs within a tolerance or a range that can achieve the same degree of functionality.

[0054] In addition, in the descriptions recorded in the specification of this application, even when terms such as "up", "down", "left", "right", "side", "bottom", "front" or "back" are used to indicate specific positions or directions, these terms are used flexibly to facilitate understanding of the contents of the implementation method and have nothing to do with the position or direction when the implementation method is actually implemented.

[0055] In addition, in the descriptions described in the specification of the present application, when it is described as "the upper surface of..." or "the lower surface of...", etc., in addition to the upper surface itself or the lower surface itself of the component being the target, it also includes a state where other components are formed on the upper surface or the lower surface of the component being the target. That is, for example, when it is described as "B is provided on the upper surface of A", it does not prevent another component "C" from being sandwiched between A and B.

[0056] <First Embodiment>

[0057] Hereinafter, a semiconductor device and a method for manufacturing the semiconductor device according to the present embodiment will be described.

[0058] <Regarding the Structure of Semiconductor Device>

[0059] Figure 1 , Figure 2 as well as Figure 3 FIG. 1 is a diagram schematically showing an example of the structure of a semiconductor device manufactured by the manufacturing method described in this embodiment. Figure 1 In the example of FIG. 1 , a SiC Schottky barrier diode (SBD) is shown.

[0060] Figure 1 This is a top view of SiC-SBD. Figure 1 As shown, a front electrode 2 is formed in a central current-carrying area, and a protective insulating film 4 is formed around the front electrode 2 to ensure insulation from the surrounding area.

[0061] Figure 2 is with Figure 1 The cross-sectional view corresponds to the A-A' section indicated by the dotted line. In a front-back conductive type power semiconductor device, the current flows along Figure 2 The Z-axis direction of the semiconductor substrate 1 is formed with a front electrode 2 on the upper surface of the semiconductor substrate 1, and a back electrode 3 on the lower surface of the semiconductor substrate 1. The front electrode 2 and the back electrode 3 are respectively wired to the outside by appropriate methods such as wires or welding. In addition, a protective insulating film 4 is provided on the periphery of the front electrode 2 to suppress poor insulation of the semiconductor device caused by discharge in the peripheral part of the chip.

[0062] Figure 3 Is Figure 2 . A front electrode 2 is formed on the upper surface of the semiconductor substrate 1, and a protective insulating film 4 is formed on the upper surface of the front electrode 2. The arithmetic mean roughness of the upper surface of the protective insulating film 4 is smaller than the arithmetic mean roughness of the interface between the protective insulating film 4 and the front electrode 2 (i.e., the lower surface of the protective insulating film 4). A plurality of vertices are provided at the upper end of the protective insulating film 4.

[0063] <Regarding the Manufacturing Equipment of Semiconductor Device>

[0064] Figure 4 : is a flowchart showing an example of a manufacturing process of a SiC-SBD according to the present embodiment. Figures 5 to 12 1 is a cross-sectional view showing an example of a manufacturing process of a SiC-SBD according to the present embodiment. Figures 5 to 12 , the manufacturing process of SiC-SBD is described in detail.

[0065] like Figure 5 As shown in FIG. 1 , after a drift layer 6 composed of n-type SiC is formed as a first epitaxial film on a first main surface (hereinafter referred to as the front surface) of an n-type SiC substrate 5 located on the positive side of the Z axis, a drift layer 7 is formed as a second epitaxial film (corresponding to the first epitaxial film) by an epitaxial crystal growth method at a growth temperature lower than the growth temperature of the drift layer 6 in a manner in contact with the upper surface of the drift layer 6 (corresponding to the second epitaxial film). Figure 4 Step ST01).

[0066] Next, if Figure 6 As shown, an interlayer insulating film 8 is formed on the upper surface of the drift layer 7 by a deposition method such as thermal oxidation or chemical vapor deposition.

[0067] Afterwards, if Figure 7 As shown, after a mask composed of a resist or the like is formed using photolithography (not shown here), the interlayer insulating film 8 in unnecessary areas is removed by dry etching using plasma or wet etching using a chemical solution, and then the mask is removed by plasma ashing or wet processing.

[0068] In addition, in the drift layer 7 opposite to the interlayer insulating film 8, in order to obtain the desired withstand voltage of the SiC-SBD, boron (B) or aluminum (Al) is used as a p-type impurity, and phosphorus (P) or nitrogen (N) is used as an n-type impurity, and ion implantation and activation are appropriately performed to form an impurity layer.

[0069] Next, after appropriate wet treatment including hydrofluoric acid or cleaning with a mixture of ammonia and hydrogen peroxide, a mixture of sulfuric acid and hydrogen peroxide, or a mixture of hydrochloric acid and hydrogen peroxide, a Schottky electrode layer 9 (corresponding to Figure 4 Step ST02).

[0070] At this time, titanium (Ti), nickel (Ni), iridium (Ir) or platinum (Pt) etc. can be appropriately selected as the electrode material. After that, the remaining electrode material formed in the peripheral area is removed by patterning based on photolithography and etching using plasma or liquid medicine. In order to reliably obtain electrical connection between the drift layer 7 and the Schottky electrode layer 9, heat treatment is performed as needed. Thus, the following is obtained: Figure 8 The cross-sectional structure is shown.

[0071] Then, if Fig. 9 As shown, aluminum, an aluminum alloy composed of aluminum and silicon, or nickel is used to form the front electrode 2 by sputtering or evaporation. Then, patterning is performed by photolithography and etching is performed by plasma or liquid medicine. Then, for example, by heating at a temperature of 150°C to 400°C for more than 15 minutes, a concave-convex (corresponding to the convex portion) can be formed on the front surface of the front electrode 2. Figure 4 Step ST03). The front electrode 2 is formed on a part of the upper surface of the drift layer 6 and the drift layer 7 via the Schottky electrode layer 9, the interlayer insulating film 8, etc.

[0072] Afterwards, if Fig.10 As shown, a protective insulating film 4 is formed. As the material of the protective insulating film 4, polyimide or silicone resin is preferably used. By using spin coating, photolithography and etching technology or inkjet coating technology of these materials, a protective insulating film 4 (corresponding to Figure 4 Step ST04). The protective insulating film 4 covers the portion of the upper surface of the drift layer 7 that is not covered by the front electrode 2. In addition, the protective insulating film 4 covers a portion of the upper surface of the front electrode 2.

[0073] After forming the protective insulating film 4, a plurality of vertices are formed on the upper surface of the protective insulating film 4 by surface treatment using plasma containing oxygen and argon. At this time, if a plurality of vertices are also formed on the upper surface of the protective insulating film 4 on the outer peripheral side of the semiconductor device, the reliability is further improved.

[0074] As a method of forming a plurality of vertices on the upper surface (upper end) of the protective insulating film 4, an appropriate processing method can be appropriately selected, such as repeating a coating technique based on inkjet multiple times and then applying a heat treatment at 250°C or higher.

[0075] Next, a heat treatment is performed at a temperature of, for example, 200° C. to 400° C., more preferably, 250° C. to 380° C., so that the slope of the protective insulating film 4 becomes as described below. Fig.13 The shape on the arc is shown as an example. In addition, the heat treatment after forming the front electrode 2 described above may also be used as the heat treatment after forming the protective insulating film 4.

[0076] Afterwards, if Fig.11 As shown, in order to reduce the loss when the power is turned on, for example, by machining using a grinding tool composed of aluminum oxide abrasive grains or diamond abrasive grains, the SiC substrate 5 is thinned (thinned) from the lower surface side of the SiC substrate 5 (corresponding to Figure 4Step ST05). In addition, the thinning (thinning) of the SiC substrate 5 can be omitted as needed.

[0077] Then, a back electrode 3 (corresponding to the Figure 4 Step ST06). For the back electrode 3, during welding, in order to prevent oxidation of the electrode material, an anti-oxidation film composed of gold, platinum, silver or a silver alloy containing palladium may be formed on the outermost surface of the back electrode 3.

[0078] Afterwards, a plurality of semiconductor devices formed on the semiconductor wafer are singulated using a dicing device to obtain Figure 1 , Figure 2 and Figure 3 The semiconductor device shown as an example.

[0079] Moreover, if Fig.12 As illustrated, the semiconductor device 10 manufactured as described above is sealed with a mold resin 14 after the upper and lower surfaces of the semiconductor device 10 are connected to the lead frame 12 using solder 11 and wires 13, thereby completing a semiconductor module.

[0080] Fig.13 2 is a diagram showing an enlarged structure of the front electrode 2 and the protective insulating film 4 of the semiconductor device 10 in the present embodiment. Fig.14 is a diagram showing the definition of arithmetic mean roughness. Fig.14 As shown, according to the definition of surface roughness (JIS B 0601: 1994, JIS B 0031: 1994), the arithmetic mean roughness Ra can be obtained by extracting only a reference length in the direction of its average line 401 from the roughness curve 400, setting the direction of the average line of the extracted part as the X-axis, and setting the direction of the vertical magnification as the Y-axis, using the formula in the figure.

[0081] The inventors used an atomic force microscope (AFM) SPM-9600 manufactured by Shimadzu Corporation to perform a line scan of 1 mm, and after obtaining the above-mentioned roughness curve 400, calculated the arithmetic mean roughness Ra. In addition, when calculating the arithmetic mean roughness Ra, it is not limited to the above-mentioned method, and any method such as a stylus-type step difference / surface roughness meter or a laser microscope that can measure in a non-contact manner can be selected.

[0082] exist Fig.13 In the embodiment, the arithmetic mean roughness of the upper surface of the protective insulating film 4 is smaller than the arithmetic mean roughness of the interface between the protective insulating film 4 and the front electrode 2 (ie, the lower surface of the protective insulating film 4). Fig.13In the embodiment, a plurality of protrusions 2 a are formed on the upper surface of the front electrode 2 , which is one reason why the arithmetic mean roughness of the interface between the protective insulating film 4 and the front electrode 2 increases.

[0083] In addition, Fig.13 In the embodiment, a plurality of vertices are formed at the end of the upper surface of the protective insulating film 4. Specifically, the end of the upper surface of the protective insulating film 4 is an inclined surface, and the vertex formed at the upper end of the inclined surface has an obtuse angle θ1, and the vertex formed at the lower end of the inclined surface has an obtuse angle θ2.

[0084] The ridgeline 4a of the side surface of the protective insulating film 4 is concave compared to a straight line extending from the end of the upper surface (specifically, the vertex formed at the lower end of the inclined surface) to the end (vertex) of the lower surface.

[0085] The inventor has Fig.12 The semiconductor module having the structure shown was subjected to a power cycle test in which the semiconductor device was repeatedly energized and de-energized.

[0086] The protective insulating film 4 receives stress caused by thermal expansion or thermal contraction from the upper surface side due to the difference in linear expansion coefficient between it and the molded resin 14 , and receives stress caused by thermal expansion or thermal contraction from the lower surface side due to the difference in linear expansion coefficient between it and the front electrode 2 .

[0087] Fig.15 Graph showing the relationship between the ratio of the arithmetic mean roughness of the upper and lower surfaces of the protective insulating film 4 and the peeling rate of the protective insulating film 4 after 100,000 power cycle tests. Fig.15 In FIG. 1 , the vertical axis represents the peeling rate of the protective insulating film 4 , and the horizontal axis represents the ratio of the arithmetic mean roughness of the upper and lower surfaces of the protective insulating film 4 (arithmetic mean roughness of the upper surface / arithmetic mean roughness of the lower surface).

[0088] according to Fig.15 By setting the ratio of the arithmetic mean roughness of the upper and lower surfaces of the protective insulating film 4 (arithmetic mean roughness of the upper surface / arithmetic mean roughness of the lower surface) to 0.9 or less, the adhesion between the protective insulating film 4 and the front electrode 2 can be made sufficient for the stress on the protective insulating film 4 from the molded resin 14. Therefore, peeling of the protective insulating film 4 can be suppressed.

[0089] When the semiconductor module subjected to the above test was opened and analyzed, it was confirmed that cracks had occurred at the sharpest corners of the protective insulating film 4 .

[0090] Fig.16This is a graph showing the relationship between the vertex angle and the crack generation rate in the above power cycle test when the ratio of the arithmetic mean roughness of the upper and lower surfaces of the protective insulating film 4 (arithmetic mean roughness of the upper surface / arithmetic mean roughness of the lower surface) is set to 0.7, focusing on the vertex with the smallest angle among the vertices formed at the end of the upper surface of the protective insulating film 4. Fig.16 In FIG. 1 , the vertical axis represents the crack generation rate of the protective insulating film 4, and the horizontal axis represents the angle [θ] of the vertex having the smallest angle among the vertices formed at the end of the upper surface of the protective insulating film 4. Fig.16 In the figure, a hollow circle mark is used to indicate the case where there is one vertex (i.e., only the vertex with the smallest angle), a black triangle mark is used to indicate the case where there are two vertices, and a black square mark is used to indicate the case where there are three vertices.

[0091] according to Fig.16 It is known that by setting the angle of the vertex formed at the end of the upper surface of the protective insulating film 4 to be greater than 90 degrees, the stress received from the molded resin 14 can be alleviated. In addition, it is known that by forming a plurality of vertices at the end of the upper surface of the protective insulating film 4, cracks generated in the protective insulating film 4 can be reduced.

[0092] In addition, the inventors have verified that Fig.13 As illustrated, if the ridgeline 4a of the side surface of the protective insulating film 4 is recessed (concave) relative to a straight line extending from the top of the upper surface toward the top of the lower surface of the protective insulating film 4, it is suitable for suppressing cracks in the protective insulating film 4.

[0093] <Second Embodiment>

[0094] In the following description, the same components as those described in the above-described embodiment are denoted by the same reference numerals, and their detailed description is appropriately omitted.

[0095] <Regarding the Structure of Semiconductor Device>

[0096] Fig.17 , Fig.18 as well as Fig.19 FIG. 1 is a diagram schematically showing an example of the structure of a semiconductor device manufactured by the manufacturing method described in this embodiment. Figure 1 In the example of FIG. 1 , a SiC Schottky barrier diode (SBD) is shown.

[0097] Fig.17 This is a top view of SiC-SBD. Fig.17As shown in FIG. 1 , a front electrode 2 is formed in the central current-carrying area, and a protective insulating film 4 is formed around the front electrode 2 to ensure insulation from the surrounding area. Figure 1 The case shown is different in that the front electrode 15 is formed to cover a part of the upper surface of the front electrode 2 .

[0098] Fig.18 is with Fig.17 The cross-sectional view corresponds to the A-A' section indicated by the dotted line. In a front-back conductive type power semiconductor device, the current flows along Fig.18 The Z-axis direction. Fig.18 In, with Figure 2 Compared with the structure shown, since the front electrode 15 is formed, the upper surface side of the power semiconductor device can be connected to the outside by using solder, and can also handle the conduction of a large current.

[0099] Fig.19 Is Fig.18 An enlarged view of the area surrounded by the dotted line. A front electrode 2 is formed on the upper surface of the semiconductor substrate 1, and a protective insulating film 4 and a front electrode 15 are formed on the upper surface of the front electrode 2. The arithmetic mean roughness of the upper surface of the protective insulating film 4 is smaller than the arithmetic mean roughness of the interface between the protective insulating film 4 and the front electrode 2. In addition, a plurality of vertices are provided at the upper end of the protective insulating film 4. In addition, the interface between the front electrode 2 and the front electrode 15 is located below the interface between the front electrode 2 and the protective insulating film 4.

[0100] <About Method of Manufacturing Semiconductor Device>

[0101] Fig. 20 : is a flowchart showing an example of a manufacturing process of a SiC-SBD according to the present embodiment. Figures 5 to 12 1 is a cross-sectional view showing an example of a manufacturing process of a SiC-SBD according to the present embodiment. Figures 5 to 12 , the manufacturing process of SiC-SBD is described in detail.

[0102] about Fig. 20 Steps ST01 to ST06 in Figure 4 The contents of steps ST01 to ST06 are the same as those of steps ST01 to ST06, so the description is omitted.

[0103] Fig.21 It means it is completed Fig. 20 A cross-sectional view of an example of the structure of a semiconductor device in step ST06 in FIG.

[0104] Next, electrodes (corresponding to Fig. 20Even if the Al or Al alloy electrode on the wafer is subjected to the conventional degreasing and pickling and then subjected to the plating process, since strong organic residues and oxide films are formed on the surface of the Al or Al alloy (hereinafter, Al or Al alloy is also referred to as Al alloy) on the wafer, metal diffusion does not occur between the Al alloy and the plated metal, and a plating layer with strong adhesion cannot be formed.

[0105] Therefore, in this process, the plating treatment of the Al alloy electrode on the wafer is carried out in the order of plasma cleaning, degreasing, pickling, zincate treatment, and plating. In addition, sufficient water washing time must be ensured between each process so that the processing liquid or residue of the previous process is not brought into the next process.

[0106] Below, refer to Fig. 22 The following is an overview of the pre-plating treatment and the plating treatment. Fig. 22 This is a flowchart showing an example of a plating pretreatment and a plating treatment.

[0107] First, a surface activation treatment (corresponding to Fig. 22 Step ST11). Here, plasma cleaning using plasma is a process for cleaning the surface of the Al alloy electrode by using plasma to oxidatively decompose or knock out organic residues that are burned on the Al alloy electrode and cannot be removed in general pre-plating treatment.

[0108] Next, degreasing and pickling (corresponding to Fig. 22 Step ST12 and step ST13). Degreasing is a process for removing light organic contamination or oxide film remaining on the surface of the Al alloy. In addition, pickling is a process for neutralizing the surface of the Al alloy and etching the surface of the Al alloy to make the surface rough, thereby improving the reactivity of the treatment solution in the subsequent process and improving the adhesion of the plating.

[0109] Next, zincate treatment (corresponding to Fig. 22 Step ST14). After that, a plating treatment is performed to form a plated film with strong adhesion. Specifically, after the electroless Ni plating treatment is performed, the electroless Au plating treatment (corresponding to Fig. 22 Step ST15 and step ST16).

[0110] Here, the zincate treatment is described. The zincate treatment refers to a treatment for removing the oxide film of Al on the surface of the Al alloy and forming a film of zinc (Zn). Specifically, when the Al alloy is immersed in an aqueous solution in which Zn is dissolved as ions, Al is dissolved as ions because Zn has a higher standard redox potential than Al. Then, through the electrons generated at this time, the Zn ions accept electrons on the surface of the Al alloy, forming a film of Zn on the surface of the Al. In addition, the oxide film of Al is also removed at this time.

[0111] Fig.23 and Fig.24 : is a flowchart showing a modification of the zincate treatment.

[0112] exist Fig.23 In the process, first, a surface activation treatment such as plasma cleaning is performed (corresponding to Fig.23 Step ST21). Then, degreasing and pickling are performed (corresponding to Fig.23 Step ST22 and step ST23).

[0113] Next, a first zincate treatment (corresponding to Fig.23 Then, zincate stripping (corresponding to step ST24) is performed. Fig.23 After step ST25), the second zincate treatment is performed again (corresponding to Fig.23 Step ST26).

[0114] After that, a plating treatment is performed to form a plated film with strong adhesion. Specifically, after the electroless Ni plating treatment is performed, the electroless Au plating treatment (corresponding to Fig.23 Step ST27 and step ST28).

[0115] exist Fig.24 In the process, first, a surface activation treatment such as plasma cleaning is performed (corresponding to Fig.24 Step ST31). Then, degreasing and pickling are performed (corresponding to Fig.24 Step ST32 and step ST33).

[0116] Next, a first zincate treatment (corresponding to Fig.24 Then, zincate stripping (corresponding to step ST34) is performed. Fig.24 After step ST35), the second zincate treatment is performed again (corresponding to step ST36). Fig.24 Step ST36). Then, after zincate stripping (corresponding to Fig.24 After step ST37), the third zincate treatment is performed again (corresponding to step ST37). Fig.24 Step ST38).

[0117] After that, a plating treatment is performed to form a plated film with strong adhesion. Specifically, after the electroless Ni plating treatment is performed, the electroless Au plating treatment (corresponding to Fig.24 Step ST39 and step ST40).

[0118] like Fig.23 as well as Fig.24 As shown in the example, after zincate treatment and zincate stripping are repeated, the Al alloy covered with Zn is immersed in concentrated nitric acid to dissolve Zn and form a thin and uniform Al oxide film on the Al surface. Then, the Al alloy is immersed in a Zn treatment solution again to cover the Al alloy surface with Zn and remove the Al oxide film.

[0119] By doing this, the oxide film on the surface of the Al alloy becomes thinner and smoother. The more times the above operation is repeated, the more uniform the Al surface becomes and the better the appearance of the plated film is. However, if productivity is considered, it is preferred to repeat the operation for 10 minutes. Fig.23 The zincate treatment shown was repeated twice, or Fig.24 The indicated zincate treatments were performed three times.

[0120] In this way, by performing zincate treatment and zincate stripping up to three times, an interface between the front electrode 2 and the front electrode 15 can be formed in such a manner that the interface is located below the interface between the front electrode 2 and the protective insulating film 4. In addition, when forming such an interface located below, it is also possible to use Fig. 22 The surface activation treatment shown (corresponding to step ST11).

[0121] Fig.25 , Fig.26 , Fig. 27 as well as Fig.28 is a diagram showing an example of the structure of a semiconductor device manufactured by the above-mentioned process. Fig. 27 Is Fig.26 Magnified view of the area surrounded by the dotted line. Fig. 27 In FIG. 1 , the interface between the protective insulating film 4 and the front electrode 2 is defined as a reference plane, and the distance to the interface between the front electrode 15 and the front electrode 2 located below the reference plane is defined as d.

[0122] Then, the inventors conducted the following semiconductor module assembly test: Fig.28 In the illustrated example, the upper surface and the lower surface of the semiconductor device 10 are respectively bonded to the lead frame 12 via solder 11 , and are further sealed with a mold resin 14 .

[0123] In the above-mentioned assembly test, the soldering step was repeated three times as an accelerated test, so that stress from the front electrode 2 , the front electrode 15 , the solder 11 or the lead frame 12 was further applied to the protective insulating film 4 .

[0124] Fig.29 This is a graph showing the relationship between the difference between the interface between the front electrode 2 and the front electrode 15 and the interface between the front electrode 2 and the protective insulating film 4 and the defective rate after the assembly test. Fig.29 In FIG. 1 , the vertical axis represents the defect rate of the semiconductor module after the assembly test, and the horizontal axis represents the difference [nm] between the interface between the front electrode 2 and the front electrode 15 and the interface between the front electrode 2 and the protective insulating film 4. Fig.29 In the figure, the negative portion of the horizontal axis indicates that the interface between the front electrode 2 and the front electrode 15 protrudes relative to the interface between the front electrode 2 and the protective insulating film 4 .

[0125] according to Fig.29 By setting the difference between the interface between the front electrode 2 and the front electrode 15 and the interface between the front electrode 2 and the protective insulating film 4 to be greater than 10 nm, the defective rate of the semiconductor module after the assembly test can be suppressed.

[0126] Furthermore, analysis of defective semiconductor modules after the above-mentioned assembly test revealed insulation failure caused by peeling of the protective insulating film 4. Therefore, by positioning the interface between the front electrode 2 and the front electrode 15 below the interface between the front electrode 2 and the protective insulating film 4, stress on the protective insulating film 4 is alleviated, and it can be said that the defective rate of the semiconductor module after the assembly test is suppressed.

[0127] <Third Embodiment>

[0128] In the following description, the same components as those described in the above-described embodiment are denoted by the same reference numerals, and their detailed description is appropriately omitted.

[0129] <About the structure of the power conversion device>

[0130] This embodiment applies the semiconductor device according to the first and second embodiments to a power converter. The power converter according to this embodiment is not limited to a specific power converter, and the following describes a case where the power converter according to this embodiment is applied to a three-phase inverter.

[0131] Fig.30 1 is a diagram schematically showing a configuration of a power conversion system to which the power conversion device 200 according to the present embodiment is applied. Fig.30The illustrated power conversion system includes a power source 100 , a power conversion device 200 , and a load 300 .

[0132] The power supply 100 is a DC power supply, and supplies DC power to the power conversion device 200. The power supply 100 may be composed of various power supplies, such as a DC system, a solar cell, a storage battery, or a rectifier circuit or an AC / DC converter connected to an AC system. In addition, the power supply 100 may be composed of a DC / DC converter that converts the DC power output from the DC system into a predetermined power.

[0133] The power conversion device 200 is a three-phase inverter connected between the power supply 100 and the load 300. The power conversion device 200 converts the direct current supplied from the power supply 100 into alternating current, and supplies it to the load 300. The power conversion device 200 includes a main conversion circuit 201 and a control circuit 203. The main conversion circuit 201 converts the input direct current into alternating current, and outputs the alternating current. The control circuit 203 outputs a control signal for controlling the main conversion circuit 201 to the main conversion circuit 201.

[0134] Load 300 is a three-phase motor driven by AC power supplied from power converter 200. Load 300 is not limited to a specific use, and is a motor mounted on various electrical devices, such as a hybrid car, electric car, railway vehicle, elevator, or air conditioning device.

[0135] The following describes the details of the power conversion device 200. The main conversion circuit 201 includes a switching element and a freewheeling diode (not shown here). The main conversion circuit 201 converts the direct current supplied from the power supply 100 into alternating current by switching the switching element, and supplies it to the load 300. The specific circuit structure of the main conversion circuit 201 has various structures, but the main conversion circuit 201 of this embodiment is a 2-level three-phase full-bridge circuit, which can be composed of 6 switching elements and 6 freewheeling diodes connected in reverse parallel to each switching element. At least one of the switching elements and the freewheeling diode of the main conversion circuit 201 applies the semiconductor device 202 involved in any one of the first embodiment, the second embodiment and their modified examples described above. The 6 switching elements are connected in series to form upper and lower arms for every 2 switching elements, and each upper and lower arm constitutes each phase (U phase, V phase, W phase) of the full-bridge circuit. In addition, the output terminals of each upper and lower arm, that is, the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0136] The main conversion circuit 201 includes a drive circuit (not shown) for driving each switching element. The drive circuit generates a drive signal for driving the switching element of the main conversion circuit 201 and supplies it to the control electrode of the switching element of the main conversion circuit 201. Specifically, the drive circuit outputs a drive signal for turning on the switching element and a drive signal for turning off the switching element to the control electrode of each switching element according to a control signal from a control circuit 203 described later. When the switching element is maintained in the on state, the drive signal is a voltage signal (on signal) above the threshold voltage of the switching element, and when the switching element is maintained in the off state, the drive signal is a voltage signal (off signal) below the threshold voltage of the switching element.

[0137] The control circuit 203 controls the switch elements of the main conversion circuit 201 to supply the desired power to the load 300. Specifically, the control circuit 203 calculates the time (on time) when each switch element of the main conversion circuit 201 should be in the on state based on the power to be supplied to the load 300. For example, the control circuit 203 can control the main conversion circuit 201 by pulse width modulation (PWM) control that modulates the on time of the switch element according to the voltage to be output. In addition, the control circuit 203 outputs a control instruction (control signal) to the drive circuit of the main conversion circuit 201 at each time, so that the on signal is output to the switch element that should be in the on state, and the off signal is output to the switch element that should be in the off state. The drive circuit outputs the on signal or the off signal as a drive signal to the control electrode of each switch element according to the control signal.

[0138] <About Method of Manufacturing Power Converter>

[0139] The manufacturing method of the power conversion device 200 has the following steps. The semiconductor device 202 is manufactured by the manufacturing method described in the first embodiment, the second embodiment, or their modified examples. The main conversion circuit 201 having the semiconductor device 202 is formed. In addition, the control circuit 203 is formed. Thus, the power conversion device 200 is formed. When the main conversion circuit 201 is formed, for example, Fig.12 As shown, the back electrode 3 of the semiconductor device 10 is bonded to the lead frame 12 via the solder 11 , and the front electrode 2 is bonded to the lead frame 12 via the lead 13 .

[0140] According to the present embodiment, as at least one of the semiconductor devices 202 constituting the main conversion circuit 201, the semiconductor device 202 according to the first embodiment or the second embodiment is used. As a result, it is possible to suppress malfunctions caused by stress from peripheral components when the semiconductor device 202 is in operation or in non-operation. As a result, the reliability of the main conversion circuit 201 is improved. Therefore, the reliability of the power conversion device 200 can be improved.

[0141] In addition, in this embodiment, an example of applying the semiconductor device 202 to a 2-level three-phase inverter is described, but this embodiment is not limited to this and can be applied to various power conversion devices. In this embodiment, the power conversion device is a 2-level power conversion device, but it can also be a multi-level power conversion device such as a 3-level power conversion device. In addition, in the case of supplying power to a single-phase load, the above-mentioned power conversion device can also be applied to a single-phase inverter. In addition, in the case of supplying power to a DC load, etc., the above-mentioned power conversion device can also be applied to a DC / DC converter or an AC / DC converter.

[0142] In addition, the power conversion device involved in this embodiment is not limited to the case where the above-mentioned load is an electric motor. For example, it can also be used as a power supply device for any one of an electric discharge machine, a laser processing machine, an induction heating cooker, and a contactless power supply system. It can also be used as a power conditioner for a solar power generation system or a power storage system.

[0143] <Fourth Embodiment>

[0144] Hereinafter, a semiconductor device and a method for manufacturing the semiconductor device according to the present embodiment will be described.

[0145] <Regarding the Structure of Semiconductor Device>

[0146] Figure 1 , Figure 2 as well as Fig.31 FIG. 1 is a diagram schematically showing an example of the structure of a semiconductor device manufactured by the manufacturing method described in this embodiment. Figure 1 In the example of FIG. 1 , a SiC Schottky barrier diode (SBD) is shown.

[0147] Fig.31 is with Figure 2 The cross-sectional view of the area surrounded by the dotted line. Figure 3 The case shown is different in that a recessed portion 40 a is provided in a side surface portion of the protective insulating film 40 .

[0148] A front electrode 2 is formed on the upper surface of the semiconductor substrate 1, and a protective insulating film 40 is further formed on the upper surface of the front electrode 2. The arithmetic mean roughness of the upper surface of the protective insulating film 40 is smaller than the arithmetic mean roughness of the side surface of the protective insulating film 40. The arithmetic mean roughness of the side surface of the protective insulating film 40 is smaller than the arithmetic mean roughness of the interface between the protective insulating film 40 and the front electrode 2 (that is, the lower surface of the protective insulating film 40). In addition, a plurality of vertices are provided at the upper end of the protective insulating film 40.

[0149] <About Method of Manufacturing Semiconductor Device>

[0150] Figure 4 1 is a flowchart showing an example of a manufacturing process of a SiC-SBD according to the present embodiment. Figure 4 In the flowchart shown in FIG. 1 , until the front electrode is formed (step ST03), the corresponding cross-sectional view Figures 5 to 9 Since this is the same as the first embodiment, the description thereof will be omitted.

[0151] Afterwards, if Fig.10 As shown, a protective insulating film 4 (protective insulating film 40 in this embodiment) is formed. As the material of the protective insulating film, polyimide or silicone resin is preferably used. By using spin coating, photolithography and etching technology or inkjet coating technology of these materials, a protective insulating film (corresponding to the outermost periphery of the front side of the SiC-SBD) is formed. Figure 4 The protective insulating film 4 (the protective insulating film 40 in this embodiment) covers the portion of the upper surface of the drift layer 7 that is not covered by the front electrode 2. In addition, the protective insulating film covers a portion of the upper surface of the front electrode 2.

[0152] After the protective insulating film 40 is formed, a surface treatment is performed using plasma containing oxygen and argon, for example, using a batch-type plasma processing device, so that a plurality of vertices are formed on the upper surface of the protective insulating film 40, and a concave portion 40a is formed on the side surface of the protective insulating film 40. In this embodiment, if a plurality of vertices are also formed on the upper surface of the protective insulating film 40 on the peripheral side of the semiconductor device, and the concavities and convexities (concave portions 40a) are formed on the side surface of the protective insulating film 40, the reliability is further improved.

[0153] Then, similarly to the first embodiment, the SiC substrate 5 is thinned (thinned) (corresponding to Figure 4 Step ST05) and subsequent steps to obtain Figure 1 , Figure 2 and Fig.31 The semiconductor device shown as an example.

[0154] When the semiconductor device thus manufactured is assembled into a Fig.12In the case of a semiconductor module of the structure shown, when a power cycle test is performed in which the semiconductor device is repeatedly switched between a power-on state and a power-off state, the protective insulating film 40 is subjected to stress caused by thermal expansion or thermal contraction from the upper surface side due to the difference in linear expansion coefficient between the protective insulating film 40 and the molded resin 14, and is subjected to stress caused by thermal expansion or thermal contraction from the lower surface side due to the difference in linear expansion coefficient between the protective insulating film 40 and the front electrode 2.

[0155] In this case, in the present embodiment, the arithmetic mean roughness of the upper surface of the protective insulating film 40 is smaller than the arithmetic mean roughness of the side surface of the protective insulating film 40, and the arithmetic mean roughness of the side surface of the protective insulating film 40 is smaller than the arithmetic mean roughness of the interface between the protective insulating film 40 and the front electrode 2 (that is, the lower surface of the protective insulating film 40). Therefore, with respect to the stress received by the protective insulating film 40 from the molded resin 14, the external force applied between the protective insulating film 40 and the front electrode 2 can be alleviated compared with the first embodiment, so that the peeling of the protective insulating film 40 can be suppressed.

[0156] <Fifth Embodiment>

[0157] Hereinafter, a semiconductor device and a method for manufacturing the semiconductor device according to the present embodiment will be described.

[0158] <Regarding the Structure of Semiconductor Device>

[0159] Figure 1 , Fig.32 as well as Fig.33 FIG. 1 is a diagram schematically showing an example of the structure of a semiconductor device manufactured by the manufacturing method described in this embodiment. Figure 1 In the example of FIG. 1 , a SiC Schottky barrier diode (SBD) is shown.

[0160] Fig.32 is with Fig.33 The cross-sectional view of the area surrounded by the dotted line. Figure 3 The case shown is different in that an inclined portion 41 b is provided on the upper surface of the protective insulating film 41 .

[0161] <About Method of Manufacturing Semiconductor Device>

[0162] Figure 4 1 is a flowchart showing an example of a manufacturing process of a SiC-SBD according to the present embodiment. Figure 4 In the flowchart shown in FIG. 1 , until the front electrode is formed (step ST03), the corresponding cross-sectional view Figures 5 to 9 Since this is the same as the first embodiment, the description thereof will be omitted.

[0163] Afterwards, if Fig.10As shown, a protective insulating film 4 (protective insulating film 41 in this embodiment) is formed. As the material of the protective insulating film, polyimide or silicone resin is preferably used. By using spin coating, photolithography and etching technology or inkjet coating technology of these materials, a protective insulating film (corresponding to the outermost periphery of the front side of the SiC-SBD) is formed. Figure 4 The protective insulating film 4 (the protective insulating film 41 in this embodiment) covers the portion of the upper surface of the drift layer 7 that is not covered by the front electrode 2. In addition, the protective insulating film covers a portion of the upper surface of the front electrode 2.

[0164] After the protective insulating film 41 is formed, a surface treatment is performed using plasma containing oxygen and argon, for example, using a batch-type plasma processing device, thereby forming a plurality of vertices on the upper surface of the protective insulating film 41. At this time, if a plurality of vertices are also formed on the upper surface of the protective insulating film 41 on the peripheral side of the semiconductor device, the reliability is further improved.

[0165] Then, a heat treatment is performed at a temperature of 250° C. to 350° C. to cure the upper surface of the protective insulating film 41. Fig.32 and Fig.33 As shown, the inclined portion 41 b having (ie, inclined at) an angle of θ3 with respect to a plane parallel to the semiconductor substrate (ie, the upper surface of the protective insulating film 41 ) can be provided.

[0166] Next, similarly to the first embodiment, the SiC substrate 5 is thinned (thinned) (corresponding to Figure 4 Step ST05) and subsequent steps to obtain Figure 1 , Fig.32 and Fig.33 The semiconductor device shown as an example.

[0167] When the semiconductor device thus manufactured is assembled into a Fig.12 In the case of the semiconductor module having the structure shown, when a power cycle test is performed in which the semiconductor device is repeatedly switched between the energized state and the non-energized state, since the thickness of the end portion of the protective insulating film 41 is thicker than the central portion of the protective insulating film 41, the stress applied to the semiconductor device from the mold resin 14 can be absorbed by the deformation of the end portion of the protective insulating film 41. Therefore, cracks generated in the protective insulating film 41 can be suppressed.

[0168] <Effects Produced by the Multiple Embodiments Described Above>

[0169] Next, examples of the effects produced by the above-described multiple embodiments are shown. In addition, in the following description, the effects are recorded based on the specific structures exemplified in the above-described multiple embodiments, but they can also be replaced with other specific structures exemplified in the specification of this application within the scope of producing the same effects. That is, for convenience, sometimes only one of the corresponding specific structures is representatively recorded below, but it can also be replaced with other specific structures corresponding to the representatively recorded specific structures.

[0170] In addition, this replacement can also be performed across multiple embodiments. That is, each structure illustrated in different embodiments can also be combined to produce the same effect.

[0171] According to the above-described embodiment, the semiconductor device includes a semiconductor layer, a first electrode layer, and an insulating film. Here, the semiconductor layer corresponds to, for example, the drift layer 6 or the drift layer 7. In addition, the first electrode layer corresponds to, for example, the front electrode 2. In addition, the insulating film corresponds to, for example, the protective insulating film 4. The front electrode 2 covers a portion of the upper surface of the drift layer 7 via the drift layer 6, the Schottky electrode layer 9, etc. The protective insulating film 4 covers another portion of the upper surface of the drift layer 7 via the drift layer 6, the Schottky electrode layer 9, etc. In addition, the protective insulating film 4 covers a portion of the upper surface of the front electrode 2. Here, the arithmetic mean roughness of the upper surface of the protective insulating film 4 is smaller than the arithmetic mean roughness of the interface between the protective insulating film 4 and the front electrode 2.

[0172] According to such a structure, the contact area between the upper part of the protective insulating film 4 and the component is smaller than the contact area between the lower part of the protective insulating film 4 and the component. Therefore, the connection between the lower part of the protective insulating film 4 and the component can be made stronger than the connection between the upper part of the protective insulating film 4 and the component, so that the peeling of the protective insulating film 4 during operation can be suppressed. According to such a structure, the reliability of the semiconductor device can be improved.

[0173] In addition, when other structures illustrated in the specification of the present application are appropriately added to the above-mentioned structure, that is, even when other structures in the specification of the present application that are not mentioned as the above-mentioned structure are appropriately added, the same effect can be produced.

[0174] In addition, according to the above-described embodiment, the end of the upper surface of the protective insulating film 4 is an inclined surface. Moreover, the vertex formed at the upper end of the inclined surface and the vertex formed at the lower end of the inclined surface are both obtuse angles. According to such a structure, by having a plurality of vertices at the upper and lower ends of the inclined surface, the stress applied to the protective insulating film 4 from the surroundings can be dispersed. In addition, by setting the angle of each vertex to be 90 degrees or more, the force applied to the vertex can be reduced, so that the generation of cracks on the protective insulating film 4 can be suppressed.

[0175] In addition, according to the above-described embodiment, the semiconductor device includes a second electrode layer covering a portion of the front electrode 2. Here, the second electrode layer corresponds to, for example, the front electrode 15. The protective insulating film 4 covers a portion of the front electrode 2. In addition, the interface between the front electrode 15 and the front electrode 2 is located below the interface between the protective insulating film 4 and the front electrode 2. According to such a structure, the force applied to the protective insulating film 4 from the front electrode 15 can be reduced. Therefore, peeling of the protective insulating film 4 can be suppressed.

[0176] According to the above-described embodiment, the ridge line 4 a of the side surface of the protective insulating film 4 is concave. With such a structure, the generation of cracks in the protective insulating film 4 can be suppressed.

[0177] In addition, according to the above-described embodiment, there are provided: a main conversion circuit 201 having the above-described semiconductor device, and converting and outputting input power; and a control circuit 203, which outputs a control signal for controlling the main conversion circuit 201 to the main conversion circuit 201. According to such a structure, the contact area between the upper part of the protective insulating film 4 and the component is smaller than the contact area between the lower part of the protective insulating film 4 and the component. Therefore, the connection between the lower part of the protective insulating film 4 and the component can be made stronger than the connection between the upper part of the protective insulating film 4 and the component, so that the peeling of the protective insulating film 4 during operation can be suppressed. According to such a structure, the reliability of the power conversion device having the semiconductor device can be improved.

[0178] According to the above-described embodiment, in the method for manufacturing a semiconductor device, the front electrode 2 is formed by covering a portion of the upper surface of the drift layer 6. Then, the protective insulating film 4 is formed by covering the other portion of the upper surface of the drift layer 6 and at least a portion of the upper surface of the front electrode 2. Here, the arithmetic mean roughness of the upper surface of the protective insulating film 4 is smaller than the arithmetic mean roughness of the interface between the protective insulating film 4 and the front electrode 2.

[0179] According to such a structure, the contact area between the upper part of the protective insulating film 4 and the component is smaller than the contact area between the lower part of the protective insulating film 4 and the component. Therefore, the connection between the lower part of the protective insulating film 4 and the component can be made stronger than the connection between the upper part of the protective insulating film 4 and the component, so that the peeling of the protective insulating film 4 during operation can be suppressed. According to such a structure, the reliability of the semiconductor device can be improved.

[0180] In addition, according to the above-described embodiment, in the manufacturing method of the power conversion device, a main conversion circuit 201 is provided, which has a semiconductor device manufactured by the above-described manufacturing method, and converts and outputs the input power. In addition, a control circuit 203 is provided to output a control signal for controlling the main conversion circuit 201 to the main conversion circuit 201. According to such a structure, the contact area between the upper part of the protective insulating film 4 and the constituent element is smaller than the contact area between the lower part of the protective insulating film 4 and the constituent element. Therefore, the connection between the lower part of the protective insulating film 4 and the constituent element can be made stronger than the connection between the upper part of the protective insulating film 4 and the constituent element, so that the peeling of the protective insulating film 4 during operation can be suppressed. According to such a structure, it is possible to suppress the malfunction caused by the stress from the peripheral components when the semiconductor device is in operation and when it is not in operation. As a result, the reliability of the main conversion circuit is improved, and the reliability of the power conversion device can be improved.

[0181] <Regarding Modifications of the Multiple Embodiments Described Above>

[0182] In the above-described embodiments, the material, size, shape, relative arrangement relationship, implementation conditions, etc. of each component are sometimes described, but these are merely examples in all aspects and are not limitative descriptions.

[0183] Therefore, numerous variations and equivalents not illustrated can be envisioned within the scope of the technology disclosed in the specification of this application, including, for example, the case where at least one constituent element is deformed, added, or omitted, and the case where at least one constituent element in at least one embodiment is extracted and combined with constituent elements in other embodiments.

[0184] In at least one embodiment described above, when a material name or the like is described without being particularly specified, the material includes other additives such as alloys, etc., unless there is any contradiction.

[0185] Furthermore, when it is described in the above-described embodiment that “one” component is included, “one or more” of the component may be included unless a contradiction occurs.

[0186] Moreover, each component in the above-described embodiments is a conceptual unit, and within the scope of the technology disclosed in the present application specification, includes a case where one component is composed of multiple structures, a case where one component corresponds to a part of a structure, and a case where one structure has multiple components.

[0187] In addition, as long as the respective components in the above-described embodiments exhibit the same functions, structures having other structures or shapes are included.

[0188] In addition, the descriptions in the specification of this application are referenced for all purposes related to the present technology and are not considered to be prior art.

[0189] Hereinafter, each aspect of the present disclosure will be collectively described as a supplementary note.

[0190] (Note 1)

[0191] A semiconductor device comprising:

[0192] Semiconductor layer;

[0193] A first electrode layer covering a portion of an upper surface of the semiconductor layer; and

[0194] an insulating film covering another portion of the upper surface of the semiconductor layer and a portion of the upper surface of the first electrode layer,

[0195] An arithmetic mean roughness of an upper surface of the insulating film is smaller than an arithmetic mean roughness of an interface between the insulating film and the first electrode layer.

[0196] (Note 2)

[0197] The semiconductor device according to Supplementary Note 1, wherein:

[0198] The end of the upper surface of the insulating film is an inclined surface,

[0199] The vertex formed at the upper end of the inclined surface and the vertex formed at the lower end of the inclined surface are both obtuse angles.

[0200] (Note 3)

[0201] The semiconductor device according to Supplement 1 or 2, wherein:

[0202] The insulating film covers a portion of the first electrode layer,

[0203] The semiconductor device further includes a second electrode layer covering a portion of the first electrode layer.

[0204] The interface between the second electrode layer and the first electrode layer is located below the interface between the insulating film and the first electrode layer.

[0205] (Note 4)

[0206] A semiconductor device according to any one of Supplementary Notes 1 to 3, wherein:

[0207] The ridge lines of the side surfaces of the insulating film are concave.

[0208] (Note 5)

[0209] A power conversion device comprising:

[0210] A main conversion circuit comprising the semiconductor device according to any one of Supplementary Notes 1 to 4, and converting input power and outputting the converted power; and

[0211] A control circuit outputs a control signal for controlling the main conversion circuit to the main conversion circuit.

[0212] (Note 6)

[0213] A method for manufacturing a semiconductor device, wherein:

[0214] forming a first electrode layer by covering a portion of the upper surface of the semiconductor layer,

[0215] forming an insulating film covering the other part of the upper surface of the semiconductor layer and at least a part of the upper surface of the first electrode layer,

[0216] An arithmetic mean roughness of an upper surface of the insulating film is smaller than an arithmetic mean roughness of an interface between the insulating film and the first electrode layer.

[0217] (Note 7)

[0218] A semiconductor device comprising:

[0219] Semiconductor layer;

[0220] A first electrode layer covering a portion of an upper surface of the semiconductor layer; and

[0221] an insulating film covering another portion of the upper surface of the semiconductor layer and a portion of the upper surface of the first electrode layer,

[0222] The arithmetic mean roughness of the upper surface of the insulating film is smaller than the arithmetic mean roughness of the side surfaces of the insulating film,

[0223] An arithmetic mean roughness of a side surface of the insulating film is smaller than an arithmetic mean roughness of an interface between the insulating film and the first electrode layer.

[0224] (Note 8)

[0225] A method for manufacturing a semiconductor device, the semiconductor device comprising:

[0226] Semiconductor layer;

[0227] A first electrode layer covering a portion of an upper surface of the semiconductor layer; and

[0228] an insulating film covering another portion of the upper surface of the semiconductor layer and a portion of the upper surface of the first electrode layer,

[0229] The arithmetic mean roughness of the upper surface of the insulating film is smaller than the arithmetic mean roughness of the side surfaces of the insulating film,

[0230] An arithmetic mean roughness of a side surface of the insulating film is smaller than an arithmetic mean roughness of an interface between the insulating film and the first electrode layer.

[0231] (Note 9)

[0232] A semiconductor device according to any one of Supplementary Notes 1 to 4 and 7, wherein:

[0233] An inclined portion inclined with respect to the upper surface is provided on the upper surface of the insulating film.

[0234] Description of symbols

[0235] 1: semiconductor substrate, 2: front electrode, 2a: convex portion, 3: back electrode, 4: protective insulating film, 4a: ridge, 5: substrate, 6: drift layer, 7: drift layer, 8: interlayer insulating film, 9: Schottky electrode layer, 10: semiconductor device, 11: solder, 12: lead frame, 13: lead, 14: molded resin, 15: front electrode, 40: protective insulating film, 40a: concave portion, 41: protective insulating film, 41b: inclined portion, 100: power supply, 200: power conversion device, 201: main conversion circuit, 202: semiconductor device, 203: control circuit, 300: load, 401: average line.

Claims

1. A semiconductor device comprising: Semiconductor layer; A first electrode layer covering a portion of an upper surface of the semiconductor layer; and an insulating film covering another portion of the upper surface of the semiconductor layer and a portion of the upper surface of the first electrode layer, An arithmetic mean roughness of an upper surface of the insulating film is smaller than an arithmetic mean roughness of an interface between the insulating film and the first electrode layer.

2. The semiconductor device according to claim 1, wherein The end of the upper surface of the insulating film is an inclined surface, The vertex formed at the upper end of the inclined surface and the vertex formed at the lower end of the inclined surface are both obtuse angles.

3. The semiconductor device according to claim 1 or 2, wherein: The insulating film covers a portion of the first electrode layer, The semiconductor device further includes a second electrode layer covering a portion of the first electrode layer. The interface between the second electrode layer and the first electrode layer is located below the interface between the insulating film and the first electrode layer.

4. The semiconductor device according to any one of claims 1 to 3, wherein: The ridge lines of the side surfaces of the insulating film are concave.

5. A power conversion device comprising: A main conversion circuit comprising the semiconductor device according to any one of claims 1 to 4, and converting input power and outputting the converted power; and A control circuit outputs a control signal for controlling the main conversion circuit to the main conversion circuit.

6. A method for manufacturing a semiconductor device, wherein: A first electrode layer is formed by covering a portion of the upper surface of the semiconductor layer, forming an insulating film covering the other part of the upper surface of the semiconductor layer and at least a part of the upper surface of the first electrode layer, An arithmetic mean roughness of an upper surface of the insulating film is smaller than an arithmetic mean roughness of an interface between the insulating film and the first electrode layer.

7. A semiconductor device comprising: Semiconductor layer; A first electrode layer covering a portion of an upper surface of the semiconductor layer; and an insulating film covering another portion of the upper surface of the semiconductor layer and a portion of the upper surface of the first electrode layer, The arithmetic mean roughness of the upper surface of the insulating film is smaller than the arithmetic mean roughness of the side surfaces of the insulating film, An arithmetic mean roughness of a side surface of the insulating film is smaller than an arithmetic mean roughness of an interface between the insulating film and the first electrode layer.

8. A method for manufacturing a semiconductor device, the semiconductor device comprising: Semiconductor layer; A first electrode layer covering a portion of an upper surface of the semiconductor layer; and an insulating film covering another portion of the upper surface of the semiconductor layer and a portion of the upper surface of the first electrode layer, The arithmetic mean roughness of the upper surface of the insulating film is smaller than the arithmetic mean roughness of the side surfaces of the insulating film, An arithmetic mean roughness of a side surface of the insulating film is smaller than an arithmetic mean roughness of an interface between the insulating film and the first electrode layer.

9. The semiconductor device according to any one of claims 1 to 4 and 7, wherein: An inclined portion inclined with respect to the upper surface is provided on the upper surface of the insulating film.

Images