Semiconductor device and manufacturing method thereof
By introducing gaps in the inorganic passivation layer of semiconductor devices and forming a protective layer, the problem of layering or cracking caused by excessive mechanical stress caused by the inorganic passivation layer, and improved the performance and reliability of the device.
Patent Information
- Application Number
- CN202480001974.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-10
- Publication Date
- 2025-01-28
AI Technical Summary
In semiconductor devices, the mechanical stress of the inorganic passivation layer increases as its thickness or area increases, resulting in the risk of layering or cracking, which in turn affects the performance and reliability of the device.
By introducing N gaps in the appropriate position of the inorganic passivation layer, it is divided into multiple independent blocks, and a protective layer is formed in the gap to reduce mechanical stress and thermal stress and prevent water vapor penetration.
It reduces the mechanical stress and thermal stress of the inorganic passivation layer, reduces the risk of layering or cracking, and improves the performance and reliability of semiconductor devices.
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Figure CN119384881A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of electronic devices, and in particular to a semiconductor device and a method for manufacturing the semiconductor device. Background Art
[0002] In semiconductor devices such as SiC power semiconductor devices, an inorganic passivation layer is usually used to cover the terminal area to achieve electrical isolation between the semiconductor surface and the environment. Under high voltage bias, the inorganic passivation layer can not only withstand the potential difference between the semiconductor surface and the environment, but also block the water vapor from the environment from penetrating into the semiconductor surface, thereby ensuring the withstand voltage characteristics of the device and ensuring the reliability of the device under high temperature, high pressure and high humidity environments. Generally, the larger the coverage area and thickness of the inorganic passivation layer, the better the protection effect on the device surface. However, as the thickness or area of the inorganic passivation layer increases, the mechanical stress of the inorganic passivation layer increases, and it may therefore face the risk of delamination or cracking in subsequent process, device packaging, and reliability testing. Once cracking or delamination occurs, water vapor may penetrate into the semiconductor surface along the cracks, resulting in the performance and reliability of the device declining. Therefore, how to reduce the risk of delamination or cracking of the inorganic passivation layer to improve the performance and reliability of the device is a technical problem that needs to be solved urgently. SUMMARY OF THE INVENTION Technical Solutions
[0003] In view of this, an embodiment of the present invention provides a semiconductor device and a method for manufacturing a semiconductor device, which can reduce the risk of delamination or cracking of an inorganic passivation layer, thereby improving the performance and reliability of the semiconductor device.
[0004] Specifically, on one hand, an embodiment of the present invention provides a semiconductor device, for example, including:
[0005] Semiconductor substrate;
[0006] An electrode layer is disposed on the first surface of the semiconductor substrate and forms a Schottky contact or an Ohmic contact with the semiconductor substrate;
[0007] an inorganic passivation layer, disposed on a surface of the electrode layer away from the semiconductor substrate and extending to a region of the first surface of the semiconductor substrate not covered by the electrode layer, wherein the inorganic passivation layer is formed with N slits to divide the inorganic passivation layer into a plurality of independent blocks, and each of the N slits is located directly above the electrode layer, and N is an integer greater than or equal to 1; and
[0008] A protective layer is disposed on a surface of the inorganic passivation layer away from the semiconductor substrate and extends into each of the N gaps.
[0009] On the other hand, an embodiment of the present invention provides a method for manufacturing a semiconductor device, for example, including:
[0010] A semiconductor structure is provided, wherein the semiconductor structure comprises a semiconductor substrate and an electrode layer, wherein the electrode layer is disposed on a first surface of the semiconductor substrate and forms a Schottky contact or an Ohmic contact with the semiconductor substrate;
[0011] forming an inorganic passivation layer on the semiconductor structure, wherein the inorganic passivation layer is formed on a surface of the electrode layer away from the semiconductor substrate and extends to a region of the first surface of the semiconductor substrate not covered by the electrode layer, the inorganic passivation layer is formed with N gaps to divide the inorganic passivation layer into a plurality of independent blocks, and each of the N gaps is located directly above the electrode layer, and N is an integer greater than or equal to 1; and
[0012] A protection layer is formed on a surface of the inorganic passivation layer facing away from the semiconductor substrate, wherein the protection layer extends into each of the N gaps. Beneficial Effects
[0013] By introducing the N gaps at appropriate positions of the inorganic passivation layer, the inorganic passivation layer is divided from a larger overall area into smaller blocks, thereby reducing the mechanical stress of the inorganic passivation layer; at the same time, the N gaps introduced can release the thermal stress caused by the difference in thermal expansion coefficients of adjacent layers, thereby avoiding the cracking or delamination of the inorganic passivation layer and improving the performance and reliability of the device. Furthermore, since the N gaps are located directly above the electrode layer, for example, during the H3TRB (High Humidity High Temperature Reverse Bias) reliability test, the electric field formed by the high voltage will be shielded by the electrode layer inside the semiconductor, and will not be distributed to the inorganic passivation layer where the gaps are located. This can effectively prevent water vapor from penetrating into the surface of the semiconductor substrate through the electric field, thereby improving device reliability. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] The specific implementation modes of the present invention will be described in detail below with reference to the accompanying drawings.
[0015] Figure 1 A schematic diagram of the local structure of a semiconductor device provided in embodiment 1 of the present invention.
[0016] Figure 2 A schematic top view of an etch stop layer, a front metal layer, a first gap, a second gap and an inorganic passivation layer in a semiconductor device provided in an embodiment of the present invention.
[0017] FIG. 3A to FIG. 3EA schematic diagram of multiple process structures of a method for manufacturing a semiconductor device provided in embodiment 2 of the present invention.
[0018] Figure 4 A schematic diagram of the local structure of a semiconductor device provided in embodiment 3 of the present invention.
[0019] FIG. 5A to FIG. 5D A schematic diagram of multiple process structures of a method for manufacturing a semiconductor device provided in embodiment 4 of the present invention.
[0020] Figure 6 A schematic diagram of the local structure of a semiconductor device provided in embodiment 5 of the present invention.
[0021] Figure 7 A schematic diagram of the local structure of a semiconductor device provided in embodiment 6 of the present invention.
[0022] Figure 8 A schematic diagram of the local structure of a semiconductor device provided in embodiment 7 of the present invention.
[0023] 9A to 9E A schematic diagram of multiple process structures of a method for manufacturing a semiconductor device provided in embodiment 8 of the present invention.
[0024] [Description of Reference Numerals]
[0025] 10. semiconductor device; 11. semiconductor substrate; 11S. first surface of semiconductor substrate; 111. epitaxial layer; 112. injection region; 13. electrode layer; 131. contact metal layer; 131e. side surface of contact metal layer; 133. etching stop layer; 133e. side surface of etching stop layer; 135. front metal layer; 1350. front metal material layer; 135e. side surface of front metal layer; 135T. top surface of front metal layer; 135B. bottom surface of front metal layer; 14. stacked oxide layer; 15. inorganic passivation layer; 151e. inner surface of inorganic passivation layer; 153e. outer surface of inorganic passivation layer; 150. inorganic passivation material layer; 17. protective layer; Gap1. first gap; Gap2. second gap; w. width; d1, d2, d3, d4. distance; CH. opening; direction from covered area to uncovered area, R. Embodiments of the present invention
[0026] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0027] In order to enable those skilled in the art to better understand the technical solution of the present invention, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work should fall within the scope of protection of the present invention.
[0028] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.
[0029] It should also be noted that the division of multiple embodiments in the present invention is only for the convenience of description and should not constitute a special limitation. The features in various embodiments can be combined and referenced to each other without contradiction.
[0030] In the related art, the inorganic passivation layer is often arranged on the surface of the electrode layer away from the semiconductor substrate, and extends to the area on the surface of the semiconductor substrate that is not covered by the electrode layer, forming a larger whole. Due to the larger area, the mechanical stress of this inorganic passivation layer topology is also larger, which makes the inorganic passivation layer prone to delamination or cracking. Therefore, the inorganic passivation layer topology provided in the following embodiments of the present invention introduces gaps at appropriate positions to divide the inorganic passivation layer from a larger whole into multiple smaller blocks, thereby reducing the mechanical stress of the inorganic passivation layer and reducing the risk of delamination or cracking of the inorganic passivation layer. At the same time, the introduced gaps can release the thermal stress caused by the difference in thermal expansion coefficients of adjacent layers, avoid the cracking of the inorganic passivation layer, and thus provide the performance and reliability of the device.
[0031] Specifically, an embodiment of the present invention provides a semiconductor device, comprising: a semiconductor substrate; an electrode layer, arranged on a first surface of the semiconductor substrate and forming a Schottky contact or an Ohmic contact with the semiconductor substrate; an inorganic passivation layer, arranged on a surface of the electrode layer away from the semiconductor substrate and extending to an area of the first surface of the semiconductor substrate not covered by the electrode layer, wherein the inorganic passivation layer is formed with N gaps to divide the inorganic passivation layer into a plurality of independent blocks, and each of the N gaps is located directly above the electrode layer, and N is an integer greater than or equal to 1; and a protective layer, arranged on a surface of the inorganic passivation layer away from the semiconductor substrate and extending into each of the N gaps.
[0032] In some embodiments, in a direction from an area of the first surface covered by the electrode layer to an area of the first surface not covered by the electrode layer, a width of a single gap among the N gaps is 1 micrometer to 3 micrometers; and / or, in a direction from an area of the first surface covered by the electrode layer to an area of the first surface not covered by the electrode layer, a distance between two adjacent gaps among the N gaps is 5 micrometers to 50 micrometers.
[0033] In some embodiments, the electrode layer includes a contact metal layer and a front metal layer, the contact metal layer is arranged on the first surface of the semiconductor substrate and forms the Schottky contact or the ohmic contact with the semiconductor substrate, and the front metal layer is arranged on the top surface of the contact metal layer away from the semiconductor substrate; the inorganic passivation layer is arranged on the top surface of the front metal layer away from the contact metal layer and extends to the area of the first surface not covered by the contact metal layer, and the N gaps include a first gap, and the first gap is located directly above the front metal layer to expose a portion of the top surface of the front metal layer.
[0034] In some embodiments, the front metal layer has a bottom surface facing the contact metal layer and a side surface connecting the top surface of the front metal layer with the bottom surface of the front metal layer; and, the first gap is arranged near a first boundary line, the first boundary line is the boundary line between the side surface of the front metal layer and the top surface of the front metal layer, and / or, the contact metal layer has a bottom surface facing the semiconductor substrate and a side surface connecting the bottom surface of the contact metal layer with the top surface of the contact metal layer, and the side surface of the contact metal layer is aligned or flush with a second boundary line, the second boundary line is the boundary line between the side surface of the front metal layer and the bottom surface of the front metal layer.
[0035] In some embodiments, the number of the first gaps is one, and the distance between the first gap and the first boundary line in the direction from the area of the first surface covered by the contact metal layer to the area of the first surface not covered by the contact metal layer is 100 nanometers to 10 microns; or, the number of the first gaps is multiple, and the multiple first gaps are spaced apart in the direction from the area of the first surface covered by the contact metal layer to the area of the first surface not covered by the contact metal layer, wherein the distance between the first gap on the side surface closest to the front metal layer and the first boundary line is 100 nanometers to 10 microns.
[0036] In some embodiments, the electrode layer also includes an etching stop layer, which is located between the contact metal layer and the front metal layer; the front metal layer has a bottom surface facing the contact metal layer and a side surface connecting the top surface of the front metal layer and the bottom surface of the front metal layer; the etching stop layer has a bottom surface facing the contact metal layer, a top surface away from the contact metal layer, and a side surface connecting the bottom surface of the etching stop layer and the top surface of the etching stop layer; in the direction from the area of the first surface covered by the contact metal layer to the area of the first surface not covered by the contact metal layer, the side surface of the etching stop layer is closer to the area of the first surface not covered by the contact metal layer relative to the side surface of the front metal layer; the inorganic passivation layer is arranged on the top surface of the front metal layer and extends to the side surface of the front metal layer, the area of the top surface of the etching stop layer not covered by the front metal layer, and the area of the first surface not covered by the contact metal layer in sequence; the N gaps also include a second gap, and the second gap is located directly above the area of the etching stop layer not covered by the front metal layer to expose a portion of the top surface of the etching stop layer.
[0037] In some embodiments, the electrode layer includes a contact metal layer, an etching stop layer and a front metal layer, the contact metal layer is arranged on the first surface of the semiconductor substrate and forms the Schottky contact or the ohmic contact with the semiconductor substrate, the etching stop layer is arranged on the top surface of the contact metal layer away from the semiconductor substrate, and the front metal layer is arranged on the top surface of the etching stop layer away from the contact metal layer; the front metal layer has a top surface away from the contact metal layer, a bottom surface facing the contact metal layer, and a side surface connecting the top surface of the front metal layer and the bottom surface of the front metal layer; the etching stop layer has a bottom surface facing the contact metal layer and a side surface connecting the bottom surface of the etching stop layer and the etching stop layer the side surface of the top surface of the first surface; in the direction from the area of the first surface covered by the contact metal layer to the area of the first surface not covered by the contact metal layer, the side surface of the etching stop layer is closer to the area of the first surface not covered by the contact metal layer relative to the side surface of the front metal layer; the inorganic passivation layer is arranged on the top surface of the front metal layer, and extends to the side surface of the front metal layer, the area of the top surface of the etching stop layer not covered by the front metal layer, and the area of the first surface not covered by the contact metal layer in sequence; the N gaps include a second gap, and the second gap is located directly above the area of the etching stop layer not covered by the front metal layer to expose a portion of the top surface of the etching stop layer.
[0038] In some embodiments, in a direction from an area of the first surface covered by the contact metal layer to an area of the first surface not covered by the contact metal layer, a distance between the second gap and a side surface of the etching stop layer is 3 micrometers to 7 micrometers.
[0039] In some embodiments, the second gap is arranged near a second boundary line, which is the boundary line between the side surface of the front metal layer and the bottom surface of the front metal layer; in the direction from the area of the first surface covered by the contact metal layer to the area of the first surface not covered by the contact metal layer, the distance between the second gap and the second boundary line is 100 nanometers to 10 microns.
[0040] In some embodiments, an opening is formed in an area of the etching stop layer not covered by the front metal layer, the opening extends from the etching stop layer to the contact metal layer, and the inorganic passivation layer extends into the opening; in a direction from an area of the first surface covered by the contact metal layer to an area of the first surface not covered by the contact metal layer, the second gap is spaced apart from the opening.
[0041] In some embodiments, a side surface of the contact metal layer is aligned or flush with a side surface of the etch stop layer, and the opening extends from a top surface of the etch stop layer to a bottom surface of the contact metal layer facing away from the etch stop layer to expose a portion of the first surface.
[0042] In some embodiments, a stacked oxide layer is also included, which is arranged on the first surface of the semiconductor substrate and is located between the inorganic passivation layer and the first surface of the semiconductor substrate; wherein the contact metal layer and the etching stop layer both extend between the inorganic passivation layer and the stacked oxide layer to partially overlap with the stacked oxide layer to form a field plate structure.
[0043] In addition, an embodiment of the present invention also provides a method for manufacturing a semiconductor device, comprising: providing a semiconductor structure, wherein the semiconductor structure includes a semiconductor substrate and an electrode layer, the electrode layer is arranged on a first surface of the semiconductor substrate and forms a Schottky contact or an Ohmic contact with the semiconductor substrate; forming an inorganic passivation layer on the semiconductor structure, wherein the inorganic passivation layer is formed on a surface of the electrode layer away from the semiconductor substrate and extends to an area of the first surface of the semiconductor substrate not covered by the electrode layer, the inorganic passivation layer is formed with N gaps to divide the inorganic passivation layer into a plurality of independent blocks, and each of the N gaps is located directly above the electrode layer, N is an integer greater than or equal to 1; and forming a protective layer on a surface of the inorganic passivation layer away from the semiconductor substrate, wherein the protective layer extends into each of the N gaps.
[0044] To facilitate a clearer understanding of various embodiments of the present invention, a number of specific implementations will be described in detail below with reference to the accompanying drawings.
[0045] [Implementation method 1]
[0046] See also Figure 1 An embodiment of the present invention provides a semiconductor device 10 , which includes, for example, a semiconductor substrate 11 , an electrode layer 13 , an inorganic passivation layer 15 and a protective layer 17 .
[0047] The semiconductor substrate 11 includes, for example, an epitaxial layer 111 of a first conductivity type and one or more implantation regions 112 of a second conductivity type formed in the epitaxial layer 111. Each implantation region 112 extends from the top surface of the epitaxial layer 111 toward the inside of the epitaxial layer 111. When there are multiple implantation regions 112, the multiple implantation regions 112 may be arranged at intervals in the epitaxial layer 111. The aforementioned epitaxial layer 111 may also be referred to as a drift layer. The first conductivity type may be n-type and the second conductivity type may be p-type; or, the second conductivity type may be n-type and the first conductivity type may be p-type. For example, the epitaxial layer 111 of the first conductivity type is, for example, a SiC drift layer, and the implantation regions 112 of the second conductivity type are, for example, regions formed by ion implantation; of course, these implantation regions 112 of the second conductivity type may be partially regions and partially regions. In addition, it is worth mentioning that the semiconductor substrate 11 may also typically have a semiconductor substrate such as a SiC substrate, located at the bottom surface of the SiC drift layer. As for the doping concentration and thickness of the semiconductor substrate and the first conductive type epitaxial layer 111, as well as the design of the longitudinal depth, ion implantation concentration, lateral width and lateral spacing of the second conductive type implantation region 112, reference can be made to existing mature technologies, so they will not be repeated here.
[0048] The electrode layer 13 is disposed on the first surface 11S of the semiconductor substrate 11 (eg, the top surface of the first conductive type epitaxial layer 111 ) and forms a Schottky contact or an Ohmic contact with the semiconductor substrate 11 , eg, forms a Schottky contact or an Ohmic contact with the first conductive type epitaxial layer 111 .
[0049] The inorganic passivation layer 15 is disposed on the surface of the electrode layer 13 facing away from the semiconductor substrate 11 and extends to the area of the first surface 11S of the semiconductor substrate 11 not covered by the electrode layer 13 (eg Figure 1 The inorganic passivation layer 15 is formed with N (N is an integer greater than or equal to 1) gaps such as the first gap Gap1 and the second gap Gap2 to divide the inorganic passivation layer 15 into a plurality of independent blocks, and each of the N gaps (such as the first gap Gap1 and the second gap Gap2) is located directly above the electrode layer 13, that is, the orthographic projection of each gap such as the first gap Gap1 and the second gap Gap2 on the first surface 11S of the semiconductor substrate 11 is located within the range of the orthographic projection of the electrode layer 13 on the first surface 11S of the semiconductor substrate 11. In addition, for example, the inorganic passivation layer 15 can be silicon oxide (SiO x ) layer or silicon nitride (SiN x ) layer, or a multilayer stacked structure of the two, or other dielectric material layers, such as silicon oxynitride (SiN x O y) layer, aluminum oxide (Al2O3) layer, hafnium oxide (HfO2) layer, etc.
[0050] The protection layer 17 is disposed on the surface of the inorganic passivation layer 15 facing away from the semiconductor substrate 11 and extends into each of the N gaps, for example, into the first gap Gap1 and the second gap Gap2 .
[0051] As can be seen from the above, this embodiment divides the inorganic passivation layer 15 into multiple independent blocks by forming N gaps, such as the first gap Gap1 and the second gap Gap2, in the inorganic passivation layer 15 directly above the electrode layer 13, thereby forming multiple (for example, four) smaller area regions, thereby reducing the mechanical stress of the inorganic passivation layer 15, thereby reducing the risk of delamination or cracking of the inorganic passivation layer 15; at the same time, the N gaps used to divide the inorganic passivation layer 15, such as the first gap Gap1 and the second gap Gap2, can release part of the thermal stress from the adjacent layers, thereby also avoiding the inorganic passivation layer 15 caused by the thermal stress of the adjacent layers. Cracking. Furthermore, since the N gaps, such as the first gap Gap1 and the second gap Gap2, are located directly above the electrode layer 13, for example, during the H3TRB reliability test, the electric field formed by the high voltage will be shielded inside the semiconductor by the electrode layer 13, and will not be distributed to the inorganic passivation layer 15 where the N gaps are located. This can effectively prevent water vapor from being accelerated to penetrate into the first surface 11S of the semiconductor substrate 11 through the electric field, thereby improving device reliability.
[0052] In some embodiments, see Figure 1 , in the area covered by the electrode layer 13 from the first surface 11S of the semiconductor substrate 11 (corresponding to Figure 1 The area not covered by the electrode layer 13 (corresponding to the area of the first surface 11S of the semiconductor substrate 11) is Figure 1 In the direction R of the [uncovered area] shown in FIG. 1 ), the width w of the first gap Gap1 and the second gap Gap2 should be as small as possible to reduce the contact area between the electrode layer 13 and the protective layer 17. The width w is, for example, 1 μm to 3 μm, such as 1 μm, 2 μm, 3 μm, etc.
[0053] In some embodiments, see Figure 1 , in the area covered by the electrode layer 13 from the first surface 11S of the semiconductor substrate 11 (corresponding to Figure 1 The area not covered by the electrode layer 13 (corresponding to the area of the first surface 11S of the semiconductor substrate 11) is Figure 1 In the direction R of the [uncovered area] shown in the figure, the distance between two adjacent gaps among the N gaps is d4, and the distance d4 is 5 microns to 50 microns.
[0054] In some embodiments, see Figure 1 The electrode layer 13, for example, includes a contact metal layer 131 and a front metal layer 135, the contact metal layer 131 is arranged on the first surface 11S of the semiconductor substrate 11 and forms a Schottky contact or an ohmic contact with the semiconductor substrate 11; the contact metal layer 131 has a bottom surface facing the semiconductor substrate 11, a top surface away from the semiconductor substrate 11, and a side surface 131e connecting the bottom surface of the contact metal layer 131 and the top surface of the contact metal layer 131, and the front metal layer 135 is arranged on the top surface of the contact metal layer 131 away from the semiconductor substrate 11; the inorganic passivation layer 14 is arranged on the top surface 135T of the front metal layer 135 away from the contact metal layer 131 and extends to the area of the first surface 11S not covered by the contact metal layer 131, and the first gap Gap1 of the N gaps is located directly above the front metal layer 135 to expose a portion of the top surface 135T of the front metal layer 135.
[0055] More specifically, in some embodiments, the electrode layer 13 further includes an etching stop layer 133, and the etching stop layer 133 is located between the contact metal layer 131 and the front metal layer 135; in other words, the etching stop layer 133 is disposed on the top surface of the contact metal layer 131 facing away from the semiconductor substrate 11, and the front metal layer 135 is disposed on the top surface of the etching stop layer 133 facing away from the contact metal layer 131. The front metal layer 135 has a bottom surface 135B facing the contact metal layer and a side surface 135e connecting the top surface 135T of the front metal layer 135 and the bottom surface 135B of the front metal layer 135; the etching stop layer 133 has a bottom surface facing the contact metal layer 131 and a side surface 133e connecting the bottom surface of the etching stop layer 133 and the top surface of the etching stop layer 133; in the area covered by the contact metal layer 131 from the first surface 11S of the semiconductor substrate 11 (corresponding to Figure 1 The area not covered by the contact metal layer 131 (corresponding to the area of the first surface 11S of the semiconductor substrate 11) is Figure 1 In the direction R of the [uncovered area] shown in FIG. 1 , the side surface 133e of the etching stop layer 133 is closer to the area of the first surface 11S that is not covered by the contact metal layer 131 (corresponding to the side surface 135e of the front metal layer 135). Figure 1The inorganic passivation layer 15 is disposed on the top surface 135T of the front metal layer 135, and sequentially extends to the side surface 135e of the front metal layer 135, the area of the top surface of the etching stop layer 133 not covered by the front metal layer 135, and the area of the first surface 11S not covered by the contact metal layer 131; the second gap Gap2 among the N gaps is located directly above the area of the etching stop layer 133 not covered by the front metal layer 135 to expose a portion of the top surface of the etching stop layer 133. The number of the second gap Gap2 is, for example, one, but the embodiment of the present invention is not limited thereto.
[0056] In some embodiments, see Figure 1 The first gap Gap1 is, for example, disposed close to a first boundary line, where the first boundary line is a boundary line between a side surface 135 e of the front metal layer 135 and a top surface 135T of the front metal layer 135 .
[0057] In some embodiments, see Figure 1 The side surface 131e of the contact metal layer 131 is, for example, aligned with or flush with the second boundary line, where the second boundary line is the boundary line between the side surface 135e of the front metal layer 135 and the bottom surface 135B of the front metal layer 135.
[0058] In some embodiments, see Figure 1 , the side surface 131e of the contact metal layer 131, the side surface 133e of the etching stop layer 133, and the second boundary line (i.e., the boundary line between the side surface 135e of the front metal layer 135 and the bottom surface 135B of the front metal layer 135) are aligned or flush. Furthermore, for example, the contact metal layer 131 may be a NiSi layer, the etching stop layer 133 may be a Ti layer or a TiAl layer, and the front metal layer 135 may be an aluminum (Al) layer, but the embodiment of the present invention is not limited thereto.
[0059] In some embodiments, see Figure 1 The number of the first gaps Gap1 is multiple (for example, two), and the multiple first gaps Gap1 are located in the area covered by the contact metal layer 131 from the first surface 11S of the semiconductor substrate 11 (corresponding to Figure 1 The area not covered by the contact metal layer 131 (corresponding to the area of the first surface 11S of the semiconductor substrate 11) is Figure 1The front metal layer 135 has a first gap Gap1 and a second gap d2 that are spaced apart in the direction R of the [uncovered area] shown in the figure, wherein the distance between the first gap Gap1 closest to the side surface 135e of the front metal layer 135 and the first boundary line (that is, the boundary line between the side surface 135e of the front metal layer 135 and the top surface 135T of the front metal layer 135) is d2; the minimum value of d2 depends on the process limit, and the maximum value is limited by the size of the passivation layer covering the slope. The larger the distance d2 is, the larger the size of the slope passivation layer is, and the higher the possibility of cracking here is. Therefore, the embodiment of the present invention designs d2 to be 100 nanometers to 10 micrometers.
[0060] In some embodiments, the second gap Gap2 should maintain a sufficient distance from the side surface 133e of the etching stop layer 133 to ensure that there is no electric field distribution in the second gap Gap2. Figure 1 , in the area covered by the contact metal layer 131 from the first surface 11S of the semiconductor substrate 11 (corresponding to Figure 1 The area not covered by the contact metal layer 131 (corresponding to the area of the first surface 11S of the semiconductor substrate 11) is Figure 1 In the direction R of the [uncovered area] shown in the figure, the distance between the second gap Gap2 and the side surface 133e of the etching stop layer 133 is d1, and d1 is in the range of 3μm to 7μm, for example, it can be 3μm, 5μm, 7μm, etc.
[0061] In some embodiments, the second gap Gap2 is disposed near the second boundary line (ie, the boundary line between the side surface 135e of the front metal layer 135 and the bottom surface 135B of the front metal layer 135). Figure 1 , in the area covered by the contact metal layer 131 from the first surface 11S of the semiconductor substrate 11 (corresponding to Figure 1 The area not covered by the contact metal layer 131 (corresponding to the area of the first surface 11S of the semiconductor substrate 11) is Figure 1 In the direction R of the [uncovered area] shown in the figure, the distance between the second gap Gap2 and the second boundary line is d3; the minimum value of d3 depends on the process limit, and the maximum value is limited by the size of the passivation layer covering the slope. The larger the distance d3, the larger the size of the slope passivation layer, and the higher the possibility of cracking here. Therefore, the embodiment of the present invention designs d3 to be 100 nanometers to 10 microns.
[0062] In some embodiments, see Figure 2 , the inorganic passivation layer 15 is a ring-shaped structure, and the first gap Gap1 and the second gap Gap2 are located between the inner surface 151e and the outer surface 153e of the inorganic passivation layer 15. Figure 2In the illustrated embodiment, the number of the first gaps Gap1 is two and they are in a closed ring shape, and they are located directly above the front metal layer 135 to expose the portion of the front metal layer 135 that is away from the top surface of the etching stop layer 133; the number of the second gaps Gap2 is one and they are in a closed ring shape, and they are located directly above the area of the etching stop layer 133 that is not covered by the front metal layer 135. Here, it should be noted that the shapes of the first gap Gap1 and the second gap Gap2 can be flexibly designed, as long as the inorganic passivation layer 15 can be divided into two or more independent blocks.
[0063] [Implementation method 2]
[0064] See also FIG. 3A to FIG. 3E The present invention provides a method for manufacturing a semiconductor device, which can be manufactured as follows Figure 1 The semiconductor device 10 shown, for example, includes the following steps.
[0065] First, a semiconductor structure is provided, which can be found in Figure 3A , 3B and Figure 3C , as follows:
[0066] A contact metal layer 131 and an etching stop layer 133 located on the first surface 11S of the semiconductor substrate 11 and away from the first surface 11S of the semiconductor substrate 11 are formed on the first surface 11S of the semiconductor substrate 11 (for example, on the top surface of the first conductive type epitaxial layer 111) by using the same photolithography step and etching step, wherein the contact metal layer 131 forms a Schottky contact or an Ohmic contact with the semiconductor substrate 11 in the subsequent annealing, and the following is obtained: Figure 3A The structure shown;
[0067] Next, a front metal material layer 1350 is formed on the top surface of the etching stop layer 133 away from the contact metal layer 131 and on the area of the first surface 11S of the semiconductor substrate 11 not covered by the contact metal layer 131, so as to obtain Figure 3B The structure shown;
[0068] Afterwards, based on the front metal material layer 1350, a front metal layer 135 is formed on the top surface of the etching stop layer 133 away from the contact metal layer 131; in a direction R (referenced to FIG. 1 ) from the area of the first surface 11S of the semiconductor substrate 11 covered by the contact metal layer 131 to the area of the first surface 11S of the semiconductor substrate 11 not covered by the contact metal layer 131. Figure 1 ), the side surface 133e of the etching stop layer 133 is closer to the area of the first surface 11S of the semiconductor substrate 11 not covered by the contact metal layer 131 relative to the side surface 135e of the front metal layer 135, and the Figure 3CHere, the contact metal layer 131, the etching stop layer 133 and the front metal layer 135 together constitute the electrode layer of the semiconductor structure. It is worth mentioning that the front metal layer 135 is formed by, for example, wet etching or dry etching the front metal material layer 1350, and in this process, the etching stop layer 133 acts as an etching barrier to protect the contact metal layer 131 below from being etched.
[0069] Then, an inorganic passivation layer 15 is formed on the semiconductor structure. Figure 3D and Figure 3E , as follows:
[0070] like Figure 3D As shown, on the top surface of the front metal layer 135 facing away from the contact metal layer 131, on the side surface of the front metal layer 135, on the top surface of the etching stop layer 133 not covered by the front metal layer 135, and on the first surface 11S of the semiconductor substrate 11 (see Figure 3A ) is deposited on the area not covered by the etching stop layer 133; and then the inorganic passivation material layer 150 is patterned by dry etching to form a Figure 3E The inorganic passivation layer 15 shown has N (N is an integer greater than or equal to 1) gaps, wherein the N gaps include a first gap Gap1 and a second gap Gap2, the first gap Gap1 is located directly above the front metal layer 135 to expose the portion of the top surface of the front metal layer 135 that is away from the contact metal layer 131, and the second gap Gap2 is located directly above the area of the etching stop layer 133 that is not covered by the front metal layer 135 to expose the portion of the top surface of the etching stop layer 133 that is away from the contact metal layer 131. It is worth mentioning here that the first gap Gap1 and the second gap Gap2 are formed simultaneously in the step of dry etching the patterned inorganic passivation material layer 150, and the etching stop layer 133 once again acts as an etching barrier to protect the contact metal layer 131 below.
[0071] Afterwards, a protective layer 17 is formed on the surface of the inorganic passivation layer 15 away from the semiconductor substrate 11, wherein the protective layer 17 covers the inorganic passivation layer 15 and extends into the N gaps such as the first gap Gap1 and the second gap Gap2; thus, a semiconductor device such as the semiconductor device 10 can be manufactured. Figure 1 The semiconductor device 10 is shown. It is worth mentioning that the material of the organic layer 17 here can be imide, which can also be called an organic protective layer, which is formed on the surface of the device by spin coating and patterned by photolithography.
[0072] [Implementation method 3]
[0073] See also Figure 4A semiconductor device provided in an embodiment of the present invention, for example, includes: a semiconductor substrate 11, an electrode layer 13, an inorganic passivation layer 15 and a protective layer 17.
[0074] The semiconductor substrate 11 includes, for example, an epitaxial layer 111 of a first conductivity type and one or more implantation regions 112 of a second conductivity type formed in the epitaxial layer 111 of the first conductivity type. Each implantation region 112 extends from the top surface of the epitaxial layer 111 toward the inside of the epitaxial layer 111. When there are multiple implantation regions 112, the multiple implantation regions 112 may be arranged at intervals in the epitaxial layer 111. The aforementioned epitaxial layer 111 may also be referred to as a drift layer. The first conductivity type may be n-type and the second conductivity type may be p-type; or, the second conductivity type may be n-type and the first conductivity type may be p-type. For example, the epitaxial layer 111 of the first conductivity type is, for example, a SiC drift layer, and the implantation regions 112 of the second conductivity type are, for example, regions formed by ion implantation; of course, these implantation regions 112 of the second conductivity type may be partially regions and partially regions. In addition, it is worth mentioning that the semiconductor substrate 11 may also typically have a semiconductor substrate such as a SiC substrate, located at the lower surface of the SiC drift layer. As for the doping concentration and thickness of the semiconductor substrate and the first conductive type epitaxial layer 111, as well as the design of the longitudinal depth, ion implantation concentration, lateral width and lateral spacing of the second conductive type implantation region 112, reference can be made to existing mature technologies, so they will not be repeated here.
[0075] The electrode layer 13 is disposed on the first surface 11S of the semiconductor substrate 11 (e.g., the top surface of the epitaxial layer 111 of the first conductivity type), and includes a contact metal layer 131 and a front metal layer 135. Specifically, the contact metal layer 131 is disposed on the first surface 11S of the semiconductor substrate 11 and forms a Schottky contact or an ohmic contact with the semiconductor substrate 11, for example, a Schottky contact or an ohmic contact with the epitaxial layer 111 of the first conductivity type. The front metal layer 135 is disposed on the top surface of the contact metal layer 131 away from the semiconductor substrate 11.
[0076] The inorganic passivation layer 15 is disposed on the top surface 135T of the front metal layer 135 away from the contact metal layer, and extends to the area of the first surface 11S of the semiconductor substrate 11 not covered by the contact metal layer 131 (corresponding to the Figure 4The inorganic passivation layer 15 is formed with a first gap Gap1 to divide the inorganic passivation layer 15 into a plurality of, for example, two independent blocks. The first gap Gap1 is located directly above the front metal layer 135 to expose a portion of the front metal layer 135 that is away from the top surface 135T of the contact metal layer 131. Furthermore, for example, the inorganic passivation layer 15 can be a silicon oxide (SiOx) layer or a silicon nitride (SiNx) layer, or a multilayer stacked structure of the two, or can be other dielectric material layers, such as a silicon oxynitride (SiNxOy) layer, an aluminum oxide (Al2O3) layer, a hafnium oxide (HfO2) layer, etc.
[0077] Furthermore, the first gap Gap1 is disposed close to the first boundary line (ie, the boundary line between the side surface 135e of the front metal layer 135 and the top surface 135T of the front metal layer 135); Figure 4 As shown, the number of the first gap Gap1 is, for example, one, which is located in the area covered by the contact metal layer 131 from the first surface 11S of the semiconductor substrate 11 (corresponding to Figure 4 The area not covered by the contact metal layer 131 (corresponding to the area of the first surface 11S of the semiconductor substrate 11) is Figure 4 In the direction R of the [uncovered area] shown in the figure, the distance between the first gap Gap1 and the first boundary line is d2, the minimum value of d2 depends on the process limit, and the maximum value is limited by the size of the passivation layer covering the slope. The larger the distance d2 is, the larger the size of the slope passivation layer is, and the higher the possibility of cracking here is. Therefore, the embodiment of the present invention designs d2 to be 100 nanometers to 10 microns. In addition, the side surface 131e of the contact metal layer 131 is aligned or flush with the second boundary line (that is, the boundary line between the side surface 135e of the front metal layer 135 and the bottom surface 135B of the front metal layer 135).
[0078] The protection layer 17 is disposed on the surface of the inorganic passivation layer 15 away from the semiconductor substrate 11 and extends into the first gap Gap1. In addition, for example, the material of the protection layer 17 can be an organic material such as imide.
[0079] and Figure 1 Compared with the semiconductor device 10 shown in the figure, the semiconductor device of the present embodiment does not have a second gap Gap2, and the second gap Gap2 will not be etched and formed in the dry etching patterning step of the corresponding inorganic passivation layer 15, so the dry etching will not corrode the first surface 11S of the semiconductor substrate 11 below the position corresponding to the second gap Gap2, so the etching stop layer 133 can be omitted in this embodiment.
[0080] [Implementation method 4]
[0081] See also FIG. 5A to FIG. 5DThe present invention provides a method for manufacturing a semiconductor device, which can be manufactured as follows Figure 4 The semiconductor device shown, for example, includes the following steps.
[0082] First, a semiconductor structure is provided, which can be found in Figure 5A and Figure 5B , as follows:
[0083] A contact metal layer 131 is formed on the first surface 11S of the semiconductor substrate 11 (for example, the top surface of the first conductive type epitaxial layer 111) by dry etching, wherein the contact metal layer 131 forms a Schottky contact or an Ohmic contact with the semiconductor substrate 11 in the subsequent annealing, and the following is obtained: Figure 5A The structure shown;
[0084] Next, a front metal layer 135 is formed on the top surface of the contact metal layer 131 away from the semiconductor substrate 11; wherein the front metal layer 135 and the contact metal layer 131 are stacked together as the electrode layer 13 of the semiconductor structure, and the following is obtained: Figure 5B It is worth mentioning that the front metal layer 135 is formed by, for example, wet etching or dry etching.
[0085] Then, an inorganic passivation layer 15 is formed on the semiconductor structure. Figure 5C and Figure 5D , as follows:
[0086] An inorganic passivation material layer 150 is deposited on the top surface of the front metal layer 135 facing away from the contact metal layer 131, on the side surface of the front metal layer 135, and on the first surface 11S of the semiconductor substrate 11 not covered by the contact metal layer 131, and then the inorganic passivation material layer 150 is patterned by dry etching to form an inorganic passivation layer 15 having a first gap Gap1, as shown in FIG. Figure 5D In addition, from Figure 5D It can also be known that the first gap Gap1 is located directly above the front metal layer 135 to expose a portion of the front metal layer 135 away from the top surface of the contact metal layer 131 , and the first gap Gap1 is located between the inner surface 151e and the outer surface 153e of the inorganic passivation layer 15 .
[0087] Afterwards, a protective layer 17 is formed on the surface of the inorganic passivation layer 15 that is away from the semiconductor substrate 11, wherein the protective layer 17 covers the inorganic passivation layer 15 and extends into the first gap Gap1; thus, a semiconductor device such as the following can be manufactured: Figure 4 It is worth mentioning that the material of the organic layer 17 here can be imide, which can also be called an organic protective layer, which is formed on the device surface by spin coating and patterned by photolithography.
[0088] [Implementation method 5]
[0089] See also Figure 6 , a semiconductor device provided by an embodiment of the present invention, Figure 1 The semiconductor device 10 shown has a substantially identical structure, except that in this embodiment, the second gap Gap2 is formed only in the inorganic passivation layer 15 directly above the region of the etching stop layer 133 not covered by the front metal layer 135, and the first gap Gap1 is not formed in the inorganic passivation layer 15. Accordingly, the inorganic passivation layer 15 is divided into two independent blocks by the second gap Gap2.
[0090] In addition, if Figure 6 As shown, the second gap Gap2 is arranged near the second boundary line (i.e., the boundary line between the side surface 135e of the front metal layer 135 and the bottom surface 135B of the front metal layer 135), and is located in the area covered by the contact metal layer 131 from the first surface 11S of the semiconductor substrate 11 (corresponding to Figure 6 The area not covered by the contact metal layer 131 (corresponding to the area of the first surface 11S of the semiconductor substrate 11) is Figure 6 In the direction R of the [uncovered area] shown in the figure, the distance between the second gap Gap2 and the second boundary line is d3; the minimum value of d3 depends on the process limit, and the maximum value is limited by the size of the passivation layer covering the slope. The larger the distance d3, the larger the size of the slope passivation layer, and the higher the possibility of cracking here. Therefore, the embodiment of the present invention designs d3 to be 100 nanometers to 10 microns.
[0091] [Implementation method 6]
[0092] See also Figure 7 , a semiconductor device provided by an embodiment of the present invention, Figure 1 The semiconductor device 10 shown in the figure has a substantially same structure, except that: an opening CH is formed in the region of the etching stop layer 133 in the electrode layer 13 of the semiconductor device of the present embodiment that is not covered by the front metal layer 135, and the opening CH extends from the etching stop layer 133 to the contact metal layer 131; and an opening CH is formed in the region covered by the contact metal layer 131 (corresponding to the region covered by the contact metal layer 131) from the first surface 11S of the semiconductor substrate 11. Figure 7 The area not covered by the contact metal layer 131 (corresponding to the area of the first surface 11S of the semiconductor substrate 11) is Figure 7In the direction R of the [uncovered area] shown in the figure, the opening CH is spaced apart from the second gap Gap2; accordingly, the inorganic passivation layer 15 also extends into the opening CH to form a mechanical interlocking structure with the etching stop layer 133, which is beneficial to enhancing the close connection between the inorganic passivation layer 15 and the etching stop layer 133.
[0093] More specifically, the side surface 131e of the contact metal layer 131 is aligned or flush with the side surface 133e of the etching stop layer 133, and the opening CH extends from the top surface of the etching stop layer 133 away from the contact metal layer 131 to the bottom surface of the contact metal layer 131 away from the etching stop layer 133 to expose the first surface 11S of the semiconductor substrate 11 (for example, the top surface of the first conductive type epitaxial layer 111).
[0094] [Implementation method 7]
[0095] See also Figure 8 , a semiconductor device provided by an embodiment of the present invention, Figure 1 The semiconductor device 10 shown has a substantially identical structure, except that: the semiconductor device of the present embodiment further includes a field oxide layer, such as a stacked oxide layer 14, which is disposed on the first surface 11S of the semiconductor substrate 11 and between the inorganic passivation layer 15 and the first surface 11S of the semiconductor substrate 11; wherein the contact metal layer 131 and the etching stop layer 133 both extend between the inorganic passivation layer 15 and the stacked oxide layer 14 to partially overlap with the stacked oxide layer 14 to form a field plate structure. For example, the stacked oxide layer 14 includes, for example, a thermal oxide layer and an interlayer oxide layer deposited on a surface of the thermal oxide layer away from the semiconductor substrate 11, wherein the thermal oxide layer and the interlayer oxide layer may be silicon oxide layers.
[0096] [Implementation method 8]
[0097] See also 9A to 9E The present invention provides a method for manufacturing a semiconductor device, which can be manufactured as follows Figure 8 The semiconductor device shown, for example, includes the following steps.
[0098] First, a semiconductor structure is provided, which can be found in Fig.9A , Fig. 9B and Fig. 9C , as follows:
[0099] A thermal oxide layer is formed on the first surface 11S of the semiconductor substrate 11 (for example, the top surface of the first conductive type epitaxial layer 111) by thermal oxidation, and an interlayer oxide layer is formed on the thermal oxide layer by chemical vapor deposition to obtain a field oxide layer, for example, a stacked oxide layer 14, located on the first surface 11S of the semiconductor substrate 11, thereby obtaining Fig.9A The structure shown;
[0100] Next, a contact metal layer 131 and an etching stop layer 133 located on the top surface of the contact metal layer 131 facing away from the semiconductor substrate 11 are formed on the first surface 11S of the semiconductor substrate 11 by the same photolithography step and etching step, wherein the contact metal layer 131 and the etching stop layer 133 are both extended to overlap with the stacked oxide layer 14 to form a field plate structure, and the contact metal layer 131 forms a Schottky contact or an Ohmic contact with the semiconductor substrate 11 in the subsequent annealing, and the following is obtained: Fig. 9B The structure shown;
[0101] Next, a front metal layer 135 is formed on the top surface of the etching stop layer 133 facing away from the contact metal layer 131; in a direction R (reference direction) from the area of the first surface 11S of the semiconductor substrate 11 covered by the contact metal layer 131 to the area of the first surface 11S of the semiconductor substrate 11 not covered by the contact metal layer 131 Figure 8 ), the side surface 133e of the etching stop layer 133 is closer to the area of the first surface 11S of the semiconductor substrate 11 not covered by the contact metal layer 131 relative to the side surface 135e of the front metal layer 135, and the Fig. 9C The structure shown in FIG. 1 is a semiconductor structure in which the contact metal layer 131, the etching stop layer 133 and the front metal layer 135 together constitute the electrode layer 13 of the semiconductor structure. It is worth mentioning that the front metal layer 135 is formed, for example, by wet etching or dry etching, and in this process, the etching stop layer 133 acts as an etching barrier to protect the contact metal layer 131 below from being etched.
[0102] Then, an inorganic passivation layer 15 is formed on the semiconductor structure. Fig.9D and Fig.9E , as follows:
[0103] like Fig.9D As shown, an inorganic passivation material layer 150 is deposited on the top surface of the front metal layer 135 facing away from the contact metal layer 131, on the side surface of the front metal layer 135, on the top surface of the etching stop layer 133 not covered by the front metal layer 135, and on the first surface 11S of the semiconductor substrate 11 not covered by the etching stop layer 133; and then the inorganic passivation material layer 150 is patterned by dry etching to form a Fig.9EThe inorganic passivation layer 15 shown has N (N is an integer greater than or equal to 1) gaps. The N gaps include, for example, a first gap Gap1 and a second gap Gap2, the first gap Gap1 being located directly above the front metal layer 135 to expose a portion of the top surface of the front metal layer 135 that is away from the etching stop layer 133, and the second gap Gap2 being located directly above the area of the etching stop layer 133 that is not covered by the front metal layer 135 to expose a portion of the top surface of the etching stop layer 133 that is away from the contact metal layer 131. It is worth mentioning here that the first gap Gap1 and the second gap Gap2 are formed simultaneously in the step of dry etching the patterned inorganic passivation material layer 150, and the etching stop layer 133 once again acts as an etching barrier to protect the contact metal layer 131 below.
[0104] Afterwards, a protective layer 17 is formed on the surface of the inorganic passivation layer 15 away from the semiconductor substrate 11, wherein the protective layer 17 covers the inorganic passivation layer 15 and extends into the N gaps such as the first gap Gap1 and the second gap Gap2; thus, a semiconductor device such as the semiconductor device 10 can be manufactured. Figure 8 It is worth mentioning that the material of the organic layer 17 here can be imide, which can also be called an organic protective layer, which is formed on the surface of the device by spin coating and patterned by photolithography.
[0105] In addition, it is worth mentioning that the semiconductor device in the aforementioned embodiment of the present invention may be a diode device or a three-terminal transistor device, and the present invention does not impose any specific limitation thereto.
[0106] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of the technical solution of the present invention.
Claims
1. A semiconductor device, characterized in that: include: Semiconductor substrate; An electrode layer is disposed on the first surface of the semiconductor substrate and forms a Schottky contact or an Ohmic contact with the semiconductor substrate; an inorganic passivation layer, disposed on a surface of the electrode layer away from the semiconductor substrate and extending to a region of the first surface of the semiconductor substrate not covered by the electrode layer, wherein the inorganic passivation layer is formed with N slits to divide the inorganic passivation layer into a plurality of independent blocks, and each of the N slits is located directly above the electrode layer, and N is an integer greater than or equal to 1; and A protective layer is disposed on a surface of the inorganic passivation layer away from the semiconductor substrate and extends into each of the N gaps.
2. The semiconductor device according to claim 1, wherein: In a direction from an area of the first surface covered by the electrode layer to an area of the first surface not covered by the electrode layer, a width of a single slit among the N slits is 1 micrometer to 3 micrometers; and / or, In a direction from an area of the first surface covered by the electrode layer to an area of the first surface not covered by the electrode layer, a distance between two adjacent gaps among the N gaps is 5 micrometers to 50 micrometers.
3. The semiconductor device according to claim 1, wherein: The electrode layer comprises a contact metal layer and a front metal layer, wherein the contact metal layer is disposed on the first surface of the semiconductor substrate and forms the Schottky contact or the Ohmic contact with the semiconductor substrate, and the front metal layer is disposed on the top surface of the contact metal layer away from the semiconductor substrate; The inorganic passivation layer is arranged on the top surface of the front metal layer away from the contact metal layer and extends to the area of the first surface not covered by the contact metal layer, and the N gaps include a first gap, and the first gap is located directly above the front metal layer to expose a portion of the top surface of the front metal layer.
4. The semiconductor device according to claim 3, characterized in that The front metal layer has a bottom surface facing the contact metal layer and a side surface connecting the top surface of the front metal layer and the bottom surface of the front metal layer; The first gap is arranged close to a first boundary line, and the first boundary line is a boundary line between a side surface of the front metal layer and a top surface of the front metal layer; And / or, the contact metal layer has a bottom surface facing the semiconductor substrate and a side surface connecting the bottom surface of the contact metal layer with the top surface of the contact metal layer, and the side surface of the contact metal layer is aligned or flush with a second boundary line, and the second boundary line is the boundary line between the side surface of the front metal layer and the bottom surface of the front metal layer.
5. The semiconductor device according to claim 4, characterized in that The number of the first gap is one, and in the direction from the area of the first surface covered by the contact metal layer to the area of the first surface not covered by the contact metal layer, the distance between the first gap and the first boundary line is 100 nanometers to 10 micrometers; Alternatively, there are multiple first gaps, and the multiple first gaps are spaced apart in a direction from an area of the first surface covered by the contact metal layer to an area of the first surface not covered by the contact metal layer, wherein a distance between the first gap closest to the side surface of the front metal layer and the first boundary line is 100 nanometers to 10 micrometers.
6. The semiconductor device according to claim 3, characterized in that The electrode layer further comprises an etching stop layer, wherein the etching stop layer is located between the contact metal layer and the front metal layer; The front metal layer has a bottom surface facing the contact metal layer and a side surface connecting the top surface of the front metal layer and the bottom surface of the front metal layer; The etching stop layer has a bottom surface facing the contact metal layer, a top surface facing away from the contact metal layer, and a side surface connecting the bottom surface of the etching stop layer and the top surface of the etching stop layer; In a direction from an area of the first surface covered by the contact metal layer to an area of the first surface not covered by the contact metal layer, a side surface of the etch stop layer is closer to the area of the first surface not covered by the contact metal layer than a side surface of the front metal layer; The inorganic passivation layer is disposed on the top surface of the front metal layer and sequentially extends to the side surface of the front metal layer, the area of the top surface of the etching stop layer not covered by the front metal layer, and the area of the first surface not covered by the contact metal layer; The N slits further include a second slit, and the second slit is located directly above a region of the etch stop layer not covered by the front metal layer to expose a portion of a top surface of the etch stop layer.
7. The semiconductor device according to claim 1, wherein: The electrode layer comprises a contact metal layer, an etching stop layer and a front metal layer, wherein the contact metal layer is arranged on the first surface of the semiconductor substrate and forms the Schottky contact or the Ohmic contact with the semiconductor substrate, the etching stop layer is arranged on the top surface of the contact metal layer away from the semiconductor substrate, and the front metal layer is arranged on the top surface of the etching stop layer away from the contact metal layer; The front metal layer has a top surface facing away from the contact metal layer, a bottom surface facing the contact metal layer, and a side surface connecting the top surface of the front metal layer and the bottom surface of the front metal layer; The etch stop layer has a bottom surface facing the contact metal layer and a side surface connecting the bottom surface of the etch stop layer and the top surface of the etch stop layer; In a direction from an area of the first surface covered by the contact metal layer to an area of the first surface not covered by the contact metal layer, a side surface of the etch stop layer is closer to the area of the first surface not covered by the contact metal layer than a side surface of the front metal layer; The inorganic passivation layer is disposed on the top surface of the front metal layer and sequentially extends to the side surface of the front metal layer, the area of the top surface of the etching stop layer not covered by the front metal layer, and the area of the first surface not covered by the contact metal layer; The N slits include a second slit, and the second slit is located directly above a region of the etch stop layer not covered by the front metal layer to expose a portion of a top surface of the etch stop layer.
8. The semiconductor device according to claim 6 or 7, characterized in that: From the first In a direction from an area of the surface covered by the contact metal layer to an area of the first surface not covered by the contact metal layer, a distance between the second gap and a side surface of the etching stop layer is 3 micrometers to 7 micrometers.
9. The semiconductor device according to claim 6 or 7, characterized in that: The second gap The second boundary line is disposed near a second boundary line, where the second boundary line is a boundary line between a side surface of the front metal layer and a bottom surface of the front metal layer; In a direction from an area of the first surface covered by the contact metal layer to an area of the first surface not covered by the contact metal layer, a distance between the second gap and the second boundary line is 100 nanometers to 10 micrometers.
10. The semiconductor device according to claim 6 or 7, characterized in that: The etch stop An opening is formed in an area of the layer not covered by the front metal layer, the opening extends from the etching stop layer to the contact metal layer, and the inorganic passivation layer extends into the opening; The second slit is spaced apart from the opening in a direction from an area of the first surface covered by the contact metal layer to an area of the first surface not covered by the contact metal layer.
11. The semiconductor device according to claim 10, characterized in that The contact metal layer The side surface of the contact metal layer is aligned with or flush with the side surface of the etch stop layer, and the opening extends from the top surface of the etch stop layer to the bottom surface of the contact metal layer away from the etch stop layer to expose a portion of the first surface.
12. The semiconductor device according to claim 6 or 7, characterized in that: Also includes layered oxygen The inorganic passivation layer is disposed on the first surface of the semiconductor substrate and is located between the inorganic passivation layer and the first surface of the semiconductor substrate; wherein the contact metal layer and the etching stop layer both extend between the inorganic passivation layer and the stacked oxide layer to partially overlap with the stacked oxide layer to form a field plate structure.
13. A method for manufacturing a semiconductor device, characterized in that: include: A semiconductor structure is provided, wherein the semiconductor structure comprises a semiconductor substrate and an electrode layer, wherein the electrode layer is disposed on a first surface of the semiconductor substrate and forms a Schottky contact or an Ohmic contact with the semiconductor substrate; forming an inorganic passivation layer on the semiconductor structure, wherein the inorganic passivation layer is formed on a surface of the electrode layer away from the semiconductor substrate and extends to a region of the first surface of the semiconductor substrate not covered by the electrode layer, the inorganic passivation layer is formed with N gaps to divide the inorganic passivation layer into a plurality of independent blocks, and each of the N gaps is located directly above the electrode layer, and N is an integer greater than or equal to 1; and A protection layer is formed on a surface of the inorganic passivation layer facing away from the semiconductor substrate, wherein the protection layer extends into each of the N gaps.