SiC MOSFET gate oxide layer degradation monitoring method based on turn-off oscillation

Abstract

The invention discloses a SiC MOSFET gate oxide layer degradation monitoring method based on turn-off oscillation, and the method comprises the steps: measuring the drain-source current change rate diDS / dt when a SiC MOSFET is turned off through the source stray inductance voltage vcir, and carrying out the measurement of the gate oxide layer degradation of the SiC MOSFET based on the offset of the negative temperature sensitivity of the threshold voltage VTH in the diDS / dt and the positive temperature sensitivity of the electron mobility mu. Zero temperature sensitivity of a source stray inductance voltage negative peak value vcircmin is realized by adjusting a driving resistor RG and a negative voltage VEE during turn-off, and the gate oxide layer degradation degree of the SiC MOSFET is monitored under a selected monitoring driving resistor RGM and a turn-off gate voltage VEEM. The monitoring method is high in universality and has a good monitoring effect on degradation of gate oxide layers of SiC MOSFETs of different models; the temperature influence is extremely small, so that the device can work in an environment with large temperature fluctuation; a pin of a monitored device does not need to be used as a measurement interface, so that the system invasiveness is small; the parameter measurement methods are many and mature; and the method has great online application potential.

Description

Technical Field

[0001] The present invention relates to the technical field of power semiconductor devices, and in particular to a method for monitoring gate oxide layer degradation of a SiC MOSFET based on source stray inductance voltage turn-off oscillation. Background Art

[0002] As a typical representative of the third generation wide bandgap power semiconductor devices, SiC MOSFET is widely used in new energy, automobile, consumer electronics and other fields with its advantages of fast switching speed and low conduction loss. Now it is gradually replacing Si-based devices in high power and high power density occasions. However, due to the immature process, the near-interface state density of the gate oxide layer of SiC MOSFET is much greater than that of Si devices. At the same time, the stress of high temperature and high field strength of SiC MOSFET combined with the high near-interface state density leads to the problem of threshold voltage instability in SiC MOSFET. When the gate is stressed, the channel carriers will be captured by near-interface traps through the tunneling effect, causing the threshold voltage to drift. Usually, the accumulation of negative charge captured by the trap will cause the threshold voltage to drift positively, while the accumulation of positive charge will cause negative drift. The positive drift of the threshold voltage will cause the on-resistance of SiC MOSFET to increase, the turn-on speed to slow down, and the parameters to gradually mismatch when connected in parallel. The negative drift will increase the risk of crosstalk mismatch. Therefore, it is necessary to monitor the degree of degradation of the gate oxide layer of SiC MOSFET to improve the reliability of the system, especially in occasions with high reliability requirements such as automobiles and aerospace.

[0003] The existing methods for monitoring the state of the gate oxide layer of SiC MOSFET mainly monitor the changes in electrical parameters caused by direct or indirect threshold voltage drift or the changes in parameters caused by device structure changes such as gate leakage current and junction capacitance. The threshold voltage directly reflects the problem of threshold voltage bias temperature instability, and changes significantly when the gate oxide layer degrades, but the threshold voltage itself is closely related to temperature and has good temperature sensitivity. Therefore, it is difficult to accurately monitor the degree of gate oxide layer degradation when the temperature changes in practical applications. In addition, both static and dynamic measurements of threshold voltage require high-precision sensors, resulting in high sampling costs. The parameter changes indirectly caused by threshold voltage offset include parameters such as on-resistance, body diode voltage drop, drain-source current change rate, Miller platform voltage and duration. Due to the good temperature sensitivity of threshold voltage, these parameters cannot exclude the interference of junction temperature. Although the gate leakage current has extremely low temperature sensitivity, it only changes at the mA level when the gate is about to be broken down, which is only suitable for early warning. The junction capacitance has extremely low temperature sensitivity, but it is difficult to sample. In addition, these state detection methods require the pin of the detection object as a sampling interface, which is somewhat invasive to the system. Summary of the invention

[0004] In view of the above-mentioned deficiencies in the prior art, the object of the present invention is to provide a SiC MOSFET gate oxide layer degradation monitoring method based on source stray inductance voltage turn-off oscillation, so as to solve the problems that the existing status monitoring method cannot eliminate temperature interference, is difficult to detect and is highly invasive.

[0005] To achieve the above object, the present invention adopts the following technical solution:

[0006] A method for monitoring gate oxide degradation of SiC MOSFET based on off-oscillation, characterized in that the source stray inductance voltage v cir Measuring the drain-source current change rate di when SiC MOSFET is turned off DS / dt, based on di DS / dt threshold voltage V TH The negative temperature sensitivity of and the positive temperature sensitivity of the electron mobility μ are offset by adjusting the drive resistance R G and negative pressure V EE Realize the negative peak value of the source stray inductance voltage v cir_min Zero temperature sensitivity and the selected monitoring drive resistor R G_M and the turn-off gate voltage V EE_M The degradation degree of SiC MOSFET gate oxide layer is monitored under the condition of negative peak value v of source stray inductance voltage. cir_min The degree of change can determine the health status of the gate oxide layer.

[0007] Further, the following steps are specifically included: Generally, SiC MOSFET works in normal R G and V EE Next; switch R regularly G and V EE R designed for monitoring G_M and V EE_M , and measure the negative peak value of the source stray inductance voltage v cir_min and the negative peak value of the source stray inductance voltage v in the healthy state cir_min Compare;

[0008] If v cir_min If it decreases, it is judged that the detected SiC MSOFET has positive bias temperature instability, otherwise it is negative bias temperature instability.

[0009] Since the gate oxide layer degrades into a long time scale aging mechanism, v cir_min The measurement cycle can be set to a longer time, such as any time from 10 hours to 100 hours. Therefore, the proposed monitoring method has little impact on the normal operation of SiC MOSFET.

[0010] See also Figure 7, which is the basic logic diagram (principle) of the gate oxide layer degradation monitoring method of the present invention. cir_min The degree of change is analyzed as a mechanism for evaluating the health status of the gate oxide layer of the SiC MOSFET being tested as follows.

[0011] Source stray inductance voltage negative peak value v cir_min The negative peak value of the induced voltage caused by the turn-off current change in the source stray inductance is expressed by the following formula:

[0012]

[0013] Among them, I L is the load current; v GS is the external gate-source voltage; V TH is the device threshold voltage; μ is the channel carrier mobility; W CH is the channel width; L CH is the channel length; C OX is the gate oxide capacitance per unit area; C ciss is the gate input capacitance; R G is the turn-off driving resistor; V EE is the turn-off gate voltage; L s is the common source parasitic inductance; L cir is the source stray inductance. When the gate oxide layer of SiC MOSFET degrades, it will cause the threshold voltage V TH drift, which leads to v cir_min changes, so v cir_min It can be used as a characteristic quantity to diagnose the degradation of SiC MOSFET gate oxide layer.

[0014] Source stray inductance voltage negative peak value v cir_min The threshold voltage V TH Negatively correlated with temperature; v cir_min The channel carrier mobility μ in the gate voltage is mainly determined by the Coulomb scattering mechanism when the gate voltage is low, so the Coulomb scattering mobility μ C The total mobility μ plays a dominant role, while the Coulomb scattering mobility μ C Positively correlated with temperature, V TH and μ C There is a counteracting effect with changes in temperature;

[0015] Threshold voltage V TH It can be expressed as:

[0016]

[0017] Among them, ψ B is the Fermi potential; T j is the junction temperature of SiC MOSFET;SiC is the dielectric constant of 4H-SiC; q is the basic charge; k is the Boltzmann parameter; N A is the p-region doping concentration, and its relationship with temperature can be expressed as:

[0018]

[0019] Among them, N C is the intrinsic excited carrier concentration, since usually N C Much larger than N A , so the threshold voltage V TH It shows negative temperature sensitivity.

[0020] μ C It can be expressed as:

[0021]

[0022] Where N is the model fitting parameter; α, β are model parameters, which are usually set to 1 in 4H-SiC; Q trap ,Q inv are the trapped charge near the interface and the charge concentration in the inversion layer, respectively; μ C The influence of temperature can be expressed as:

[0023]

[0024] Therefore, the channel carrier mobility μ is positively correlated with temperature.

[0025] Source stray inductance voltage negative peak value v cir_min The relationship with temperature can be described as:

[0026]

[0027] in

[0028]

[0029] Therefore, the negative peak value of the source stray inductance voltage v cir_min The relationship between the temperature and the turn-off drive resistance R G and negative pressure V EE Influence, by adjusting R G and V EE Can achieve v cir_min Zero temperature sensitivity can be achieved to realize the state monitoring of SiC MOSFET gate oxide layer degradation without temperature interference.

[0030] Compared with the prior art, the present invention has the following beneficial effects:

[0031] 1. The present invention creatively proposes to turn off the negative peak value v of the stray inductance voltage of the circuitcir_min Modeling analysis shows that the threshold voltage V will decrease with the degradation of the gate oxide layer. TH Therefore, it can be used as a characteristic quantity for monitoring the state of gate oxide layer degradation. In addition, by measuring the negative peak value of the source stray inductance voltage v cir_min The temperature-dependent V TH The temperature sensitivity modeling analysis of μ and μ obtains the negative peak value of the source stray inductance voltage v cir_min The temperature sensitivity model of the turn-off drive resistor R is proposed by analyzing the model. G and negative pressure V EE Realize the negative peak value of the source stray inductance voltage v cir_min Zero temperature sensitivity can realize the state monitoring of SiCMOSFET gate oxide layer degradation without temperature interference.

[0032] 2. This monitoring method is highly versatile and has a good monitoring effect on the gate oxide layer degradation of different types of SiC MOSFETs. It does not require the pins of the monitored device as a measurement interface, but only requires a section of the current loop as a monitoring interface, so it is extremely intrusive to the system. The measurement interface of this method does not need to directly contact the pins of the monitored device. For hardware circuits that have been designed, this method can also change the original design structure to the minimum extent; and by sampling the busbar stray inductance, it can save measurement costs in systems where multiple SiC MOSFETs are working.

[0033] 3. This gate oxide layer degradation state monitoring method is minimally affected by temperature, which is conducive to working in an environment with large temperature fluctuations; when the device junction temperature or ambient temperature changes, the gate oxide layer degradation degree can still be accurately monitored. The parameter measurement methods are numerous and mature; it has great potential for online application.

[0034] 4. State characteristic quantity v used in the gate oxide layer degradation state monitoring method cir_min The measurement is simple. It can be measured using loop stray inductance, or using existing mature solutions such as Rogowski coils and mutual inductance. The use of a peak hold circuit can greatly reduce the bandwidth requirements for sampling. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 The sampling interface of the present invention and the SiC MOSFET shutdown process; wherein, (a) is a schematic diagram of the sampling interface; (b) is the gate voltage v during the shutdown process GS , drain-source voltage v DS and current i DS and source stray inductance voltage v cir Theoretical change diagram;

[0036] Figure 2 is the v of Example 1 under double pulse test (600V, 20A) cir_min In VEE_M Temperature sensitivity and R G Test waveform of

[0037] Figure 3 is the threshold voltage V of the embodiment 1 of the present invention TH Test waveforms in high temperature gate bias experiments;

[0038] Figure 4 is the v of Example 1 of the present invention in the double pulse test (600V, 20A) cir_min The changes in the gate oxide layer degradation experiment and the experimental waveform with temperature; where (a) is v cir Changes with the degradation of the gate oxide layer; (b) is v cir_min Varies with gate oxide degradation and temperature;

[0039] Figure 5 The experimental waveform of Example 2 of the present invention under the double pulse test (600V, 20A); wherein (a) is R G_M Select the test waveform; (b) is the V of Example 2 TH Test waveform in high temperature gate bias experiment; (c) is v cir Experimental waveform with gate oxide layer degradation; (d) is v cir_min Experimental waveforms with gate oxide degradation and temperature variation;

[0040] Figure 6 The experimental waveform of Example 3 of the present invention under the double pulse test (600V, 20A); wherein (a) is R G_M Select the test waveform; (b) is the V of Example 3 TH Test waveform in high temperature gate bias experiment; (c) is v cir Experimental waveform with gate oxide layer degradation; (d) is v cir_min Experimental waveforms with gate oxide degradation and temperature variation;

[0041] Figure 7 It is a basic logic diagram of the gate oxide layer degradation monitoring method of the present invention. DETAILED DESCRIPTION

[0042] The present invention is further described in detail below with reference to the accompanying drawings and embodiments.

[0043] The present invention provides a method for monitoring the gate oxide layer degradation of SiC MOSFET based on the turn-off oscillation of the source stray inductance voltage, and uses the negative peak value v of the source stray inductance voltage to monitor the gate oxide layer degradation of SiC MOSFET. cir_min The degree of change is used as the basis for evaluating the health status of the gate oxide layer of the SiC MOSFET being tested, and the source stray inductance voltage v cir Measuring the drain-source current change rate di when SiC MOSFET is turned off DS / dt, based on di DS / dt threshold voltage V TH The negative temperature sensitivity of and the positive temperature sensitivity of the electron mobility μ are offset by adjusting the drive resistance R G and negative pressure V EE Realize the negative peak value of the source stray inductance voltage v cir_min Zero temperature sensitivity and the selected monitoring drive resistor R G_M and the turn-off gate voltage V EE_M Monitoring the degradation of SiC MOSFET gate oxide layer.

[0044] Choose a periodic switching drive resistor voltage R G_M and V EE_M And measure the negative peak value of the source stray inductance voltage v cir_min , if v cir_min If the gate oxide layer is degraded, the gate oxide layer is determined to have changed. cir_min The degree of change can determine the health status of the gate oxide layer.

[0045] The specific steps include: Generally, SiC MOSFET works in normal R G and V EE Next; switch R regularly G and V EE R designed for monitoring G_M and V EE_M And measure the negative peak value of the source stray inductance voltage v cir_min , and v in a healthy state cir_min Compare, if v cir_min If it decreases, it is judged that the detected SiC MSOFET has positive bias temperature instability; otherwise, it is negative bias temperature instability.

[0046] Since the gate oxide layer degrades into a long time scale aging mechanism, v cir_min The measurement period can be set to a longer time, so the proposed monitoring method has little impact on the normal operation of SiC MOSFET.

[0047] See also Figure 1 (a) is a schematic diagram of the SiC MOSFET circuit model and sampling interface. Its measurement interface does not need to directly contact the pins of the monitored device, but only needs to take a section of the current loop as the monitoring interface, so it is minimally invasive to the system.

[0048] Figure 1 (b) is the theoretical change diagram of voltage and current during the shutdown process. The tested parameter v cir_min It is generated by the change of drain-source current during the turn-off process. The state characteristic quantity v is measured using the loop stray inductance cir_min Indirect measurement DSThe minimum value of / dt realizes the monitoring of gate oxide layer degradation state. It can be seen that this method is simple to measure and has low invasiveness.

[0049] The present invention measures the minimum value v of the stray inductance voltage of the shut-off loop cir_min Implementing a temperature-independent SiC MOSFET gate oxide degradation monitoring method, v cir_min It can be expressed as

[0050]

[0051] The gate oxide layer will cause the threshold voltage V TH Drift thus causing v cir_min changes, so v cir_min It can be used as a state characteristic quantity to monitor the degradation of SiCMOSFET gate oxide layer. cir_min The threshold voltage V is mainly affected by temperature. TH and electron mobility μ, the temperature sensitivity of both can be expressed as

[0052]

[0053] So v cir_min The temperature sensitivity of

[0054]

[0055] According to the analysis, v cir_min The temperature sensitivity and V EE and R G Related, rewrite v cir_min The temperature sensitivity of

[0056]

[0057] Therefore, by changing V EE and R G Implement v cir_min Zero temperature sensitivity, thus achieving gate oxide layer status monitoring without temperature influence.

[0058] The method of the present invention is verified in the double pulse test, which is considered to be able to accurately reproduce the transient waveform of SiC MOSFET under a given load current and bus voltage. Take a section of the current loop at the negative pole of the test circuit as the test interface. The stray inductance of this section of the loop is L cir .

[0059] Example 1

[0060] The double pulse test and parameters of the device under test for the SiC MOSFET model C3M0040120D are shown in Table 1:

[0061] Table 1 Experimental parameters

[0062]

[0063] Monitor the selected V EE should be as large as possible to meet the needs of more SiC MOSFETs, and a larger V EE_M The corresponding R G_M smaller, making |v cir_min | is larger, reducing the difficulty of measurement. However, if V EE_M This may cause gate failure and increase the risk of breakdown caused by drain-source overvoltage at turn-off. Therefore, the minimum turn-off negative voltage recommended by the product data sheet provided by the manufacturer of the device being tested is selected as V EE_M The C3M0040120D data sheet recommends a minimum negative voltage of -8V, so V EE_M =8V. At V EE_M Down cir_min The temperature sensitivity and drive resistance R G The relationship is as Figure 2 shown.

[0064] according to Figure 2 It can be seen that when R G =24Ω when v cir_min It shows zero temperature sensitivity. Therefore, R G_M =24Ω.

[0065] In order to verify the effectiveness of this method when the gate oxide layer is degraded, a high-temperature gate bias experiment is performed on the device under test to achieve gate oxide layer degradation. The high-temperature gate bias selection applies 32V DC stress and 150℃ temperature stress to the gate of the device under test, and shorts the source and drain of the device under test at the same time. Figure 3 The threshold voltage V of two experimental devices from the same batch under high temperature gate bias is shown. TH The V of device 1 and device 2 under 42 hours stress TH They increased by 48.88% and 54.38% respectively, proving that gate oxide degradation occurred in the device under test.

[0066] Figure 4 Shown in V EE_M =8V, R G_M =24Ω, the v of the two devices under test cir_min The changes of the accumulated time of high temperature gate bias test and the v cir_min Experimental waveforms with temperature (25℃-150℃). V of device 1 and device 2 under 42 hours of stress cir_min The temperature decreased by 6.55% and 7.09% respectively, making the v cir_min The maximum change was 0.103%. Figure 4 It can be seen that in VEE_M =8V, R G_M =24Ω, the gate oxide degradation caused by v cir_min The change is much greater than the change caused by temperature, so it can be considered that the invented condition monitoring method has eliminated the influence of temperature.

[0067] Example 2

[0068] The minimum gate voltage of the SiC MOSFET model C3M0032120D is specified in the data sheet as -8V, so V EE_M =8V. Figure 5 (a) shows V EE_M =8V, C3M0032120D's v cir_min The temperature sensitivity of R G The test results show that when R G When v is 20Ω cir_min It has zero temperature sensitivity, so R G_M =20Ω. Figure 5 (b) shows the threshold voltage V of the C3M0032120D device in the high temperature gate bias test. TH The test results, Figure 5 (c) shows the v cir Experimental waveform with gate oxide layer degradation time, Figure 5 (d) shows the v cir_min Experimental waveforms of gate oxide degradation over time and temperature.

[0069] Example 3

[0070] The minimum gate voltage of the SiC MOSFET model C3M0021120D is specified in the data sheet as -8V, so V EE_M =8V. Figure 6 (a) shows V EE_M =8V, C3M0021120D's v cir_min The temperature sensitivity of R G The test results show that when R G When v is 8.2Ω cir_min It has zero temperature sensitivity, so R G_M =8.2Ω. Figure 6 (b) shows the threshold voltage V of the C3M0021120D device in the high temperature gate bias test. TH The test results, Figure 6 (c) shows the v cir Experimental waveform with gate oxide layer degradation time, Figure 6 (d) shows the v cir_minExperimental waveforms of gate oxide degradation over time and temperature.

[0071] The quantitative data of the test results of Example 2 and Implementation 3 are shown in Table 2.

[0072] Table 2 Experimental results of Example 2 and Example 3

[0073]

[0074]

[0075] As can be seen from Table 2, the gate oxide layer degradation state monitoring method of the present invention can accurately monitor the degradation degree of various types of SiC MOSFETs when the gate oxide layer is degraded, and the interference caused by temperature is much smaller than the change caused by the gate voltage layer degradation. Due to differences in device structure, the monitoring conditions of different devices may be different and need to be adjusted in advance.

[0076] It can be seen from the results of Example 1, Example 2 and Example 3 that the gate oxide layer degradation monitoring method of SiC MOSFET based on off-oscillation according to the present invention can effectively realize the gate oxide layer degradation state monitoring excluding the temperature influence in various types of SiC MOSFET, and the measurement is simple and the intrusion to the system is small, which makes up for the shortcoming that the current SiC MOSFET state monitoring method cannot accurately monitor the degree of gate oxide layer degradation under the conditions of large temperature changes or large load fluctuations.

[0077] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit the technical solution. Those skilled in the art should understand that those modifications or equivalent substitutions of the technical solution of the present invention that do not depart from the purpose and scope of the technical solution should be included in the scope of the claims of the present invention.

Claims

1. A method for monitoring gate oxide degradation of SiC MOSFET based on off-oscillation, characterized in that: Using the source stray inductance voltage v cir Measuring the drain-source current change rate d when SiC MOSFET is turned off i DS / d t , based on d i DS / d t Middle threshold voltage V TH Negative temperature sensitivity and electron mobility m The positive temperature sensitivity is offset by adjusting the drive resistance during shutdown. R G and negative pressure V EE Realize the negative peak value of the source stray inductance voltage v cir_min Zero temperature sensitivity and the selected monitoring drive resistor R G_M and turn-off gate voltage V EE_M The degradation degree of SiC MOSFET gate oxide layer is monitored according to the negative peak value of source stray inductance voltage. v cir_min The degree of change can determine the health status of the gate oxide layer.

2. The method for monitoring gate oxide degradation of SiC MOSFET based on off-oscillation according to claim 1, characterized in that: The following steps are included: Generally, SiC MOSFET works in normal R G and V EE Next; switch regularly R G and V EE Designed for monitoring R G_M and V EE_M , and measure the negative peak value of the source stray inductance voltage v cir_min and the negative peak value of the source stray inductance voltage under healthy conditions v cir_min Compare; like v cir_min If it decreases, it is judged that the detected SiC MSOFET has positive bias temperature instability, otherwise it is negative bias temperature instability.

3. The method for monitoring gate oxide layer degradation of SiC MOSFET based on off-oscillation according to claim 1, characterized in that: As the gate oxide layer degrades into a long-term aging mechanism, the negative peak value of the source stray inductance voltage v cir_min The measurement period can be set to any time between 10 hours and 100 hours, so the proposed monitoring method has little impact on the normal operation of SiC MOSFET.

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