Radar processing module test system

Abstract

The invention provides a radar processing module test system, and belongs to the technical field of lightning protection, and the test system comprises a test tool which is used as a carrier plate for testing a processing module and is used for providing high-speed PCIE bus interface test resources; and the hardware core machine is used for integrating the test function module and the main control unit, test software is configured in the main control unit, the test software adopts a layered architecture design, and the test software with the layered architecture comprises an application layer, a network layer and a virtual driving layer. The radar processing module test system provided by the invention adopts test software with a layered architecture, and has the attributes of flexibility, high reusability and high expansibility, and a test program is independent of a test component. When the test assembly needs to be replaced, a new instrument driving program can be used under the condition that the test program is kept unchanged, so that the total cost of creating and maintaining the test program is reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of lightning protection, and in particular relates to a radar processing module testing system. Background Art

[0002] In recent years, the performance requirements of airborne radar equipment have continued to increase, and the design complexity of radar has also continued to increase. In order to meet the radar's large-scale data transmission needs, radar processing modules often have multiple external bus interfaces. In terms of bandwidth, they cover low-speed and high-speed interfaces; in terms of signal type, they involve electrical interfaces and optical interfaces, which puts higher requirements on the testing capabilities of radar processing modules.

[0003] The traditional processing module testing solution requires various types of professional testing equipment. Testers need to set up a physical testing environment and manually write test cases. This solution is costly, time-consuming, labor-intensive, and error-prone. The testing process is relatively repetitive and cumbersome, and it is even more difficult to provide support for field test troubleshooting.

[0004] There is an urgent need to develop a radar processing module testing device with high integration and efficient testing, which can realize automatic testing of processing modules with fewer testing resources and a relatively simple testing process, meet the hardware full life cycle testing requirements of module debugging and testing, subsystem integration and verification, and meet the support requirements of field maintenance and training exercises. Summary of the invention

[0005] In order to solve the above problems, the purpose of the present invention is to provide a radar processing module testing system, which adopts a universal and flexible design concept, constructs modular test resources and standardized test interfaces, realizes the soft definition of universal hardware test environment, test cases and hardware universal test interfaces, and realizes the automatic judgment and analysis and statistics of test results.

[0006] In order to achieve the above object, the present invention provides the following technical solution, a radar processing module testing system, the testing system comprising:

[0007] A test fixture, used as a carrier board for processing module testing and for providing high-speed PCI E bus interface test resources; and

[0008] Hardware core machine, used to integrate test function modules and main control unit,

[0009] The main control unit is equipped with test software.

[0010] The test software adopts a layered architecture design, and the layered architecture test software includes an application layer, a network layer and a virtual driver layer.

[0011] The radar processing module test system provided by the present invention also has the following characteristics: the test fixture includes a base, an aviation plug fixed on the base, and a PCB printed board.

[0012] The front side of the PCB is provided with a VPX connector connected to the processing module and a switch button for controlling the working mode selection of the processing module.

[0013] The back of the PCB is provided with an ARM processor for information interaction with external test equipment, an FPGA for exchanging working mode information with the ARM processor and for PCI E bus communication with the processing module, and a PCI E switch matrix for receiving commands sent by the ARM processor to control the on / off of channels between the FPGA and the processing module.

[0014] The radar processing module test system provided by the present invention also has the following characteristics: the ARM processor is used to test ICD interaction, interface configuration management, test timing control, transmission and reception success rate statistics, error information reporting and internal temperature control of the test tooling.

[0015] The radar processing module test system provided by the present invention also has the following feature: the FPGA module loads the configuration logic of EP or RC in the multi-version configuration program under the control of the ARM processor.

[0016] The radar processing module test system provided by the present invention also has the following characteristics: the PC IE switch matrix includes a plurality of PC IE single-pole double-throw switches, and the plurality of PC IE single-pole double-throw switches form a tree structure with an input end as a root node and an output end as a plurality of branch nodes.

[0017] The input end of the tree-structured PC IE switch matrix is ​​connected to the PC IE channel of the FPGA, and the multiple branch nodes at the output end are respectively connected to the processing modules.

[0018] The on and off of the multiple branch nodes of the tree structure are controlled by an ARM processor.

[0019] The radar processing module test system provided by the present invention also has the following characteristics: the hardware core machine includes a main control unit, a PC IE switching bridge, a multi-protocol serial port module, an ARI NC429 bus communication module, an avionics FC communication module, an optical fiber communication module, an ARI NC818 video conversion module, a video acquisition module and an Ethernet module.

[0020] The radar processing module test system provided by the present invention also has the following feature: the PC IE switching bridge provides 8 installation slots for functional modules and 4 PC IE expansion slots.

[0021] The radar processing module testing system provided by the present invention also has the following characteristics: the application layer is used to provide a graphical editing interface for test cases, to provide breakpoint debugging and operation control interface for test cases, to provide a query and analysis interface for test data, and to provide a test report generation and saving interface.

[0022] The radar processing module testing system provided by the present invention also has the following feature: the network layer uses distributed real-time communication middleware to define a global data space, and the global data space is used for data exchange between the application layer and the virtual driver layer.

[0023] The radar processing module test system provided by the present invention also has the following characteristics: the virtual driver layer is used for the test resource drive of the test system, receives instructions from the application layer through the network layer, performs tests according to the instructions, and outputs them.

[0024] The virtual driver layer is also used to receive feedback from the test resource and transmit the feedback to the application layer through the network layer.

[0025] Beneficial Effects

[0026] The radar processing module test system provided by the present invention adopts a layered architecture test software, which has the properties of flexibility, strong reusability and high scalability, and the test program is independent of the test component. When the test component needs to be replaced, a new instrument driver can be used while the test program remains unchanged, thereby reducing the overall cost of creating and maintaining the test program.

[0027] The radar processing module test system provided by the present invention adopts a PC IE bus test solution based on the "FPGA+ARM+PC IE bus signal switch matrix" architecture, which can fully utilize the high real-time characteristics of FPGA to meet the real-time requirements of PC IE high-speed bus testing, and can also use the ARM processor to realize test process control. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0029] Figure 1 A hardware architecture diagram of a radar processing module testing device provided in an embodiment of the present invention;

[0030] Figure 2 A software architecture diagram of a radar processing module testing device provided in an embodiment of the present invention;

[0031] Figure 3 A schematic diagram of the structure of a radar processing module testing device provided in an embodiment of the present invention;

[0032] Figure 4 This is a PC IE high-speed bus test implementation scheme in an embodiment of the present invention;

[0033] Figure 5 The figure is a schematic diagram of the switching principle of the PC IE high-speed bus test signal in an embodiment of the present invention. DETAILED DESCRIPTION

[0034] The present invention is further described in detail below in conjunction with the accompanying drawings and examples, but it should be noted that these implementation modes are not limitations of the present invention, and any equivalent transformations or substitutions in functions, methods, or structures made by ordinary technicians in the field based on these implementation modes are all within the scope of protection of the present invention.

[0035] In the description of the embodiments of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the invention.

[0036] In addition, the terms "first", "second", "third", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", etc. may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0037] The terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the invention can be understood according to specific circumstances.

[0038] like Figure 1-Figure 5As shown, an embodiment of the present invention provides a radar processing module test system, which includes: a test tool, which is used as a carrier board for processing module testing and is used to provide high-speed PC IE bus interface test resources; and a hardware core machine, which is used to integrate test function modules and a main control unit. The main control unit is configured with test software, and the test software adopts a layered architecture design. The layered architecture test software includes an application layer, a network layer and a virtual driver layer.

[0039] In the above embodiment, a VPX slot is installed on the front of the test tooling base plate to realize the functions required by the test tooling. The back of the test tooling base plate integrates ARM, FPGA, PCI E switching switch and other modules. The multi-channel PCIEx4 bus signals derived from the processing module are connected to the PCI Ex4 interface of the FPGA through the PC IE bus signal switch matrix.

[0040] In some embodiments, the test tooling includes a base, an aviation plug fixed on the base, and a PCB printed board. The front side of the PCB printed board is provided with a VPX connector connected to the processing module and a switch button for controlling the working mode selection of the processing module. The back side of the PCB printed board is provided with an ARM processor for interacting with external test equipment, an FPGA for exchanging working mode information with the ARM processor and communicating with the processing module via the PCI E bus, and a PCI E switch matrix for receiving commands issued by the ARM processor to control the on / off of channels between the FPGA and the processing module.

[0041] In the above embodiment, FPGA serves as the core processor of the processing module PCI E high-speed bus test device, is responsible for completing data communication with the processing module, and realizes the test of PCI E bus signal link status, rate and data transmission.

[0042] In some embodiments, the ARM processor is used to test ICD interaction, interface configuration management, test timing control, transmission and reception success rate statistics, error information reporting, and internal temperature control of the test fixture. In the above embodiment, the ARM processor serves as the main controller of the PCI E high-speed bus test device and communicates with external test equipment through the LAN bus.

[0043] In some embodiments, the FPGA module loads the configuration logic of EP or RC in the multi-version configuration program under the control of the ARM processor. The FPGA module can load the configuration logic of EP or RC in the multi-version configuration program under the control of the ARM processor to match the PCI E bus configuration of the processing module.

[0044] In some embodiments, the PCI E switch matrix includes multiple PCI E single-pole double-throw switches, and the multiple PCI E single-pole double-throw switches form a tree structure with an input end as a root node and an output end as multiple branch nodes. The input end of the PCIE switch matrix with the tree structure is connected to the PCI E channel of the FPGA, and the multiple branch nodes at the output end are respectively connected to the processing modules. The on and off of the multiple branch nodes of the tree structure are controlled by the ARM processor.

[0045] In some embodiments, TI's DS160PR412 / DS160PR421 PCI E bus signal switch is used to support the switching of PCI E 1.0 or 2.0 or 3.0 or 4.0 bus signals. Under the control of the ARM processor, the PCI E bus signal switch matrix can use a PCI E channel to complete the testing of multiple PCI E channels of the processing module through a time-sharing test method. The PCI E signal switching principle diagram is shown in FIG. Figure 5 shown.

[0046] In some embodiments, the hardware core machine is as follows: Figure 1 As shown, it includes a main control unit, a PCI E switching bridge, a multi-protocol serial port module, an ARI NC429 bus communication module, an avionics FC communication module, an optical fiber communication module, an ARI NC818 video conversion module, a video acquisition module and an Ethernet module. Figure 1 Only currently used slots are listed, and the system can reserve PCIE expansion slots for expansion.

[0047] In some embodiments, the PCI E switching bridge provides 8 installation slots for functional modules and 4 PC IE expansion slots for realizing data exchange between the main control unit and other module functions.

[0048] In some embodiments, the main control unit adopts an i7 processor and comes standard with 16G memory; the multi-protocol serial port module supports multiple serial port protocols of RS232 / RS422 / RS485, and supports serial port communication at a maximum rate of 10Mbps; the ARI NC429 bus communication module provides 8 configurable ARI NC429 channels for transmission and reception, and supports ARI NC429 standard rate and custom rate; the avionics FC communication module is a full-height half-length PCI E board, supports FC-AE-ASM protocol, and complies with FC-FS and FC-LS protocol standards; the fiber optic communication module provides 2 x4 fiber optic interfaces with adjustable rate, supporting SRIO or Aurora protocol; the ARI NC818 video conversion module can work independently without the need for external CPU environment support, and supports conversion between ARI NC818 and DVI; the video acquisition module supports DVI video acquisition with a maximum input resolution of 1080p.

[0049] In some embodiments, the application layer is used to provide a graphical editing interface for test cases, to provide breakpoint debugging and operation control interface for test cases, to provide a query and analysis interface for test data, and to provide a test report generation and saving interface.

[0050] In the above embodiments, the application layer mainly refers to the test development environment, which has the characteristics of visualization and integration, adopts the Internet's MVVM development framework, adopts the full dynamic loading technology based on IOC, and the real-time data recording technology based on time series database technology. It can provide reusable software components and support the writing of test cases by graphically dragging components, effectively lowering the development threshold and improving development efficiency; supports the mapping of test cases to hardware resources, and can realize the automatic execution of test processes according to test cases; supports code debugging of test cases and management of component libraries and databases; optimizes the database design of the built-in high-performance real-time database, taking into account the speed and real-time requirements of data writing and querying, ensuring that the access speed of multiple data terminals will not be reduced, and manages test data in a unified modeling and storage manner, and all test data are stored in the database.

[0051] In some embodiments, the network layer uses distributed real-time communication middleware to define a global data space, and the global data space is used for data exchange between the application layer and the virtual driver layer.

[0052] In the above embodiment, the network layer uses a new generation of distributed real-time communication middleware DDS, which defines a global data space (Global Data Space), which contains different domains (Domain) and topics (Topic). A domain is a logical partition in the DDS network, and a topic describes the type of data transmitted on the network. Using the publish-subscribe communication mode, publishers and subscribers exchange data through topics, which has the characteristics of decentralization, independent architecture, and strong scalability, and realizes stable, reliable, and timely data exchange.

[0053] In some embodiments, the virtual driver layer is used to drive the test resources of the test system, receive instructions from the application layer through the network layer, perform tests and outputs according to the instructions, and the virtual driver layer is also used to receive feedback from the test resources and pass the feedback to the application layer through the network layer.

[0054] In the above embodiment, the virtual driver layer is responsible for driving all the test hardware resources in the system, and can accept instructions from the application layer and output various parameters of the hardware resources. The virtual driver layer adopts an open unified specification, shields the hardware implementation details from the upper layer application, realizes the complete decoupling between the test software and the hardware environment, and minimizes the impact on the application when the board instrument changes.

[0055] When the radar processing module testing device provided by any of the aforementioned embodiments is working, the hardware core machine runs the test software, accesses and controls the stimulus / test components in sequence according to the compiled test cases, provides test stimulus to the processing module, and collects, analyzes, displays and saves data on its output signals.

[0056] The specific implementation steps are as follows:

[0057] S1: Preparation before testing

[0058] S1.1: Test resource adaptation: Write adapters for each test component and complete the development of the virtual driver layer.

[0059] S1.2: Test case design: Design automated test cases, including test input, operation steps, etc.

[0060] S1.3: Test process setting: Write an automated test process based on the test cases so that the test device can perform test tasks according to the designed test process.

[0061] S2: Testing Process

[0062] S2.1: Cables and optical fiber cables connecting the hardware core machine and the test fixture;

[0063] S2.2: Start the test device and run the test software, which can automatically identify all test resources;

[0064] S2.3: Run the automated test script and automatically execute the test steps in the script sequence. Take the fiber bus test as an example:

[0065] S2.3.1: Automatically generate a certain number of test data packets, and the generation rules include random numbers, increasing numbers, and constants;

[0066] S2.3.2: Control the test resource to send test data packets;

[0067] S2.3.3: Wait for the processing module to return data;

[0068] S2.3.4: Perform data comparison. If the received data is completely consistent with the sent data, this round of testing is considered successful. If the comparison fails, the bit error rate statistics are performed.

[0069] S2.3.5: Repeat the above steps according to the test script process to perform stress testing;

[0070] S2.3.6: Automatically save data.

[0071] S2.4: Perform the optical fiber bus test, avionics FC bus test, ARI NC 429 bus test, RS422 / RS485 bus test and other test items in sequence according to step S2.3;

[0072] S2.5: Collect, analyze and display test results, automatically prompt defects and problems in the processing module, and provide possible causes of failures and suggestions for debugging and troubleshooting.

[0073] S2.6: Automatically generate test reports to record the test process and test results.

[0074] The radar processing module testing device provided in any of the aforementioned embodiments adopts the form of "test tooling + hardware core machine + test software", has the characteristics of miniaturization and lightweight, and can meet the testing requirements of various scenarios such as laboratory debugging, production line testing, and field troubleshooting.

[0075] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principle of the present invention shall be included in the protection scope of the present invention. The above description is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and variations can be made without departing from the technical principles of the present invention. These improvements and variations should also be regarded as the protection scope of the present invention.

Claims

1. A radar processing module testing system, characterized in that: The test system comprises: Test fixture, used as a carrier board for processing module testing and for providing high-speed PCIE bus interface test resources; and Hardware core machine, used to integrate test function modules and main control unit, The main control unit is equipped with test software. The test software adopts a layered architecture design, and the layered architecture test software includes an application layer, a network layer and a virtual driver layer.

2. The radar processing module testing system according to claim 1, characterized in that: The test fixture comprises a base, an aviation plug fixed on the base and a PCB printed board. The front side of the PCB is provided with a VPX connector connected to the processing module and a switch button for controlling the working mode selection of the processing module. The back of the PCB is provided with an ARM processor for information interaction with external test equipment, an FPGA for exchanging working mode information with the ARM processor and for PCIE bus communication with the processing module, and a PCIE switch matrix for receiving commands sent by the ARM processor to control the on / off of channels between the FPGA and the processing module.

3. The radar processing module testing system according to claim 2, characterized in that: The ARM processor is used to test ICD interaction, interface configuration management, test timing control, transmission and reception success rate statistics, error information reporting and internal temperature control of the test tooling.

4. The radar processing module testing system according to claim 2, characterized in that: The FPGA module loads the configuration logic of EP or RC in the multi-version configuration program under the control of the ARM processor.

5. The radar processing module testing system according to claim 2, characterized in that: The PCIE switch matrix includes a plurality of PCIE single-pole double-throw switches, and the plurality of PCIE single-pole double-throw switches form a tree structure with an input end as a root node and an output end as a plurality of branch nodes. The input end of the tree-structured PCIE switch matrix is ​​connected to the PCIE channel of the FPGA, and the multiple branch nodes at the output end are respectively connected to the processing modules. The on and off of the multiple branch nodes of the tree structure are controlled by an ARM processor.

6. The radar processing module testing system according to claim 1, characterized in that: The hardware core machine includes a main control unit, a PCIE switching bridge, a multi-protocol serial port module, an ARINC429 bus communication module, an avionics FC communication module, an optical fiber communication module, an ARINC818 video conversion module, a video acquisition module and an Ethernet module.

7. The radar processing module testing system according to claim 6, characterized in that: The PCIE switching bridge provides 8 installation slots for functional modules and 4 PCIE expansion slots.

8. The radar processing module testing system according to claim 1, characterized in that: The application layer is used to provide a graphical editing interface for test cases, a breakpoint debugging and operation control interface for test cases, a query and analysis interface for test data, and a test report generation and saving interface.

9. The radar processing module testing system according to claim 1, characterized in that: The network layer uses distributed real-time communication middleware to define a global data space, and the global data space is used for data exchange between the application layer and the virtual driver layer.

10. The radar processing module testing system according to claim 1, characterized in that: The virtual driver layer is used for the test resource driver of the test system, receives instructions from the application layer through the network layer, performs tests and outputs according to the instructions, The virtual driver layer is also used to receive feedback from the test resource and transmit the feedback to the application layer through the network layer.

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