Zero carry mismatch extensible digit type high-precision photon flight time timing circuit

Abstract

The invention relates to a zero carry mismatch digit-expandable high-precision photon flight time timing circuit, and belongs to the technical field of photoelectric detection / three-dimensional laser radar. The device comprises a photosensitive element, a photosensitive element pixel circuit connected with the photosensitive element, a timing circuit connected with the photosensitive element pixel circuit, and a data reading circuit connected with the timing circuit. The timing circuit comprises a time-to-digital conversion circuit which is connected with a peripheral clock and time sequence control circuit and comprises a high-precision low-order sampling circuit and a high-order sampling circuit, and a mismatch correction circuit which is connected with the time-to-digital conversion circuit and comprises a phase jump trigger circuit and a digital continuity comparison circuit. And the carry mismatch correction circuit is connected with the flip detection circuit and comprises a numerical value continuity comparison circuit. According to the invention, the problems of high error code of timing quantization, non-monotonous timing result and reduced timing precision when a timing circuit is applied to a device with a larger array scale can be solved, the time quantization range is expanded, and the timing precision of practical application is improved.

Description

Technical Field

[0001] The invention belongs to the technical field of photoelectric detection / three-dimensional laser radar, relates to a photoelectric focal plane, and in particular to a zero-carry mismatch expandable bit number type high-precision photon flight time timing circuit. Background Art

[0002] Photon flight time timing is mainly used in the field of active laser detection. By counting the time it takes for photons to be emitted and reflected by the target back to the detector, the path length between the active light source, the target, and the detector is obtained to complete three-dimensional distance detection. High-precision timing circuits achieve state conversion between code values ​​through carry propagation between registers, output frequency division, and data feedback. The electrical delay of the register limits the further improvement of key performance parameters such as timing accuracy and timing range. There are mainly the following situations:

[0003] 1. Carry mismatch. Carry mismatch comes from the flip time deviation between the timing circuit registers, the metastable state caused by the asynchronous photon event response, etc., which causes the high-bit error of the timing quantization and the non-monotonic timing result. The existing delayed sampling circuit samples the high-bit counter after the high-bit flips for a period of time, and there is a problem of untimely sampling due to low sampling frequency; the existing multiple calibration sampling circuit requires multiple groups of buffers to realize the sampling data buffer, which has the problem of high buffer pressure;

[0004] 2. Timing range limitation: The photoelectric focal plane using APD photosensors can achieve near single-photon sensitivity, and the typical application scenario is target detection within a hundred kilometers. By expanding the number of register bits to meet the timing range, the state conversion delay of different bits increases with the number of register levels, which limits the maximum timing accuracy under a large timing range;

[0005] 3. Array scalability. Long-distance target recognition requires a large photosensitive element array scale and resolution. Due to the limitations of circuit power consumption and pixel area, it is difficult to simultaneously save the accuracy of the timing results and the number of bits to be saved. Existing timing circuits with shared and folded structures place some registers outside the pixel area, resulting in a longer signal propagation path, which limits the application of high-precision timing circuits in larger array-scale devices. Summary of the invention

[0006] In view of this, the purpose of the present invention is to provide a high-precision photon time-of-flight timing circuit with a zero-carry mismatch and expandable bit number, so as to solve the problems of high-bit errors in timing quantization, non-monotonic timing results and reduced timing accuracy faced when the timing circuit is applied to larger array-scale devices, expand the time quantization range, and improve the timing accuracy of the readout circuit in practical applications.

[0007] In order to achieve the above object, the present invention provides the following technical solutions:

[0008] A zero-carry mismatch scalable bit number type high-precision photon flight time timing circuit, the core part of which is a pixel circuit architecture, which includes:

[0009] A photosensitive element pixel circuit is connected to an independent photosensitive element, and can realize level comparison after the photosensitive element responds and output the result in the form of an electrical signal "true" or "false" to the timing circuit, and control the timing of the timing circuit in the pixel to stop, and its output end is connected to the timing circuit;

[0010] A timing circuit, used for photon flight time measurement and timing, and simultaneously for high-bit counter carry mismatch correction and high-bit correction data caching, with its input end connected to the photosensitive element pixel circuit, the pixel peripheral clock and the timing control circuit, and its output end connected to the data readout circuit;

[0011] The data readout circuit is used for serially reading out the data in the data buffer, and its input end is connected to the output end of the timing circuit.

[0012] Furthermore, the timing circuit includes a time-to-digital conversion circuit, a flip detection circuit and a carry mismatch correction circuit, which are used to realize photon timing, timing high-order data mismatch detection and mismatch data correction functions.

[0013] Furthermore, the time-to-digital conversion circuit is respectively connected to the photosensitive pixel circuit, the pixel peripheral clock and timing control circuit, the flip detection circuit and the data readout circuit, and includes a high-precision low-bit sampling circuit and a high-bit sampling circuit.

[0014] Among them, the high-precision low-bit sampling circuit is used to sample the timing high-frequency clock phase and output the high-precision timing result to achieve high-precision timing. Its input end is connected to the clock signal generated by the clock and timing control circuit and the output signal of the photosensitive pixel circuit, and the output end is connected to the flip detection circuit and the input end of the data readout circuit. The high-bit sampling circuit is used to sample a large range of quantized timing values. Its input end is connected to the clock signal generated by the clock and timing control circuit, and the output end is connected to the flip detection circuit.

[0015] Furthermore, the flip detection circuit is connected to the time digital conversion circuit and the carry mismatch correction circuit respectively to realize the flip detection of the high-bit counter, including a phase jump trigger circuit and a numerical consistency check circuit. Among them, the input end of the phase jump trigger circuit is connected to the output end of the high-precision low-bit sampling circuit, and its output end is connected to the numerical consistency check circuit; the output end of the numerical consistency check circuit is connected to the carry mismatch correction circuit.

[0016] Furthermore, the phase jump trigger circuit is used to generate a clock signal detected by a high-bit counter, and includes a clock frequency multiplication subcircuit of M groups of XOR gates and D flip-flops cascaded. In each frequency multiplication subcircuit, the output end of the XOR gate is connected to the clock input end of the D flip-flop, the input end of the D flip-flop is connected to its inverting output end, and the output end of the D flip-flop is connected to the second input end of the XOR gate. The first input end of the XOR gate of the first-stage frequency multiplication subcircuit is connected to the first high-frequency clock signal, and the first input end of the XOR gate of the subsequent frequency multiplication subcircuit is sequentially connected to the output signal of the XOR gate of the previous frequency multiplication subcircuit.

[0017] Among them, the output signal of the XOR gate is twice the frequency of the input clock. Then the M-level frequency multiplication sub-circuit is connected, and the output detection clock is 2 times the input clock signal. M The frequency multiplier is consistent with the frequency at which the low-order timing value flips.

[0018] Furthermore, the numerical consistency check circuit is used to detect the rollover of the high-order counter, and comprises a high-order buffer area composed of N D flip-flops, N groups of XNOR gates and an AND gate with multiple input terminals. The input terminal of each D flip-flop in the high-order buffer area is connected to the output terminal of the D flip-flop in the high-order sampling circuit in a one-to-one correspondence; the first input terminal of each XNOR gate is connected to the output terminal of the D flip-flop in the high-order sampling circuit in a one-to-one correspondence, and the second input terminal is connected to the output terminal of the D flip-flop in the high-order buffer area in a one-to-one correspondence; the input terminal of the multi-input AND gate is connected to the output terminal of each XNOR gate, and the output terminal of the multi-input AND gate is connected to the carry mismatch correction circuit.

[0019] In the timing state, the flip clock signal of the high-order sampling circuit is the first high-frequency clock signal. The detection clock generated by the phase jump trigger circuit is used as the clock signal of the D flip-flop in the high-order buffer area. The high-order sampling circuit value is sampled and stored in the high-order buffer area at each low-order timing value flipping moment. The values ​​stored in the high-order buffer area and the high-order counter are compared by an XOR gate. If the comparison results are consistent, the logic "true" is output, and if the comparison results are inconsistent, the logic "false" is output. The N groups of comparison results are input into the multi-terminal AND gate, and the logic "true" or "false" test results are output in the form of electrical signals as the jump occurrence signal to determine whether the high-order counter is flipped.

[0020] Furthermore, the carry mismatch correction circuit realizes the high-bit mismatch count correction function and stores the corrected high-bit timing value, the input end is connected to the output end of the flip detection circuit, and the output end is connected to the data readout circuit, the mode switching signal controls the switching of the timing and data readout modes, and the data refresh signal controls the refresh of the data stored in the data buffer. It includes a data ferry area composed of N D flip-flops, a data buffer composed of N D flip-flops, a two-way selector and a value continuity comparison circuit.

[0021] The input end of the D flip-flop in the data ferrying area is connected to the output end of the D flip-flop in the high-order buffer area in a one-to-one correspondence, and the clock input end of the D flip-flop in the data ferrying area is connected to the output end of the multi-input AND gate in the numerical consistency check circuit; the input end of the D flip-flop in the data buffer area is connected to the output end of the D flip-flop in the data ferrying area in a one-to-one correspondence, and the clock input end of the D flip-flop in the data buffer area is connected to the output end of the second selector.

[0022] In the timing state, the high-order sampling circuit jump signal serves as the clock signal of the D flip-flop in the data ferrying area. When the jump occurs and the jump stabilizes, the high-order sampling circuit jump signal is set from "0" to "1", and the data stored in the high-order buffer area is transferred to the data ferrying area, and compared with the high-order timing data stored in the data buffer for numerical continuity. The comparison result is transmitted to the data buffer as a data refresh signal to determine whether a carry mismatch occurs, and the detection clock signal is allowed to enter the data buffer as the clock signal of the D flip-flop, and the data stored in the data ferrying area is transferred to the data buffer to refresh the buffer; in the read state, the read clock enters the data buffer to read the high-order timing data stored in the data buffer.

[0023] Furthermore, the numerical continuity comparison circuit can realize the continuity check of high-bit timing data, and comprises an N-bit counter composed of a group of counting units, N groups of XNOR gates, a logic subcircuit and a multi-terminal input AND gate. Each counting unit includes a selector and a D flip-flop, the input end of the D flip-flop is connected to the output end of the selector, and the clock input end of the D flip-flop is connected to the output end of the multi-input AND gate in the numerical consistency check circuit. In multiple counting units, the first input end of the selector in the first counting unit is connected to the output end of the logic subcircuit, and the first input end of the selector in the subsequent counting unit is sequentially connected to the output end of the D flip-flop of the previous counting unit; in multiple counting units, the second input end of each selector is connected to the output end of each D flip-flop in the data buffer in a one-to-one correspondence. The first input end of each XNOR gate is connected to the output end of each D flip-flop in the data ferry area in a one-to-one correspondence, and the second input end is connected to the output end of each D flip-flop in the counting unit. The input end of the multi-input AND gate is connected to the output end of each XNOR gate, and the output end of the multi-input AND gate is connected to the input end of the first selector. The input end of the first selector is connected to the detection clock and the output end of the multi-input AND gate in the value continuity comparison circuit. The input end of the second selector is connected to the mode switching signal, the read clock and the output signal of the first selector, and the output signal of the second selector is used as the clock signal of the D flip-flop in the data buffer. Among them, the logic subcircuit adjusts its structure according to the number of bits of the counter. For example, when the number of counting units is 10, that is, the number of bits of the counter is 10 bits, the logic subcircuit includes an inverter and a same-OR gate.

[0024] The working principle of the numerical continuity comparison circuit is as follows: a jump signal is generated after the high-order sampling circuit is flipped, the numerical continuity comparison circuit realizes the data buffer data +1 logic, the XOR gate circuit performs consistency check between the timing value after flipping stored in the data buffer and the data after the high-order buffer data +1, and outputs logic "true" if the comparison results are consistent, and outputs logic "false" if the comparison results are inconsistent, N groups of comparison results are input into the multi-terminal AND gate, and the logic "true" or "false" test results are output in the form of electrical signals as data refresh signals, and the logic "true" is output if the test results are consistent, and the logic "false" is output if the test results are inconsistent, and the refresh of the timing data stored in the data buffer is controlled to ensure that the data buffer is updated only when the high-order counter value after flipping = the counter value before flipping +1, thereby eliminating the carry mismatch phenomenon.

[0025] The beneficial effects of the present invention are:

[0026] 1) The present invention proposes a flip detection circuit, which can detect the flip of the high-order counter through the low-segment phase jump trigger circuit and the high-segment counter value consistency check circuit for the timing data output by the time digital conversion circuit, and generate a high-order counter carry mismatch detection signal;

[0027] 2) The present invention proposes a carry mismatch correction circuit, which can achieve high-precision large-range time quantization and carry mismatch elimination, thereby solving the problems of high-bit error in timing quantization, non-monotonic timing results and reduced timing accuracy faced when the photon time-of-flight timing circuit is applied to larger array-scale devices.

[0028] Other advantages, objectives and features of the present invention will be described in the following description to some extent, and to some extent, will be obvious to those skilled in the art based on the following examination and study, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

[0030] Figure 1 This is a schematic diagram of the pixel circuit structure of the core part of the photon flight time timing circuit of the present invention;

[0031] Figure 2 It is a schematic diagram of the structure of the time digital conversion circuit;

[0032] Figure 3 It is a schematic diagram of the structure of the flip detection circuit;

[0033] Figure 4Schematic diagram of the structure of the carry mismatch correction circuit;

[0034] Figure 5 Schematic diagram of carry mismatch correction example. DETAILED DESCRIPTION

[0035] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner, and the following embodiments and features in the embodiments can be combined with each other without conflict.

[0036] Among them, the drawings are only used for illustrative explanations, and they only represent schematic diagrams rather than actual pictures, and should not be understood as limitations on the present invention. In order to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of actual products. For those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0037] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "front", "rear", etc. indicate the orientation or position relationship, they are based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, the terms describing the position relationship in the drawings are only used for illustrative purposes and cannot be understood as limiting the present invention. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0038] like Figure 1 As shown, the pixel circuit architecture of the core part of the zero-carry mismatch expandable bit number high-precision photon time-of-flight timing circuit proposed in an embodiment of the present invention includes a photosensitive element, a photosensitive element pixel circuit, a timing circuit and a data readout circuit. In addition to the core pixel circuit architecture, it also includes a peripheral clock and timing control circuit.

[0039] The photosensitive element pixel circuit includes a quenching circuit that can realize level pull-up, a reset signal generating circuit that can self-generate a reset signal, a reset circuit that can realize level pull-down, a limiting circuit that can realize level clamping, a detection circuit that can realize level comparison after the photosensitive element responds and output the result in the form of an electrical signal as logical "true" or "false", and a level conversion circuit that can realize conversion between different voltage domains, which is used to detect the occurrence of photon events.

[0040] The timing circuit is composed of a time-to-digital conversion circuit, a flip detection circuit, and a carry mismatch correction circuit. The time-to-digital conversion circuit has the ability to measure the photon flight time; the flip detection circuit performs a counter high-bit jump occurrence test, generates a detection clock signal through a low-bit phase jump trigger circuit, detects the high-bit counter data jump situation through a numerical consistency test circuit, and outputs a high-bit counter data jump occurrence detection result; the carry mismatch correction circuit detects the carry mismatch phenomenon through the jump occurrence detection result output by the flip detection circuit, and corrects the mismatched high-bit counter data to eliminate the erroneous jump of the high-bit data.

[0041] like Figure 2 As shown, the time-to-digital conversion circuit realizes high-precision timing and wide-range time quantization through a high-precision low-bit sampling circuit containing an M-bit register and a high-bit sampling circuit containing an N-bit counter. The circuit controls the switching of the circuit timing and readout working modes through a mode switching signal. When switching to the timing mode, the trigger signal arrives to realize high-precision low-bit phase value sampling. After the photon event trigger signal arrives, the counter in the high-bit sampling circuit starts to flip. After receiving a photon signal once in the timing interval, a low-bit and high-bit timing data storage is generated.

[0042] like Figure 3 As shown, the flip detection circuit includes a phase jump trigger circuit and a numerical consistency check circuit. The phase jump trigger circuit can realize the generation of the detection clock signal of the numerical consistency check circuit, which passes the input high-frequency clock signal through the M-level frequency multiplication circuit and outputs a clock signal with the same frequency as the flip of the low-bit timing value; the numerical consistency check circuit can realize the flip detection of the high-bit counter, which includes a group of buffer areas, which cache the high-bit counter sampling value when the low-bit timing value flips, and realizes the consistency check of the high-bit buffer area and the high-bit counter storage data through the logic gate circuit. The test result is output as a logic "true" or "false" in the form of an electrical signal and transmitted to the carry mismatch correction circuit, which controls the carry mismatch correction circuit to realize the continuity check and mismatch correction of the high-bit timing value.

[0043] like Figure 4As shown, the carry mismatch correction circuit includes a data ferry area, a data buffer area, and a numerical continuity comparison circuit. The data ferry area can realize the refresh of the high-order timing data after the counter flips and stabilizes. The input jump occurrence signal is used as the clock signal of the register in the data ferry area, and the counter flip data cached in the high-order buffer area of ​​the flip detection circuit is transferred to the register storage; the data buffer area stores the high-order count value after mismatch correction; the numerical continuity comparison circuit compares the continuity of the data before and after the counter flips to eliminate the carry mismatch phenomenon.

[0044] like Figure 5 As shown, under normal circumstances, the high-order counter flips in sequence, and each time the counter flips, the decoded value is +1, and the decoded value rises in steps; however, due to the carry mismatch phenomenon of the high-order counter, the count value may fall back after the counter flips. Through the pixel circuit architecture, the high-order counter carry detection and carry mismatch correction can be realized, and the corrected data can be output.

[0045] In the pixel circuit, the data readout circuit realizes serial readout of pixel timing data according to the written clock signal.

[0046] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution, which should be included in the scope of the claims of the present invention.

Claims

1. A zero-carry mismatch expandable bit number high-precision photon flight time timing circuit, characterized in that: It includes a photosensitive element, a photosensitive element pixel circuit, a timing circuit and a data readout circuit; The photosensitive element pixel circuit realizes level comparison after the photosensitive element responds, and outputs the result to the timing circuit in the form of an electrical signal, the input end of the photosensitive element pixel circuit is connected to the photosensitive element, and the output end is connected to the timing circuit; The timing circuit is used to measure the photon flight time and timing, and simultaneously perform high-bit counter carry mismatch correction and high-bit correction data caching. The timing circuit includes a time-to-digital conversion circuit, a flip detection circuit, and a carry mismatch correction circuit; the input end of the time-to-digital conversion circuit is connected to the output end of the photosensitive pixel circuit, and the output end is connected to the flip detection circuit; the output end of the flip detection circuit is connected to the input end of the carry mismatch correction circuit; the output end of the carry mismatch correction circuit is connected to the data readout circuit; The photon flight time timing circuit also includes a clock and timing control circuit for generating a clock signal. The clock and timing control circuit are respectively connected to the timing circuit and the data readout circuit.

2. The photon flight time timing circuit according to claim 1, characterized in that: The time-to-digital conversion circuit includes a high-precision low-bit sampling circuit and a high-bit sampling circuit; the high-precision low-bit sampling circuit is connected to the photon response signal, reset signal, clock signal and mode switching signal generated by the photosensitive pixel circuit, and is used to sample the timing high-frequency clock phase and output a high-precision timing result, and the output end of the high-precision low-bit sampling circuit is connected to the flip detection circuit; the high-bit sampling circuit is connected to the high-frequency clock generated by the clock and timing control circuit and the trigger signal and reset signal generated by the photosensitive pixel circuit, and is used to sample a large range of quantized timing values, and the output end of the high-bit sampling circuit is connected to the flip detection circuit.

3. The photon flight time timing circuit according to claim 1 or 2, characterized in that: The flip detection circuit includes a phase jump trigger circuit and a numerical consistency check circuit; The phase jump trigger circuit includes a plurality of cascaded frequency multiplication subcircuits, each of which includes a D flip-flop and an XOR gate, wherein the output end of the XOR gate is connected to the clock input end of the D flip-flop, the input end of the D flip-flop is connected to its inverting output end, and the output end of the D flip-flop is connected to the second input end of the XOR gate; in the plurality of cascaded frequency multiplication subcircuits, the first input end of the XOR gate of the first frequency multiplication subcircuit is connected to the first high-frequency clock signal, and the first input end of the XOR gate of the subsequent frequency multiplication subcircuit is sequentially connected to the output signal of the XOR gate of the previous frequency multiplication subcircuit; the output end of the XOR gate of the last frequency multiplication subcircuit outputs a detection clock signal and is connected to the input end of the numerical consistency check circuit; The numerical consistency check circuit includes a plurality of XNOR gates, a multi-input AND gate, and a high-order buffer area composed of a plurality of D flip-flops; the number of the XNOR gates is equal to the number of the D flip-flops; the input end of each D flip-flop in the high-order buffer area is connected one-to-one with the output end of the D flip-flop in the high-order sampling circuit; the first input end of each XNOR gate is connected one-to-one with the output end of the D flip-flop in the high-order sampling circuit, and the second input end is connected one-to-one with the output end of the D flip-flop in the high-order buffer area; the input end of the multi-input AND gate is connected to the output end of each XNOR gate, and the output end of the multi-input AND gate is connected to the carry mismatch correction circuit.

4. The photon flight time timing circuit according to claim 3, characterized in that: The carry mismatch correction circuit includes a data ferry area, a data buffer area and a value continuity comparison circuit; The data ferrying area and the data buffer area both include a plurality of D flip-flops; the input ends of the D flip-flops in the data ferrying area are connected to the output ends of the D flip-flops in the high-order buffer area in a one-to-one correspondence, and the clock input ends of the D flip-flops in the data ferrying area are connected to the output ends of the multi-input AND gates in the numerical consistency check circuit; the input ends of the D flip-flops in the data buffer area are connected to the output ends of the D flip-flops in the data ferrying area in a one-to-one correspondence, and the clock input ends of the D flip-flops in the data buffer area are connected to the output ends of the second selector; The numerical continuity comparison circuit includes a logic subcircuit, a plurality of XNOR gates, a multi-input AND gate and a plurality of cascaded counting units; each of the counting units includes a selector and a D flip-flop, the input end of the D flip-flop is connected to the output end of the selector, and the clock input end of the D flip-flop is connected to the output end of the multi-input AND gate in the numerical consistency check circuit; in the plurality of cascaded counting units, the first input end of the selector in the first counting unit is connected to the output end of the logic subcircuit, and the first input end of the selector in the subsequent counting units is sequentially connected to the output end of the D flip-flop of the previous counting unit; in the plurality of cascaded counting units, the second input end of each selector is connected to the output end of each D flip-flop in the data buffer in a one-to-one correspondence; the first input end of each XNOR gate is connected to the output end of each D flip-flop in the data ferry area in a one-to-one correspondence, and the second input end is connected to the output end of each D flip-flop in the counting unit; the input end of the multi-input AND gate is connected to the output end of each XNOR gate, and the output end of the multi-input AND gate is connected to the input end of the first selector; The input end of the first selector is connected to the detection clock and the output end of the multi-input AND gate in the numerical continuity comparison circuit; the input end of the second selector is connected to the mode switching signal, the readout clock and the output signal of the first selector.

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