Dual-power channel time schedule controller circuit

Abstract

The invention discloses a dual-power channel time schedule controller circuit, and belongs to the field of analog circuits. According to the invention, the driving instruction signals G1 and G2 can be quickly transmitted to the peripheral device according to the requirements of time sequence validity and priority, and the peripheral device outputs the corresponding power supply V1 or V2 according to the instructions of G1 and G2, so that the safety and stability of power supply products can be improved, and equipment can adapt to the scene of power failure caused by emergencies; the system can be widely applied to industrial handheld instruments, battery backup systems, server design, computer peripherals and other scenes, and is good in product market prospect and high in practicability.

Description

Technical Field

[0001] The present invention relates to the technical field of analog circuits, and in particular to a dual-power supply channel timing controller circuit. Background Art

[0002] With the development of science and technology, smart products have covered all aspects of life. These products cannot do without power chips for power supply, but most of the current power chips are single power supply, and there are certain hidden dangers in reliability and stability. Many important occasions, such as industrial handheld instruments, battery backup systems, server designs and computer peripherals, require dual power supplies to maintain the stability of the system so that the equipment can work normally. At present, there is no timing controller circuit for dual power supply channels on the market. Therefore, the present invention uses a timing controller for dual power supply channels. The internal chip generates a driving signal for controlling peripheral devices according to priority and effectiveness, so that the power supply V1 or V2 is selected, and V1 or V2 is accurately transmitted to the VOUT output terminal through the peripheral device. The power supply equipment can be effectively managed from the source to avoid the point-to-point failure of a single power supply causing the equipment to not work properly, thereby ensuring the safety and stability of the equipment. Summary of the invention

[0003] The object of the present invention is to provide a dual power supply channel timing controller circuit to solve the problems in the background technology.

[0004] In order to solve the above technical problems, the present invention provides a dual power supply channel timing controller circuit, including: an overvoltage and undervoltage detection module, a validity timing module, a reverse detection comparator module, a forward conduction comparator module, a logic control module, a gate drive module, and peripheral devices;

[0005] The overvoltage and undervoltage detection module detects and compares the input voltage and generates an enable signal to the validity timing module;

[0006] The validity timing module checks whether the channel is valid;

[0007] The reverse detection comparator module realizes the reverse detection function when the chip is started to prevent surge;

[0008] The forward conducting comparator module is a channel conducting module;

[0009] The logic control module performs logic selection of channels;

[0010] The gate drive module outputs a drive enable signal to the peripheral device;

[0011] The peripheral device is a back-to-back PMOS power tube outside the chip.

[0012] In one embodiment, the overvoltage and undervoltage detection module includes two comparators, two inverters and a NOR gate; the positive input end of one comparator and the negative input end of the other comparator are respectively connected to a voltage divider link, and the negative input end of one comparator and the positive input end of the other comparator are commonly connected to a reference voltage Vref; the output ends of the two comparators are respectively connected to the input ends of the two inverters, and the output ends of the two inverters are connected to the two input ends of the NOR gate, and the NOR gate outputs an enable signal OV_UV_OK_*, where * is 1 or 2, and OV_UV_OK_1 and OV_UV_OK_2 represent the enable signals of channel 1 or channel 2 respectively.

[0013] In one embodiment, the validity timing module is a channel validity detection module. When the enable signals OV_UV_OK_1 and OV_UV_OK_2 are valid, the validity timing module works normally. At this time, the square wave generated by the square wave generator passes through a 6-bit timer, i.e., 32 timing cycles. The validity timing module outputs an enable signal CHANNEL_VALID_*, where * is 1 or 2; CHANNEL_VALID_1 and CHANNEL_VALID_2 represent the enable signals of channel 1 or channel 2, respectively.

[0014] In one implementation, the reverse detection comparator module determines whether VOUT is higher than its own input port V1 / V2 by detecting the voltage difference between its own input port V1 / V2 and the VOUT port, and the reverse detection comparator module only works when the circuit is started; when the input port V1-VOUT of the reverse detection comparator module in channel 1>125mV, channel 1 starts normally, and the reverse detection comparator module outputs an enable signal CHANNEL_OFF_1; when the input port V2-VOUT of the reverse detection comparator module in channel 2>125mV, channel 2 starts normally, and the reverse detection comparator module outputs an enable signal CHANNEL_OFF_2; and the priority of the input port V1 of the reverse detection comparator module in channel 1 is higher than the input port V2 of the reverse detection comparator module in channel 2.

[0015] In one embodiment, the forward conducting comparator module, when VG1-VS1>300mV, wherein VG1 is the voltage of the output enable G1 port of channel 1, VS1 is the source common terminal of the peripheral devices in channel 1, the forward conducting comparator module of channel 1 outputs an enable signal SWITCH_1; when VG2-VS2>300mV, wherein VG2 is the voltage of the output enable G2 port of channel 2, VS2 is the source common terminal of the peripheral devices in channel 2, the forward conducting comparator module of channel 2 outputs an enable signal SWITCH_2.

[0016] In one implementation, the logic control module performs a logic operation on the enable signals CHANNEL_VALID_1, CHANNEL_OFF_1 and SWITCH_1 for channel 1 and outputs an enable signal G1_EN; and performs a logic operation on the enable signals CHANNEL_VALID_1, CHANNEL_VALID_2, CHANNEL_OFF_2 and SWITCH_2 for channel 2 and outputs an enable signal G2_EN.

[0017] In one embodiment, the gate drive module is an output drive enable signal module. When the enable signals G1_EN and G2_EN are valid, channel 1 outputs enable signal G1 and channel 2 outputs enable signal G2. Enable signal G1 controls peripheral device 1 and enable signal G2 controls peripheral device 2.

[0018] A dual-power channel timing controller circuit provided by the present invention can quickly transmit drive instruction signals G1 and G2 to peripheral devices according to the requirements of timing validity and priority. The peripheral devices output corresponding power supplies V1 or V2 according to the instructions of G1 and G2. The present invention can improve the safety and stability of power supply products, so that the equipment can adapt to the scenario of power outage caused by emergencies; it has a wide range of applications in scenarios such as industrial handheld instruments, battery backup systems, server designs and computer peripherals, and the product has good market prospects and strong practicality. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 The present invention provides a schematic diagram of the structure of a dual-power channel timing controller circuit.

[0020] Figure 2 It is a structural schematic diagram of the overvoltage and undervoltage detection module provided by the present invention.

[0021] Figure 3 It is an output waveform diagram of the overvoltage and undervoltage detection module provided by the present invention.

[0022] Figure 4 It is a structural schematic diagram of the validity timing module provided by the present invention.

[0023] Figure 5 This is an output waveform diagram of the validity timing module provided by the present invention.

[0024] Figure 6 It is a structural schematic diagram of the reverse detection comparator module provided by the present invention.

[0025] Figure 7 It is a structural schematic diagram of the logic control module provided by the present invention.

[0026] Figure 8The present invention provides a dual-power channel timing controller circuit output waveform diagram. DETAILED DESCRIPTION

[0027] The following is a further detailed description of a dual power supply channel timing controller circuit proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0028] The present invention provides a dual power supply channel timing controller circuit, the structure of which is as follows: Figure 1 As shown, it includes an overvoltage and undervoltage detection module, a validity timing module, a reverse detection comparator module (comparator 1), a forward conduction comparator module (comparator 2), a logic control module, a gate drive module, and peripheral devices.

[0029] Figure 2 The figure shows the structural diagram of the overvoltage and undervoltage detection module. Figure 2 The _* in the figure represents channel 1 or channel 2. The overvoltage and undervoltage detection module has two built-in comparators. Channel 1 divides V1 through external resistors R1_1, R2_1, and R3_1 to generate UV1 and OV1, which are processed internally by the overvoltage and undervoltage detection module and output enable signal OV_UV_OK_1; channel 2 divides V2 through external resistors R1_2, R2_2, and R3_2 to generate UV2 and OV2, which are processed internally by the overvoltage and undervoltage detection module and output enable signal OV_UV_OK_2. Figure 3 This is the output waveform of the overvoltage and undervoltage detection module. There are three reference voltages of Vref: 0.97V, 1V, and 1.03V. For OV voltage detection, the rising edge reference voltage is 1V and the falling edge reference voltage is 0.97V; for UV voltage detection, the falling edge reference voltage is 1V and the rising edge reference voltage is 1.03V.

[0030] Figure 2The figure shows a schematic structural diagram of the validity timing module. The validity timing module is a channel validity detection module. Whether Channel 1 and Channel 2 are valid still requires a verification time to determine the channel validity, so as to ensure channel switching after the power supply is stable, provide an accurate channel voltage, and prevent the back-and-forth switching between Channel 1 and Channel 2 caused by power supply jitter, resulting in cross-conduction. When the enable signal OV_UV_OK1 is valid, the validity timing module of Channel 1 can work normally. After the square wave generated by the square wave generator passes through a 6-bit timer, that is, 32 timing cycles, the enable signal CHANNEL_VALID_1 is output, proving that Channel 1 is valid; when the enable signal OV_UV_OK2 is valid, the validity timing module of Channel 2 can work normally. After the square wave generated by the square wave generator passes through a 6-bit timer, that is, 32 timing cycles (OV, UV valid time), the enable signal CHANNEL_VALID_2 is output, proving that Channel 2 is valid. The square wave generated by the square wave generator is used to simulate the valid time. After the square wave passes through a 6-bit counter, that is, 32 timing cycles (OV, UV valid time), referring to Figure 5 as shown, at this time the CHANNEL_VALID_* signal flips, and Channel 1 and Channel 1 are valid, and the channel can work normally.

[0031] The reverse detection comparator module (Comparator 1) realizes the function of reverse detection when the chip starts up to prevent surges. By detecting the voltage difference between the V1 or V2 port and the VOUT port to determine whether VOUT is higher than V1 or V2, this module only works when the circuit starts up. When V1 - VOUT > 125 mV, Channel 1 can start up normally, and Comparator 1 outputs the enable signal CHANNEL_OFF_1; when V2 - VOUT > 125 mV, Channel 2 can start up normally, and Comparator 1 outputs the enable signal CHANNEL_OFF_2. This module only works when the circuit starts up, and the internal enable shields this comparator during normal operation. As Figure 6 shown is a schematic structural diagram of the reverse detection comparator module provided by the present invention. The main principle is to use different resistors to generate different voltage differences to achieve. When V1 - VOUT = I * R5 > 125 mV, Comparator 1 outputs the enable signal CHANNEL_OFF_1, indicating that V1 is greater than VOUT, and Channel 1 can output normally; when V2 - VOUT = I * R5 > 125 mV, Comparator 1 outputs the enable signal CHANNEL_OFF_2, indicating that V2 is greater than VOUT, and Channel 2 can output normally. When V1 < VOUT or V2 < VOUT, Comparator 1 outputs an invalid enable signal, and Comparator 1 only works when power is reapplied.

[0032] The forward conduction comparator module (comparator 2) realizes the logical selection of channel 1 and channel 2. The schematic diagram is similar to that of comparator 1. A comparator is used to detect the voltage difference between VS (the source common terminal of the peripheral device) and the VG port. This voltage difference is used to measure the gate closing threshold of the channel. When the voltage difference between the VS1 port and the G1 port does not exceed 300mV (i.e. VS1-VG1=I*R<300mV), the output enable signal SWITCH_1 of comparator 2 is invalid and channel 1 is closed; when the voltage difference between the VS1 port and the G1 port exceeds 300mV (i.e. VS1-VG1=I*R>300mV), the output enable signal SWITCH_1 of comparator 2 is valid and channel 1 can be opened normally; the principle of channel 2 is the same.

[0033] For channel 1, the logic control module performs a logic operation on the enable signals CHANNEL_VALID_1, CHANNEL_OFF_1 and SWITCH_1, and outputs the enable signal G1_EN; for channel 2, the logic control module performs a logic operation on the enable signals CHANNEL_VALID_1, CHANNEL_VALID_2, CHANNEL_OFF_2 and SWITCH_2, and outputs the enable signal G2_EN. Figure 7 , the validity of channel 1 and channel 2 are detected at the same time. Since the priority of V1 port is higher than that of V2 port, when both channel 1 and channel 2 are valid, the enable signal CHANNEL_VALID_1 of channel 1 will not only be input to the logic control module 1 of channel 1, but also to the logic control module 2 of channel 2. At this time, the logic control module 2 of channel 2 will perform logical operations on CHANNEL_VALID_1, CHANNEL_VALID_2, CHANNEL_OFF_2 and SWITCH_2, and output the invalid enable signal G2_EN, so as to shield the output of channel 2, thereby giving priority to the voltage transmission of channel 1 where the V1 port is located.

[0034] Reference Figure 8 The final output waveform of V1, V2, G1, G2 is as follows: Figure 8 As shown. Before t1, V1, V2, G1, and G2 are all high, VOUT output is 0, and both peripheral devices do not work, so both channels do not work; from t1 to t2, V1 is high and G1 is low, V2 is high and G2 is high, VOUT output is high, peripheral device 1 works, and peripheral device 2 does not work, so channel 1 works and transmits V1 voltage to VOUT; after t2, V1 is low and G1 is low, V2 is high and G2 is low, VOUT output is high, peripheral device 1 does not work, and peripheral device 2 works, so channel 2 works and transmits V2 voltage to VOUT.

[0035] In summary, in combination with the detailed description of the present invention in the accompanying drawings and specific embodiments, a dual power channel timing controller circuit structure of the present invention is extremely simple, and has the characteristics of strong practicality and simple structure.

[0036] In the present invention, words such as "connect", "connected", "connected", "connected" and "connected" that indicate electrical connection, unless otherwise specified, indicate direct or indirect electrical connection. The upper and lower ends of all the above-mentioned resistors are defined according to the direction of current flow. The end of the resistor through which the current first passes is the upper end, and the other end is the lower end.

[0037] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A dual power supply channel timing controller circuit, characterized in that: include: Overvoltage and undervoltage detection module, validity timing module, reverse detection comparator module, forward conduction comparator module, logic control module, gate drive module, peripheral devices; The overvoltage and undervoltage detection module detects and compares the input voltage and generates an enable signal to the validity timing module; The validity timing module checks whether the channel is valid; The reverse detection comparator module realizes the reverse detection function when the chip is started to prevent surge; The forward conducting comparator module is a channel conducting module; The logic control module performs logic selection of channels; The gate drive module outputs a drive enable signal to the peripheral device; The peripheral device is a back-to-back PMOS power tube outside the chip.

2. The dual power supply channel timing controller circuit according to claim 1, characterized in that: The overvoltage and undervoltage detection module includes two comparators, two inverters and a NOR gate; the positive input end of one comparator and the negative input end of the other comparator are respectively connected to the voltage divider link, and the negative input end of one comparator and the positive input end of the other comparator are commonly connected to the reference voltage Vref; the output ends of the two comparators are respectively connected to the input ends of the two inverters, and the output ends of the two inverters are connected to the two input ends of the NOR gate, and the NOR gate outputs an enable signal OV_UV_OK_*, where * is 1 or 2, and OV_UV_OK_1 and OV_UV_OK_2 represent the enable signals of channel 1 or channel 2 respectively.

3. The dual power supply channel timing controller circuit as claimed in claim 2, characterized in that: The validity timing module is a channel validity detection module. When the enable signals OV_UV_OK_1 and OV_UV_OK_2 are valid, the validity timing module works normally. At this time, the square wave generated by the square wave generator passes through a 6-bit timer, i.e., 32 timing cycles, and the validity timing module outputs an enable signal CHANNEL_VALID_*, where * is 1 or 2; CHANNEL_VALID_1 and CHANNEL_VALID_2 represent the enable signals of channel 1 or channel 2, respectively.

4. The dual power supply channel timing controller circuit as claimed in claim 3, characterized in that: The reverse detection comparator module determines whether VOUT is higher than its own input port V1 / V2 by detecting the voltage difference between its own input port V1 / V2 and the VOUT port, and the reverse detection comparator module only works when the circuit is started; when the input port V1-VOUT of the reverse detection comparator module in channel 1>125mV, channel 1 starts normally, and the reverse detection comparator module outputs an enable signal CHANNEL_OFF_1; when the input port V2-VOUT of the reverse detection comparator module in channel 2>125mV, channel 2 starts normally, and the reverse detection comparator module outputs an enable signal CHANNEL_OFF_2; and the priority of the input port V1 of the reverse detection comparator module in channel 1 is higher than the input port V2 of the reverse detection comparator module in channel 2.

5. The dual power supply channel timing controller circuit as claimed in claim 4, characterized in that: The forward conducting comparator module, when VG1-VS1>300mV, wherein VG1 is the voltage of the output enable G1 port of channel 1, VS1 is the source common terminal of the peripheral devices in channel 1, the forward conducting comparator module of channel 1 outputs an enable signal SWITCH_1; when VG2-VS2>300mV, wherein VG2 is the voltage of the output enable G2 port of channel 2, VS2 is the source common terminal of the peripheral devices in channel 2, the forward conducting comparator module of channel 2 outputs an enable signal SWITCH_2.

6. The dual power supply channel timing controller circuit as claimed in claim 5, characterized in that: For channel 1, the logic control module performs a logic operation on the enable signals CHANNEL_VALID_1, CHANNEL_OFF_1 and SWITCH_1 to output an enable signal G1_EN; for channel 2, the logic control module performs a logic operation on the enable signals CHANNEL_VALID_1, CHANNEL_VALID_2, CHANNEL_OFF_2 and SWITCH_2 to output an enable signal G2_EN.

7. The dual power supply channel timing controller circuit according to claim 6, characterized in that: The gate drive module is an output drive enable signal module. When the enable signals G1_EN and G2_EN are valid, channel 1 outputs the enable signal G1 and channel 2 outputs the enable signal G2. The enable signal G1 controls the peripheral device 1 and the enable signal G2 controls the peripheral device 2.

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