Power consumption mode switching system, power consumption mode switching method and processor

Abstract

The invention discloses a power consumption mode switching system, a power consumption mode switching method and a system on chip. The system comprises a task core used for generating an entry request of a preset power consumption mode; the power consumption management core is used for configuring a switching time sequence of a preset power consumption mode; the power consumption controller is connected with the task core and the power consumption management core and is used for receiving the entry request or generating an exit request of a preset power consumption mode according to the received wake-up request; the power consumption mode controller is connected with the power consumption controller and is used for executing a switching time sequence according to the entry request or the exit request so as to generate a control signal; and the plurality of hardware control devices are respectively connected with the power consumption mode controller and are used for entering a preset power consumption mode or exiting the preset power consumption mode according to the control signal, and the control types of different hardware control devices are different. The technical problem that the switching effect of the power consumption mode is poor in the prior art is solved.

Description

Technical Field

[0001] The present application relates to the field of system on chip, and in particular, to a power consumption mode switching system, a power consumption mode switching method and a system on chip. Background Art

[0002] At present, power mode switching is mainly achieved through two methods: software control and hardware control. Although the software control method is highly flexible and can customize the timing and strategy of power mode switching for different task scenarios, it has problems such as large delay and high software design complexity. For scenarios that require rapid response, the delay of software control may affect the user experience and even affect the performance and stability of the system. The hardware control method can significantly reduce the delay and increase the speed of power mode switching, but due to its fixed nature and lack of sufficient flexibility, it is difficult to adapt to most task scenarios. When special needs arise during the user use stage, the hardware control method may not be able to make corresponding adjustments.

[0003] These two traditional control methods have their own limitations. Software control is flexible but has high latency, while hardware control is fast but lacks flexibility. Therefore, the industry faces the challenge of how to maintain low latency while providing sufficient flexibility to cope with various mission scenarios. This problem is particularly prominent in the control of power mode switching, because incorrect power mode timing or control strategy may lead to serious consequences such as functional failure and failure to effectively reduce power consumption, affecting system reliability, performance and user experience.

[0004] To address the above-mentioned problems, no effective solution has been proposed yet. Summary of the invention

[0005] The embodiments of the present application provide a power consumption mode switching system, a power consumption mode switching method and a processor, so as to at least solve the technical problem of poor switching effect of power consumption modes in the related art.

[0006] According to one aspect of an embodiment of the present application, a power consumption mode switching system is provided, including: a task core, used to generate an entry request for a preset power consumption mode; a power consumption management core, used to configure the switching timing of the preset power consumption mode; a power consumption controller, connected to the task core and the power consumption management core, and used to receive an entry request, or generate an exit request for the preset power consumption mode according to a received wake-up request; a power consumption mode controller, connected to the power consumption controller, and used to execute the switching timing according to the entry request or the exit request to generate a control signal; and multiple hardware control devices, respectively connected to the power consumption mode controllers, and used to enter the preset power consumption mode or exit the preset power consumption mode according to the control signal, wherein different hardware control devices have different control types.

[0007] According to one aspect of an embodiment of the present application, a power consumption mode switching method is provided, including: a task core, used to generate an entry request for a preset power consumption mode; a power consumption management core, used to configure the switching timing of the preset power consumption mode; a power consumption controller, connected to the task core and the power consumption management core, used to receive an entry request, or generate an exit request for the preset power consumption mode according to a received wake-up request; a power consumption mode controller, connected to the power consumption controller, used to execute the switching timing according to the entry request or the exit request to generate a control signal; and multiple hardware control devices, respectively connected to the power consumption mode controllers, used to enter the preset power consumption mode or exit the preset power consumption mode according to the control signal, wherein different hardware control devices have different control types.

[0008] According to another aspect of the embodiments of the present application, a system on chip is also provided, including: any one of the systems in the above embodiments.

[0009] According to another aspect of the embodiments of the present application, a computing device is provided, including: a memory storing an executable program; and a processor for running the program, wherein the program executes any one of the methods in the above embodiments when it is run.

[0010] According to another aspect of an embodiment of the present application, a computer-readable storage medium is also provided, the computer-readable storage medium including a stored executable program, wherein when the executable program is running, the device where the computer-readable storage medium is located is controlled to execute the methods in each embodiment of the present application.

[0011] According to another aspect of the embodiments of the present application, a computer program product is also provided, including a computer program, and when the computer program is executed by a processor, the method in each embodiment of the present application is implemented.

[0012] According to another aspect of an embodiment of the present application, a computer program product is also provided, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method in each embodiment of the present application is implemented.

[0013] According to another aspect of the embodiments of the present application, a computer program is also provided, and when the computer program is executed by a processor, the methods in the various embodiments of the present application are implemented.

[0014] In an embodiment of the present application, a task core is used to generate an entry request for a preset power consumption mode; a power consumption management core is used to configure the switching timing of the preset power consumption mode; a power consumption controller is connected to the task core and the power consumption management core, and is used to receive an entry request, or generate an exit request of the preset power consumption mode according to the received wake-up request; a power consumption mode controller is connected to the power consumption controller, and is used to execute the switching timing according to the entry request or the exit request to generate a control signal; a plurality of hardware control devices are respectively connected to the power consumption mode controller, and are used to enter the preset power consumption mode or exit the preset power consumption mode according to the control signal, wherein the control types of different hardware control devices are different, so as to achieve the switching effect of improving the power consumption mode. It is easy to notice that when the system load is reduced or enters a specific standby state, the task core detects this change and generates a request to enter the preset power consumption mode accordingly. The generation of this request is immediate and direct, avoiding the delay of software scheduling, so that it can respond quickly to load changes, and the power consumption management core can ensure that before entering the preset power consumption mode, the system can adjust the power consumption control timing of each module according to specific needs. By configuring the timing reasonably, the failure of hardware functions caused by improper control sequence can be avoided. After receiving the entry request or exit request of the power consumption controller, the power consumption mode controller executes according to the configured switching timing and generates the corresponding control signal. By controlling multiple hardware control devices through control signals, the delay of power consumption mode switching can be reduced and the switching speed can be improved. Since each hardware control device is responsible for different control types, this division of labor and cooperation mode ensures the comprehensiveness and efficiency of the system when switching power consumption modes, avoids the singleness and complexity of software control, and improves the switching efficiency of power consumption modes through the instant request generation of the task core, the flexible timing configuration of the power consumption management core, the hardware control signal generation of the power consumption mode controller, and the division of labor and cooperation of multiple hardware control devices, thereby solving the technical problem of poor switching effect of power consumption modes in related technologies.

[0015] It is easy to notice that the above general description and the following detailed description are only for the purpose of exemplifying and explaining the present application, and do not constitute a limitation of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0017] Figure 1 is a hardware structure block diagram of a RISC-V system for implementing a power consumption mode switching method according to an embodiment of the present application;

[0018] Figure 2 is a schematic diagram of a system on chip according to an embodiment of the present application;

[0019] Figure 3 is a schematic diagram of a power consumption mode switching system according to Embodiment 1 of the present application;

[0020] Figure 4 is a structural schematic diagram of a low power consumption control system according to an embodiment of the present application;

[0021] Figure 5 is a schematic diagram of a power consumption mode controller according to an embodiment of the present application;

[0022] Figure 6 is a schematic diagram of a power consumption mode switching state machine according to an embodiment of the present application;

[0023] Figure 7 is a schematic diagram of a timing and control interface mapping relationship according to an embodiment of the present application;

[0024] Figure 8 is a schematic diagram of a low-power software controller according to an embodiment of the present application;

[0025] Fig. 9 is a schematic diagram of a timing and control interface mapping relationship according to an embodiment of the present application;

[0026] Fig.10 It is a schematic diagram of a process of software and hardware collaboratively controlling power consumption mode switching according to an embodiment of the present application;

[0027] Fig.11 is a flow chart of a power consumption mode switching method according to an embodiment of the present application;

[0028] Fig.12 is a schematic diagram of a power consumption mode switching device according to an embodiment of the present application. DETAILED DESCRIPTION

[0029] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0030] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0031] First, some nouns or terms that appear in the description of the embodiments of the present application are subject to the following explanations:

[0032] Phase Locked Loop (PLL): A phase locked loop is a closed-loop feedback control system that generates an output signal that is frequency locked to a reference signal. In electronic devices, PLLs are often used for signal generation, frequency synthesis, and clock signal generation and recovery, for example in applications that require stable, precise frequency control, such as communication systems, computer clocks, and audio and video processing circuits.

[0033] Double Data Rate Synchronous Dynamic Random Access Memor (DDR): Double Data Rate Synchronous Dynamic Random Access Memor is a high-speed memory technology. DDR doubles the data transfer rate by transferring data on both the rising and falling edges of each clock cycle.

[0034] Power Management Integrated Circuit (PMIC): A power management integrated circuit is a chip used to manage power functions in electronic devices. PMIC can integrate multiple power management functions, such as voltage conversion, battery charging, power sequencing, voltage regulation and monitoring, and is often used in complex systems to improve battery efficiency, provide power protection, and ensure stable performance under different load conditions.

[0035] An Input / Output Controller (I / O controller for short) is a controller used to manage the input and output devices of a computer system. The I / O controller is responsible for processing the transmission of data between the computer system and external devices, including interface protocol conversion, data caching, data transmission control and other functions.

[0036] At present, the power consumption of chips is closely related to performance, reliability, heat dissipation, cost, and battery life. Therefore, it is a common technical means in the industry to adjust the power consumption mode of the chip in real time according to the working status and load of the chip to reduce the power consumption of the chip. For example, when a laptop is idle for a long time, it will automatically enter the sleep state. When the laptop is in the sleep state, the user taps a button to wake it up immediately. Behind the laptop state switching is the switching of the chip power consumption mode.

[0037] As the chip scale continues to increase and the design complexity continues to increase, the power consumption mode control of the chip is becoming more and more complex. Relying on software to configure the status of each module in the system in sequence to complete the power consumption mode switching not only increases the complexity of software design, but also has a high power consumption mode switching delay, which brings a poor user experience. Using the power consumption mode hardware switching circuit to realize the switching of the status of each module in the system can effectively improve the speed of power consumption mode switching, but at the same time, the flexibility and robustness of the system must be considered. Once a power consumption switching sequence is wrong, it will cause the chip function to fail. Therefore, how to balance the low latency and high reliability of chip power consumption mode switching is very important and meaningful.

[0038] According to an embodiment of the present application, a power consumption mode switching method is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0039] The method embodiment provided in Embodiment 1 of the present application can be executed in a RISC-V system, a RISC-V chip or a similar device. Figure 1 is a hardware structure block diagram of a RISC-V system for implementing a power consumption mode switching method according to an embodiment of the present application. Figure 1As shown, the RISC-V system 100 can be divided from the bottom layer to the upper layer into a reduced instruction set architecture 101 (including a basic instruction set 101-1 and an extended instruction set 101-2), a hardware layer 102 (including a processor 102-1, a peripheral hardware circuit 102-2, etc.), an interface layer 103, an operating system layer 104 (supporting multiple operating systems 104-1, 104-2, ..., 104-n, such as Linux, FreeSBD, RT-Tread, etc.), a middleware and library layer 105 (including a system library 105-1, an API 105-2 and a middleware service 105-3) and an application layer 106 (including multiple user programs and services 106-1, 106-2, ..., 106-n). The RISC-V system 100 also includes a tool chain 107 from the underlying hardware to the application layer. The tool chain may include a compiler and assembler 107-1, a linker 107-2, a debugger 107-3, a simulator and emulator 107-4, an integrated development environment 107-5, a hardware description language tool 107-6, a performance analysis tool 107-7, and a version control system 107-8, etc.

[0040] The instruction set architecture 101 defines the basic operations and instruction sets supported by the processor 102-1, including a basic instruction set and an extended instruction set, wherein the basic instruction set represents a basic integer instruction set, such as RV32I and RV64I, and the extended instruction set can be floating point, atomic operations, compressed instructions, etc.

[0041] The interface layer 103 includes the specific design of the processor, such as pipeline design, cache structure, execution unit, branch prediction, etc. This layer is the process of mapping abstract instructions to physical hardware.

[0042] The operating system layer 104 is located above the hardware and provides a hardware abstraction layer and management mechanism, so that applications can interact with the hardware through system calls. The operating system is responsible for managing processor resources, memory, device drivers, task scheduling, etc.

[0043] The middleware and library layer 105 provides a rich set of services and interfaces to help applications run more efficiently. For example, the standard library provides functions such as file operations and mathematical calculations, while the middleware can provide complex services such as network communications and graphical user interfaces.

[0044] The application layer 106 uses the functions and services provided by the lower layer to implement specific application logic. These applications can be command line tools, graphical interface applications, server-side services, etc.

[0045] The tool chain 107 is a key component that connects the underlying hardware to the upper-level software. Various tools in the tool chain 107 function at different levels to support the entire process from hardware design to software development, ensuring the consistency and effectiveness of the entire system design.

[0046] It should be noted that the layered design of the RISC-V architecture allows decoupling between different layers, so that each layer can be developed and optimized independently.

[0047] In an optional embodiment, Figure 2 Shown using the above Figure 1 Schematic diagram of the RISC-V architecture system on chip (SOC). Figure 2 is a schematic diagram of a system on chip according to an embodiment of the present application, such as Figure 2 As shown, the SOC includes at least one RISC-V core 202 (only one is shown in the figure), and the RISC-V core 202 is connected to peripheral devices through a bus 204, including but not limited to ROM 206 (Read-Only Memory), RAM 208 (Random Access Memory), timer 210, UART (Universal Asynchronous Receiver / Transmitter) 212, GPIO (General Purpose Input / Output) 214, SPI (Serial Peripheral Interface Bus) 216, etc.

[0048] Under the above operating environment, this application provides Figure 3 The power mode switching system is shown. Figure 3 Schematic diagram of a power consumption mode switching system according to Embodiment 1 of the present application. Figure 3 As shown, the system 300 includes: a task core 302 , a power management core 304 , a power consumption controller 306 , a power consumption mode controller 308 , and a plurality of hardware control devices 310 .

[0049] Among them, the task core is used to generate an entry request for a preset power consumption mode; the power consumption management core is used to configure the switching timing of the preset power consumption mode; the power consumption controller is connected to the task core and the power consumption management core, and is used to receive an entry request, or generate an exit request for the preset power consumption mode according to a received wake-up request; the power consumption mode controller is connected to the power consumption controller, and is used to execute the switching timing according to the entry request or the exit request to generate a control signal; multiple hardware control devices are respectively connected to the power consumption mode controller, and are used to enter the preset power consumption mode or exit the preset power consumption mode according to the control signal, wherein different hardware control devices have different control types.

[0050] The above-mentioned power consumption controller may include a power consumption controller of a task core and a power consumption controller of a power consumption management core. When entering the low power consumption process, the power consumption controller of the task core controls the task core to enter low power consumption and then initiates a request to enter low power consumption to the power consumption mode controller. When entering the low power consumption process, the power consumption controller of the power consumption management core controls the power consumption management core to enter low power consumption after receiving a power consumption mode switching completion indication from the power consumption mode controller. When exiting the low power consumption process, the power consumption controller of the task core controls the task core to exit low power consumption after receiving a power consumption mode switching completion indication from the power consumption mode controller. When exiting the low power consumption process, the power consumption controller of the power consumption management core receives a system wake-up signal, controls the power consumption management core to exit low power consumption, and then initiates a request to exit low power consumption to the power consumption mode controller.

[0051] Furthermore, the power consumption software controller can be connected to the power consumption mode controller through a control interface, and receive a control signal sent by the power consumption mode controller. Generate a low power consumption request interrupt and send it to the power consumption management core. Receive the entry and exit low power consumption completion feedback signal written into the register by the power consumption management core, and then send the feedback signal to the power consumption mode controller. Count the control signal and store the count value in the register.

[0052] The above-mentioned task core can be a processor or core responsible for processing a specific task, and the task core can be a processor or microprocessor responsible for application-level processing. The task core can be the main computing unit in the system-level chip, and the working state of the task core is related to the performance and power consumption of the system. When the system is in a low-load or standby state, its power consumption can be significantly reduced by reducing the operating frequency and voltage of the task core or shutting down unnecessary functional modules. Conversely, when the system requires high-performance operation or processing sudden tasks, the task core must quickly return to normal power consumption mode to ensure sufficient computing power and response speed. The task core can detect its own working state and load condition. When it finds that the system is in a low-load state, it can actively request to enter a low-power mode to save power.

[0053] The above-mentioned power consumption mode controller is a device for managing the switching of system power consumption modes. It receives power consumption control requests from the power consumption controllers corresponding to the task core and the power consumption management core, and generates corresponding control signals according to these requests, thereby realizing the switching of power consumption modes. The function of the power consumption mode controller is to adjust the power consumption mode of the device in real time according to the requests of the power consumption controllers corresponding to the task core and the power consumption management core, so as to achieve better power consumption management and performance under different workloads. By responding to the requests of the task core and the power consumption management core in a timely manner, the power consumption mode controller can effectively reduce the power consumption of the device, extend the battery life of the device, and improve the performance of the device. The power consumption mode controller can effectively balance the relationship between power consumption and performance, improve the energy efficiency ratio of the device, and enhance the user experience.

[0054] The power management core mentioned above may be a core for processing power control strategies and executions. The power management core is responsible for configuring the switching timing of power consumption modes and cooperating with the power consumption mode controller to complete the power consumption mode switching controlled by software and hardware in collaboration.

[0055] The power consumption mode controller can be used to receive a request for entering or exiting a power consumption mode sent by a task core or a power consumption management core corresponding to the power consumption controller, and generate a control signal according to a preset switching sequence and send it to the hardware control device.

[0056] The above-mentioned hardware control device can be a hardware controller that directly controls the corresponding power consumption state of each device in the system, such as a Phase Locked Loop Controller (PLL controller for short), a Double Data Rate Synchronous Dynamic Random Access Memory Controller (DDR controller for short), an Input / Output Controller (I / O controller for short), etc. The power consumption mode of each managed hardware controller can be adjusted according to the control signal sent by the power consumption mode controller.

[0057] The above-mentioned preset power consumption mode may be a low power consumption mode or any other predefined power consumption mode, which is used to reduce the power consumption of the system under specific conditions (such as sleep, standby).

[0058] The switching sequence mentioned above can refer to the order and timing of the control actions of various parts of the system when entering or exiting a preset power consumption mode. It can be the order and timing of each hardware module performing its specific control actions when the chip switches from one power consumption mode to another. In low-power design, when the system enters a low-power consumption mode such as sleep, hibernation or standby, or wakes up from these modes and returns to normal working mode, different hardware modules need to be controlled in a certain order and time to ensure the stability of the system and the optimization of power consumption.

[0059] For example, when the system needs to enter a low-power mode, the switching sequence may include the following steps:

[0060] Step 1: Turn off unnecessary clock signals (clock generators).

[0061] Step 2: Turn off the power supply of the power management chip (PMIC) to non-critical hardware modules.

[0062] Step 3, precharge the dynamic random access memory (DDR) or enter a self-refresh mode.

[0063] Step 4, turn off the phase-locked loop (PLL) to reduce power consumption associated with frequency generation.

[0064] Step 5, reset some hardware modules (reset generator).

[0065] Step 6: Wait for confirmation feedback from all modules that they have entered a low power consumption state.

[0066] During the wake-up process, the switching sequence can be configured to ensure that the hardware modules are activated in the correct order, such as restoring the clock signal first and then gradually activating other hardware resources. The switching sequence can be executed by the hardware circuit, that is, the power mode controller mentioned above, and the power management core can be used to configure the switching sequence of the preset power mode, thereby ensuring low latency while also providing flexibility and robustness, ensuring efficient and safe power mode switching.

[0067] When the task core detects that the system needs to enter a preset power consumption mode (such as a low power consumption mode), the task core can generate an entry request. The power consumption controller of the task core receives the entry request initiated by the task core, controls the task core to enter low power consumption, and then initiates an entry request to the power consumption mode controller. The power consumption management core is responsible for configuring the timing of the entire switching process, and when the system needs to exit from the preset power consumption mode, it cooperates with the power consumption mode controller to complete the power consumption mode switching controlled by software and hardware in collaboration. The power consumption controller of the power consumption management core receives the system wake-up request, controls the power consumption management core to exit low power consumption, and then initiates an exit request to the power consumption mode controller. Based on the received request, the power consumption mode controller controls multiple hardware control devices to switch the power consumption mode according to the preset timing, that is, from normal mode to low power consumption mode, or from low power consumption mode to normal mode. Low latency of power consumption mode switching can be guaranteed through hardware control, and flexibility can be provided by configuring the switching timing of the preset power consumption mode according to different task requirements and special scenarios through the power consumption management core.

[0068] Exemplarily, when the electronic device is not in use by the user, the task core detects the system idle state and triggers a request to enter the low power mode. After receiving the request, the power management core configures the system power mode and hardware switching timing to minimize delay and power consumption, for example, first turning off the unnecessary PLL, then controlling the DDR to enter the self-refresh state, and finally turning off some I / O interfaces. The power mode controller generates a control signal according to the preset timing, and sends it to the PLL controller, DDR controller and I / O controller in sequence, so that these hardware modules enter the low power state. When the user uses the electronic device again, the power management core power controller receives a system wake-up request, such as a system interrupt or a request passed in through IO. Control the power management core to exit the low power mode and control the system power mode switcher to switch the mode. The I / O interface can be restored first, then DDR, and finally PLL, so that the system can quickly restore to a full-function state, while ensuring the integrity of the power mode switching, avoiding possible omissions in the hardware fixed switching process, and ensuring the reliability of the system and user satisfaction. In this way, the system can not only respond quickly to the switching of power modes, but also flexibly respond to various task requirements and special scenarios, thereby improving the power management performance and user experience of the entire system.

[0069] In the above embodiment of the present application, the hardware control device includes: a first control interface, connected to the power consumption mode controller, for receiving a control signal; a hardware controller, correspondingly connected to the first control interface, for entering a preset power consumption mode or exiting a preset power consumption mode according to the control signal, and feeding back the control state of the preset power consumption mode to the power consumption mode controller, wherein the control state is used to indicate whether the hardware controller has successfully entered the preset power consumption mode or successfully exited the preset power consumption mode.

[0070] The first control interface mentioned above may be a communication bridge between the hardware control device and the power consumption mode controller. The first control interface may be an interface directly connected to the hardware controller, such as an interface for connecting to a PLL controller, a DDR controller, and the like.

[0071] The control signal mentioned above may be a signal for instructing the hardware to perform a specific operation. The control signal refers to an instruction issued by the power consumption mode controller, which is used to instruct the hardware control device to enter or exit a preset power consumption mode.

[0072] The above-mentioned hardware controller may be a circuit that directly controls the state of a certain hardware module, such as a PLL controller that is used to control the working mode of a phase-locked loop, and a DDR controller that is used to control the power consumption state of a DDR memory.

[0073] The control state mentioned above refers to the state feedback of whether the hardware controller successfully enters or exits the preset power mode after executing the power mode switching operation. This state is used by the power mode controller to determine whether the power mode switching is completed.

[0074] The hardware control device receives the control signal of the power mode controller through the first control interface. The hardware controller adjusts the hardware module controlled by it to enter or exit the low power mode according to the received control signal, and feeds back its control state to the power mode controller to confirm whether the power mode switching operation is successfully executed. Through the cooperation between the hardware control device and the power mode controller, the low power mode switching is fast and reliable. Compared with relying entirely on software control, this method greatly reduces the delay of power mode switching and improves the efficiency of power mode switching.

[0075] Exemplarily, when the smart watch detects that the user has not used it for a long time, the task core (the operating system of the smart watch) will request to enter the low power mode through the power mode controller. After receiving the request, the power mode controller sends a control signal to the hardware controller through the first control interface, such as first sending a control signal to the DDR controller to request it to enter the low power mode. The first control interface receives the control signal and sends the control signal to the DDR controller. The DDR controller receives the control signal, adjusts the DDR memory controlled by it to enter the low power mode, and sends control status feedback to the power mode controller to confirm that the DDR memory has successfully entered the low power mode. After that, the power mode controller controls other hardware controllers, such as the PLL controller, the PMIC controller, etc., in sequence through the first control interface according to the preset timing to enter the low power mode. In the whole process, the interaction between the hardware control device and the power mode controller enables the smart watch to enter the low power mode in a very short time, prolong the battery life, and ensure the correctness and stability of the system function. Even in the case where some hardware controllers cannot respond, such as the PMIC controller does not respond, the system can adjust the strategy in time according to the feedback control state to avoid the failure of the power mode switching and ensure the reliability of the system.

[0076] In the above embodiment of the present application, the power consumption mode controller includes: a control circuit, which is used to generate a one-hot code according to an entry request or an exit request, wherein the one-hot code is used to represent the encoding method of the switching timing; a state machine, connected to the control circuit, which is used to generate a control signal according to the one-hot code and a timing judgment condition, wherein the timing judgment condition is used to indicate whether the currently executed timing in the switching timing is the last valid timing.

[0077] The one-hot code mentioned above may be generated in the control circuit according to the request and the timing configuration register, wherein the request may be an entry request or an exit request.

[0078] The above-mentioned control circuit can be a hardware logic circuit for processing input signals and generating corresponding control signals. In the present application, the main responsibility of the control circuit is to convert the request signal for power mode switching into a unique hot code for easy recognition by the state machine, and to generate a control signal based on the state signal fed back by the state machine and output it to the hardware controller.

[0079] The control circuit is responsible for processing the request to switch the power mode and generating a one-hot code to instruct the state machine to execute a specific switching sequence. One-hot code is a coding method that can represent the currently active state among multiple states in binary form, where only one bit is 1 and the rest are 0. This coding method can clearly indicate the specific state the system is currently in.

[0080] Exemplarily, when the task core sends a request to enter a low power mode or a request to exit a low power mode to the system, the control circuit first parses the request and generates a one-hot code according to the information in the pre-configured power mode and switching timing register. The one-hot code will correspond to a specific step or timing in the power mode switching process.

[0081] In the process of generating the one-hot code, the control circuit also needs to generate a timing judgment condition, which is used to tell the state machine whether the power mode switching timing currently executed is the last valid timing in the entire switching process. This judgment condition is used to ensure the integrity and certainty of the power mode switching, which can help the state machine understand when the power mode switching will be completed, so that it can take corresponding subsequent actions, such as sending a mode switching completion indication or entering a waiting wake-up state.

[0082] The control circuit not only generates the one-hot code and timing judgment conditions, but also receives feedback signals from each hardware controller and combines these feedback signals to generate an overall timing completion feedback signal, which is used to notify the state machine whether the current timing switch has been successfully completed. In addition, the control circuit will transparently transmit the power mode information in the power mode register to each control interface to control the corresponding module to enter or exit the low power state.

[0083] The control circuit can convert software requests into one-hot codes that can be understood by hardware, instructing the state machine to perform power mode switching at a specific timing. It can also process feedback from each hardware controller to ensure the accuracy and reliability of power mode switching, effectively combining the flexibility of software and the efficiency of hardware.

[0084] The one-hot code mentioned above is a coding method in which each state is represented by only one bit, and all other bits are in the opposite state (usually zero). In power mode switching, the one-hot code is used to indicate the timing that should be executed currently. The one-hot code can be used to control the timing of power mode switching. By converting the timing configuration into a one-hot code, it is possible to accurately control which operation the state machine performs in each timing, and at the same time clearly identify whether the current operation is the last operation, thereby achieving flexible and efficient power mode switching.

[0085] The state machine can be a hardware based on the transition between states, used to execute a series of predefined rules or operations until the final state is reached. The state machine is used to parse the one-hot code and generate a timing conversion state according to the timing judgment condition.

[0086] The above timing judgment condition is used to judge whether the currently executed power consumption mode switching timing is a logic signal of the last valid timing in the entire sequence.

[0087] When a low-power entry or exit request is received, the control circuit converts the request into a one-hot code and generates a timing judgment condition to determine whether the current timing is the last one in the valid sequence. The state machine generates a timing conversion state based on the received one-hot code and the timing judgment condition, and the control circuit generates a control signal based on the timing conversion state to control the corresponding hardware controller to enter or exit the low-power state. The control circuit also receives a feedback signal from the hardware controller to confirm whether the timing control signal is executed correctly. After the last valid timing is completed, the control circuit generates a mode switching completion indication to notify the state machine and the processor's power controller. The processor's power controller controls the power management core to enter the low-power state or controls the task core to exit the low-power state based on the mode switching completion indication.

[0088] By using one-hot codes and timing judgment conditions, the power mode controller achieves fast, reliable and flexible switching of low power modes. One-hot codes allow the state machine to clearly identify the timing that should be processed at the moment, avoiding the delay of complex software scheduling; the timing judgment conditions ensure that the hardware can correctly complete the mode switch after executing the valid timing, enhancing the robustness and reliability of the system. This hardware control method not only reduces the delay of power mode switching, but also improves flexibility through software configuration timing, allowing the system to adapt to various task requirements and avoiding potential risks caused by fixed hardware timing.

[0089] For example, suppose that in a computing device equipped with a RISC-V processor, the user triggers the sleep mode after a long period of inactivity, and the power mode controller of the laptop needs to control multiple modules such as the CPU, DDR memory, PLL, and I / O interface to enter a low power state. The control circuit converts the timing information into a unique hot code according to the timing register configured by the power management core. For example, timing 1 is set to control DDR to enter low power consumption, and the unique hot code is 7'b0000100`. The state machine starts to execute the timing of controlling DDR to enter low power consumption according to the unique hot code and timing judgment conditions. After receiving the low power control signal, the DDR controller enters a low power state and feeds back a completion signal to the control circuit. The control circuit confirms that timing 1 has been completed according to the feedback signal, and continues to execute the next timing control. This process is repeated until the state machine detects that the current timing is the last valid timing and the timing has been completed, and the control circuit generates a mode switching completion indication, notifies the power management core power controller, and the power management core controller controls the power management core to enter low power consumption, and the system officially enters a low power mode. It should be noted that the numerical values ​​involved above are only for illustration and are not intended to be specific limitations.

[0090] Through the above control process, not only does hardware control reduce the delay of power mode switching, but also the flexibility and reliability of the system are enhanced through the arbitrary timing switching method configured by the power management core, so that the chip can more effectively respond to different task scenarios and user needs, and achieve a balance between power consumption control and system performance.

[0091] In the above embodiment of the present application, the power consumption mode switching system further includes: a timing configuration register connected to the power consumption management core, and used to store the switching timing after receiving the switching timing configured by the power consumption management core.

[0092] The timing configuration register is a hardware register used to store control signal sequences. It records the order and time intervals of each module's actions during a specific operation (such as power mode switching) according to the system configuration requirements. These registers are key components for implementing hardware circuit timing control and can be dynamically adjusted according to software configuration to adapt to different system states and load requirements.

[0093] The above-mentioned timing configuration registers may include but are not limited to low-power entry timing configuration registers, low-power exit timing configuration registers, and power consumption mode registers of each control object. These three groups of registers determine the entire low-power entry and exit mode switching timing and the low-power consumption mode of each module.

[0094] In the process of power mode switching, the power management core first sets multiple sets of timing configurations for different power modes according to system requirements, and sets the operation sequence and time interval of each module during the power mode switching process. When the system needs to enter low power mode, the power management core selects and issues a set of configurations according to the selected power mode, which are stored in the timing configuration register. Subsequently, at the start of the power mode switching, the power mode controller reads the information in the timing configuration register, and controls each hardware module to enter the low power state in sequence according to the predetermined timing, or restores to the normal working state according to the pre-configured exit timing when waking up.

[0095] In an embodiment of the present application, the timing configuration register is connected to the power management core through a bus. After the power management core configures the timing configuration register, it triggers the power mode controller to complete the power mode switching, providing the ability to dynamically adjust the power mode switching timing at the hardware level. This not only reduces the complexity of software configuration and reduces the delay of power mode switching, but also ensures the flexibility and robustness of power mode switching. Through the timing configuration register, users can flexibly set the switching order of power modes according to different task requirements and usage scenarios, avoiding system function failure or inefficiency problems that may be caused by fixed timing, and enhancing the overall performance of the system and user experience.

[0096] For example, suppose that when the system is idle, the power management core finds through analysis that power consumption can be further reduced without affecting system responsiveness. At this time, the power management core will configure the low-power entry timing configuration register and set a low-power entry timing, such as turning off the PLL first, then letting the DDR enter the low-power state, and finally controlling the power management core to enter low power. When the user triggers the wake-up operation, the system will recover according to the pre-configured low-power mode exit timing. The power management core will be awakened first, then the DDR, and finally the PLL. In this way, not only the delay of power mode switching is significantly reduced, but also the flexibility and reliability of the entire process are enhanced. When dealing with changing task scenarios, it can manage power consumption more efficiently and intelligently, improving the overall performance and user experience of the system.

[0097] In the above embodiment of the present application, the power consumption mode switching system also includes: a second control interface, connected to the power consumption management core, and used to receive a control signal; a software controller, connected to the second control interface and the first control interface, and used to generate a count value according to the control signal, wherein the count value is used to represent a numerical value obtained by counting the control signal; the power consumption management core, used to call the control program corresponding to the count value, and enter or exit the preset power consumption mode by executing the control program.

[0098] The first control interface is used as a communication connection structure between the power management core and the software controller.

[0099] The software controller may be a power mode switching system, in addition to the first control interface that directly communicates with the hardware controller, an additional software controllable interface circuit for inserting software control logic into the hardware switching process. The software controller may be a low power software controller.

[0100] The software controller is composed of a control circuit and a request counting circuit, and can receive entry requests and exit requests from the power mode controller, and notify the power management core by counting and interrupting, so that the software can intervene in the control process.

[0101] The above-mentioned count value may be a result value obtained by counting the control signal by the request counting circuit, and is used by the software to identify the current stage of the power consumption mode switching so as to execute the corresponding control program.

[0102] The power mode switching system introduces a software controller to control specific timing points in the hardware switching process. In the switching process, the power mode controller sends a control signal to the software controller according to the preset timing configuration, triggers counting and generates a count value. The power management core calls the pre-stored control program based on the count value read to perform specific power mode switching operations, such as shutting down unnecessary circuits and reducing clock frequency.

[0103] Through the combination of hardware control and software control, the present application overcomes the problem of large delay of software control alone, as well as the shortcomings of poor flexibility and versatility of hardware control alone. The collaborative control of software and hardware improves the speed of power mode switching, while providing sufficient flexibility to meet the needs of different scenarios. When the system needs to quickly enter a low-power state, hardware control can quickly complete the control of most modules to reduce latency. However, if the control of a specific module is omitted in the hardware control process, or the user has new low-power control requirements during system operation, the software controller and the power management core can call the corresponding software control program according to the count value to control the omitted modules or meet new control requirements, thereby ensuring the integrity and flexibility of power mode switching while maintaining the advantage of switching speed.

[0104] For example, suppose the system is using high-performance mode for complex calculations, and the user triggers a request for the system to enter low-power mode. The power mode switching system first sends a low-power request to the power mode controller by the task core, and the controller starts execution from timing 1 according to the preset timing configuration. At timing 2 and timing 6, the controller sends a low-power entry request to the software controller, triggers the counting circuit to count, generates a specific count value, and sends an interrupt notification to the power management core. After the power management core reads the count value, it reads and executes the pre-stored control program according to the count value. For example, the control program at timing 2 may include adjusting the power consumption state of the PLL, and the control program at timing 6 may involve special power consumption settings for the PMIC. Through such software and hardware collaborative control, the system can quickly and accurately enter the low-power mode. Even if the control of some modules may be omitted in the hardware control process, the software control can ensure the integrity and reliability of the entire switching process, while meeting the power consumption requirements in specific scenarios.

[0105] In the above embodiment of the present application, the software controller includes: a request counting circuit, which is used to count the control signal according to the trigger information of the control signal to obtain a count value.

[0106] The trigger information is specific data or conditions carried in the control signal, which is used to determine the processing method of the control signal. The trigger information may include but is not limited to the type, quantity, frequency or order of the control signal.

[0107] In the low power mode switching process, the trigger information may be the order and number of low power request signals and wake-up request signals issued by the power mode controller, and the power management core determines the low power control program to be executed based on this information.

[0108] The request counting circuit described above can be used to monitor and count the number of control signals received within a certain period of time. The request counting circuit can be used in system design that requires counting the frequency or number of operations. The request counting circuit can be used to monitor the number of low-power request and wake-up request signals received from the power mode controller, and these count values ​​are used to determine the low-power control program executed by the power management core.

[0109] When the request counting circuit receives a control signal, the counting circuit can update an internal counter, and the value of this counter is the count value, which is used to reflect the reception of the control signal. After obtaining the count value, the count value can be converted into an operation instruction set that can be understood by the power management core. Different count values ​​are matched with different control programs or operation instructions through soft coding and other methods.

[0110] In an optional embodiment, the request counting circuit receives the control signal initiated by the power mode controller, counts it, and generates a count value. This count value is output to the register, and the power management core reads the count value in the register and determines the low power control program to be executed through the soft coding mechanism. This process not only takes advantage of the low latency characteristics of the hardware, but also retains the flexibility and programmability of the software, so that the system can dynamically adjust the power control strategy according to the count value (i.e., the frequency and sequence of the control signal).

[0111] The above-mentioned soft coding is a coding mechanism implemented at the software level, as opposed to hard coding, which is usually implemented at the hardware level. Soft coding is mainly used in fields such as data processing, communication protocols, and control logic, allowing the coding process or coding information to be dynamically adjusted at runtime rather than being fixed at the design or production stage. In the scenario of hardware-software co-design, soft coding can be used to define and control the behavior of hardware components in terms of power management, timing control, etc. The execution process or operation mode of the hardware can be determined by software-controlled register configuration, algorithm decision-making, or the operation of the state machine. The flexibility of soft coding lies in that it can change with changes in software requirements without modifying the hardware design, thereby improving the programmability and adaptability of the system.

[0112] The request counting circuit enables the control signal of power mode switching to be accurately counted. By soft-coding the mapping relationship between the count value and the low-power control program, the fast response and flexibility of power mode switching are achieved. This method avoids the limitations of hardware fixed timing switching, while reducing the delay caused by software control, ensuring efficient power management of the chip under different task requirements. The power management core can quickly determine and execute a more appropriate low-power control strategy based on the actual control signal sequence received, improving the overall response speed of the system and the accuracy of power control.

[0113] Exemplarily, if the power consumption mode controller needs to dynamically adjust the power consumption mode according to the task requirements. In the process of entering the low power consumption mode, the control signal is triggered at timing 1, timing 3, and timing 5 respectively, and the request counting circuit records that a total of 3 low power consumption requests have been triggered. After receiving the request interrupt, the power management core reads the count value (for example, 3) output by the request counting circuit to the register, and parses it through the soft coding table to find out that this represents the low power consumption mode of turning off the PLL controller, DDR controller, and PMIC controller. Therefore, the second control interface of the software controller can be combined with the hardware control as a supplementary interface for the hardware control, while also retaining the flexibility of dynamically adjusting the power consumption control process according to specific task requirements.

[0114] Figure 4 is a schematic diagram of a low power consumption control system according to an embodiment of the present application. Figure 4 As shown, the task core can be responsible for requesting to enter the low power mode, the power management core is responsible for configuring the power mode and switching timing, the processor low power controller is responsible for controlling the processor to enter and exit low power consumption, the power mode controller is responsible for switching the system power mode, and the controllers of each module connected to the power mode controller include but are not limited to the hardware controllers such as the PLL controller, DDR controller, IO controller, clock generator, PMIC controller, reset generator, etc. listed in this application. The controllers of the above modules can complete the low power control of each module in the system by receiving the request of the power mode controller. The first control interface is set between the power mode controller and the controllers of each module, and the low power software controller is connected to the power management core and the power mode controller through the first control interface and the second control interface.

[0115] Combination Figure 4 , the power mode switching process includes the following steps:

[0116] Step S401: The task core requests the system to enter low power consumption and notifies the power management core.

[0117] Step S402, the power management core configures the power consumption mode and switches the timing register;

[0118] Step S403, the processor low power consumption controller of the task core controls the task core to enter a low power consumption mode;

[0119] Step S404, the processor low power controller of the task core initiates a low power request to the power mode controller;

[0120] Step S405, the power consumption mode controller starts power consumption mode switching, executing from timing 1 to timing N;

[0121] Step S406, the power consumption mode controller completes the power consumption mode switching and issues a mode switching completion indication;

[0122] Step S407, the processor low power controller of the power management core receives the power mode switching completion indication, and controls the power management core to enter the low power mode;

[0123] Step S408, the power management core enters the low power mode and waits for wake-up, and the low power entry process is completed;

[0124] Step S409: the low power consumption controller of the power consumption management core receives the wake-up request and controls the power consumption management core to exit the low power consumption mode;

[0125] Step S410, the power management core is awakened;

[0126] Step S411, the low power controller of the power management core initiates a wake-up request to the power mode controller;

[0127] Step S412, the power consumption mode controller starts power consumption mode switching, executing from timing 1 to timing N;

[0128] Step S413, the power consumption mode controller completes the power consumption mode switching and issues a mode switching completion indicator;

[0129] Step S414, the power consumption manager of the task core receives the power consumption mode switching completion indication, and controls the task core to exit low power consumption;

[0130] Step S415, the task core is awakened, and the low power mode exit process is completed.

[0131] In the above steps S405 to S412, the power consumption mode controller supports low power consumption mode switching at any timing.

[0132] Figure 5 is a schematic diagram of a power consumption mode controller according to an embodiment of the present application, such as Figure 5 As shown, the control circuit receives low-power entry timing configuration registers (each timing has a set of registers), low-power exit timing configuration registers (each timing has a set of registers), and power consumption mode registers of each control object (each control interface has a set of registers) from registers. These three sets of registers determine the entire low-power entry and exit mode switching timing and the low-power mode of each module.

[0133] The control circuit and the state machine receive a low-power entry request initiated by the low-power controller of the task core, and receive a low-power exit request initiated by the low-power controller of the power management core. The control circuit converts the low-power entry and exit timing configuration registers into a unique hot code and sends it to the state machine, and generates a judgment condition of whether each timing is the last valid timing and sends it to the state machine. The control circuit receives a low-power entry feedback signal and a low-power exit feedback signal from each control interface in the module controller, generates a feedback signal for each timing and sends it to the state machine. The control circuit receives a state indication signal of the state machine, generates a low-power entry request signal and a low-power exit request signal and sends them to the control interface of each module controller, generates a mode switching completion indication signal, and sends it to the state machine and the low-power controller of the processor. The control circuit also transparently transmits the input power mode register to each control interface to control the power mode of the control object.

[0134] Figure 6 is a schematic diagram of a power consumption mode switching state machine according to an embodiment of the present application, such as Figure 6 As shown, the workflow of the state machine includes the following steps:

[0135] Step S601 : After receiving a low power consumption request, the low power consumption entry and wake-up control state machine switches from an “idle state” to an “entering low power consumption state”.

[0136] Step S602, the timing conversion control state machine starts to work, and if the next timing is not the last valid timing, the timing conversion state machine enters "timing state 1" from "idle state".

[0137] Step S603, the timing conversion control state machine is in "timing state 1". If the next timing is the last valid timing and the current timing is completed, it directly enters the "final state"; if the current timing is invalid or the current timing is completed, it enters the next timing, and repeats this step until it enters the "final state".

[0138] Step S604, the timing conversion state machine returns from the "final state" to the "idle state", and the control circuit generates a mode switching completion indication, notifies the low power entry and wake-up control state machine, and notifies the processor low power controller.

[0139] Step S605, the low power consumption entry and wake-up control state machine enters the "waiting wake-up state", and the switching into the low power consumption mode is completed.

[0140] Step S606: The low power consumption entry and wake-up control state machine receives the wake-up request and enters the "exit low power consumption state".

[0141] Step S607, repeating the above steps S602 to S604, the low power consumption entry and wake-up control state machine returns to the "idle state", and the exit from the low power consumption mode is completed.

[0142] The power mode controller divides the mode switching process into N timings (N can be determined according to actual needs). Figure 7 is a schematic diagram of a timing and control interface mapping relationship according to an embodiment of the present application, such as Figure 7 As shown, each timing corresponds to a set of programmable timing configuration registers, which determine the control interface of the timing operation. For example, if the control interface 3 is operated at timing 1, the configuration register of timing 1 is 3'b011, if the control interface is not operated at timing 2, the configuration register of timing 2 is 3'b000, if the control interface 1 is operated at timing 3, the configuration register of timing 3 is 3'b001, if the control interface 4 is operated at timing 4, the configuration register of timing 4 is 3'b100, if the control interface 5 is operated at timing 5, the configuration register of timing 5 is 3'b101, if the control interface 2 is operated at timing 6, the configuration register of timing 6 is 3'b010, and if the control interface 6 is operated at timing 7, the configuration register of timing 7 is 3'b110. The specific implementation method is that the one-hot code is the one-hot code of the low-power entry timing configuration register and the low-power exit timing configuration register, and the values ​​of the low-power entry request signal and the low-power exit request signal are equivalent to the one-hot code.

[0143] Taking Table 2 as an example, in timing state 1, the low-power entry timing configuration register is configured to 3'b011, the output low-power entry request signal bit 2 is high, the one-hot code is 7'b0000100, and this bit is hard-wired to the DDR controller, thereby realizing low-power control of DDR. In timing state 2, the low-power entry timing configuration register is configured to 3'b000, the output low-power entry request signal is none, the one-hot code is 7'b0000000, and no control is performed. In timing state 3, the low-power entry timing configuration register is configured to 3'b001, the output low-power entry request signal bit 0 is high, the one-hot code is 7'b0000001, and this bit is hard-wired to the PLL controller, thereby realizing low-power control of PLL. In timing state 4, the low-power entry timing configuration register is configured as 3'b100, the 3rd bit of the output low-power entry request signal is high, the one-hot code is 7'b0001000, and the bit is hard-wired to the IOPAD controller, thereby realizing low-power control of the IO PAD. In timing state 5, the low-power entry timing configuration register is configured as 3'b101, the 4th bit of the output low-power entry request signal is high, the one-hot code is 7'b0010000, and the bit is hard-wired to the CLK controller, thereby realizing low-power control of the CLK. In timing state 6, the low-power entry timing configuration register is configured as 3'b010, the 1st bit of the output low-power entry request signal is high, the one-hot code is 7'b0000010, and the bit is hard-wired to the RST controller, thereby realizing low-power control of the RST. In timing state 7, the low power entry timing configuration register is configured to 3'b110, the 5th bit of the output low power entry request signal is high, and the unique hot code is 7'b0100010. This bit is hardwired to the PMIC controller to achieve low power control of the PMIC. When the timing configuration is 0, it means that there is no operation in this timing state, that is, invalid timing. Therefore, by configuring the configuration register of each "timing state", the power consumption mode switching of any timing can be achieved.

[0144] Table 2

[0145]

[0146] In summary, the power mode controller realizes power mode switching with arbitrary timing. Users can reasonably configure the timing configuration registers according to their needs, so as to complete the power mode switching safely and reliably and avoid the risks brought by hardware fixed switching timing.

[0147] The present application proposes a power consumption mode hardware switching method, which designs a hardware circuit that supports arbitrarily configurable low-power consumption control timing, so that users can reasonably configure the power consumption mode timing according to task requirements. Since it is a hardware switching circuit, the power consumption mode switching speed is improved and the complexity of software design is reduced. In addition, since the low-power consumption control timing supports arbitrary configuration rather than hardware fixed, users can customize the corresponding power consumption mode timing according to the actual task scenario, thereby increasing the flexibility and reliability of the system. This power consumption mode hardware switching circuit is suitable for various systems with power consumption switching requirements and has a certain degree of versatility.

[0148] In another optional embodiment, Figure 4 On the basis of this, in step S405 to step S412, the power consumption mode controller controls each control interface to complete the switching of power consumption modes with arbitrary timing, wherein control interface 1 is connected to the low power consumption software controller, and the other control interfaces are connected to the hardware controllers of each module, and the power consumption mode switching method of software and hardware collaborative control is realized by combining the software and hardware control interfaces.

[0149] Figure 8 is a schematic diagram of a low power consumption software controller according to an embodiment of the present application, such as Figure 8 As shown, the low-power software controller consists of a control circuit and a request counting circuit. The control circuit receives the low-power request and wake-up request initiated by the power mode controller, generates a request interrupt, and notifies the power management core. The request counting circuit receives the low-power request and wake-up request initiated by the power mode controller to count, and outputs the count value to the register. After receiving the request interrupt, the power management core reads the value of the counter to determine the low-power control program to be executed (the software performs a soft coding on the count value and the low-power control program). The control circuit receives the low-power feedback signal and the wake-up feedback signal from the register, and feeds back to the power mode controller.

[0150] Fig. 9 is a schematic diagram of a timing and control interface mapping relationship according to an embodiment of the present application, such as Fig. 9 As shown, the power mode controller divides the mode switching process into N timings (N is determined according to actual needs), and each timing corresponds to a set of programmable timing configuration registers, which determine whether the control interface of the timing operation is software control or hardware control. Fig. 9The figure shows the corresponding workflow for entering low power consumption (the exit low power consumption process is similar). The power controller switches from sequence 1 to sequence N. Each sequence controls a group of control interfaces, where sequences 2 and 6 control software control interfaces, and the remaining sequences control hardware control interfaces, thereby realizing a method for switching power consumption modes with cross-control of software and hardware. For example, if control interface 3 is operated at sequence 1, the configuration register of sequence 1 is 3'b011. If control interface 1 is operated at sequence 2, the configuration register of sequence 2 is 3'b001. If control interface 4 is operated at sequence 3, the configuration register of sequence 3 is 3'b100. If control interface 2 is operated at sequence 4, the configuration register of sequence 4 is 3'b010. If control interface 6 is operated at sequence 5, the configuration register of sequence 5 is 3'b110. If control interface 1 is operated at sequence 6, the configuration register of sequence 6 is 3'b001.

[0151] Fig.10 is a schematic diagram of a software and hardware collaborative control power consumption mode switching process according to an embodiment of the present application, such as Fig.10 As shown, the low power consumption software control process includes:

[0152] Step S1001: the low power software controller receives a low power entry request from the power mode controller.

[0153] Step S1002, request the counting circuit to count and save it to the register.

[0154] Step S1003: the control circuit generates a request interrupt.

[0155] Step S1004 , the power management core receives a request interrupt and reads a count register.

[0156] Step S1005: the power management core clears the request interrupt.

[0157] Step S1006 , the power management core executes a corresponding low power control program according to the count value, and the specific control command is determined according to the pre-agreed soft coding.

[0158] Step S1007 , the power management core writes the low power feedback register, indicating that the software-controlled low power operation has been completed.

[0159] Step S1008: the control circuit generates a low power consumption feedback signal.

[0160] Step S1009: the power consumption mode controller receives the feedback signal, completes the current low power consumption control sequence, and enters the next sequence.

[0161] The power mode switching process includes:

[0162] Step S1101 , the power consumption controller switches to sequence 1 .

[0163] Step S1102, control interface 3 is controlled to control the clock generator.

[0164] Step S1103: the power consumption controller switches to sequence 2.

[0165] Step S1104, controller interface 1 is controlled, and the software takes over low power consumption control.

[0166] Step S1105 , the power consumption controller switches to sequence 3 .

[0167] Step S1106, control interface 4 to be controlled, and control IO.

[0168] Step S1107 , the power consumption controller switches to sequence 4 .

[0169] Step S1108 , control interface 2 to be controlled, and control PMIC.

[0170] Step S1109 , the power consumption controller switches to sequence 5 .

[0171] Step S1110, the control interface 6 is controlled to control the PLL.

[0172] Step S1111 , the power consumption controller switches to sequence 6 .

[0173] Step S1112, control interface 1 is controlled, and the software takes over the low power consumption control.

[0174] This application has connected a software-controlled interface in the entire power mode hardware switching process, which not only effectively reduces the delay of power mode switching, but also effectively responds to certain special scenarios, such as the lack of control of a module in the hardware switching process, resulting in power consumption not meeting expectations, or the user has added some low-power control requirements. The collaborative control of power mode switching by software and hardware not only improves the speed of power mode switching, but also provides users with great flexibility and versatility.

[0175] The present application also designs a hardware circuit in which software and hardware can collaboratively control the low-power state of each module in the system. Hardware control effectively reduces the delay of power mode switching, and software control flexibly responds to certain special scenarios that occur during the user's use phase, such as a certain module is not controlled enough in the hardware switching process, resulting in power consumption not meeting expectations, or the user has added certain low-power control requirements. The collaborative control of power mode switching by software and hardware not only improves the speed of power mode switching, but also provides users with great flexibility. This method is applicable to various systems with power switching requirements and has a certain degree of versatility.

[0176] The present application proposes a hardware circuit that supports arbitrarily configurable low-power control timing, which is convenient for users to reasonably configure the power mode switching timing according to task requirements. It reduces the complexity of software design, enhances system flexibility and reliability, and effectively improves the speed of power mode switching. This method is applicable to various systems with power switching requirements and has certain versatility. Furthermore, the present application also proposes a hardware circuit in which software and hardware can collaboratively control the low-power state of each module in the system. Hardware control effectively reduces the delay of power mode switching, and software control flexibly responds to certain special scenarios that occur during the user's use phase, such as a certain module is not controlled in the hardware switching process, resulting in power consumption not meeting expectations, or the user has added certain low-power control requirements. The collaborative control of power mode switching by software and hardware not only improves the speed of power mode switching, but also provides users with great flexibility. This method is applicable to various systems with power switching requirements and has certain versatility.

[0177] According to an embodiment of the present application, a power consumption mode switching method is also provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0178] Fig.11 is a flow chart of a power consumption mode switching method according to an embodiment of the present application, such as Fig.11 As shown, the method includes:

[0179] Step S1102, in response to receiving an entry request for a preset power consumption mode sent by a power consumption controller in a power consumption mode switching system, or receiving an exit request for a preset power consumption mode sent by a power consumption controller, controlling the power consumption mode controller in the power consumption mode switching system to execute a switching sequence according to the entry request or the exit request to generate a control signal.

[0180] The switching timing is the switching timing of the preset power consumption mode configured by the power consumption management core in the power consumption mode switching system.

[0181] The switching timing is the switching timing of the preset power consumption mode configured by the power consumption management core.

[0182] In an optional embodiment, the power mode controller is in a standby state, waiting to receive a power mode switching request from the task core or the low power controller of the power management core. When the task core detects that the system needs to enter a low power state (for example, the device is in standby or idle mode), it will send an entry request to the low power controller of the task core. After the low power controller of the task core controls the task core to enter low power, it sends an entry request to the power mode controller. Similarly, when the low power controller of the power management core detects that the system needs to wake up from a low power state (for example, user interaction or increased system load), it will control the power management core to exit the low power mode and send an exit request to the power mode controller. The "preset power mode" here refers to the low power mode or high performance mode predefined by the system according to the current working state and load conditions, and the "switching timing" refers to the control order and time arrangement of each hardware control device when entering or exiting these preset power modes. This timing is configured by the power management core according to system requirements to ensure that all hardware control devices can switch states in an appropriate order and time.

[0183] Step S1104 , controlling multiple hardware control devices in the power consumption mode switching system to enter a preset power consumption mode or exit a preset power consumption mode according to a control signal.

[0184] Among them, different hardware control devices have different control types.

[0185] In an optional embodiment, the power mode controller executes the configured switching sequence according to the received request and generates corresponding control signals. These control signals will be transmitted to multiple hardware control devices in the system, and each device will perform specific power mode switching operations according to the received control signals, such as turning off or on the power supply, adjusting the clock frequency, entering or exiting a deep sleep state, etc. Since different hardware control devices have different control types, different hardware control devices will respond to and execute different operations on control signals, which ensures that the system can perform refined control for different hardware characteristics during the power mode switching process.

[0186] By directly responding to the control signal through the hardware control device, the scheduling delay of the software layer is avoided, and the rapid execution of the power mode switching is ensured. The timing of the power mode switching can be flexibly configured by the power management core according to the current task requirements, which enables the system to adapt to various usage scenarios and load conditions, and improves the versatility and adaptability of the power mode switching. Through the preset switching timing, it can be ensured that the power mode switching between the hardware control devices is coordinated and consistent, avoiding the failure of the system function caused by the timing error, and enhancing the robustness and stability of the system. Through the fast power mode switching, the wake-up time of the device from the sleep state to the active state, or the waiting time from the active state to the sleep state is reduced, thereby improving the response speed of the device and providing users with a smoother and more timely use experience. Transferring part of the power mode switching control to the hardware layer reduces the burden of software design, so that software development is more focused on the upper application logic, rather than the underlying hardware state management, and simplifies the design and maintenance of the overall system. This application effectively combines the low latency of hardware and the flexibility of software, realizes efficient, flexible and reliable control of power mode switching, and is of great significance to improving the energy efficiency and user experience of modern high-performance computing systems, Internet of Things devices, mobile terminals, etc.

[0187] Through the above steps, in response to receiving an entry request of a preset power consumption mode sent by a power consumption controller in a power consumption mode switching system, or receiving an exit request of a preset power consumption mode sent by a power consumption controller, the power consumption mode controller in the power consumption mode switching system is controlled to execute a switching sequence according to the entry request or the exit request to generate a control signal, wherein the switching sequence is the switching sequence of the preset power consumption mode configured by the power consumption management core in the power consumption mode switching system; multiple hardware control devices in the power consumption mode switching system are controlled to enter the preset power consumption mode or exit the preset power consumption mode according to the control signal, wherein the control types of different hardware control devices are different, thereby achieving an improved switching effect of the power consumption mode. It is easy to notice that when the system load is reduced or enters a specific standby state, the task core detects this change and generates a request to enter the preset power consumption mode accordingly. The generation of this request is immediate and direct, avoiding the delay of software scheduling, so that it can quickly respond to load changes, and the power consumption management core can ensure that before entering the preset power consumption mode, the system can adjust the power consumption control sequence of each module according to specific needs. By configuring the timing reasonably, the failure of hardware functions caused by improper control sequence can be avoided. The power mode controller receives the entry request of the task core or the system wake-up request, such as the system interrupt or the trigger signal entering from the IO, and executes according to the configured switching timing to generate the corresponding control signal. By controlling multiple hardware control devices through the control signal, the delay of power mode switching can be reduced and the switching speed can be improved. Since each hardware control device is responsible for different control types, this division of labor and cooperation mode ensures the comprehensiveness and efficiency of the system when switching power modes, avoids the singleness and complexity of software control, and improves the switching efficiency of the power mode through the instant request generation of the task core, the flexible timing configuration of the power management core, the hardware control signal generation of the power mode controller, and the division of labor and cooperation of multiple hardware control devices, thereby solving the technical problem of poor switching effect of power mode in related technologies.

[0188] In the above-mentioned embodiment of the present application, multiple hardware control devices in the power consumption mode switching system are controlled to enter a preset power consumption mode or exit a preset power consumption mode according to a control signal, including: generating a one-hot code according to an entry request or an exit request, wherein the one-hot code is used to represent the encoding method of the switching timing; generating a control signal according to the one-hot code and a timing judgment condition, wherein the timing judgment condition is used to indicate whether the currently executed timing in the switching timing is the last valid timing.

[0189] In an optional embodiment, the generation of one-hot codes and the use of timing judgment conditions are the key to achieving efficient and flexible control of power mode switching hardware circuits. When the system receives requests to enter or exit low power consumption, these requests will be converted into one-hot codes, which is a coding method that can ensure that only one control object is activated in any timing, avoiding conflicts and unnecessary power consumption that may be caused by multiple control objects switching power modes at the same time. At the same time, through the timing judgment conditions, the circuit can determine whether the currently executed timing is the last valid timing, which enables the system to quickly issue an indication of mode switching completion after completing all necessary operations, thereby avoiding unnecessary waiting time and reducing the overall power mode switching delay.

[0190] Through the above steps, the speed of power mode switching is improved. Due to direct operation at the hardware level, the delay of software configuration and the uncertainty of system scheduling are avoided. Secondly, the flexibility and robustness of the system can be maintained, and users can adapt to different task scenarios by configuring timing registers. Since it supports the configuration of arbitrary timing, this solution has high versatility and can be applied to a variety of systems that require power mode switching, not limited to specific chips or devices, which provides designers with greater choice and innovation possibilities.

[0191] By combining the one-hot code with the timing judgment condition, the present application achieves fast response, flexible configuration and high reliability of power consumption mode switching.

[0192] In the above embodiment of the present application, the method also includes: controlling a software controller in the power consumption mode switching system to generate a count value according to a control signal, and entering or exiting a preset power consumption mode by executing a control program corresponding to the count value.

[0193] In this application, by introducing a software control interface into the power mode switching system, the coordinated control of hardware and software is realized, and the flexibility and versatility of the system are enhanced. Specifically, when the power mode controller controls the software controller, a count value associated with the control signal can be generated, and this count value is further interpreted by the power management core to determine which set of preset low power control programs to execute.

[0194] When the power consumption management of a key module is omitted in the hardware control process, the software control interface can dynamically intervene to ensure that all modules can enter or exit the low power consumption mode as expected, thereby avoiding performance or power consumption issues caused by incomplete power consumption control. Secondly, this combination of software and hardware control mechanism allows users to customize the power consumption mode switching process according to actual needs. Even if new power consumption management requirements arise during the product life cycle, they can be adapted through software updates without changing the hardware design. This not only reduces design costs, but also improves user experience. Through the coordinated control of software and hardware, this application achieves the dual advantages of low latency and high flexibility in power consumption mode switching, and is suitable for a wide range of power consumption control scenarios.

[0195] In the above embodiment of the present application, the software controller in the power consumption mode switching system is controlled to generate a count value corresponding to the control signal, including: controlling the request counting circuit in the software controller to count the control signal according to the trigger information of the control signal to obtain the count value.

[0196] In the present application, by introducing a software control interface, that is, a low-power software controller, in the power mode switching system, effective supplementation and flexible control of the hardware switching process are achieved. Specifically, when the hardware control cannot meet the power mode switching requirements in a specific scenario, such as when the hardware switching process omits the control of a key module or the user proposes a new low-power control requirement during the chip use phase, the low-power software controller can generate a count value corresponding to the control signal, which encodes the information of the specific low-power control program to be executed. Subsequently, the power management core can identify and execute the corresponding control program based on the read count value to accurately enter or exit the preset power mode. This solution combining software and hardware control not only maintains the advantages of fast response and low latency brought by hardware switching, but also gives the system high flexibility and robustness in the face of complex and changeable task scenarios, ensures the chip's high efficiency and reliability in power consumption control, and effectively avoids the problem of functional failure or inaccurate power consumption control caused by fixed hardware processes, thereby realizing the refined management of chip power consumption without affecting the user experience, and improving the performance and user satisfaction of the overall system.

[0197] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0198] It should be noted that, for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the described order of actions, because according to the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0199] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods of each embodiment of the present application.

[0200] According to an embodiment of the present application, a power consumption mode switching device for implementing the above power consumption mode switching method is also provided. Fig.12 is a schematic diagram of a power consumption mode switching device according to an embodiment of the present application, such as Fig.12 As shown, the device includes: a first control module 1202 and a second control module 1204 .

[0201] Among them, the first control module is used to control the power consumption mode controller in the power consumption mode switching system to execute the switching timing according to the entry request or the exit request in response to receiving an entry request of the preset power consumption mode sent by the power consumption controller in the power consumption mode switching system, or receiving an exit request of the preset power consumption mode sent by the power consumption controller, so as to generate a control signal, wherein the switching timing is the switching timing of the preset power consumption mode configured by the power consumption management core in the power consumption mode switching system; the second control module is used to control multiple hardware control devices in the power consumption mode switching system to enter the preset power consumption mode or exit the preset power consumption mode according to the control signal, wherein different hardware control devices have different control types.

[0202] It should be noted that the first control module 1302 and the second control module 1304 correspond to steps S1202 to S1204 in the above embodiment, and the examples and application scenarios implemented by the two modules and the corresponding steps are the same, but are not limited to the contents disclosed in the above embodiment 1. It should be noted that the above modules or units may be hardware components or software components stored in a memory (e.g., memory 104) and processed by one or more processors (e.g., processors 102a, 102b, ..., 102n), and the above modules may also be part of the device and may be run in the computer terminal 10 provided in the first embodiment.

[0203] It should be noted that the preferred implementation scheme involved in the above embodiments of the present application is the same as the scheme provided in Example 1, as well as the application scenario and implementation process, but is not limited to the scheme provided in Example 1.

[0204] In an embodiment of the present application, a computing device may be provided, including: a memory storing an executable program; and a processor for running the program, wherein when the program is running, any one of the methods in the above embodiments is executed. It should be noted that the computing device may be a chip, which is not limited here.

[0205] In this embodiment, the computer terminal can execute the program code in the method.

[0206] A person of ordinary skill in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructing the hardware related to the terminal device through a program, and the program can be stored in a computer-readable storage medium, and the storage medium may include: a flash drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0207] The embodiment of the present application further provides a computer-readable storage medium. Optionally, in this embodiment, the computer-readable storage medium can be used to store the program code executed by the method provided in the above embodiment.

[0208] Optionally, in this embodiment, the above storage medium may be located in any one of the computing devices in the computing device group in the computer network, or in any one of the mobile terminals in the mobile terminal group.

[0209] In an embodiment of the present application, a task core is used to generate an entry request for a preset power consumption mode; a power consumption management core is used to configure the switching timing of the preset power consumption mode; a power consumption controller is connected to the task core and the power consumption management core, and is used to receive an entry request, or generate an exit request of the preset power consumption mode according to the received wake-up request; a power consumption mode controller is connected to the power consumption controller, and is used to execute the switching timing according to the entry request or the exit request to generate a control signal; a plurality of hardware control devices are respectively connected to the power consumption mode controller, and are used to enter the preset power consumption mode or exit the preset power consumption mode according to the control signal, wherein the control types of different hardware control devices are different, so as to achieve the switching effect of improving the power consumption mode. It is easy to notice that when the system load is reduced or enters a specific standby state, the task core detects this change and generates a request to enter the preset power consumption mode accordingly. The generation of this request is immediate and direct, avoiding the delay of software scheduling, so that it can respond quickly to load changes, and the power consumption management core can ensure that before entering the preset power consumption mode, the system can adjust the power consumption control timing of each module according to specific needs. By configuring the timing reasonably, the failure of hardware functions caused by improper control sequence can be avoided. After receiving the entry request or exit request of the power consumption controller, the power consumption mode controller executes according to the configured switching timing and generates the corresponding control signal. By controlling multiple hardware control devices through control signals, the delay of power consumption mode switching can be reduced and the switching speed can be improved. Since each hardware control device is responsible for different control types, this division of labor and cooperation mode ensures the comprehensiveness and efficiency of the system when switching power consumption modes, avoids the singleness and complexity of software control, and improves the switching efficiency of power consumption modes through the instant request generation of the task core, the flexible timing configuration of the power consumption management core, the hardware control signal generation of the power consumption mode controller, and the division of labor and cooperation of multiple hardware control devices, thereby solving the technical problem of poor switching effect of power consumption modes in related technologies.

[0210] The embodiment of the present application further provides a computer program product. Optionally, in this embodiment, the computer program product may include a computer program, and the computer program implements the method provided in the embodiment when executed by a processor.

[0211] The embodiments of the present application also provide a computer program product. Optionally, the computer program product may include a non-volatile computer-readable storage medium, which may be used to store a computer program, and when the computer program is executed by a processor, the method provided in the embodiments is implemented.

[0212] The embodiment of the present application further provides a computer program. Optionally, in this embodiment, when the computer program is executed by a processor, the method provided in the above embodiment is implemented.

[0213] The serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0214] In the above embodiments of the present application, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant description of other embodiments.

[0215] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

[0216] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0217] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above integrated units may be implemented in the form of hardware.

[0218] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, disk or optical disk and other media that can store program codes.

[0219] The above is only a preferred implementation of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A power consumption mode switching system, characterized in that: include: A task core, used for generating an entry request of a preset power consumption mode; A power consumption management core, used for configuring the switching timing of the preset power consumption mode; A power consumption controller, connected to the task core and the power consumption management core, configured to receive the entry request, or generate an exit request of the preset power consumption mode according to the received wake-up request; a power consumption mode controller, connected to the power consumption controller, and configured to execute the switching sequence according to the entry request or the exit request to generate a control signal; A plurality of hardware control devices are respectively connected to the power consumption mode controller and are used to enter the preset power consumption mode or exit the preset power consumption mode according to the control signal, wherein different hardware control devices have different control types.

2. The power consumption mode switching system according to claim 1, characterized in that: The hardware control device comprises: A first control interface, connected to the power consumption mode controller, for receiving a control signal; A hardware controller, connected to the first control interface, is used to enter the preset power consumption mode or exit the preset power consumption mode according to the control signal, and to feedback the control state of the preset power consumption mode to the power consumption mode controller, wherein the control state is used to indicate whether the hardware controller successfully enters the preset power consumption mode or successfully exits the preset power consumption mode.

3. The power consumption mode switching system according to claim 1, characterized in that: The power consumption mode controller comprises: A control circuit, configured to generate a one-hot code according to the entry request or the exit request, wherein the one-hot code is used to represent an encoding method of the switching timing; A state machine is connected to the control circuit and is used to generate the control signal according to the one-hot code and a timing judgment condition, wherein the timing judgment condition is used to indicate whether the currently executed timing in the switching timing is the last valid timing.

4. The power consumption mode switching system according to claim 1, characterized in that: The power consumption mode switching system further includes: A timing configuration register, connected to the power management core via a bus, and configured to store the switching timing after receiving the switching timing configured by the power management core; The power consumption mode register is connected to the power consumption management core through a bus, and is used to store the preset power consumption mode after receiving the preset power consumption mode configured by the power consumption management core.

5. The power consumption mode switching system according to claim 2, characterized in that: The power consumption mode switching system further includes: A second control interface, connected to the power consumption management core, for receiving a control signal; a software controller connected to the second control interface and the first control interface, and configured to generate a count value according to the control signal, wherein the count value is used to represent a numerical value obtained by counting the control signal; The power consumption management core is used to call the control program corresponding to the count value, and enter the preset power consumption mode or exit the preset power consumption mode by executing the control program.

6. The power consumption mode switching system according to claim 5, characterized in that: The software controller comprises: The request counting circuit is used to count the control signal according to the trigger information of the control signal to obtain the count value.

7. A method for switching power consumption modes, characterized in that: include: In response to receiving an entry request of a preset power consumption mode sent by a power consumption controller in a power consumption mode switching system, or receiving an exit request of the preset power consumption mode sent by the power consumption controller, controlling the power consumption mode controller in the power consumption mode switching system to execute a switching timing according to the entry request or the exit request to generate a control signal, wherein the switching timing is a switching timing of the preset power consumption mode configured by a power consumption management core in the power consumption mode switching system; Control multiple hardware control devices in the power consumption mode switching system to enter the preset power consumption mode or exit the preset power consumption mode according to the control signal, wherein different hardware control devices have different control types.

8. The power consumption mode switching method according to claim 7, characterized in that: Controlling a plurality of hardware control devices in the power consumption mode switching system to enter the preset power consumption mode or exit the preset power consumption mode according to the control signal comprises: Generate a one-hot code according to the entry request or the exit request, wherein the one-hot code is used to represent an encoding method of the switching timing; The control signal is generated according to the one-hot code and a timing judgment condition, wherein the timing judgment condition is used to indicate whether the timing currently executed in the switching timing is the last valid timing.

9. The power consumption mode switching method according to claim 7, characterized in that: The method further comprises: Controlling a software controller in the power consumption mode switching system to generate a count value according to the control signal; The preset power consumption mode is entered or exited by executing a control program corresponding to the count value.

10. The power consumption mode switching method according to claim 9, characterized in that: Controlling a software controller in the power consumption mode switching system to generate a count value corresponding to the control signal includes: The request counting circuit in the software controller is controlled to count the control signal according to the trigger information of the control signal to obtain the count value.

11. A system on chip, characterized in that: include: A system as claimed in any one of claims 1 to 6.

12. A computing device, characterized in that: include: A memory storing an executable program; A processor, configured to run the program, wherein the program executes the method according to any one of claims 7 to 10 when running.

13. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes a stored executable program, wherein when the executable program is executed, the device where the storage medium is located is controlled to execute the method according to any one of claims 7 to 10.

14. A computer program product, characterized in that It comprises a computer program which, when executed by a processor, implements the method according to any one of claims 7 to 10.

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