Binary translation method, binary translator, electronic device and readable storage medium

Abstract

The embodiment of the present invention provides a binary translation method, a binary translator, an electronic device and a readable storage medium, the method comprising: if the current instruction is identified as an indirect jump instruction, calling a preset instruction; the instruction code of the preset instruction includes a first operand and a second operand; the first operand points to a first register, and the second operand points to a second register; the first register stores a target PC value; the second register is used to store the calculation result of the preset instruction; the preset instruction executes a preset calculation logic to calculate the target index value corresponding to the target PC value in a hash table, and writes the target index value into the second register; reads the target index value from the second register, and queries whether the target PC value hits the hash table through the target index value, and executes the next instruction based on the query result. The embodiment of the present invention can reduce the number of instruction translations of high-frequency instructions and improve the execution efficiency of the binary translator.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a binary translation method, a binary translator, an electronic device and a readable storage medium. Background Art

[0002] Binary translation can convert the binary code of one ISA (Instruction Set Architecture) into the binary code of another instruction set architecture. Through binary translation technology, an application of one ISA (source architecture) can run on another ISA (target architecture).

[0003] As the performance of microprocessors continues to improve, the feasibility of running source programs of one CPU architecture under another CPU architecture through binary translation is becoming increasingly strong, which has led to more development of binary translation technology. However, this technology still has technical problems such as low translation efficiency and excessive redundant operations. Summary of the invention

[0004] In view of the above problems, an embodiment of the present invention is proposed to provide a binary translation method that overcomes the above problems or at least partially solves the above problems, which can reduce the number of instruction translations of high-frequency instructions, reduce the number of context switches, and improve the execution efficiency of the binary translator, thereby improving the speed at which the binary translator executes the program.

[0005] Correspondingly, the embodiment of the present invention also provides a binary translator, an electronic device, and a computer program product to ensure the implementation and application of the above method.

[0006] In a first aspect, an embodiment of the present invention discloses a binary translation method, which is applied to a binary translator. The method includes:

[0007] If the current instruction is identified as an indirect jump instruction, a preset instruction is called; the instruction code of the preset instruction includes a first operand and a second operand; the first operand points to a first register, and the second operand points to a second register; the first register stores a target PC value, which is used to point to the address of the next instruction; the second register is used to store a calculation result of the preset instruction;

[0008] The preset instruction executes preset calculation logic to calculate the target index value corresponding to the target PC value in the hash table, and writes the target index value into the second register; the hash table is used to record the address of the translated instruction in the code cache;

[0009] The target index value is read from the second register, and the target PC value is queried through the target index value to see whether it hits the hash table, and the next instruction is executed based on the query result.

[0010] In a second aspect, an embodiment of the present invention discloses a binary translator, the binary translator comprising:

[0011] The instruction calling module is used to call a preset instruction if the current instruction is identified as an indirect jump instruction; the instruction code of the preset instruction includes a first operand and a second operand; the first operand points to a first register, and the second operand points to a second register; the first register stores a target PC value, which is used to point to the address of the next instruction; the second register is used to store the calculation result of the preset instruction;

[0012] An instruction execution module, configured to execute a preset calculation logic for the preset instruction to calculate a target index value corresponding to the target PC value in a hash table, and write the target index value into the second register; the hash table is configured to record the address of the translated instruction in the code cache;

[0013] A target jump module is used to read the target index value from the second register, and query whether the target PC value hits the hash table through the target index value, and execute the next instruction based on the query result.

[0014] In the third aspect, an embodiment of the present invention discloses an electronic device, comprising: a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the steps of the binary translation method as described in any of the above.

[0015] In a fourth aspect, an embodiment of the present invention discloses a readable storage medium, on which a program or instruction is stored, and when the program or instruction is executed by a processor, the binary translation method as described in any of the above can be implemented.

[0016] In a fifth aspect, an embodiment of the present invention discloses a computer program product, including a computer program, which, when executed by a processor, performs the steps of any of the aforementioned binary translation methods.

[0017] The embodiments of the present invention include the following advantages:

[0018] The embodiment of the present invention provides a binary translation method, which is applied to a binary translator. When the binary translator completes the translation of the current TB, executes the current TB, and when the last instruction of the current TB is executed and the instruction is identified as an indirect jump instruction, the preset instruction of the present invention is called. The preset instruction is a hardware instruction newly added by the present invention, and the instruction code of the preset instruction includes a first operand and a second operand; the first operand points to a first register, and the second operand points to a second register; the first register stores a target PC value, which is used to point to the address of the next instruction; the second register is used to store the calculation result of the preset instruction. The preset instruction is used to execute the preset calculation logic to calculate the target index value corresponding to the target PC value in the hash table, and write the target index value into the second register. After the preset instruction is executed, the binary translator can read the target index value from the second register, and query whether the target PC value hits the hash table through the target index value, and execute the next instruction based on the query result. The embodiment of the present invention implements the operation step of "calculating the target index value corresponding to the target PC value in the hash table" by calling a preset instruction (a newly added hardware instruction), and implements the operation that requires the execution of three instructions through one instruction, thereby reducing the number of instructions required for translating and executing indirect jump instructions. Therefore, the execution efficiency of the binary translator can be improved by reducing the number of instruction translations of high-frequency instructions, reducing the number of context switches, and thereby improving the speed at which the binary translator executes the program. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a schematic diagram of a binary translation architecture of the present invention;

[0020] Figure 2 is a flowchart of a binary translation method embodiment of the present invention;

[0021] Figure 3 is a schematic diagram of the structure of the hardware instructions newly added in the embodiment of the present invention;

[0022] Figure 4 is a schematic diagram of a preset instruction executing a preset calculation logic in an example of an embodiment of the present invention;

[0023] Figure 5 is a schematic diagram of a preset instruction executing a preset calculation logic in another example of an embodiment of the present invention;

[0024] Figure 6 It is a flowchart of a binary translation method according to an embodiment of the present invention;

[0025] Figure 7 is a structural block diagram of a binary translator embodiment of the present invention;

[0026] Figure 8 It is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0027] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0028] The terms "first", "second", etc. in the specification and claims of the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable when appropriate, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In the embodiments of the present invention, the term "multiple" refers to two or more, and other quantifiers are similar.

[0029] Binary translation technology can solve the problem of binary-level applications running across instruction set architectures. Specifically, binary translation technology can convert instruction sequences in one instruction set architecture into instruction sequences in another instruction set architecture.

[0030] Reference Figure 1 , shows a schematic diagram of a binary translation architecture, which includes a disassembler, an optimizer, a translator, and an assembler. First, the source program is input into the disassembler for disassembly and cutting into basic blocks, and the information of each instruction in each basic block is obtained; the optimizer analyzes the information obtained after disassembly, finds out the possible instruction sequences to be optimized, and marks them; the translator translates each instruction according to the information obtained after disassembly, and performs some optimizations during the translation process with the assistance of the marking information provided by the optimizer; the optimized translated instructions are finally sent to the assembler for assembly. A basic block (Translation Block, TB) usually ends with a control flow changing instruction (such as an indirect jump instruction, a function call instruction, etc.).

[0031] In an embodiment of the present invention, the source platform is also referred to as a client platform, and the target platform is also referred to as a host platform or a local platform. The processor of the source platform may be a processor based on a first instruction set architecture. The processor of the target platform may be a processor based on a second instruction set architecture. The second instruction set architecture is a different instruction set architecture from the first instruction set architecture.

[0032] Binary translation includes static binary translation and dynamic binary translation. Static binary translation is to translate binary program A (source program) on the source platform before it is executed, so as to translate binary program A into binary program B (target program) on the target platform. Dynamic binary translation is to translate the executed code fragments when the binary program is running. The binary translation method of the embodiment of the present invention can be applied to the scenario of dynamic binary translation, and the binary translator of the embodiment of the present invention refers to a dynamic binary translator.

[0033] Dynamic binary translation refers to the translation of the executed fragments when translating and executing the client platform program on the host platform (HOST platform), translating the guest instructions (GUEST instructions) into TB of host instructions (HOST instructions) in units of TB, saving them in the code cache, and then executing the translated TB. The process of a typical dynamic binary translation is as follows: the binary translator takes the program counter (PC) of the client platform as input, and first searches the code cache to see if there is a translated TB corresponding to the current value of the program counter. If so, jump to the translated TB for direct execution; if not, translate it. That is, the translation process includes: constructing TB, translating TB, and inserting the translated TB into the code cache.

[0034] The Program Counter (PC) is a register in a computer processor that stores the address of the next instruction.

[0035] The translated TB is stored in the code cache so that it can be efficiently recalled when the translated TB is repeatedly executed. After the TB is ready, the binary translator will switch from the translation state to the execution state and hand it over to the host operating system to execute the translated HOST instructions. The translation and execution of the binary translator are based on TB. Whenever a TB is executed and the next TB needs to be searched or translated, it needs to switch to the translation state. The transition between these two states requires a context switch. During this process, the state of the registers needs to be saved, which involves more memory access operations, which will result in additional performance overhead and affect the efficiency of the translator.

[0036] Reference Figure 2, shows a flowchart of a binary translation method embodiment of the present invention, the method is applied to a binary translator, and the method may include the following steps:

[0037] Step 101: If the current instruction is identified as an indirect jump instruction, a preset instruction is called; the instruction code of the preset instruction includes a first operand and a second operand; the first operand points to a first register, and the second operand points to a second register; the first register stores a target PC value, which is used to point to the address of the next instruction; the second register is used to store the calculation result of the preset instruction;

[0038] Step 102, the preset instruction executes preset calculation logic to calculate the target index value corresponding to the target PC value in the hash table, and writes the target index value into the second register; the hash table is used to record the address of the translated instruction in the code cache;

[0039] Step 103: read the target index value from the second register, and query whether the target PC value hits the hash table through the target index value, and execute the next instruction based on the query result.

[0040] The binary translation method provided by the embodiment of the present invention can be applied to a dynamic binary translator to optimize the translation and execution efficiency of indirect jump instructions during the binary translation process.

[0041] In the embodiment of the present invention, the binary translator takes the program counter of the client platform as input, and first searches the code cache for whether there is a translated TB corresponding to the current value of the program counter. If there is, jump to the translated TB and execute directly; if not, enter the translation state for translation. After the current basic unit translation is completed, the translated TB is stored in the code cache, and enter the execution state to execute the translated TB. When the last instruction of the TB is executed and the current instruction is identified as an indirect jump instruction, check whether the next instruction has been translated according to the target PC value of the next instruction. If it has been translated, the address of the next instruction (HOST instruction) after translation in the code cache (i.e., the jump target address of the indirect jump instruction) can be obtained, jump directly to the jump target address, and execute the next instruction (i.e., execute the next TB). If it has not been translated yet, switch to the translation state for translation.

[0042] In order to quickly find out whether a GUEST instruction (such as the next instruction) has been translated, a hash table is maintained in the dynamic binary translator to record the address of the translated instruction in the code cache. Since different PC values ​​may calculate the same index value (hash conflict), in order to avoid hash conflicts, each item in the hash table can further include the following two parts: the PC value of the GUEST instruction and the address of the translated instruction corresponding to the PC value in the code cache. The index value of each item in the hash table is obtained by hashing the PC value using a specified hash algorithm.

[0043] Referring to Table 1, an example of a hash table is shown.

[0044] Table 1

[0045]

[0046] As shown in Table 1, the hash table may include several table entries, each of which is used to record the TB first address of the translated instruction in the code cache. Each table entry includes an index value, which is calculated based on the PC value of the GUEST instruction. The TB first address of the GUEST instruction in the code cache after translation can be queried through the index value. Furthermore, in order to avoid hash conflicts, each item in the hash table records the PC value of the GUEST instruction in addition to the TB first address of the GUEST instruction in the code cache after translation. By performing a hash calculation on the target PC value through a specified hash algorithm (such as by calling the tb_jmp_cache_hash_func hash function), the target index value corresponding to the target PC value can be obtained. The hash table can be queried through the target index value to determine whether the target PC value hits the hash table, so that it can be known whether the GUEST instruction corresponding to the target PC value has been translated.

[0047] Further, querying whether the target PC value hits the hash table through the target index value may include:

[0048] The hash table is queried by the target index value. If there is a target item corresponding to the target index value, and the PC value recorded in the target item is consistent with the target PC value, then the target PC value hits the hash table, indicating that the GUEST instruction corresponding to the target PC value has been translated; or

[0049] The hash table is queried by the target index value. If there is a target item corresponding to the target index value, and the PC value recorded in the target item is inconsistent with the target PC value, then the target PC value does not hit the hash table, indicating that the GUEST instruction corresponding to the target PC value has not been translated; or

[0050] The hash table is queried through the target index value. If the target item corresponding to the target index value does not exist, the target PC value does not hit the hash table, indicating that the GUEST instruction corresponding to the target PC value has not been translated.

[0051] In a specific implementation, the target index value corresponding to the target PC value in the hash table is calculated, usually by performing an XOR calculation on the high-order address and the low-order address of the target PC value. The high-order address refers to the high-order byte of the target PC value, and the low-order address refers to the low-order byte of the target PC value. For example, for a 32-bit target PC value, the high-order address refers to bits 16 to 31 of the target PC value, and the low-order address refers to bits 0 to 15 of the target PC value. For a 64-bit target PC value, the high-order address refers to bits 32 to 63 of the target PC value, and the low-order address refers to bits 0 to 31 of the target PC value.

[0052] However, XOR calculation usually requires the following three instructions: first, use an instruction to shift the high-order address of the target PC to the right, so as to save the high-order address to the low-order of a temporary register; then use an instruction to XOR the temporary register with the register storing the target PC value; finally, use another instruction to shift the XOR result to the left and save it to the specified register. In this way, the target index value corresponding to the target PC value in the hash table can be obtained from the specified register.

[0053] Since indirect jump instructions are high-frequency instructions, if each time an indirect jump instruction is executed, the above three instructions need to be executed to calculate the target index value corresponding to the target PC value of the next instruction, which will affect the translation and execution efficiency of the indirect jump instruction.

[0054] To solve this problem, the embodiment of the present invention optimizes the step of "calculating the target index value corresponding to the target PC value in the hash table" and implements it using a new hardware instruction (referred to as a preset instruction in the embodiment of the present invention). The preset instruction is a custom hardware instruction supported by the CPU. Figure 3 , shows a schematic diagram of the structure of the hardware instructions (preset instructions) newly added in the embodiment of the present invention. Figure 3 As shown, the instruction code of the preset instruction includes an operation code (Opcode), a first operand and a second operand. The operation code is used to indicate that the instruction is a preset instruction, the first operand points to a first register, and the second operand points to a second register; the first register stores a target PC value, which is used to point to the address of the next instruction; the second register is used to store the calculation result of the preset instruction.

[0055] In an optional embodiment of the present invention, the length of the instruction code of the preset instruction is consistent with the instruction code length of the instruction in the instruction set architecture of the host platform, the first register and the second register are general fixed-point registers of the host platform, the number of bits occupied by the first operand and the second operand in the instruction code is determined according to the number of general fixed-point registers of the host platform, and the lowest bit of the instruction code is the third operand.

[0056] In one example, the instruction in the instruction set architecture of the host platform is a 64-bit instruction, and the instruction code is specified to be 32 bits. To be applicable to the host platform, the newly added preset instruction of the present invention can be a 64-bit instruction, and the instruction code of the preset instruction is 32 bits. The preset instruction implements the operation of calculating the target index value by operating the first register and the second register. The first register and the second register can be general fixed-point registers of the host platform. The number of bits occupied by the first operand and the second operand in the instruction code is determined according to the number of general fixed-point registers of the host platform. For example, if the host platform has a total of 32 general fixed-point registers, then in binary, 5 bits can be used to represent these 32 general fixed-point registers, so the first operand and the second operand can each occupy 5 bits in the instruction code. The third operand is an immediate number used to represent the calculation method, which only occupies 1 bit. The remaining number of bits in the instruction code can be used to represent the operation code.

[0057] Typically, the instruction code uses the low bits to represent the operand and the high bits to represent the opcode. In one example, the instruction code of the preset instruction is 32 bits, and the 32-bit instruction code includes a 21-bit opcode, a 5-bit first operand, a 5-bit second operand, and a 1-bit third operand. Specifically, the [0] bit (bit 0) of the instruction code represents the third operand (immediate number). The [1:5] bits (bits 1 to 5) of the instruction code represent the second operand (the address of the second register). The [6:10] bits (bits 6 to 10) of the instruction code represent the first operand (the address of the first register). The [11:31] bits (bits 11 to 31) of the instruction code represent the opcode (Opcode).

[0058] When the preset instruction executes the preset calculation logic, the address of the first register can be obtained based on the first operand, so that the first register can be operated, such as performing an XOR calculation on the target PC value stored in the first register. The address of the second register can be obtained based on the second operand, so that the second register can be operated, such as writing the calculation result into the second register and performing a shift operation.

[0059] The embodiment of the present invention calls the preset instruction when executing the last instruction of the current TB and identifying that the current instruction is an indirect jump instruction; the preset calculation logic is executed through the preset instruction, and the preset calculation logic is used to calculate the target index value corresponding to the target PC value in the hash table, and write the target index value into the second register; thus, after the preset instruction is executed, the target index value can be read from the second register, and the hash table can be queried based on the target index value to determine whether the target PC value hits the hash table. If the target PC value hits the hash table, the address of the translated instruction corresponding to the target PC value in the code cache can be obtained from the target table entry corresponding to the target index value, and then the next instruction can be directly jumped to the address to execute the next instruction, which is the first instruction of the next basic block.

[0060] The embodiment of the present invention implements the operation step of "calculating the target index value corresponding to the target PC value in the hash table" by calling a preset instruction (a newly added hardware instruction). The operation that needs to execute three instructions is implemented by one instruction, which reduces the number of instructions required to translate and execute indirect jump instructions. Therefore, the execution efficiency of the binary translator can be improved by reducing the number of instructions translated for high-frequency instructions, reducing the number of context switches, and thus improving the speed at which the binary translator executes the program.

[0061] Furthermore, if Figure 3 As shown, the instruction code of the preset instruction may further include a third operand, and the third operand may be an immediate number used to identify the calculation method adopted by the preset calculation logic; the calculation method is determined according to the type of the binary translator.

[0062] In a specific implementation, different types of binary translators may be used to perform dynamic binary translation. For example, a binary translator based on QEMU or other types of binary translators may be used. QEMU supports simulation and virtualization of operating systems and programs of multiple architectures.

[0063] Since different types of binary translators may use different sizes of hash tables, there may be differences in the methods of calculating the target index value corresponding to the target PC value in the hash table, and in the methods of performing XOR and shift operations on the target PC value. The different sizes of hash tables include the total length of the hash table (the number of entries contained in the hash table) and the length of each entry in the hash table. For example, the size of the hash table in QEMU is different from that in other types of binary translators.

[0064] To make the preset instruction of the present invention applicable to a variety of different types of binary translators. The instruction code of the preset instruction may also include a third operand, which may be an immediate number for identifying the calculation method adopted by the preset calculation logic; the calculation method is determined according to the type of binary translator. In a specific implementation, different immediate numbers corresponding to the third operand may be set for different types of binary translators, and different immediate numbers correspond to different calculation methods, that is, the preset instruction may calculate the target index value corresponding to the target PC value in the hash table according to the calculation logic indicated by the immediate number, and the calculation method of the calculation logic is determined according to the type of binary translator.

[0065] Exemplarily, if the value of the immediate number is the first value, the target index value corresponding to the target PC value in the hash table is calculated using calculation method 1; calculation method 1 corresponds to the first type of binary translator. If the value of the immediate number is the second value, the target index value corresponding to the target PC value in the hash table is calculated using calculation method 2; calculation method 2 corresponds to the second type of binary translator. And so on.

[0066] In one example, the first numerical value is 1, indicating that the binary translator type is the first type. The second numerical value is 0, indicating that the binary translator type is the second type. That is, if a binary translator based on the first type is used, when the binary translator calls the preset instruction, an immediate value of 1 can be passed into the third operand. When the preset instruction executes the preset calculation logic, the calculation method 1 will be used to calculate the target index value corresponding to the target PC value in the hash table. If a binary translator based on the second type is used, when the binary translator calls the preset instruction, an immediate value of 0 can be passed into the third operand. When the preset instruction executes the preset calculation logic, the calculation method 2 will be used to calculate the target index value corresponding to the target PC value in the hash table.

[0067] It is understandable that the embodiments of the present invention are not limited to the above two types of binary translators. In specific implementations, different calculation methods corresponding to different types of binary translators can be set as needed. Furthermore, for the same type of binary translator, the hash table used may also be different due to different translator versions. Therefore, the calculation method corresponding to different versions of the binary translator for the immediate value in the third operand can also be set.

[0068] In an optional embodiment of the present invention, the executing the preset calculation logic may include:

[0069] Step S11, performing an XOR calculation on the first designated bit and the second designated bit of the target PC value stored in the first register, and writing the XOR calculation result into the third designated bit in the second register;

[0070] Step S12, clearing the fourth designated bit in the second register;

[0071] Step S13, shift the second register left by a preset bit, and fill the lower preset bit with zero.

[0072] In an embodiment of the present invention, the preset instruction can execute steps S11 to S13 to calculate the target index value corresponding to the target PC value in the hash table.

[0073] After the current TB is translated, the current TB is executed. When the last instruction of the current TB is executed and the instruction is identified as an indirect jump instruction, the preset instruction of the present invention is called and the corresponding parameters are passed in. Specifically, the parameters passed in may include the address of the first register, the address of the second register, and the immediate value. The first register stores the target PC value, which is used to point to the address of the next instruction. The second register is a register allocated by the binary translator for the preset instruction and is used to store the calculation result of the preset instruction. The value of the immediate number is used to indicate the calculation logic corresponding to different types of binary translators.

[0074] The preset instruction executes corresponding calculation logic according to the immediate value in the third operand, performs XOR and shift operations on the target PC value in the first register, and writes the target index value finally calculated into the second register.

[0075] Since different types of binary translators may use hash tables of different sizes, resulting in different lengths of index values, there are differences in XOR and shift operations when calculating the target index value corresponding to the target PC value in the hash table. Therefore, the preset bit, the first designated bit, the second designated bit, the third designated bit, and the fourth designated bit are determined according to the length of the hash table entries or the length of the hash table used by different types of binary translators. That is, the calculation method of the preset calculation logic executed by the preset instruction is further determined according to the total length of the hash table and the length of the hash table entries. Different calculation methods refer to that the preset bit, the first designated bit, the second designated bit, the third designated bit, and the fourth designated bit in steps S11~S13 may be different.

[0076] In an optional embodiment of the present invention, before calling the preset instruction, the method may further include:

[0077] According to the type of the binary translator, the total length of the hash table and the length of the hash table entries are determined; according to the length of the hash table entries, the first designated bit, the second designated bit, the third designated bit and the fourth designated bit are determined; and according to the total length of the hash table, the preset bit is determined.

[0078] Exemplarily, the total length of the hash table used by the first type of binary translator is 2 16 Item, the length of the hash table item is 16 bytes, then when the first type of binary translator is used, the specific calculation method of the preset instruction can be determined according to the type of binary translator, such as calculation method 1. In calculation method 1, the first designated bit, the second designated bit, the third designated bit and the fourth designated bit can be determined according to the length of the hash table item (16 bytes); and the total length of the hash table (2 16 ) determines the preset position.

[0079] Exemplarily, the total length of the hash table used by the second type of binary translator is 2 12 Item, the length of the hash table item is 16 bytes, then when the second type of binary translator is used, the specific calculation method of the preset instruction can be determined according to the type of binary translator, such as calculation method 2. In calculation method 2, the first designated bit, the second designated bit, the third designated bit and the fourth designated bit can be determined according to the length of the hash table item (16 bytes); and the total length of the hash table (2 12 ) determines the preset position.

[0080] Specifically, the preset position is determined according to the length of each table entry in the hash table. Step S13 shifts the second register left by the preset position and fills the lower preset position with zero, in order to calculate the offset of the target index value in the memory relative to the base address of the hash table according to the table entry length of the hash table. The base address of the hash table refers to the starting address of the hash table, which is maintained by the translator and stored in the designated register. The information stored in the corresponding table entry in the HASH table can be read through "base address of the hash table + offset".

[0081] For example, if the length of each entry in the hash table is 16 bytes, the second register is shifted left by a preset position (4 bits), and the lower preset position (lower 4 bits) is padded with zeros, that is, the value in the second register is multiplied by 16. Exemplarily, as shown in Table 1, assuming that the target index value is 3, corresponding to the 4th entry in the hash table, the memory address of the 4th entry is the base address of the hash table plus the offset of the 4th entry. Since each entry is 16 bytes long, the offset of the 4th entry can be obtained by multiplying the target index value 3 by 16.

[0082] It is understandable that the preset position may be different according to the different lengths of the hash table entries used by different types of translators. Optionally, determining the preset position according to the length of the hash table entry may include: if the length of the hash table entry is 2 i , then the preset bit is determined to be i, where i is a positive integer. The unit of i is bit, and the unit of the entry length is byte.

[0083] Assume that the preset position is represented by i, and the length of the hash table entry = 2 i For example, if the length of each entry in the hash table is 8 bytes, the preset bit is 3; if the length of each entry in the hash table is 32 bytes, the preset bit is 5.

[0084] Furthermore, the first designated bit, the second designated bit, the third designated bit, and the fourth designated bit are determined according to the total length of the hash table. The total length of the hash table refers to the number of entries that the hash table can include. For example, the total length of the hash table is 12, which means that the hash table can include 2 12 =4096 entries. For another example, the total length of the hash table is 16, which means that the hash table can include 2 16 =65536 table entries.

[0085] In an optional embodiment of the present invention, determining the first designated bit, the second designated bit, the third designated bit, and the fourth designated bit according to the total length of the hash table may include:

[0086] If the total length of the hash table is 2 j , j is a positive integer, then the first designated bit is determined to be the jth to (2j-1)th bit of the first register, the second designated bit is determined to be the 0th to (j-1)th bit of the first register, the third designated bit is determined to be the 0th to (j-1)th bit of the second register, and the fourth designated bit is determined to be the jth to the highest bit of the second register.

[0087] The first designated bit and the second designated bit need to perform an XOR calculation, so the lengths of the first designated bit and the second designated bit are consistent.

[0088] In one example, when the type of the binary translator is the first type, the length of the hash table is 2 16 , that is, j=16, the first designated bit is the 16th to 31st bit, the second designated bit is the 0th to 15th bit, the third designated bit is the 0th to 15th bit, and the fourth designated bit is the 16th to 63rd bit.

[0089] Reference Figure 4 , shows a schematic diagram of a preset instruction executing a preset calculation logic in an example of an embodiment of the present invention. Figure 4As shown, when the immediate value (bit [0] of the instruction code) is 1, it indicates that the binary translator used is of the first type. The preset calculation logic executed by the preset instruction adopts calculation method 1, which can be specifically as follows: the [31:16] bits and [15:0] bits of the target PC value stored in the first register are XORed bit by bit, and the result of the XOR calculation is written to the [15:0] bits of the second register, and the [63:16] bits of the second register are cleared, and then the second register is shifted left by 4 bits, and the right 4 bits (bits [3:0]) are filled with zeros. As a result, bits [19:0] of the second register are the calculated target index value, and the remaining bits are 0. Among them, the purpose of filling [3:0] with 0 is to play the role of multiplication by 16.

[0090] Further, the reading the target index value from the second register may include:

[0091] The 0th bit to the (j+preset bit-1)th bit of the second register are read to obtain a target index value.

[0092] Exemplarily, when the type of the binary translator is the first type, the length of the hash table is 2 16 , that is, j=16, the reading of the target index value from the second register may include: reading the 0th bit to the 19th bit (16+4-1=19) of the second register to obtain the target index value.

[0093] When the type of the binary translator is the first type, after the binary translator calls the preset instruction and executes it, the binary translator can read bits 0 to 19 of the second register to obtain the target index value (the offset of the table entry corresponding to the target index value relative to the starting address of the hash table in the memory).

[0094] It is understandable that the subsequent calculation of the binary translator can read the complete value in the second register, that is, read the [63:0] bits of the second register, except that the [63:20] bits are all 0, which does not affect the result. The bits that actually work are the [19:0] bits.

[0095] In another example, when the type of the binary translator is the second type, the length of the hash table is 2 12 , that is, j=12, the first designated bit is the 12th to 23rd bit, the second designated bit is the 0th to 11th bit, the third designated bit is the 0th to 11th bit, and the fourth designated bit is the 12th to 63rd bit.

[0096] It can be understood that the above-mentioned settings of the first designated bit, the second designated bit, the third designated bit and the fourth designated bit are only for exemplary purposes, and the corresponding first designated bit, the second designated bit, the third designated bit and the fourth designated bit can be set according to the total length of the hash table.

[0097] Reference Figure 5 , shows a schematic diagram of a preset instruction executing a preset calculation logic in another example of an embodiment of the present invention. Figure 5 As shown, when the immediate value (the [0] bit of the instruction code) is 0, it indicates that the binary translator used is the second type. The preset calculation logic executed by the preset instruction adopts calculation method 2, which can be specifically as follows: the [23:12] bits and [11:0] bits of the target PC value stored in the first register are XORed bit by bit, and the result of the XOR calculation is written to the [11:0] bits of the second register, and the [63:12] bits of the second register are cleared, and then the second register is shifted left by 4 bits, and the right 4 bits ([3:0] bits) are filled with zero. Therefore, the [15:0] bits of the second register are the calculated target index value, and the remaining bits are 0.

[0098] Furthermore, when the type of the binary translator is the second type, the length of the hash table is 2 12 , that is, j=12, the reading of the target index value from the second register may include: reading the 0th bit to the 15th bit (12+4-1=15) of the second register to obtain the target index value.

[0099] When the type of the binary translator is the second type, after the binary translator calls the preset instruction and executes it, the binary translator can read bits 0 to 15 of the second register to obtain the target index value (the offset of the table entry corresponding to the target index value relative to the starting address of the hash table in the memory).

[0100] It is understandable that the subsequent calculation of the binary translator can read the complete value in the second register, that is, read the [63:0] bits of the second register, except that the [63:16] bits are all 0, which does not affect the result. The bits that actually work are the [15:0] bits.

[0101] The preset instruction of the embodiment of the present invention can execute different calculation logics on the target PC value for different types of binary translators to calculate the corresponding target index value. For different types of binary translators, one preset instruction of the embodiment of the present invention can be used to implement an operation that originally requires three instructions to complete, which can improve the scope of application of the preset instruction of the embodiment of the present invention, and further improve the translation efficiency of different types of binary translators.

[0102] In an optional embodiment of the present invention, executing the next instruction based on the query result includes:

[0103] In the execution state, if the target PC value is found to hit the hash table, the target address corresponding to the target PC value is read from the hash table, and the program jumps to the target address to execute the next instruction.

[0104] Reference Figure 6 , shows a schematic diagram of a binary translation method flow in an embodiment of the present invention. Figure 6 As shown, in an embodiment of the present invention, when the binary translator is in the translation state, if it is recognized that the current instruction is an indirect jump instruction, a call instruction for calling the preset instruction is added. Therefore, when the binary translator is in the execution state, when it executes to the end of the current TB (the last instruction is an indirect jump instruction), the preset instruction will be executed. The preset instruction can accelerate the process of finding whether the target PC value hits the hash table by executing the preset calculation logic. If it hits, it means that the next TB has been translated, and the target address corresponding to the target PC value (that is, the first address of the next translated TB in the code cache) can be read from the hash table, and the execution state directly jumps to the next TB for execution. If it does not hit, it means that the next TB has not been translated yet, and it will jump to a section of code that executes context switching to perform context switching, thereby returning to the translation state for translation.

[0105] Among them, the target PC value hits the hash table, which means that the target index value exists in the hash table, and the PC value of the GUEST instruction stored in the table entry queried by the target index value is consistent with the target PC value, so that the TB first address in the code cache stored in the table entry can be read as the target address of the jump. A miss includes that the target index value does not exist in the hash table, or that the target index value exists in the hash table, but the PC value of the GUEST instruction stored in the table entry queried by the target index value is inconsistent with the target PC value.

[0106] Specifically, if the target PC value hits the hash table, and because the hash table records the addresses of the translated instructions in the code cache, the target address corresponding to the target PC value read from the hash table is the TB first address of the HOST instruction in the code cache after the GUEST instruction corresponding to the target PC value is translated, that is, the starting address of the next TB in the code cache. When the next TB has been translated and exists in the code cache, the control flow can jump directly to the starting address of the TB. These processes are all executed directly in the execution state by writing the machine code of the HOST platform, so that the two TBs can complete the jump faster without context switching, reducing the number of context switches, increasing the execution efficiency of the binary translator, and thus improving the speed at which the binary translator runs the program.

[0107] In summary, an embodiment of the present invention provides a binary translation method, which is applied to a binary translator. When the binary translator completes the translation of the current TB, executes the current TB, and when the last instruction of the current TB is executed and the instruction is identified as an indirect jump instruction, the preset instruction of the present invention is called. The preset instruction is a hardware instruction newly added by the present invention, and the instruction code of the preset instruction includes a first operand and a second operand; the first operand points to a first register, and the second operand points to a second register; the first register stores a target PC value, which is used to point to the address of the next instruction; the second register is used to store the calculation result of the preset instruction. The preset instruction is used to execute the preset calculation logic to calculate the target index value corresponding to the target PC value in the hash table, and write the target index value into the second register. After the preset instruction is executed, the binary translator can read the target index value from the second register, and query whether the target PC value hits the hash table through the target index value, and execute the next instruction based on the query result. The embodiment of the present invention implements the operation step of "calculating the target index value corresponding to the target PC value in the hash table" by calling a preset instruction (a newly added hardware instruction), and implements the operation that requires the execution of three instructions through one instruction, thereby reducing the number of instructions required for translating and executing indirect jump instructions. Therefore, the execution efficiency of the binary translator can be improved by reducing the number of instruction translations of high-frequency instructions, reducing the number of context switches, and thereby improving the speed at which the binary translator executes the program.

[0108] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0109] Reference Figure 7 , shows a structural block diagram of a binary translator embodiment of the present invention, the binary translator may include:

[0110] The instruction calling module is used to call a preset instruction if the current instruction is identified as an indirect jump instruction; the instruction code of the preset instruction includes a first operand and a second operand; the first operand points to a first register, and the second operand points to a second register; the first register stores a target PC value, which is used to point to the address of the next instruction; the second register is used to store the calculation result of the preset instruction;

[0111] An instruction execution module, configured to execute preset calculation logic according to the preset instruction to calculate a target index value corresponding to the target PC value in a hash table, and write the target index value into the second register; the hash table is configured to record the address of the translated instruction in the code cache;

[0112] A target jump module is used to read the target index value from the second register, and query whether the target PC value hits the hash table through the target index value, and execute the next instruction based on the query result.

[0113] Optionally, the instruction code of the preset instruction also includes a third operand, which is an immediate number used to identify a calculation method adopted by the preset calculation logic; the calculation method is determined according to the total length of the hash table and the length of the table entries in the hash table.

[0114] Optionally, the length of the instruction code of the preset instruction is consistent with the instruction code length of the instruction in the host platform instruction set architecture, the first register and the second register are general fixed-point registers of the host platform, the number of bits occupied by the first operand and the second operand in the instruction code is determined according to the number of general fixed-point registers of the host platform, and the lowest bit of the instruction code is the third operand.

[0115] Optionally, the instruction execution module includes:

[0116] a calculation submodule, configured to perform an XOR calculation on a first designated bit and a second designated bit of the target PC value stored in the first register, and write a result of the XOR calculation into a third designated bit in the second register;

[0117] a clearing submodule, used for clearing a fourth designated bit in the second register;

[0118] The shift submodule is used to shift the second register left by a preset bit and fill the lower preset bit with zero.

[0119] Optionally, the binary translator further includes:

[0120] A first determination module, used to determine the total length of the hash table and the length of the entries of the hash table according to the type of the binary translator;

[0121] A second determining module, configured to determine the first designated bit, the second designated bit, the third designated bit, and the fourth designated bit according to the total length of the hash table;

[0122] The third determining module is used to determine the preset bit according to the length of the entry of the hash table.

[0123] Optionally, the third determining module is specifically configured to:

[0124] If the length of the hash table entry is 2 i , i is a positive integer, then the preset position is determined to be i.

[0125] Optionally, the second determining module is specifically configured to:

[0126] If the total length of the hash table is 2 j , j is a positive integer, then the first designated bit is determined to be the jth bit to the (2j-1)th bit of the first register, the second designated bit is determined to be the 0th bit to the (j-1)th bit of the first register, the third designated bit is determined to be the 0th bit to the (j-1)th bit of the second register, and the fourth designated bit is determined to be the jth bit to the highest bit of the second register;

[0127] The target jump module is specifically used for:

[0128] The 0th bit to the (j+preset bit-1)th bit of the second register are read to obtain a target index value.

[0129] Optionally, when the type of the binary translator is the first type, the first designated bit is the 16th to 31st bit, the second designated bit is the 0th to 15th bit, the third designated bit is the 0th to 15th bit, and the fourth designated bit is the 16th to 63rd bit;

[0130] The target jump module is specifically used to read the 0th bit to the 19th bit of the second register to obtain the target index value.

[0131] Optionally, when the type of the binary translator is the second type, the first designated bit is the 12th to 23rd bit, the second designated bit is the 0th to 11th bit, the third designated bit is the 0th to 11th bit, and the fourth designated bit is the 12th to 63rd bit;

[0132] The target jump module is specifically used to read the 0th to 15th bits of the second register to obtain a target index value.

[0133] Optionally, the target jump module is specifically used to read the target address corresponding to the target PC value from the hash table and jump to the target address to execute the next instruction in the execution state if the target PC value is found to hit the hash table.

[0134] Optionally, the target jump module includes:

[0135] A first query submodule is used to query the hash table through the target index value. If there is a target item corresponding to the target index value, and the PC value recorded in the target item is consistent with the target PC value, then the target PC value hits the hash table; or

[0136] a second query submodule, configured to query the hash table by the target index value, and if a target item corresponding to the target index value exists, and the PC value recorded in the target item is inconsistent with the target PC value, then the target PC value does not hit the hash table; or

[0137] The third query submodule is used to query the hash table through the target index value. If there is no target item corresponding to the target index value, the target PC value does not hit the hash table.

[0138] The embodiment of the present invention provides a binary translator. When the binary translator completes the translation of the current TB and executes the current TB, and when the last instruction of the current TB is executed and the instruction is identified as an indirect jump instruction, the preset instruction of the present invention is called. The preset instruction is a hardware instruction newly added by the present invention. The instruction code of the preset instruction includes a first operand and a second operand; the first operand points to a first register, and the second operand points to a second register; the first register stores a target PC value, which is used to point to the address of the next instruction; the second register is used to store the calculation result of the preset instruction. The preset instruction is used to execute the preset calculation logic to calculate the target index value corresponding to the target PC value in the hash table, and write the target index value into the second register. After the preset instruction is executed, the binary translator can read the target index value from the second register, and query whether the target PC value hits the hash table through the target index value, and execute the next instruction based on the query result. The embodiment of the present invention implements the operation step of "calculating the target index value corresponding to the target PC value in the hash table" by calling a preset instruction (a newly added hardware instruction), and implements the operation that requires the execution of three instructions through one instruction, thereby reducing the number of instructions required for translating and executing indirect jump instructions. Therefore, the execution efficiency of the binary translator can be improved by reducing the number of instruction translations of high-frequency instructions, reducing the number of context switches, and thereby improving the speed at which the binary translator executes the program.

[0139] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0140] Reference Figure 8 , is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. Figure 8 As shown, the electronic device includes: a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the steps of the binary translation method of the above-mentioned embodiment.

[0141] An embodiment of the present invention provides a non-transitory computer-readable storage medium. When instructions in the storage medium are executed by a program or a processor of a terminal, the terminal is enabled to perform the steps of the binary translation method of the aforementioned embodiment.

[0142] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0143] Those skilled in the art will appreciate that the embodiments of the embodiments of the present invention may be provided as methods, binary translators, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0144] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0145] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0146] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0147] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0148] Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A binary translation method, characterized in that: Applied to a binary translator, the method comprises: If the current instruction is identified as an indirect jump instruction, a preset instruction is called; the instruction code of the preset instruction includes a first operand and a second operand; the first operand points to a first register, and the second operand points to a second register; the first register stores a target PC value, which is used to point to the address of the next instruction; the second register is used to store a calculation result of the preset instruction; The preset instruction executes preset calculation logic to calculate the target index value corresponding to the target PC value in the hash table, and writes the target index value into the second register; the hash table is used to record the address of the translated instruction in the code cache; Read the target index value from the second register, and query whether the target PC value hits the hash table through the target index value, and execute the next instruction based on the query result; The executing preset calculation logic includes: Perform an XOR calculation on the first designated bit and the second designated bit of the target PC value stored in the first register, and write the result of the XOR calculation to the third designated bit in the second register; clear the fourth designated bit in the second register; shift the second register left by a preset bit, and fill the lower preset bit with zero; The first designated bit, the second designated bit, the third designated bit and the fourth designated bit are determined according to the total length of the hash table; and the preset bit is determined according to the length of the entry of the hash table.

2. The method according to claim 1, characterized in that: The instruction code of the preset instruction also includes a third operand, which is an immediate number used to identify a calculation method adopted by the preset calculation logic; the calculation method is determined according to the total length of the hash table and the length of the table entries in the hash table.

3. The method according to claim 2, characterized in that The length of the instruction code of the preset instruction is consistent with the instruction code length of the instruction in the instruction set architecture of the host platform. The first register and the second register are general fixed-point registers of the host platform. The number of bits occupied by the first operand and the second operand in the instruction code is determined according to the number of general fixed-point registers of the host platform. The lowest bit of the instruction code is the third operand.

4. The method according to claim 1, characterized in that: Before calling the preset instruction, the method further includes: Determining the total length of the hash table and the length of the entries of the hash table according to the type of the binary translator; Determine the first designated bit, the second designated bit, the third designated bit, and the fourth designated bit according to the total length of the hash table; The preset bit is determined according to the length of the entry of the hash table.

5. The method according to claim 4, characterized in that The determining the preset bit according to the length of the entry of the hash table includes: If the length of the hash table entry is 2 i , i is a positive integer, then the preset position is determined to be i.

6. The method according to claim 4, characterized in that The determining the first designated bit, the second designated bit, the third designated bit, and the fourth designated bit according to the total length of the hash table includes: If the total length of the hash table is 2 j , j is a positive integer, then the first designated bit is determined to be the jth bit to the (2j-1)th bit of the first register, the second designated bit is determined to be the 0th bit to the (j-1)th bit of the first register, the third designated bit is determined to be the 0th bit to the (j-1)th bit of the second register, and the fourth designated bit is determined to be the jth bit to the highest bit of the second register; The reading the target index value from the second register comprises: The 0th bit to the (j+preset bit-1)th bit of the second register are read to obtain a target index value.

7. The method according to claim 1, characterized in that The step of executing the next instruction based on the query result includes: In the execution state, if the target PC value is found to hit the hash table, the target address corresponding to the target PC value is read from the hash table, and the program jumps to the target address to execute the next instruction.

8. The method according to claim 1, characterized in that: Each item in the hash table includes a PC value of a client instruction and an address of a translated instruction corresponding to the PC value in a code cache; querying whether the target PC value hits the hash table through the target index value includes: The hash table is queried by the target index value. If a target item corresponding to the target index value exists and the PC value recorded in the target item is consistent with the target PC value, the target PC value hits the hash table; or If there is a target item corresponding to the target index value, and the PC value recorded in the target item is inconsistent with the target PC value, then the target PC value does not hit the hash table; or If there is no target item corresponding to the target index value, the target PC value does not hit the hash table.

9. A binary translator, characterized in that: The binary translator comprises: The instruction calling module is used to call a preset instruction if the current instruction is identified as an indirect jump instruction; the instruction code of the preset instruction includes a first operand and a second operand; the first operand points to a first register, and the second operand points to a second register; the first register stores a target PC value, which is used to point to the address of the next instruction; the second register is used to store the calculation result of the preset instruction; An instruction execution module, configured to execute preset calculation logic according to the preset instruction to calculate a target index value corresponding to the target PC value in a hash table, and write the target index value into the second register; the hash table is configured to record the address of the translated instruction in the code cache; A target jump module, used for reading the target index value from the second register, and querying whether the target PC value hits the hash table through the target index value, and executing the next instruction based on the query result; The instruction execution module includes: a calculation submodule, configured to perform an XOR calculation on a first designated bit and a second designated bit of the target PC value stored in the first register, and write a result of the XOR calculation into a third designated bit in the second register; a clearing submodule, used for clearing a fourth designated bit in the second register; A shift submodule, used for shifting the second register left by a preset position and filling a lower preset position with zero; The first designated bit, the second designated bit, the third designated bit and the fourth designated bit are determined according to the total length of the hash table; and the preset bit is determined according to the length of the entry of the hash table.

10. The binary translator according to claim 9, characterized in that: The instruction code of the preset instruction also includes a third operand, which is an immediate number used to identify a calculation method adopted by the preset calculation logic; the calculation method is determined according to the total length of the hash table and the length of the table entries in the hash table.

11. The binary translator according to claim 10, characterized in that: The length of the instruction code of the preset instruction is consistent with the instruction code length of the instruction in the instruction set architecture of the host platform. The first register and the second register are general fixed-point registers of the host platform. The number of bits occupied by the first operand and the second operand in the instruction code is determined according to the number of general fixed-point registers of the host platform. The lowest bit of the instruction code is the third operand.

12. The binary translator according to claim 9, characterized in that: The binary translator also includes: A first determination module, used to determine the total length of the hash table and the length of the entries of the hash table according to the type of the binary translator; A second determining module, configured to determine the first designated bit, the second designated bit, the third designated bit, and the fourth designated bit according to the total length of the hash table; The third determining module is used to determine the preset bit according to the length of the entry of the hash table.

13. The binary translator according to claim 12, characterized in that: The third determination module is specifically used to: If the length of the hash table entry is 2 i , i is a positive integer, then the preset position is determined to be i.

14. The binary translator according to claim 12, characterized in that: The second determining module is specifically used to: If the total length of the hash table is 2 j , j is a positive integer, then the first designated bit is determined to be the jth bit to the (2j-1)th bit of the first register, the second designated bit is determined to be the 0th bit to the (j-1)th bit of the first register, the third designated bit is determined to be the 0th bit to the (j-1)th bit of the second register, and the fourth designated bit is determined to be the jth bit to the highest bit of the second register; The target jump module is specifically used for: The 0th bit to the (j+preset bit-1)th bit of the second register are read to obtain a target index value.

15. The binary translator according to claim 9, characterized in that: The target jump module is specifically used to read the target address corresponding to the target PC value from the hash table and jump to the target address to execute the next instruction in the execution state if the target PC value is found to hit the hash table.

16. The binary translator according to claim 9, characterized in that: The target jump module comprises: A first query submodule is used to query the hash table through the target index value. If there is a target item corresponding to the target index value, and the PC value recorded in the target item is consistent with the target PC value, then the target PC value hits the hash table; or a second query submodule, configured to query the hash table by the target index value, and if a target item corresponding to the target index value exists, and the PC value recorded in the target item is inconsistent with the target PC value, then the target PC value does not hit the hash table; or The third query submodule is used to query the hash table through the target index value. If there is no target item corresponding to the target index value, the target PC value does not hit the hash table.

17. An electronic device, characterized in that: include: A processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other via the communication bus; The memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the steps of the binary translation method according to any one of claims 1 to 8.

18. A readable storage medium, characterized in that: The readable storage medium stores a program or instruction, and when the program or instruction is executed by a processor, the steps of the binary translation method according to any one of claims 1 to 8 are implemented.

19. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the binary translation method according to any one of claims 1 to 8 are implemented.

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