Method for print recovery of memory array and memory system

Abstract

The invention relates to a method for print recovery of a memory array and a memory system. In some cases, memory cells may be embossed, which may refer to conditions in which cells tend to store one logic state rather than another, are not susceptible to being written to different logic states, or both. Imprinted memory cells may be recovered using a recovery or repair process, which may be initiated according to various conditions, detection, or inference. In some examples, a system may be configured to perform a print recovery operation that is adjusted or selected according to a characterized severity of a print, mode of operation, environmental conditions, and other factors. Imprint management techniques can improve the steadiness, accuracy, or efficiency of a memory system or components thereof operable in the presence of conditions associated with memory cell imprint.

Description

[0001] Information about divisional applications

[0002] This application is a divisional application. The parent application is an invention patent application with application date of September 22, 2020, application number 202011000948.9, and invention name “Method and memory system for footprint recovery of memory array”.

[0003] Cross-references

[0004] This patent application claims priority to U.S. patent application No. 16 / 581,005, filed by Strand et al. on September 24, 2019, entitled “IMPRINT RECOVERY FOR MEMORY ARRAYS,” which is assigned to the present assignee and is expressly incorporated herein by reference in its entirety.

[0005] The technical field relates to footprint management of memory systems. Background Art

[0006] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, etc. Information is stored by programming different states of the memory device. For example, binary devices most often store one of two states, usually represented by a logical 1 or a logical 0. In other devices, more than two states may be stored. To access the stored information, a component of the device may read or sense at least one stored state in the memory device. To store information, a component of the device may write or program a state in the memory device.

[0007] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), etc. Memory devices can be volatile or non-volatile. Non-volatile memory such as FeRAM can maintain stored logic states for a long period of time even in the absence of external power. Volatile memory devices such as DRAM may lose their stored states when disconnected from the external power supply. FeRAM is able to achieve densities similar to volatile memory, but can have non-volatile characteristics because of the use of ferroelectric capacitors as storage devices.

[0008] Some memory types may be subject to imprinting, which may refer to various conditions in which a memory cell tends to store one logic state rather than another, is less susceptible to being written to a different logic state (e.g., a different logic state than that stored prior to a write operation), or both. In some cases, the likelihood of imprinting may vary over time (e.g., a longer duration of a memory cell storing one logic state may be associated with an increased likelihood that the memory cell is imprinted by that logic state). Additionally or alternatively, the likelihood of imprinting may increase with temperature (e.g., a higher temperature of a memory cell storing one logic state may be associated with an increased likelihood that the memory cell is imprinted by that logic state). Imprinted memory cells may be associated with read errors, write errors, or other characteristics or vulnerabilities that may impair the operation of the memory device or a system in which the memory device is included. Summary of the invention

[0009] A method is described. The method may include: determining that a group of memory cells are imprinted in respective first logical states; restricting access to the group of memory cells based at least in part on determining that the group of memory cells are imprinted in the respective first logical states; performing a footprint recovery procedure on the group of memory cells while access to the group of memory cells is restricted, the footprint recovery procedure being intended to improve the ability of the group of memory cells to switch between storing the respective first logical states and storing respective second logical states; and granting access to the group of memory cells after performing the footprint recovery procedure.

[0010] Another method is described. The method may include: determining to improve the ability of a group of memory cells to switch between storing different logical states; modifying operating parameters of the group of memory cells based at least in part on the determination to improve the ability of the group of memory cells to switch between storing different logical states; and operating the group of memory cells based at least in part on the modified operating parameters.

[0011] Another method is described. The method may include: determining that a group of memory cells are imprinted in respective first logical states; determining a severity with which the group of memory cells are imprinted in the respective first logical states; determining whether the severity satisfies a threshold; selecting between a first footprint recovery method and a second footprint recovery method based at least in part on whether the severity satisfies the threshold, the first footprint recovery method and the second footprint recovery method both being intended to improve the ability of the group of memory cells to switch from storing the respective first logical states to storing respective second logical states, wherein the first footprint recovery method restricts access to the group of memory cells, and wherein the second footprint recovery method permits access to the group of memory cells; and applying the selected footprint recovery method to the group of memory cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 An example of a system supporting footprint management according to examples disclosed herein is shown.

[0013] Figure 2 An example of a memory die supporting footprint management of a memory system according to examples disclosed herein is shown.

[0014] Figure 3A and 3B An example of non-linear electrical characteristics of a ferroelectric memory cell with a hysteresis curve according to various examples disclosed herein is shown.

[0015] Figure 4A and 4B Examples of non-linear electrical characteristics of an imprinted ferroelectric memory cell with a hysteresis curve according to various examples disclosed herein are shown.

[0016] Figure 5 An example of a system supporting footprint management of a memory system according to examples disclosed herein is shown.

[0017] Figure 6 An example of a process flow supporting footprint management of a memory system according to examples disclosed herein is shown.

[0018] Figure 7 Graphs illustrating footprint detection conditions that may support footprint management of a memory system according to examples disclosed herein.

[0019] Fig. 8A and 8B An example of a footprint evaluation process in support of footprint management of a memory system according to examples disclosed herein is shown.

[0020] Fig. 9 An example of cell biasing in support of footprint management of a memory system according to examples disclosed herein is shown.

[0021] Fig.10 An example of signaling supporting footprint management of a memory system according to examples disclosed herein is shown.

[0022] Fig.11 An example of a state diagram supporting footprint management of a memory system according to examples disclosed herein is shown.

[0023] Figures 12 to 16 An example of a process flow supporting footprint management of a memory system according to examples disclosed herein is shown.

[0024] Fig.17A block diagram of a memory device supporting footprint management of a memory system according to aspects of the present disclosure is shown.

[0025] Figures 18 to 20 A flow chart illustrating one or more methods of supporting footprint management of a memory system according to examples disclosed herein is shown. DETAILED DESCRIPTION

[0026] A memory device may be subjected to various conditions when used as part of an electronic device, such as a mobile device, a personal computer, a wireless communication device, a server, an Internet of Things (IoT) device, a vehicle, or a vehicle component. In some cases, one or more memory cells of a memory device may be imprinted, which may refer to various conditions in which a memory cell of the memory device tends to store one logic state rather than another logic state, is less susceptible to being written to a different logic state (e.g., a different logic state than that stored prior to a write operation), or both. The likelihood of a memory cell being imprinted by a logic state may be related to the length of time that the logic state is stored uninterruptedly (e.g., continuously), the temperature of the memory cell when the logic state is stored, or other factors.

[0027] In one example, a memory device may be subjected to imprinting due to exposure to high temperatures for a sustained period of time, such as being in a hot vehicle, in direct sunlight, or in other environments, where such conditions may be referred to as static baking (e.g., when one or more memory cells are maintained in a particular logic state during exposure to high temperatures). In some cases, static baking may imprint (e.g., thermally imprint) individual memory cells of a memory device such that they are biased or trapped in a first state (e.g., a state corresponding to a logic 0) rather than another state (e.g., a state corresponding to a logic 1). In another example, memory cells of a memory device may store a logic state under manufacturing conditions, or a charge state or material state that may or may not be associated with data. A memory device may undergo a certain amount of imprinting prior to being installed in a system or operating in a system, such as imprinting over time while idle in a warehouse or without power, which may result in performance degradation or failure during initial operation. In another example, imprinting may be caused accidentally or maliciously by operating parameters or access patterns.

[0028] An imprinted memory cell may be associated with adverse properties when compared to an unimprinted memory cell. For example, an imprinted memory cell may prevent charge flow during an access operation (e.g., a read or write operation), may prevent polarization changes during an access operation, may prevent material property changes, such as atomic distribution or arrangement changes, resistance changes, or threshold voltage changes, or may be associated with other properties that are different from unimprinted memory cells (e.g., properties that are asymmetric with respect to different logical states). In one example, when a write operation is performed on the imprinted memory cell to write a target logical state, the memory cell may not store the target logical state, or the memory device may be unable to read the memory cell when storing the target state, which may cause access errors (e.g., write errors, read errors) or data corruption.

[0029] In some cases, the imprinted memory cells may be recovered (e.g., de-imprinted, disengaged, repaired, normalized, equalized) using a recovery or repair process. For example, the memory cells of the array may be recovered (e.g., from a recoverable imprint) by applying various biasing techniques, such as applying one or more voltages or voltage pulses on the memory cells, or performing multiple access operations (e.g., multiple read operations, multiple write operations, multiple read and write operations) on the memory cells of the memory array. In various examples, such biasing may be performed in a maintenance or recovery mode that may or may not be associated with a particular data access (e.g., as requested or commanded by a host device, on a scheduled basis, based on detection or prediction that an imprint has occurred), or in an imprint maintenance or recovery mode that modifies parameters of an access operation (e.g., a read operation, a write operation, a refresh operation) while supporting data transfer in the imprint maintenance or recovery mode. In some cases, the parameters may be permanently or indefinitely modified to support imprint recovery or prevention (e.g., the duration or magnitude of the access voltage may be modified). Such techniques can mitigate the effects of imprinting, such as returning the memory cells to generally normalized, equalized, or otherwise symmetric characteristics with respect to different logic states.

[0030] Recovery operations associated with memory cell imprinting according to the described techniques can be initiated based on various conditions or detections. For example, an electronic device or a memory device can detect conditions associated with imprinting (e.g., conditions associated with high temperatures, conditions associated with maintaining a logic state for a relatively long duration, an indication that the memory device is powered on for the first time, an unintentional or malicious access pattern that can produce an imprint), and initiate recovery operations based at least in part on the detected conditions. In other words, in some instances, the likelihood of imprinting can be inferred based on operating conditions, or the presence of imprinting can be predicted in other ways. In some instances, such detection can be based on signaling transmitted between an electronic device (e.g., a host device, a host controller) and a memory device, or various tracking, monitoring, sensing, or computing operations performed by one or both of the memory device or the electronic device containing the memory device.

[0031] In some cases, the electronic device or memory device may not have an imprint indication, or may lack information related to determining or predicting whether imprinting has occurred or may occur. For example, during the use of the electronic device, such as when the electronic device is powered off or loses power (e.g., when the battery is exhausted, when the power supply is disconnected), or when the electronic device is in standby mode or other modes in which the memory device is powered off or otherwise does not monitor operating conditions or environmental conditions, the memory device may be powered off or deactivated. During the power-off, deactivated, or standby state, the electronic device and the memory device may be exposed to one or more operating or environmental conditions that may affect the operation of the memory device, but the device may not detect the conditions associated with imprinting. For example, if the device is not powered on, the device may not monitor thermal history or conditions. Therefore, in some instances, the memory device may perform an imprint detection procedure (e.g., detecting the presence of imprinting in the memory device) to determine whether an imprint recovery operation should be performed on the memory array. A memory device or a system including a memory device may initiate or perform such a detection procedure when initiated in response to a request from a host device (e.g., as part of an initialization, power-on, or boot-up process), or on any other scheduled (e.g., periodic) or event-driven (e.g., triggered) basis (including the various scenarios described herein).

[0032] The technology according to the present disclosure can improve the robustness, accuracy or efficiency with which a memory device or a host device of a memory device or a system including a memory device and a host device can operate in the presence of conditions associated with memory cell imprinting. For example, according to the described technology, a memory device, a host device or both of them can perform various operations to detect the presence of memory cell imprinting or infer the possibility of memory cell imprinting. The memory device can be configured to perform various operations in response to such detection or inference, which can be more efficient than continuously or preemptively performing such operations. In some examples, the system can be configured to characterize the severity or directionality of the imprinting and perform an imprint recovery operation that is adjusted or selected according to the characterized severity or directionality. In addition or alternatively, the imprint recovery operation can be customized by the system for a specific operating condition of the memory device or host device, such as an operating mode or environmental condition, which in some examples can be based at least in part on signaling or operational negotiation between the memory device and the host device. In some cases, the described technology can also consider various aspects of data retention or operational integrity, including various signaling, data transfer or operational management between the memory device and the host device.

[0033] First, in reference Figure 1 Features of the present disclosure are described in the context of the memory systems and memory dies described in 4. Figures 5 to 16 Features of the present disclosure are described in the context of blot detection and recovery techniques. These and other features of the present disclosure are further referenced as referenced Figures 17 to 20 The described memory footprint management is illustrated and described by a device diagram and a flow chart.

[0034] Figure 1 An example of a system 100 supporting footprint management according to examples disclosed herein is shown. The system 100 may include an external memory controller 105, a memory device 110, and a plurality of channels 115 coupling the external memory controller 105 with the memory device 110. The system 100 may include one or more memory devices, but for ease of description, the one or more memory devices may be described as a single memory device 110.

[0035] System 100 may include portions of an electronic device, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a vehicle, or other system. In some examples, system 100 may be an example of a portable electronic device. For example, system 100 may illustrate aspects of a computer, a laptop, a tablet computer, a smartphone, a cellular phone, a wearable device, an Internet-connected device, a vehicle controller, and the like. Memory device 110 may be a component of the system configured to store data of one or more other components of system 100.

[0036] At least a portion of system 100 may be an example of a host device. Such a host device may be an example of a device that uses memory to perform a process, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop, a tablet computer, a smart phone, a cellular phone, a wearable device, an Internet-connected device, some other stationary or portable electronic device, etc. In some cases, a host device may refer to hardware, firmware, software, or a combination thereof that implements the functionality of external memory controller 105. In some cases, external memory controller 105 may be referred to as a host or a host device.

[0037] In some cases, memory device 110 may be a standalone device or component configured to communicate with other components of system 100 and provide physical memory addresses or spaces that may be used or referenced by system 100. In some instances, memory device 110 may be configured to cooperate with one or more different types of systems 100. Signaling between components of system 100 and memory device 110 may be used to support modulation schemes for modulating signals, various pin designs for transmitting signals, various form factors for physical packaging of system 100 and memory device 110, clock signaling and synchronization between system 100 and memory device 110, timing conventions, and / or other factors.

[0038] The memory device 110 may be configured to store data of components of the system 100. In some cases, the memory device 110 may act as a slave device of the system 100 (e.g., responding to and executing commands provided by the system 100 through the external memory controller 105). Such commands may include access commands for access operations, such as write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands. The memory device 110 may include two or more memory dies 160 (e.g., memory chips) to support the desired or specified data storage capacity. The memory device 110 including two or more memory dies may be referred to as a multi-die memory or package (also referred to as a multi-chip memory or package).

[0039] System 100 may further include a processor 120, a basic input / output system (BIOS) component 125, one or more peripheral components 130, and an input / output (I / O) controller 135. The components of system 100 may be in electronic communication with each other using a bus 140.

[0040] Processor 120 may be configured to provide control or other functionality for at least a portion of system 100. Processor 120 may be a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or a combination of these types of components. In these cases, processor 120 may be an instance of a central processing unit (CPU), a graphics processing unit (GPU), a general purpose graphics processing unit (GPGPU), or a system on a chip (SoC), among other instances.

[0041] BIOS component 125 may be a software component including BIOS operating as firmware that may initialize and run various hardware components of system 100. BIOS component 125 may also manage the flow of data between processor 120 and various components of system 100 (e.g., peripheral components 130, I / O controller 135). BIOS component 125 may include a program or software stored in read-only memory (ROM), flash memory, or any other non-volatile memory.

[0042] Peripheral component 130 may be any input device or output device or interface to such devices and may be integrated into or with system 100. Examples may include a disk controller, a sound controller, a graphics controller, an Ethernet controller, a modem, a Universal Serial Bus (USB) controller, a serial or parallel port, or a peripheral card slot such as a peripheral component interconnect (PCI) or a dedicated graphics port. Peripheral component 130 may be other components that are understood by those skilled in the art to be peripheral devices.

[0043] I / O controller 135 may manage data communications between processor 120 and peripheral components 130, input device 145, or output device 150. I / O controller 135 may manage peripheral devices that are not integrated into or with system 100. In some cases, I / O controller 135 may represent a physical connection or port to an external peripheral component.

[0044] Input 145 may represent a device or signal external to system 100 that provides information, signals, or data to system 100 or its components. This may include a user interface, or interfacing with or between other devices. In some cases, input 145 may be a peripheral device that interfaces with system 100 through one or more peripheral components 130, or may be managed by I / O controller 135.

[0045] Output 150 may represent a device or signal external to system 100 that is configured to receive output from system 100 or any of its components. Examples of output 150 may include a display, an audio speaker, another processor on a printed device or printed circuit board, etc. In some cases, output 150 may be a peripheral device that interfaces with system 100 through one or more peripheral components 130, or may be managed by I / O controller 135.

[0046] The components of system 100 may be composed of general or special purpose circuitry designed to perform their functions. This may include various circuit elements, such as conductive lines, transistors, capacitors, inductors, resistors, amplifiers, or other active or passive elements, configured to perform the functions described herein.

[0047] The memory device 110 may include a device memory controller 155 and one or more memory dies 160. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, and / or local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, and / or memory array 170-N). The memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more sectors), where each memory cell is configured to store at least one bit of digital data. In some cases, the memory array 170 may include ferroelectric RAM (FeRAM) memory cells. Reference Figure 2 Features of memory array 170 and / or memory cells are described in further detail.

[0048] The memory device 110 may be an example of a two-dimensional (2D) memory cell array or an example of a three-dimensional (3D) memory cell array. For example, a 2D memory device may include a single memory die 160. A 3D memory device may include two or more memory dies 160 (e.g., memory die 160-a, memory die 160-b, and / or any number of memory dies 160-N). In a 3D memory device, multiple memory dies 160-N may be stacked on top of each other (relative to a substrate) or stacked next to each other. In some cases, the memory dies 160-N in a 3D memory device may be referred to as a board, a level, a layer, or a die. A 3D memory device may include any number of stacked memory dies 160-N (e.g., two, three, four, five, six, seven, eight). Compared to a single 2D memory device, this may increase the number of memory cells that may be positioned on a substrate, which in turn may reduce manufacturing costs or increase the performance of the memory array, or both. In a certain 3D memory device, different plates may share at least one common access line, such that some plates may share at least one of a word line, a digit line, and / or a plate line.

[0049] The device memory controller 155 may include circuitry or components configured to control the operation of the memory device 110. The device memory controller 155 may include hardware, firmware, instructions, or other configurations that enable the memory device 110 to perform various operations, and may be configured to receive, transmit, or execute commands, data, or control information related to the components of the memory device 110. The device memory controller 155 may be configured to communicate with an external memory controller 105, one or more memory dies 160, or a processor 120. In some cases, the memory device 110 may receive data and / or commands from the external memory controller 105. For example, the memory device 110 may receive a write command that instructs the memory device 110 to store specific data on behalf of a component of the system 100 (e.g., the processor 120) or a read command that instructs the memory device 110 to provide specific data stored in the memory die 160 to a component of the system 100 (e.g., the processor 120). In some cases, the device memory controller 155 may control the operation of the memory device 110 described herein in conjunction with the local memory controller 165 of the memory die 160. Examples of components included in the device memory controller 155 and / or the local memory controller 165 may include a receiver for receiving signals (e.g., from the external memory controller 105), a transmitter for transmitting signals (e.g., to the external memory controller 105), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating signals to be transmitted, or various other circuit systems configured to support the described operations of the device memory controller 155 or the local memory controller 165.

[0050] A local memory controller 165 (e.g., local to the memory die 160) may be configured to control the operation of the memory die 160. In some examples, the local memory controller 165 may be configured to communicate (e.g., receive or transmit data and / or commands) with the device memory controller 155. The local memory controller 165 may support the device memory controller 155 in controlling the operation of the memory device 110 as described herein. In some cases, the memory device 110 may not include a device memory controller 155, and the local memory controller 165 or the external memory controller 105 may perform the various functions described herein. Thus, the local memory controller 165 may be configured to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 105 or the processor 120.

[0051] The external memory controller 105 may be configured to enable communication of information, data, and / or commands between components of the system 100 (e.g., the processor 120) and the memory device 110. The external memory controller 105 may act as a liaison between the components of the system 100 and the memory device 110, so that the components of the system 100 may not need to know the details of the operation of the memory device. The components of the system 100 may present requests (e.g., read commands or write commands) to the external memory controller 105 for the external memory controller 105 to satisfy. The external memory controller 105 may convert or translate communications exchanged between the components of the system 100 and the memory device 110. In some cases, the external memory controller 105 may include a system clock that generates a common (source) system clock signal. In some cases, the external memory controller 105 may include a common data clock that generates a common (source) data clock signal.

[0052] In some cases, the external memory controller 105 or other components of the system 100, or their functionality described herein, may be implemented by the processor 120. For example, the external memory controller 105 may be hardware, firmware, or software, or some combination thereof, implemented by the processor 120 or other components of the system 100. Although the external memory controller 105 is depicted as being external to the memory device 110, in some cases, the external memory controller 105 or their functionality described herein may be implemented by the memory device 110. For example, the external memory controller 105 may be hardware, firmware, or software, or some combination thereof, implemented by the device memory controller 155 or one or more local memory controllers 165. In some cases, the external memory controller 105 may be distributed across the processor 120 and the memory device 110, such that portions of the external memory controller 105 are implemented by the processor 120 and other portions are implemented by the device memory controller 155 or the local memory controller 165. Likewise, in some cases, one or more functions attributed herein to device memory controller 155 or local memory controller 165 may in some cases be performed by external memory controller 105 (separate from or included in processor 120 ).

[0053] Components of system 100 may exchange information with memory device 110 using multiple channels 115. In some examples, channels 115 may be configured to support communication between external memory controller 105 and memory device 110. Each channel 115 may include or be associated with one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. For example, channel 115 may include a first terminal including one or more pins or pads located at external memory controller 105 and one or more pins or pads located at memory device 110. A pin may be an example of a conductive input or output point of a device of system 100, and a pin may be configured to act as part of a channel. In some cases, a pin or pad of a terminal may be part of a signal path of channel 115. Additional signal paths may be coupled to the terminals of a channel to route signals within a component of system 100. For example, memory device 110 may include signal paths (e.g., signal paths internal to memory device 110 or components thereof, such as internal to memory die 160) that route signals from terminals of channel 115 to various components of memory device 110 (e.g., device memory controller 155, memory die 160, local memory controller 165, memory array 170).

[0054] Channel 115 (and associated signal paths and terminals) can be dedicated to transmitting specific types of information. In some cases, channel 115 can be an aggregate channel and therefore can include multiple individual channels. For example, data channel 190 can be x4 (e.g., including four signal paths), x8 (e.g., including eight signal paths), x16 (including sixteen signal paths), etc. The signals transmitted through the channel can use a double data rate (DDR) timing scheme. For example, some symbols of the signal can be registered on the rising edge of the clock signal, and other symbols of the signal can be registered on the falling edge of the clock signal. The signals transmitted through the channel can use single data rate (SDR) signaling. For example, one symbol of the signal can be registered for each clock cycle.

[0055] In some cases, channel 115 may include one or more command and address (CA) channels 186. CA channel 186 may be configured to transmit commands between external memory controller 105 and memory device 110, including control information associated with the commands (e.g., address information). For example, CA channel 186 may include a read command with an address of desired data. In some cases, CA channel 186 may register on a rising clock signal edge and / or a falling clock signal edge. In some cases, CA channel 186 may include any number of signal paths to decode address and command data (e.g., eight or nine signal paths).

[0056] In some cases, channel 115 may include one or more clock signal (CK) channels 188. CK channel 188 may be configured to transmit one or more common clock signals between external memory controller 105 and memory device 110. Each clock signal may be configured to oscillate between a high state and a low state and coordinate the actions of external memory controller 105 and memory device 110. In some cases, the clock signal may be a differential output (e.g., a CK_t signal and a CK_c signal), and the signal path of CK channel 188 may be configured accordingly. In some cases, the clock signal may be single-ended. CK channel 188 may include any number of signal paths. In some cases, clock signal CK (e.g., CK_t signal and CK_c signal) may provide a timing reference for command and addressing operations of memory device 110 or other full system operations of memory device 110. Therefore, clock signal CK may be variously referred to as control clock signal CK, command clock signal CK, or system clock signal CK. The system clock signal CK may be generated by a system clock, which may include one or more hardware components (eg, oscillators, crystals, logic gates, transistors, etc.).

[0057] In some cases, channels 115 may include one or more data (DQ) channels 190. Data channels 190 may be configured to transfer data and / or control information between external memory controller 105 and memory device 110. For example, data channels 190 may transfer (e.g., bidirectionally) information to be written to memory device 110 or information to be read from memory device 110.

[0058] In some cases, channel 115 may include one or more other channels 192 that may be dedicated for other purposes. These other channels 192 may include any number of signal paths.

[0059] In some cases, the other channels 192 may include one or more write clock signal (WCK) channels. Although the 'W' in WCK may nominally stand for "write", the write clock signal WCK (e.g., WCK_t signal and WCK_c signal) may provide a timing reference (e.g., a timing reference for both read and write operations) that is commonly used for access operations of the memory device 110. Therefore, the write clock signal WCK may also be referred to as a data clock signal WCK. The WCK channel may be configured to transmit a common data clock signal between the external memory controller 105 and the memory device 110. The data clock signal may be configured to coordinate access operations (e.g., write operations or read operations) of the external memory controller 105 and the memory device 110. In some cases, the write clock signal may be a differential output (e.g., WCK_t signal and WCK_c signal), and the signal path of the WCK channel may be configured accordingly. The WCK channel may include any number of signal paths. The data clock signal WCK may be generated by a data clock, which may include one or more hardware components (e.g., an oscillator, a crystal, a logic gate, a transistor, etc.).

[0060] In some cases, other channels 192 may include one or more error detection code (EDC) channels. An EDC channel may be configured to transmit error detection signals, such as checksums, in order to improve system reliability. An EDC channel may include any number of signal paths.

[0061] Channel 115 may couple external memory controller 105 and memory device 110 using a variety of different architectures. Examples of various architectures may include a bus, a point-to-point connection, a crossbar switch, a high-density interposer such as a silicon interposer, or a channel formed in an organic substrate, or some combination thereof. For example, in some cases, the signal path may at least partially include a high-density interposer such as a silicon interposer or a glass interposer.

[0062] The signals transmitted over the channel 115 may be modulated using a variety of different modulation schemes. In some cases, a binary symbol (or binary level) modulation scheme may be used to modulate the signals transmitted between the external memory controller 105 and the memory device 110. The binary symbol modulation scheme may be an example of an M-ary modulation scheme, where M is equal to two. Each symbol of the binary symbol modulation scheme may be configured to represent one bit of digital data (e.g., a symbol may represent a logical 1 or a logical 0). Examples of binary symbol modulation schemes include, but are not limited to, non-return to zero (NRZ), unipolar encoding, bipolar encoding, Manchester encoding, pulse amplitude modulation (PAM) with two symbols (e.g., PAM2), and the like.

[0063] In some cases, a multi-symbol (or multi-level) modulation scheme may be used to modulate signals transmitted between the external memory controller 105 and the memory device 110. The multi-symbol modulation scheme may be an example of an M-ary modulation scheme, where M is greater than or equal to three. Each symbol of the multi-symbol modulation scheme may be configured to represent more than one bit of digital data (e.g., a symbol may represent a logical 00, a logical 01, a logical 10, or a logical 11). Examples of multi-symbol modulation schemes include, but are not limited to, PAM3, PAM4, PAM8, and other PAM configurations, quadrature amplitude modulation (QAM), quadrature phase shift keying (QPSK), and the like. A multi-symbol signal (e.g., a PAM3 signal or a PAM4 signal) may be a signal modulated using a modulation scheme that includes at least three levels to encode more than one information bit. Multi-symbol modulation schemes and symbols may alternatively be referred to as non-binary, multi-bit, or high-order modulation schemes and symbols.

[0064] In some cases, one or more memory cells of the memory array 170 may be imprinted, which may refer to various conditions in which a memory cell is prone to storing one logic state rather than another, is less susceptible to being written to a different logic state (e.g., a different logic state than that stored prior to a write operation), or both. The likelihood of a memory cell being imprinted by a logic state may be related to the length of time that the logic state is stored (e.g., continuous duration, uninterrupted duration), the temperature of the memory cell when the logic state is stored, inadvertent or malicious access patterns, or other factors. According to the described techniques, components of the system 100 may be configured to selectively perform various operations to mitigate or recover from such imprinting, which may improve the robustness, accuracy, or efficiency with which the memory device 110, a host device, or the entire system 100 may operate in the presence of conditions associated with memory cell imprinting.

[0065] For example, according to the described techniques, the memory device 110, the host device (e.g., the external memory controller 105), or both may perform various operations to detect the presence of memory cell footprints or infer the possibility of memory cell footprints. The memory device 110 may be accordingly configured to perform various operations in response to such detection or inference, which may be more efficient than continuously or preemptively performing such operations. In some examples, one or more components of the system 100 may be configured to characterize the severity or directionality of the imprint and perform footprint recovery operations that are adjusted or selected based on the characterized severity or directionality. Additionally or alternatively, the footprint recovery operations may be customized by the system 100 for specific operating conditions of the memory device 110, the host device (e.g., the external memory controller 105), or the entire system 100, such as operating modes or environmental conditions, which in some examples may be based at least in part on signaling or operational negotiation between the memory device 110 and the host device (e.g., the external memory controller 105).

[0066] Figure 2 An example of a memory die 200 supporting footprint management of a memory system according to examples disclosed herein is shown. The memory die 200 may be a reference Figure 1 1. An example of a memory die 160 is described. In some cases, the memory die 200 may be referred to as a memory chip, a memory device, or an electronic memory device. The memory die 200 may include one or more memory cells 205 that are each programmable to store a different logic state (e.g., a programmed state in a set of two or more possible states). For example, the memory cell 205 may be configured to store one bit of digital logic at a time (e.g., a logic 0 or a logic 1). In some cases, the memory cell 205 (e.g., a multi-level memory cell 205) may be configured to store more than one bit of digital logic at a time (e.g., a logic 00, a logic 01, a logic 10, or a logic 11).

[0067] In some examples, the memory cell 205 may store a charge representing a programmable logic state (e.g., storing a charge in a capacitor, a capacitive memory element, a capacitive storage element). In one example, a charged and uncharged capacitor may represent two logic states, respectively. In another example, a capacitor with a positive charge (e.g., a first polarity, a positive polarity) and a capacitor with a negative charge (e.g., a second polarity, a negative polarity) may represent two logic states, respectively. A DRAM or FeRAM architecture may use such a design, and the capacitor employed may include a dielectric material having a linear or parasitic polarization characteristic as an insulator. In some examples, different charge levels of the capacitor may represent different logic states, which in some examples may support more than two logic states in the corresponding memory cell 205. In some examples, such as the FeRAM architecture, the memory cell 205 may include a ferroelectric capacitor having a ferroelectric material as an insulating (e.g., non-conductive) layer between the terminals of the capacitor. Different levels or polarities of polarization of the ferroelectric capacitor may represent different logic states (e.g., supporting two or more logic states in the corresponding memory cell 205). Ferroelectric materials have nonlinear polarization properties, including further references Figure 3A and 3B Those discussed in detail.

[0068] In some examples, the memory cell 205 may store a logic state using a configurable material, which may be referred to as a memory element, a memory storage element, a material element, a material storage element, a material portion, a polarity written material portion, and the like. The configurable material of the memory cell 205 may have one or more variable and configurable features or characteristics (e.g., material states) that represent (e.g., correspond to) different logic states. For example, the configurable material may take different forms, different atomic configurations, different crystallinity, different atomic distributions, or otherwise maintain different features. In some examples, such features may be associated with different resistances, different threshold voltages, or other characteristics that are detectable or distinguishable during a read operation to identify the logic state stored by the configurable material. In some examples, the configurable material may refer to a chalcogenide-based storage component. For example, a chalcogenide storage element may be used in a phase change memory (PCM) cell or a self-selected memory cell. The chalcogenide storage element may be an example of a resistive memory or a threshold memory.

[0069] Operations such as reading and writing can be performed on memory cell 205 by activating or selecting access lines such as word line 210, digit line 215, and / or plate line 220. In some cases, digit line 215 may also be referred to as a bit line. References to access lines, word lines, digit lines, plate lines, bit lines, or the like are interchangeable without affecting understanding or operation. Activating or selecting word line 210, digit line 215, or plate line 220 may include applying a voltage to the corresponding access line (e.g., "biasing" the corresponding access line).

[0070] The memory die 200 may include access lines (e.g., word lines 210, digit lines 215, plate lines 220) arranged in a grid-like pattern. Memory cells 205 may be positioned at the intersections of the word lines 210, digit lines 215, and / or plate lines 220. By biasing the word lines 210, digit lines 215, and plate lines 220 (e.g., applying voltages to the word lines 210, digit lines 215, or plate lines 220), individual memory cells 205 may be accessed at their intersections.

[0071] Accessing the memory cells 205 may be controlled by a row decoder 225, a column decoder 230, and a plate driver 235. For example, the row decoder 225 may receive a row address from a local memory controller 265 and activate a word line 210 based on the received row address. The column decoder 230 may receive a column address from a local memory controller 265 and activate a digit line 215 based on the received column address. The plate driver 235 may receive a plate address from a local memory controller 265 and activate a plate line 220 based on the received plate address, or may activate a common plate or plate node common to a segment of the accessed memory cells 205. For example, the memory die 200 may include a plurality of word lines 210 labeled WL_1 to WL_M, a plurality of digit lines 215 labeled DL_1 to DL_N, and a plurality of plate lines labeled PL_1 to PL_P, where M, N, and P depend on the size of the memory array. By activating word lines 210, digit lines 215, and plate lines 220, for example, WL_1, DL_3, and PL_1, memory cells 205 can be accessed at their intersections. Regardless of whether it is a two-dimensional or three-dimensional configuration, the intersection of word lines 210 and digit lines 215 can be referred to as the address of memory cell 205. In some cases, the intersection of word lines 210, digit lines 215, and plate lines 220 can be referred to as the address of memory cell 205.

[0072] Memory cell 205 may include a logic storage component, such as capacitor 240 and switch component 245. In some examples, capacitor 240 may be an example of a ferroelectric capacitor. A first node (e.g., cell bottom, bottom node) of capacitor 240 may be coupled to switch component 245, and a second node (e.g., cell plate, plate node) of capacitor 240 may be coupled to plate line 220. Switch component 245 may be an example of a transistor or any other type of switching device that selectively establishes or cancels electronic communication between two components.

[0073] Selecting or deselecting the memory cell 205 can be achieved by activating or deactivating the switch component 245. The capacitor 240 (e.g., the bottom of the cell) can be electronically connected to the digital line 215 using the switch component 245. For example, when the switch component 245 is deactivated, the capacitor 240 can be isolated from the digital line 215, and when the switch component 245 is activated, the capacitor 240 can be coupled to the digital line 215. In some cases, the switch component 245 is a transistor, and its operation is controlled by applying a voltage to the transistor gate, wherein the voltage difference between the transistor gate and the transistor source is greater than or less than the threshold voltage of the transistor. In various examples, the switch component 245 can be a p-type transistor or an n-type transistor. The word line 210 can be electronically connected to the gate of the switch component 245, and the switch component 245 can be activated / deactivated based on the voltage applied to the word line 210.

[0074] The sensing component 250 may be configured to detect the state (e.g., polarization state, charge state) stored by the capacitor 240 of the memory cell 205, and based on the detected state, determine the logic state of the memory cell 205. The sensing component 250 may include one or more sense amplifiers for amplifying or otherwise converting signals generated by accessing the memory cell 205. For example, during a read operation, the capacitor 240 of the memory cell 205 may output a signal to its corresponding digit line 215 (e.g., discharge the charge), which may cause the voltage of the digit line 215 to change. The sense amplifier may detect small changes in the charge or voltage of the digit line 215 during the read operation, and may generate a signal corresponding to a logic 0 or a logic 1 based on the detected charge.

[0075] In some examples, the sensing component 250 can be configured to compare a signal received from the memory cell 205 (e.g., via the digital line 215) to a reference line 255 (e.g., a reference voltage). The sensing component 250 can determine the stored state of the memory cell 205 based on the comparison. In one example, according to binary signaling, if the voltage of the digital line 215 is higher than the reference line 255, the sensing component 250 can determine that the stored state of the memory cell 205 is a logic 1, and if the voltage of the digital line 215 is lower than the reference line 255, the sensing component 250 can determine that the stored state of the memory cell 205 is a logic 0. The sensing component 250 can include various transistors, amplifiers, or another circuit system for detecting and amplifying the signal difference. The detected logic state of the memory cell 205 can be provided as an output of the sensing component 250 (e.g., to the input / output component 260), and the detected logic state can be indicated to another component of the memory device 110 that includes the memory die 200, such as the device memory controller 155 (e.g., directly or using the local memory controller 265). In some cases, the sensing component 250 can be in electronic communication with the row decoder 225, the column decoder 230, and / or the plate driver 235.

[0076] In some cases, the sense component 250 or reference line 255 may be configured (e.g., by the local memory controller 265) to control or adjust a reference voltage used to determine (read) a stored logic state of the memory cell 205 (e.g., according to various operating modes or other adjustments). For example, during an access mode (e.g., a mode in which application data may be written to or read from the memory cell 205), the sense component 250 and reference line 255 may be configured to determine (e.g., read) a stored state of the memory cell 205 using a default reference voltage. The default reference voltage may be configured or set to a voltage level that reduces or minimizes errors during a sensing operation or otherwise maximizes a read window (e.g., a reference voltage that equalizes or centralizes with respect to detecting different logic states). For example, the default voltage may be configured (e.g., as a static configuration, as a configuration that is adjusted during operation) to be a voltage level between the voltage of the digit line 215 when reading a memory cell 205 storing a logical 1 and the voltage of the digit line 215 when reading a memory cell 205 storing a logical 0 (e.g., equidistant relative to the digit line 215 voltage associated with a logical 1 and the digit line 215 voltage associated with a logical 0). Accurate determination of the stored memory state may be facilitated.

[0077] The local memory controller 265 may control access to the memory cell 205 through various components (eg, the row decoder 225, the column decoder 230, the plate driver 235, and the sensing component 250). The local memory controller 265 may be a reference Figure 1 105. In some cases, one or more of the row decoder 225, column decoder 230, plate driver 235, and sensing component 250 may be co-located with the local memory controller 265. The local memory controller 265 may be configured to receive data from the external memory controller 105 or reference Figure 1 The device memory controller 155 is described to receive commands and / or data, convert the commands and / or data into information that can be used by the memory die 200, perform one or more operations on the memory die 200, or transmit data from the memory die 200 to the external memory controller 105 or the device memory controller 155 in response to performing one or more operations. The local memory controller 265 can generate row, column and / or board line address signals to activate the target word line 210, the target digital line 215 and the target board line 220. The local memory controller 265 can also generate and control various voltages or currents used during the operation of the memory die 200. In general, the amplitude, shape or duration of the applied voltage or current discussed herein can be adjusted or varied and can be different for different operations discussed when operating the memory die 200.

[0078] In some cases, the local memory controller 265 may be configured to perform a write operation (e.g., a programming operation) on one or more memory cells 205 of the memory die 200. During a write operation, the memory cells 205 of the memory die 200 may be programmed to store a desired logic state. In some cases, multiple memory cells 205 may be programmed during a single write operation. The local memory controller 265 may identify a target memory cell 205 on which a write operation is performed. The local memory controller 265 may identify a target word line 210, a target digit line 215, and / or a target plate line 220 that are in electronic communication with the target memory cell 205 (e.g., an address of the target memory cell 205). The local memory controller 265 may activate the target word line 210, the target digit line 215, or the target plate line 220 (e.g., apply a voltage to the word line 210, the digit line 215, or the plate line 220) to access the target memory cell 205. Local memory controller 265 may apply a specific signal (eg, voltage) to digit line 215 and a specific signal (eg, voltage) to plate line 220 during a write operation to store a specific state in capacitor 240 of memory cell 205 that indicates a desired logic state.

[0079] In some cases, the local memory controller 265 may be configured to perform a read operation (e.g., a sensing operation) on one or more memory cells 205 of the memory die 200. During the read operation, the logic state stored in the memory cell 205 of the memory die 200 may be determined. In some cases, multiple memory cells 205 may be sensed during a single read operation. The local memory controller 265 may identify the target memory cell 205 on which the read operation is performed. The local memory controller 265 may identify the target word line 210, the target digit line 215, and / or the target plate line 220 that are in electronic communication with the target memory cell 205 (e.g., the address of the target memory cell 205). The local memory controller 265 may activate the target word line 210, the target digit line 215, and / or the target plate line 220 (e.g., apply a voltage to the word line 210, the digit line 215, or the plate line 220) to access the target memory cell 205. The target memory cell 205 may pass a signal to the sensing component 250 in response to biasing the access line. The sensing component 250 may amplify the signal. The local memory controller 265 may activate the sensing component 250 (e.g., latch the sensing component) and thereby compare the signal received from the memory cell 205 with the reference line 255. Based on the comparison, the sensing component 250 may determine the logic state stored on the memory cell 205. As part of the read operation, the local memory controller 265 may transmit the logic state stored on the memory cell 205 to the external memory controller 105 (or device memory controller).

[0080] In some memory architectures, accessing a memory cell 205 may degrade or destroy the logic state stored in the memory cell 205, and a rewrite or refresh operation may be performed to return the initial logic state to the memory cell 205. For example, in a DRAM or FeRAM, the capacitor of the memory cell 205 may be partially or completely discharged during a sensing operation, thereby destroying the logic state previously stored in the memory cell 205. Therefore, in some instances, the logic state stored in the memory cell 205 may be rewritten after an access operation (e.g., in a rewrite operation) to return the memory cell to its initial logic state. The local memory controller 265 may rewrite the logic state to the target memory cell after a read operation, and in some cases, the rewrite operation may be considered part of the read operation. In some cases, activating a single access line (e.g., word line 210, digit line 215, plate line 220) may cause all memory cells 205 coupled to the activated access line to discharge. Thus, several or all of the memory cells 205 coupled to an access line associated with an access operation (eg, all cells in an access row, all cells in an access column) may be rewritten after the access operation.

[0081] In some examples, reading the memory cell 205 may be non-destructive. That is, after reading the memory cell 205, the logic state of the memory cell 205 may not need to be rewritten. However, in some examples, the logic state of the memory cell 205 may or may not need to be refreshed in the absence or presence of other access operations. For example, the logic state stored by the memory cell 205 may be refreshed at periodic intervals by applying appropriate write, rewrite, refresh or equalization pulses or biases to maintain the stored logic state. Refreshing the memory cell 205 can reduce or eliminate read disturbance errors or logic state corruption caused by charge leakage or changes in the atomic configuration of the memory element over time.

[0082] In some cases, environmental conditions such as static baking can cause programmable features of the memory cell 205 to shift or change. For example, in FeRAM applications, static baking can cause polarization capacity, coercivity, or other aspects of charge mobility of the memory cell 205 to shift or change, which can cause the memory cell 205 to be biased toward a particular logic state (e.g., biased toward being written to or read as a logic 1 state, or biased toward being written to or read as a logic 0 state). In memory applications using configurable materials (e.g., material memory elements), these or other conditions can cause variable and configurable features or characteristics to be unable to change in response to a write operation, such as being unable to be programmed with a different atomic configuration, being unable to be programmed with a different crystallinity, being unable to be programmed with a different atomic distribution, or being unable to be programmed with some other feature associated with a different logic state. Such changes in programmable features can be referred to as imprinting, and can result in read or write characteristics that are different from when imprinting had not occurred (e.g., asymmetric with respect to logic state). For example, when a write operation is performed on an imprinted memory cell having an initial state that is intended to change the logic state of the memory cell, the memory cell 205 may remain or return to the initial (e.g., imprinted) state, or may otherwise be read as storing the initial state. For example, if the memory cell 205 is imprinted in a 0 logic state, then after an attempt is made to write the memory cell 205 with a logic 1 state (e.g., after performing a write operation corresponding to a logic 1 state), the memory cell 205 may continue to remain in a 0 logic state, or continue to be read as storing a logic 0 state.

[0083] In some cases, the memory die 200 or the memory device 110 or the system 100 including the memory die 200 can be configured to perform a footprint detection procedure to determine whether to perform a footprint recovery operation. In some cases, the footprint detection procedure can evaluate or determine the number of memory cells 205 that have been imprinted or trapped in a certain logic state, or otherwise determine or infer the presence, severity, or directionality of imprinting.

[0084] In one example, the footprint detection procedure may include writing or attempting to write at least a first set of logic states to a set of memory cells 205. The memory die 200 may be configured or used to read the set of memory cells 205 and perform an analysis procedure that compares the written logic states with the logic states read from the set of memory cells 205 to determine whether a recovery operation should be performed. As used herein, a written logic state may refer to a logic state that is attempted to be written or intended to be written, and a written logic state may refer to an attempt to write a logic state, but in some cases, the writing of the logic state may not be successful (e.g., due to footprints of the target memory cells 205).

[0085] In some cases, for one or more write operations, and using one or more read reference voltages, a footprint detection program may determine how many logic states read from the set of memory cells 205 fail to match the corresponding respective logic states that were written. For example, the memory die 200 (e.g., the local memory controller 265) or a memory device or host device that otherwise operates the memory die 200 may determine that a mismatch or error has occurred when the logic state read from a memory cell 205 is different than the logic state written to the memory cell 205. The footprint detection program may count the number of mismatches or errors to determine whether a recovery operation should be performed, which may include performing one or more comparisons or other calculations based on the number of mismatches or errors.

[0086] In some cases, to support footprint detection or evaluation procedures, the sensing component 250 or reference line 255 can be configured to adjust the reference voltage from a default reference voltage to a reference voltage greater than or less than the default reference voltage (e.g., an offset reference voltage). It can be expected that using an offset reference voltage when reading a group of memory cells 205 will introduce or otherwise be associated with a certain number of mismatches or errors (e.g., an expected difference between a stored logic state and a detected logic state), regardless of the footprint. For example, the first offset reference voltage can be closer to a digital line voltage associated with a logical 1 than the default reference voltage, which can reduce or eliminate the read margin associated with reading a memory cell storing a logical 1. This can increase the read mismatches or errors associated with the sensing operation. That is, even without a footprint, the sensing operation modified to use an offset reference voltage can be expected to produce a certain number of erroneous reads, such as detecting a logical 0 when reading a memory cell 205 that actually stores a logical 1. In some examples, various aspects of expected and measured mismatches or errors can be utilized in footprint evaluation, as described herein.

[0087] In some cases, the footprint detection or assessment procedure can be configured to adjust the reference voltage from a default reference voltage to a plurality of different reference voltages (e.g., a plurality of offset reference voltages) that are greater than or less than the default reference voltage, wherein each of the offset reference voltages can be associated with a respective expected number of mismatches or errors (e.g., according to a random or probabilistic distribution). In some cases, a determination can be made whether to perform a footprint recovery procedure by comparing a determined number of mismatches observed when reading memory cells 205 using the operating reference voltage or the offset reference voltage to a corresponding expected number of mismatches, and possibly using a correlation analysis as described herein.

[0088] In some cases, the imprinted memory cell 205 can be restored (e.g., de-imprinted, detached, repaired, normalized, equalized) using various imprint recovery or repair processes. For example, the memory cell 205 can be restored by applying various biasing techniques, such as applying one or more voltages or voltage pulses on the memory cell 205 (e.g., according to a voltage pulse or bias applied via the digital line 215, the plate line 220, or both). In various examples, such voltage pulses or biases may include one or more pulses, wherein the pulses may be applied according to different impulses, steps, ramps, or other characteristic shapes having different durations, amplitudes, polarities, and combinations thereof. In some examples, such voltage pulses may be applied based on the severity or directionality of the detected or inferred imprint, based on the operating conditions of the memory cell 205 at the time of imprint recovery, based on the operating mode of the memory die 200 or a memory device or host device associated with the memory die 200, or various combinations thereof.

[0089] Additionally or alternatively, the memory cell 205 can be restored by performing access operations (e.g., multiple read operations, multiple write operations, multiple read and write operations) on the memory cell 205, which can be customized (e.g., modified) or otherwise specifically performed for footprint restoration (e.g., according to a footprint restoration or maintenance mode). For example, the footprint repair operation can include cycling the logic state on the memory cell 205 by writing multiple opposite logic states to the memory cell 205 (e.g., including applying a repeated or alternating write bias). In some cases, during the repair or maintenance operation, the memory cell 205 can be cycled a defined number of times, or repeatedly cycled for a defined amount of time. In some cases, the repair operation can include performing multiple read operations on the memory cell 205 (e.g., including applying a repeated or alternating read bias), and the read operations can be included as part of a cycling procedure (e.g., with or without corresponding write or rewrite operations). Additionally or alternatively, the refresh operation may be modified for the specific purpose of footprint recovery (e.g., by extending the refresh duration, by increasing the refresh bias amplitude), which may or may not be performed during an operating mode that supports data exchange with a host device in various examples. In some examples, a read operation may be used to determine when footprint in memory cell 205 is reduced, or more generally, to characterize the severity of footprint. For example, a read operation may be used to compare a read logic state or memory cell 205 with a logic state intended to be written to memory cell 205 to determine whether they match, or whether a read signal associated with the read logic state is closer to a reference voltage than expected or desired.

[0090] In various examples, such biasing may be performed in a maintenance or recovery mode of the memory die 200 that may or may not be associated with a particular data access (e.g., as requested or commanded by a host device), which may include various signaling or data exchanges between the host device and memory devices including the memory die 200 and possibly other auxiliary memory devices that may support various data retention, redundancy, or integrity techniques. Such techniques may mitigate the effects of imprinting, such as returning the memory cells 205 to generally normalized, equalized, or otherwise symmetric characteristics with respect to different logic states, and improve robustness against vulnerabilities that may be associated with imprinting.

[0091] Figure 3A and 3B 300 - a and 300 - b respectively illustrate nonlinear electrical characteristics of a ferroelectric memory cell according to various examples disclosed herein. Figure 2An example of a write process and a read process of a memory cell 205 of a ferroelectric capacitor 240 is described. Hysteresis curves 300 - a and 300 - b depict the charge Q stored on the ferroelectric capacitor 240 as a function of the voltage difference V between the terminals of the ferroelectric capacitor 240 . cap The curve that changes (for example, according to the voltage difference V cap allows charge to flow into or out of a ferroelectric capacitor). For example, a voltage difference V cap The voltage difference between the plate line side of capacitor 240 and the digit line side of capacitor 240 (e.g., the difference between the voltage at the plate node and the voltage at the bottom node, which may be referred to as V plate -V bottom ,like Figure 2 ).

[0092] Ferroelectric materials are characterized by electric polarization, wherein the material can maintain a non-zero charge in the absence of an electric field. Examples of ferroelectric materials include barium titanate (BaTiO3), lead titanate (PbTiO3), lead zirconium titanate (PZT), and strontium bismuth tantalate (SBT). The ferroelectric capacitor 240 described herein may include these or other ferroelectric materials. The electric polarization within the ferroelectric capacitor 240 produces a net charge at the surface of the ferroelectric material and attracts opposite charges through the terminals of the ferroelectric capacitor 240. Therefore, the charge can be stored at the interface of the ferroelectric material and the capacitor terminals. Because the electric polarization can be maintained for a relatively long time, or even indefinitely, compared to capacitors that do not have ferroelectric properties, such as those used in some DRAM arrays, charge leakage can be greatly reduced. The use of ferroelectric materials can remove the need to perform refresh operations for some memory architectures, so that maintaining the logic state of the FeRAM architecture can be associated with lower power consumption than maintaining the logic state of the DRAM architecture.

[0093] The hysteresis curves 300-a and 300-b can be understood from the perspective of a single terminal of the ferroelectric capacitor 240. For example, if the ferroelectric material has a negative polarization, then a positive charge accumulates at the associated terminal of the ferroelectric capacitor 240. Similarly, if the ferroelectric material has a positive polarization, then a negative charge accumulates at the associated terminal of the ferroelectric capacitor 240. In addition, it should be understood that the voltages in the hysteresis curves 300-a and 300-b represent the voltage difference across the capacitor (e.g., the potential between the terminals of the ferroelectric capacitor 240) and are directional. For example, a positive voltage can be achieved by applying a positive voltage to the corresponding terminal (e.g., the cell plate) and maintaining a reference terminal (e.g., the bottom of the cell) at ground or virtual ground (or approximately zero volts (0V)). In some instances, a negative voltage can be applied by maintaining the corresponding terminal (e.g., the cell plate) at ground and applying a positive voltage to the reference terminal (e.g., the bottom of the cell). In other words, a positive voltage can be applied to achieve a negative voltage difference V across the ferroelectric capacitor 240 cap , and thereby negatively polarizes the terminal in question. Similarly, two positive voltages, two negative voltages, or any combination of positive and negative voltages may be applied to the appropriate capacitor terminals to produce the voltage difference V shown in hysteresis curves 300-a and 300-b. cap .

[0094] As depicted by the hysteresis curve 300-a, the ferroelectric material used for the ferroelectric capacitor 240 may remain positively or negatively polarized when there is no net voltage difference between the terminals of the ferroelectric capacitor 240. For example, the hysteresis curve 300-a shows two possible polarization states: a charge state 305-a and a charge state 310-a, which may represent a negative saturation polarization state and a positive saturation polarization state, respectively. The charge states 305-a and 310-a may be in a physical condition showing a residual polarization (Pr) value, which may refer to the polarization or charge that remains after the external bias (e.g., voltage) is removed. According to the example of the hysteresis curve 300-a, when no voltage difference is applied across the ferroelectric capacitor 240, the charge state 305-a may represent a logical 0, and when no voltage difference is applied across the ferroelectric capacitor 240, the charge state 310-a may represent a logical 1. In some examples, the logic values ​​of the corresponding charge states or polarization states may be inverted or interpreted in an opposite manner to accommodate other schemes of operating the memory cell 205 .

[0095] A logical 0 or 1 can be written to the memory cell by applying a net voltage difference across the ferroelectric capacitor 240 to control the electrical polarization of the ferroelectric material and, therefore, the charge on the capacitor terminals. For example, the voltage 315 can be a voltage equal to or greater than the positive saturation voltage, and applying the voltage 315 across the ferroelectric capacitor 240 can cause charge accumulation until the charge state 305-b is reached (e.g., writing a logical 0). After removing the voltage 315 from the ferroelectric capacitor 240 (e.g., applying a zero net voltage across the terminals of the ferroelectric capacitor 240), the charge state of the ferroelectric capacitor 240 can follow the path 320 shown between the charge state 305-b and the charge state 305-a at zero voltage across the capacitor. In other words, the charge state 305-a can represent a logical 0 state at the equalized voltage across the ferroelectric capacitor 240 that is already positively saturated.

[0096] Similarly, voltage 325 can be a voltage equal to or less than the negative saturation voltage, and applying voltage 325 across ferroelectric capacitor 240 can produce charge accumulation until charge state 310-b is reached (e.g., writing a logic 1). After voltage 325 is removed from ferroelectric capacitor 240 (e.g., applying a net zero voltage across the terminals of ferroelectric capacitor 240), the charge state of ferroelectric capacitor 240 can follow path 330 shown between charge state 310-b and charge state 310-a at zero voltage across the capacitor. In other words, charge state 310-a can represent a logic 1 state at the equalized voltage across ferroelectric capacitor 240 that has been negatively saturated. In some examples, voltage 315 and voltage 325 representing the saturation voltage can have the same magnitude, but opposite polarity across ferroelectric capacitor 240.

[0097] To read or sense the stored state of ferroelectric capacitor 240, a voltage may also be applied across ferroelectric capacitor 240. In response to the applied voltage, the subsequent charge Q stored by the ferroelectric capacitor changes, and the degree of change may depend on the initial polarization state, the applied voltage, the intrinsic or other capacitance on the access line, and other factors. In other words, the charge state or access line voltage resulting from the read operation may depend on whether charge state 305-a or charge state 310-a or some other charge state was initially stored, as well as other factors.

[0098] Hysteresis curve 300-b shows an example of an access operation for reading stored charge states 305-a and 310-a. Figure 2 The plate line 220 and the digit line 215 are depicted as applying a read voltage 335 as a voltage difference. The hysteresis curve 300-b may illustrate a read operation where the read voltage 335 is a positive voltage difference V cap (For example, where V plate -V bottomis positive). A positive read voltage across ferroelectric capacitor 240 may be referred to as a "plate high" read operation, where plate line 220 is initially at a high voltage and digit line 215 is initially at a low voltage (e.g., ground voltage). Although read voltage 335 is shown as a positive voltage across ferroelectric capacitor 240, in an alternative access operation, the read voltage may be a negative voltage across ferroelectric capacitor 240, which may be referred to as a "plate low" read operation.

[0099] A read voltage 335 may be applied across the ferroelectric capacitor 240 while the memory cell 205 is selected (e.g., by Figure 2 210 actuates switch component 245). Upon application of read voltage 335 to ferroelectric capacitor 240, charge may flow into or out of ferroelectric capacitor 240 via associated digit line 215 and plate line 220, and in some examples, different charge states or access line voltages may depend on whether ferroelectric capacitor 240 is in charge state 305-a (e.g., logic 0), charge state 310-a (e.g., logic 1), or some other charge state.

[0100] When a read operation is performed on ferroelectric capacitor 240 at charge state 305-a (e.g., logic 0), additional positive charge may accumulate on ferroelectric capacitor 240, and the charge state may follow path 340 until the charge and voltage of charge state 305-c is reached. The amount of charge flowing through capacitor 240 may be related to an intrinsic or another capacitance (e.g., an intrinsic capacitance of digit line 215, a capacitance of a capacitor or capacitive element coupled to digit line 215, or a combination thereof) of digit line 215 or another access line (e.g., a signal line from digit line 215 opposite an amplifier such as a charge transfer sense amplifier). In a "plate high" read configuration, read operations associated with charge states 305-a and 305-c, or more generally read operations associated with a logic 0 state, may be associated with a relatively smaller amount of charge transfer (e.g., compared to read operations associated with charge states 310-a and 310-c, or more generally, compared to reading a logic 1 state).

[0101] As shown by the transition between charge state 305-a and charge state 305-c, the resulting voltage 350 across ferroelectric capacitor 240 can be a relatively large positive value because the voltage change at capacitor 240 is relatively large for a given change in charge. Thus, after reading a logical 0 in a "plate high" read operation, the plate line voltage V is equal to 310-c in charge state 310-c. PL and V cap (For example, V plate -V bottom) can be a relatively low voltage. Such a read operation may not change the remnant polarization of the ferroelectric capacitor 240 storing the charge state 305-a, so after performing the read operation, if the read voltage 335 is removed (e.g., by applying a zero net voltage on the ferroelectric capacitor 240, by equalizing the voltage on the ferroelectric capacitor 240), the ferroelectric capacitor 240 can return to the charge state 305-a via the path 340. Therefore, performing a read operation with the charge state 305-a with a positive read voltage on the ferroelectric capacitor 240 can be considered a non-destructive read process. In some cases, a rewrite operation may not be required or can be omitted in such a situation.

[0102] When a read operation is performed on ferroelectric capacitor 240 at charge state 310-a (e.g., logic 1), the stored charge may or may not reverse polarity because a net positive charge accumulates on ferroelectric capacitor 240, and the charge state may follow path 360 until the charge and voltage of charge state 310-c are reached. The amount of charge flowing through ferroelectric capacitor 240 may also be related to the intrinsic or another capacitance of digit line 215. In a "plate high" read configuration, read operations associated with charge states 310-a and 310-c, or more generally, read operations associated with a logic 1 state, may be associated with a relatively large amount of charge transfer or a relatively small capacitor voltage V cap associated (eg, compared to read operations associated with charge states 305 - a and 305 - c , or more generally, compared to read operations associated with a logic 1 state).

[0103] As shown by the transition between charge state 310-a and charge state 310-c, in some cases, the resulting voltage 355 can be a relatively small positive value because the voltage change at capacitor 240 is relatively small for a given change in charge. Thus, after reading a logical 1 in a "plate high" read operation, the plate line voltage V PL and V cap (For example, V plate -V bottom )'s difference digital line voltage can be a relatively high voltage.

[0104] The transition from charge state 310-a to charge state 310-d may illustrate a sensing operation associated with a local decrease or local reversal of polarization or charge of ferroelectric capacitor 240 of memory cell 205 (e.g., a decrease in the magnitude of charge Q from charge state 310-a to charge state 310-d). In other words, depending on the characteristics of the ferroelectric material, after performing a read operation, ferroelectric capacitor 240 may not return to charge state 310-a if read voltage 335 is removed (e.g., by applying a net zero voltage across ferroelectric capacitor 240, by equalizing the voltage across ferroelectric capacitor 240). In contrast, when a net zero voltage is applied across ferroelectric capacitor 240 following a read operation of charge state 310-a utilizing read voltage 335, the charge state may follow path 365 from charge state 310-c to charge state 310-d, showing a net decrease in polarization magnitude (e.g., a less positively polarized charge state than initial charge state 310-a, as shown by the charge difference between charge state 310-a and charge state 310-d). Thus, performing a read operation with charge state 310-a with a positive read voltage across ferroelectric capacitor 240 may be described as a destructive read process.

[0105] In some cases, a rewrite operation (e.g., applying voltage 325) may be performed after performing such a read operation, which may cause the memory cell to transition from charge state 310-d to charge state 310-a (e.g., indirectly, such as via charge state 310-b). In various examples, such a rewrite operation may be performed after any read operation, and may also be selectively performed based on certain circumstances (e.g., when the read voltage and the write voltage associated with the detected logic state are opposite). However, in some sensing schemes, the reduced remnant polarization may still be read as the same stored logic state as the saturated remnant polarization state (e.g., supporting detection of a logic 1 based on both charge state 310-a and charge state 310-d), thereby providing a degree of non-volatility to the memory cell 205 relative to the read operation.

[0106] In other examples (e.g., when the ferroelectric material is capable of maintaining polarization in the presence of at least a certain level of depolarizing field, when the ferroelectric material has sufficient coercivity, not shown), after performing a read operation, the ferroelectric capacitor 240 may return to the charge state 310-a if the read voltage is removed, and performing such a read operation in the charge state 310-a with a positive read voltage across the ferroelectric capacitor 240 may be described as a non-destructive read process. In these cases, a rewrite operation may not be required after such a read operation.

[0107] The position of charge state 305-c and charge state 310-c after initiating a read operation may depend on several factors, including the particular sensing scheme and circuitry. In some cases, the final charge may depend on the net capacitance of digit line 215 coupled to memory cell 205, which may include intrinsic capacitance, integrated capacitance, and the like. For example, if ferroelectric capacitor 240 is initially electrically coupled to digit line 215 at 0V, and read voltage 335 is applied to plate line 220, the voltage of digit line 215 may rise when memory cell 205 is selected due to charge flowing from ferroelectric capacitor 240 to the net capacitance of digit line 215. Thus, in some instances, the voltage measured at sensing component 250 may not be equal to read voltage 335 or resulting voltage 350 or 355, but instead may depend on the voltage of digit line 215 after the charge sharing period.

[0108] The position of charge state 305-c and charge state 310-c on hysteresis curve 300-b after initiating a read operation may depend on the net capacitance of digit line 215 and may be determined by load line analysis. In other words, charge states 305-c and 310-c may be defined relative to the net capacitance of digit line 215 or another access line (e.g., a signal line from digit line 215 opposite to the charge transfer sense amplifier). Therefore, the voltage of ferroelectric capacitor 240 after initiating a read operation (e.g., voltage 350 when reading ferroelectric capacitor 240 storing charge state 305-a, voltage 355 when reading ferroelectric capacitor 240 storing charge state 310-a) may be different and may depend on the initial state of ferroelectric capacitor 240. In some instances, the amount of polarization change of ferroelectric capacitor 240 of memory cell 205 caused by the sensing operation may be selected according to a particular sensing scheme. In some examples, a sensing operation with a larger polarization change of the ferroelectric capacitor 240 of the memory cell 205 can be associated with a relatively greater robustness (eg, a wider sensing margin) when detecting the logic state of the memory cell 205 .

[0109] The initial state (eg, charge state, logic state) of the ferroelectric capacitor 240 can be determined by comparing the voltage of the digit line 215 or the signal line (if applicable) resulting from the read operation with a reference voltage (eg, via a reference Figure 2In some instances, the digit line voltage may be determined by reference line 255 as described above. In some instances, the digit line voltage may be the difference between read voltage 335 and the final voltage on capacitor 240 (e.g., (read voltage 335 - voltage 350) when reading ferroelectric capacitor 240 having stored charge state 305-a, or (read voltage 335 - voltage 355) when reading ferroelectric capacitor 240 having stored charge state 310-a). In some instances, the digit line voltage may be the sum of the plate line voltage and the final voltage on ferroelectric capacitor 240 (e.g., voltage 350 when reading ferroelectric capacitor 240 having stored charge state 305-a, or voltage 355 when reading ferroelectric capacitor 240 having stored charge state 310-a).

[0110] In some examples, a read operation of memory cell 205 can be associated with a fixed voltage of digit line 215, wherein the charge state of ferroelectric capacitor 240 after initiating the read operation can be the same regardless of its initial charge state. For example, in a read operation in which digit line 215 and plate line 220 are maintained at a fixed relative voltage that supports read voltage 335, ferroelectric capacitor 240 can advance to charge state 370 for both the case of ferroelectric capacitor initial stored charge state 305-a and the case of ferroelectric capacitor initial stored charge state 310-a. Thus, in some examples, the initial charge state or logic state of ferroelectric capacitor 240 can be determined based at least in part on a charge difference associated with a read operation, rather than using a voltage difference of digit line 215 to detect the initial charge state or logic state. For example, as shown by hysteresis curve 300-b, a logical 0 can be detected based on a charge Q difference between charge state 305-a and charge state 370 (e.g., a relatively small amount of charge transfer), and a logical 1 can be detected based on a charge Q difference between charge state 310-a and charge state 370 (e.g., a relatively large amount of charge transfer).

[0111] In some examples, such detection can be supported by a charge transfer sense amplifier, a cascode (e.g., transistors configured in a cascode arrangement), or another signal generating circuitry between digit line 215 and a signal line coupled to the sense amplifier, where the voltage of the signal line can be based at least in part on the amount of charge transferred by capacitor 240 after initiating a read operation (e.g., where the charge transfer described can correspond to the amount of charge passing through the charge transfer sense amplifier, the cascode, or the other signal generating circuitry). In such examples, the voltage of the signal line can be compared to a reference voltage (e.g., at sensing component 250) to determine the logic state initially stored by ferroelectric capacitor 240, even if digit line 215 remains at a fixed voltage level.

[0112] In some instances where digit line 215 is maintained at a fixed read voltage 335, capacitor 240 may be positively saturated after a read operation, regardless of whether capacitor 240 is initially in charge state 305-a (e.g., logic 0) or initially in charge state 310-a (e.g., logic 1). Thus, after such a read operation, capacitor 240 may be at least temporarily charged or polarized according to a logic 0 state, regardless of its initial or target logic state. Thus, a rewrite operation may be required at least when capacitor 240 is intended to store a logic 1 state, wherein such a rewrite operation may include applying a write voltage 325 to store a logic 1 state, as described with reference to hysteresis curve 300-a. Such a rewrite operation may be configured or otherwise described as a selective rewrite operation, because a rewrite voltage may not need to be applied when capacitor 240 is intended to store a logic 0 state. In some instances, such an access scheme may be referred to as a "2Pr" scheme, in which the charge difference used to distinguish between logic 0 and logic 1 may be equal to twice the remnant polarization of memory cell 205 (e.g., the charge difference between charge state 305-a, a positive saturation charge state, and charge state 310-a, a negative saturation charge state).

[0113] In some sensing schemes, a reference voltage may be generated such that the reference voltage is between possible voltages (e.g., of a digit line 215, a signal line) that may result from reading different logic states. For example, when reading a logic 1, the reference voltage may be selected to be lower than the resulting voltage of the digit line 215 or signal line, and when reading a logic 0, the reference voltage may be selected to be higher than the resulting voltage of the digit line 215 or signal line, or vice versa, depending on the conventional use case. In other examples, the comparison may be made at a portion of the sensing component 250 or associated sense amplifier that is different from the portion coupled to the digit line 215 or signal line, and thus when reading a logic 1, the reference voltage may be selected to be lower than the resulting voltage at the comparison portion of the sensing component 250 or associated sense amplifier, and when reading a logic 0, the reference voltage may be selected to be higher than the resulting voltage at the comparison portion of the sensing component 250 or sense amplifier. During the comparison at the sensing component 250 or sense amplifier, the sensed voltage may be determined to be higher or lower than the reference voltage, and the stored logic state (e.g., logic 0, logic 1) of the memory cell 205 may be determined accordingly.

[0114] During the sensing operation, the signal resulting from reading the various memory cells 205 may be a function of manufacturing, operational or other variations between the various memory cells 205. For example, the capacitors 240 of the various memory cells 205 may have different levels of capacitance, saturation, polarization, or coercivity, such that a logical 0 may be associated with different charge levels of different memory cells 205, and a logical 1 may be associated with different charge levels of different memory cells 205. Furthermore, an intrinsic or another capacitance may be different for different digit lines 215 or for different signal lines in the memory device 110, and may also vary within a digit line 215 from the perspective of different memory cells 205 on the same digit line 215. Thus, for these and other reasons, reading a logical 0 may be associated with different voltage levels of a digit line 215 or signal line for different memory cells 205 (e.g., the resulting voltage 350 may be different for different memory cells 205), and reading a logical 1 may be associated with different voltage levels of different memory cells 205 (e.g., the resulting voltage 355 may be different for different memory cells 205).

[0115] In some examples, a default reference voltage may be provided that is between a statistically average voltage associated with reading a logic 0 and a statistically average voltage associated with reading a logic 1, but the reference voltage may be relatively closer to a voltage resulting from reading one of the logic states of any given memory cell 205. The minimum difference between the voltage resulting from reading a particular logic state (e.g., a statistical value for reading a plurality of memory cells 205 of a memory device) and the associated default reference voltage level may be referred to as a “minimum read voltage difference” or “read margin,” and having a lower minimum read voltage difference or read margin may be associated with difficulty or sensitivity in reliably sensing the logic state of a memory cell 205 in a given memory device 110 or memory die 200.

[0116] The examples of hysteresis curves 300-a and 300-b can illustrate the equalization or normalization characteristics of a memory cell 205 including a ferroelectric capacitor 240 when subjected to a write pulse or a read pulse. However, based on various operating or environmental conditions, the ferroelectric capacitor 240 may be imprinted with a particular logic state, which may refer to various conditions in which the ferroelectric capacitor 240 tends to store one logic state rather than another logic state, is not easily written to a different logic state (e.g., a logic state different from the logic state stored before the write operation), or both. For example, compared to hysteresis curves 300-a and 300-b, the imprinted ferroelectric capacitor 240 may be associated with higher coercivity (e.g., relative to a changed or inverted polarization state), reduced saturation polarization, shallower polarization slope, or other characteristics that may be asymmetric relative to different logic states. A memory array having an imprinted ferroelectric capacitor 240 may be associated with read errors, write errors, or other characteristics that may impair the operation of the memory device or a system including the memory device. According to examples disclosed herein, the imprinted ferroelectric capacitor 240 can be restored (eg, de-imprinted, debonded, repaired, normalized, equalized) using various imprint restoration or repair processes.

[0117] Figure 4A and 4B An example of nonlinear electrical characteristics of an imprinted ferroelectric memory cell with hysteresis curves 400-a and 400-b according to various examples disclosed herein is shown. Hysteresis curves 400-a and 400-b show examples of characteristics of a ferroelectric capacitor 240 that may be shifted due to being imprinted by a logic state or charge state (e.g., imprinting of a logic 1, imprinting of a charge state 310-a), which may be related to a configuration change of an electrostatic domain in the ferroelectric memory cell 205. For example, the shifted characteristics of the hysteresis curves 400-a and 400-b shown by the imprinted hysteresis curve 440 may be due to a condition in which the ferroelectric capacitor 240 has maintained a certain charge state for a relatively long time or is under relatively high temperature conditions, or both (e.g., under static baking conditions).

[0118] Figure 4A An example of a shift from a de-imprinted hysteresis curve 430-a to an imprinted hysteresis curve 440-a is shown, which may correspond to a coercive magnetic shift of the ferroelectric capacitor 240. In some examples, the coercive magnetic shift to the imprinted hysteresis curve 440-a may be associated with an increased resistance to changing polarization during a write operation, such as a common increased resistance to domains changing polarization states (e.g., where domains are able to reverse their polarization, but where such reversal generally requires a relatively high voltage bias).

[0119] For example, according to hysteresis curve 400-a, when the imprinted ferroelectric capacitor 240 storing charge state 310-a is biased with voltage 315 (eg, a write bias associated with writing a logic 0, as shown in reference Figure 3A 315 ), charge may accumulate until charge state 405-a is reached. However, in contrast to charge state 305-b, which may correspond to a saturated condition of the equalized or normalized ferroelectric capacitor 240 in which the polarization of the ferroelectric capacitor is completely reversed, charge state 405-a may not correspond to a saturated condition, but may instead illustrate an instance of a localized polarization reversal in response to write voltage 315. After removing voltage 315 from ferroelectric capacitor 240 (e.g., applying a net zero voltage across the terminals of ferroelectric capacitor 240), the charge state of ferroelectric capacitor 240 may follow path 420-a shown between charge state 405-a and charge state 405-b at zero voltage across the capacitor.

[0120] In various examples, charge state 405-b may have a lower charge than charge state 305-a (e.g., the charge state of memory cell 205 without imprinting corresponds to a logical 0). Although the illustrative example of hysteresis curve 400-a shows charge state 405-b as having a positive net charge Q under various circumstances (e.g., various severity of imprinting, various degrees of coercive magnetic offset, various degrees of polarization reversal among a set of domains of memory cell 205 or ferroelectric capacitor 240), the net charge of charge state 405-b may have positive or negative values. Thus, in various circumstances, such charge states may illustrate storing a logical 0 or a logical 1, or may illustrate a charge state that may be read by a memory device as storing a logical 0 or a logical 1. In other words, due to the shift from the de-imprinted hysteresis curve 430-a to the imprinted hysteresis curve 440-a, applying a voltage 315 to the imprinted memory cell may successfully or fail to write a ferroelectric capacitor imprinted with a logic 1 to a logic 0, or may not support the ferroelectric capacitor being successfully read as a logic 0.

[0121] Figure 4BAn example of a shift from the de-imprinted hysteresis curve 430-b to the imprinted hysteresis curve 440-b is shown, which may illustrate a shift or collapse in the saturation polarization or polarization capacity of the ferroelectric capacitor 240. In some examples, the shift or collapse to the imprinted hysteresis curve 440-a may be associated with some domains in the ferroelectric capacitor being unable to have their polarization reversed during a write operation (e.g., where some of the domains are frozen or trapped in a certain polarization state). In some examples, the coercivity of the domains that are able to reverse their polarization may be substantially the same or similar to the coercivity of the domains in the de-imprinted state, but the capacity for polarization reversal (e.g., at a saturation voltage or bias) may be reduced. In other examples, such imprinting may also be accompanied by various aspects of the shift in the coercivity of those domains that are able to have their polarization reversed (e.g., as shown in reference to Figure 4A described).

[0122] For example, according to hysteresis curve 400-b, when an imprinted ferroelectric capacitor 240 storing charge state 310-a is biased with voltage 315 (e.g., a write bias associated with writing a logic 0, as described with reference to FIG. 3), charge may accumulate until charge state 405-c is reached. However, compared to charge state 305-b, which may correspond to a saturation condition of a de-imprinted (e.g., equalized or normalized) ferroelectric capacitor 240 in which the polarization of the ferroelectric capacitor is fully reversed, in response to write voltage 315, charge state 405-c may correspond to an effective saturation condition of a ferroelectric capacitor having reduced capacity for polarization reversal or unable to support polarization reversal. After removing voltage 315 from ferroelectric capacitor 240 (e.g., applying a net zero voltage across the terminals of ferroelectric capacitor 240), the charge state of ferroelectric capacitor 240 may follow path 420-b shown between charge state 405-c and charge state 405-d at zero voltage across the capacitor.

[0123] In various examples, charge state 405-d may have a lower charge than charge state 305-a (e.g., the charge state of the de-imprinted memory cell 205 corresponds to a logical 0). Although the illustrative example of hysteresis curve 400-b shows charge state 405-b as having a negative net charge Q under various circumstances (e.g., various imprinting severities, various degrees of polarization immobility among a set of domains of memory cell 205 or ferroelectric capacitor 240), the net charge of charge state 405-d may have positive or negative values. Thus, in various circumstances, such charge states may illustrate storing a logical 0 or a logical 1, and may also illustrate charge states that may be read by a memory device as storing a logical 0 or a logical 1. In other words, due to the shift from the de-imprinted hysteresis curve 430-b to the imprinted hysteresis curve 440-b, applying voltage 315 to the imprinted memory cell may or may not successfully write the ferroelectric capacitor imprinted with a logical 1 to a logical 0, or may not support the ferroelectric capacitor being successfully read as a logical 0.

[0124] Although hysteresis curves 400-a and 400-b illustrate simplified examples of mechanisms that may be associated with imprinting in ferroelectric capacitor 240, other mechanisms or conditions, or combinations thereof, may be associated with memory cell imprinting. For example, a memory cell imprinted with a logic 1 may be associated with a reference Figure 3A , 3B , 4A, and 4B, and may have a different charge state after imprinting (e.g., due to charge degradation during imprinting, due to collapse of the saturation polarization of the imprinted logic state or charge state during imprinting itself, due to charge leakage, due to a change in the saturation polarization of the charge state 310-a that may change or reduce when overwritten with a logic 1 state). In another example, the imprinting may change (e.g., widen) the distribution of polarization reversal voltages over a set of domains in the ferroelectric capacitor 240, which may be associated with a shallower slope of Q between different polarization states (e.g., over the polarization reversal region) compared to V cap This may or may not be accompanied by a common shift in coercivity or a change in polarization reversal capacity (e.g., as in Ref. Figure 4A and 4B In some examples, imprinting in ferroelectric capacitor 240 can be associated with other phenomena or various combinations of these and other phenomena.

[0125] In some cases, the footprint of the ferroelectric memory cell 205 (e.g., as indicated by Figure 4A or Figure 4Bor otherwise shown) can be driven by local electrostatic interactions in the memory cell 205 that prevents a domain (e.g., a charge domain) from remaining in a written state. For example, when an appropriate write bias is applied, the imprinted memory cell 205 is able to change its charge state or polarization state. However, when the write bias is removed, the memory cell 205 can return to the imprinted charge state or polarization state, which can be referred to as reverse switching, reduction, or rebound. Therefore, it may be necessary to perform an imprint recovery operation (e.g., in a repair mode, in a maintenance mode, in a recovery mode) to normalize or equalize the memory cells in the memory device to address or mitigate these effects (e.g., return the charge mobility of the memory cell 205 to a normalized or equalized state, return to the hysteresis curve 430 of the removed imprint, restore the residual polarization capacity, normalize or equalize the coercivity).

[0126] In some examples, imprint recovery can be supported by subjecting the memory cell 205 to an opposite state (e.g., opposite to the imprinted state) for a duration long enough to alter the local electrostatic configuration, which restores the memory cell to the imprinted state. For example, recovery can be aided by the duration of exposure to applied bias and charge state switching (e.g., bias switching, charge switching, polarization switching).

[0127] With respect to bias time, mobile charged defects can change the configuration within the memory cell 205 in accordance with the applied bias, which can also be consistent with the desired polarization state. In some examples, such a process may be adjusted with the total accumulated bias time. However, the bias time is only beneficial if the internal electric field is consistent with the applied electric field. For example, a large accumulation of localized charge within the memory cell 205 may shield the applied field and prevent local reconfiguration of defects in some portions of the memory cell 205. Although a unipolar (e.g., non-switching, non-cycling) bias can be used to support imprint recovery and has certain advantages, in some instances, a cycling approach may be more effective.

[0128] With respect to charge state switching, in some instances, repeated switching of an applied bias can provide domains within the memory cell 205 with repeated opportunities to undergo random switching events. For example, for a domain that may or may not undergo a polarization switching event at a given voltage or bias according to a probability distribution, repeated charge switching can provide more opportunities for the domain to switch polarization, thereby increasing the probability that such a switch actually occurs. In some instances, state or bias switching can also increase the internal temperature of the memory cell 205 unit, which can further enhance defect or domain mobility. Therefore, both the increase in temperature and repeated opportunities for repolarization can help the imprint recovery of the memory cell 205.

[0129] Such a mechanism may facilitate a phenomenon referred to as "waking up" or "recovering" from the processed (time zero, initial, starting) imprinted state of the memory cell 205. This mechanism may also facilitate recovery from fatigue, which may be associated with charge domains that symmetrically do not participate in the polarization switching process (e.g., neither participates in polarization switching, either from logic 0 polarization to logic 1 polarization or from logic 1 polarization to logic 0 polarization). In some instances, fatigue recovery may be driven by "waking up" domains within the cell that were not previously involved in polarization switching. Because fatigue may be defined as the loss of polarization signal caused by repeated switching of polarization states, recovery from fatigue may rely on changes in the applied bias (e.g., higher bias or longer pulses compared to typical or initial operating conditions).

[0130] Although certain aspects of memory cell imprinting are described with reference to ferroelectric memory applications, imprint management according to the present disclosure may also be applicable to other memory technologies that experience drift or other shifts in characteristics that may be asymmetric with respect to different logic states. For example, material memory elements such as phase change, resistive, or threshold memory may experience material separation or fixation due to memory cell imprinting (e.g., due to storing a logic state for a duration, due to storing a logic state at a high temperature), where such effects may be associated with storing or reading one particular logic state rather than another logic state (e.g., asymmetrically associated with, drifting toward it). In some instances, in such applications, the imprinted memory cell 205 may be associated with increased resistance to changing from one configurable material property or characteristic to another configurable material property or characteristic, which may correspond to phenomena such as relatively greater resistance to changing from one threshold voltage to another threshold voltage, relatively greater resistance to changing from one resistance to another resistance, and other characteristics.

[0131] In various examples, the footprint restoration operation, which may include signal or pulse cycling or bias time or cycling of access operations, may normalize or equalize characteristics of the material memory element, such as normalizing or equalizing material distribution, moving defects to one end or the other, distributing defects more evenly within the cell, or moving the material memory element for atomic reconfiguration. For example, in certain phase change memory applications, footprint restoration may selectively apply aspects of a seasoning step according to the various techniques for footprint management described herein.

[0132] Figure 5 An example of a system 500 for supporting footprint management of a memory system according to examples disclosed herein is shown. The system 500 may include reference Figure 14, and so on. For example, system 500 may include host device 510 and memory device 540. In some examples, system 500 may also include one or more auxiliary memory devices 590, which may include memory devices having the same or similar functionality as memory device 540 in various examples, or memory devices having different configurations or features. For example, auxiliary memory device 590 may include a memory device configured to provide additional storage capacity to host device 510, a redundant memory device for redundant or backup information storage, a memory device with different access speeds or non-volatility, a memory device with a different storage architecture, a memory device arranged or configured with different roles in a memory hierarchy, and so on.

[0133] In some cases, one or more memory cells of memory array 555 (eg, reference Figure 2 The memory cells 205 described herein may be imprinted, or may be susceptible to being imprinted, which may refer to various conditions in which a memory cell tends to store one logic state rather than another, is less susceptible to being written to a different logic state (e.g., a different logic state than that stored prior to a write operation), or both. In some instances, imprinting itself may degrade or destroy the logic state stored at the memory cell, but such effects may not directly cause problems for the operation of the system 500. For example, imprinting may occur when the system 500 is powered off or inactive, but the system 500 may not be configured to rely on the memory device 540 to provide non-volatile data storage. However, after powering on or booting up the system 500, for example, the host device 510 may attempt to write data to the memory device 540 (e.g., transfer data from a non-volatile storage device, such as a non-volatile auxiliary storage device 590, such as a hard drive or flash memory device, as part of a boot operation, as a BIOS level operation, as part of or prior to loading an operating system), and such a write operation may not be successful due to the imprinted state of the memory array 555. In other words, in some instances or configurations, the basic ongoing operations (eg, writing and reading) of the imprinted memory cells may be more problematic than the loss of information associated with the imprinting itself.

[0134] According to various examples of the described techniques, components of the system 500 may be configured to perform various operations to detect such imprinting, infer such imprinting, mitigate such imprinting, inhibit such imprinting, or recover from such imprinting, which may improve the robustness, accuracy, or efficiency with which the memory device 540, the host device 510, or the entire system 500 may operate in the presence of conditions associated with memory cell imprinting. For example, the memory device 540, the host device 510, or both may perform various operations to detect the presence of imprinting in the memory array 555, or infer the possibility of such imprinting, and the memory device 540 may be correspondingly configured to perform various operations on the memory array 555 in response to such detection or inference. Imprint recovery procedures such as those described herein may include various memory cell biasing or access techniques that are specifically initiated or modified to accelerate equalization or normalization of imprinted memory cells that may exhibit asymmetric characteristics with respect to different logic states. In some cases, the described techniques may also consider various aspects of data retention or operational integrity, including various signaling, data transfer, or operational management between the host device 510 , the memory device 540 , and any auxiliary memory devices 590 .

[0135] The described footprint management techniques may employ various distributions of detection, calculation, evaluation, and operation between the memory device 540 and the host device. In some examples, the memory device 540 may include chip-level or transistor-level circuitry (e.g., of the local memory controller 265, of the device memory controller 155, of the local memory controller 165) configured to support various footprint management techniques. Additionally or alternatively, the memory device 540 may include an onboard processor or integrated processor (e.g., a processor with integrated RAM, a processor with integrated RAM controller) coupled to an associated memory die and configured or programmed to support various footprint management techniques. Additionally or alternatively, the host device 510 may include a processor, a controller, or another circuitry configured or programmed to support various footprint management techniques, which may include various signaling to or from the memory device 540 or any auxiliary memory device 590.

[0136] In some examples, one or more components of the system 500 may be configured to characterize the severity (e.g., magnitude, degree) or directionality of the imprint (e.g., whether the imprint is more associated with one logical state than with another logical state, or is more sensitive to one logical state than to another logical state, whether the imprint is asymmetric) and perform a footprint recovery operation that is adjusted or selected according to the characterized severity or direction. Additionally or alternatively, the footprint recovery operation may be customized by the system 500 for a specific operating condition of the memory device 540, the host device 510, or the entire system 500, such as an operating mode or environmental condition, which in some examples may be based at least in part on signaling or operational negotiation between the memory device 540 and the host device 510. Additionally or alternatively, the footprint recovery operation may be based on various operating modes, permissions, approvals, or prohibitions, which may be based at least in part on signaling or operational negotiation between the memory device 540 and the host device 510.

[0137] The host device 510 may be a host device or a reference device. Figure 1 The host device may include a host device interface 515, a host device controller 520, and a footprint manager 525. Although the host device interface 515, the host device controller 520, and the footprint manager 525 are shown as separate components, one or more of the described components, or portions thereof, may be collectively or generally described as components, controllers, processors, or circuitry configured to perform the various techniques described herein.

[0138] The host device interface 515 may be a reference Figure 1 The described examples of one or more channels 115 may also be associated therewith in other ways. For example, the host device interface 515 may include a transceiver that supports bidirectional signaling or communication (e.g., commands, status indications, data, and other information) with the memory device 540 (e.g., with the memory interface 545). In some examples, the host device interface 515 may also provide power to the memory device 540 (e.g., from a battery of the host device 510, from a power supply of the host device 510, from a power supply wired to the host device 510).

[0139] The host device controller 520 may be a processing element in the host device 510 that exchanges information (e.g., application data, user data) with the memory device 540. For example, the host device controller 520 may issue a read command and receive data from the memory device 540 in response to the read command, or the host device controller 520 may issue a write command to the memory device 540 accompanied by or otherwise associated with write data provided to the memory device 540. The host device controller 520 may also control various other aspects of the operation of the host device 510. For example, the host device controller 520 may manage various operating modes or configurations of the host device 510, may control various information or control signaling between the host device 510 and the memory device 540, or control various operations of the host device 510 in response to signaling from the memory device 540.

[0140] The footprint manager 525 may be configured to perform various operations related to footprint detection or footprint recovery described herein, or to control or modify other operations of the host device 510 that are otherwise related to footprint management of the memory device 540. In some examples, this approach may support offloading aspects of footprint management from the memory device 540 to the host device 510, which may support relatively lean memory architectures (e.g., having relatively limited onboard processing power or performance), enable support for relatively complex technologies by enhancing the capabilities of the host device 510, and other benefits.

[0141] In some examples, the footprint manager 525 can detect various conditions that can be associated with possible imprinting of the memory array 555 (e.g., temperature, time, failure of the host device 510, access patterns that can inadvertently or maliciously produce imprinting, blue screen events). In response to such detection, the footprint manager 525 can issue a command to the memory device 540 to perform an imprint detection procedure (e.g., for the memory device 540 to directly evaluate whether the memory array 555 has been imprinted), or to the memory device 540 to perform an imprint recovery procedure (e.g., regardless of whether the memory device 540 detected imprinting). In some examples, such commands can be accompanied by information for triggering such commands, an indication of the severity detected in the condition, an indication of the condition that the memory device 540 can use to identify or select an imprint recovery procedure, or an indication of how aggressively the imprint recovery should be performed. In some examples, footprint manager 525 may support selection of a footprint recovery method based on system status, user demand, or other parameters, and may indicate the selection to memory device 540 or may provide information to memory device 540 so that memory device 540 may make such a selection.

[0142] In some examples, the footprint manager 525 may authorize or approve the memory device 540 to enter a recovery mode, which may or may not support ongoing data operations (e.g., read operations, write operations, data exchanges between the host device 510 and the memory device 540) during the recovery mode. In some examples, the footprint manager 525 may receive an indication that the memory device 540 is performing a recovery operation, and may suspend access operations of the memory device 540 or may perform access operations of the memory device 540 at a slower rate or in an otherwise degraded or less efficient mode. In some examples, the footprint manager 525 may deny a request by the memory device 540 to perform a footprint detection or recovery operation, or may prevent or disallow such operations (e.g., when the host device 510 is operating in a mode that requires certain performance from the memory device 540, when the memory device 540 may perform such operations by default but the host device 510 deems such operations to be disabled).

[0143] In some examples, the footprint manager 525 can receive an indication from the memory device 540 that the memory array 555 is stamped or may be stamped, and the footprint manager 525 can issue or initiate (e.g., via the host device controller 520) a pattern of access commands specifically configured to mitigate the footprint of the memory array 555. For example, in response to such an indication of detected or inferred footprint of the memory array, the footprint manager 525 can issue read, write, or refresh commands associated with a pattern of logic states, such as a solid pattern of logic states or write operations that cycle or alternate between other patterns of logic states (e.g., according to alternating logic states, according to an alternating checkerboard pattern, according to inverted write-back operations).

[0144] The system may also include a memory device 540, which may be a reference Figure 1 and 2 An example of a memory device 110, memory die 160, or memory die 200 is described. Memory device 540 may include a memory interface 545, a memory controller 550, one or more memory arrays 555 (e.g., memory array 555-a and memory array 555-b), a footprint detection component 560, a footprint recovery component 565, and an error correction code (ECC) component 570. Although memory interface 545, memory controller, footprint detection component 560, footprint recovery component 565, and ECC component 570 are shown as separate components, one or more of the described components, or portions thereof, may be collectively or generally described as a component, controller, processor, or circuitry configured to perform the various techniques described herein.

[0145] The memory interface 545 may be a reference Figure 1115. The memory interface 545 may be associated with or otherwise communicate with the described examples of one or more channels 115. For example, the memory interface 545 may include a transceiver that supports bidirectional signaling or communication (e.g., commands, status indications, data, and other information) with the host device 510 (e.g., with the host device interface 515). In some examples, the memory interface 545 may also receive power from the host device 510.

[0146] The memory controller 550 may be a processing element in the memory device 540 that exchanges information (e.g., application data, user data) with the host device 510. For example, the memory controller 550 may receive a read command and transmit responsive data to the host device 510 in response to the read command, or the memory controller 550 may receive a write command from the host device 510 accompanied by or otherwise associated with write data provided from the host device 510. The memory controller 550 may also control various other aspects of the operation of the memory device 540. For example, the memory controller 550 may manage various operating modes or configurations of the memory device 540, may control various information or control signaling between the memory device 540 and the host device 510, or control various operations of the memory device 540 in response to signaling from the host device 510.

[0147] In some examples, the memory controller 550 may receive commands from the memory interface 545, process the commands, and execute the commands (e.g., by interacting with the memory array 555 or other aspects of the memory device 540). The memory controller 550 may be configured in various ways and may be an instance of the device memory controller 155, the local memory controller 165, the local memory controller 265, or a combination thereof, or otherwise include them, or refer to their functionality. In some examples, the memory controller 550 may include hardware or circuitry (e.g., transistor-level circuitry) configured for various techniques for combinational logic, or may be a separate processing component or chip in the memory device 540 that interfaces with the memory array 555.

[0148] The memory array 555 may be a reference Figure 1 and 2 An example of a memory array 170 is described. In some examples, the memory array 555 can include a memory cell array 205 that includes ferroelectric capacitors as corresponding memory storage elements. However, the described footprint management techniques can be performed using other types of memory arrays 555, such as memory arrays having material storage elements that store logic states based on variable and configurable material properties.

[0149] Footprint detection component 560 may be configured to perform various operations to detect or predict the presence of memory cell footprints in memory array 555. In some examples, footprint detection component 560 may operate independently of footprint manager 525 or in the absence of footprint manager 525 to support various footprint detection techniques within memory device 540. For example, footprint detection component 560 may operate autonomously without coordinating footprint detection techniques with host device 510 (e.g., using processing capabilities on a die or other integrated circuit system or memory device 540). In some examples, this approach may facilitate footprint detection techniques that benefit from a deeper understanding of chip-level conditions or other relatively direct understanding of operating conditions (e.g., without the need to express such understanding to the host device), and may support memory device 540 being agnostic to different host devices of different types or capabilities. In other examples, footprint detection component 560 may operate based on signaling exchanged with footprint manager 525 in a coordinated footprint management system, which may support footprint management coordination between host device 510 and memory devices. In some examples, this approach may support offloading aspects of footprint management from memory device 540 to host device 510, which may support relatively streamlined memory architectures (e.g., having relatively limited onboard processing power or performance), enable support for relatively complex technologies by enhancing the capabilities of host device 510, and other benefits.

[0150] The footprint detection component 560 can support various detections that support the selective or adjusted application of footprint recovery techniques. For example, although certain aspects of footprint recovery may generally benefit the memory device, performing the recovery procedure may require a certain amount of time or other system resources, which may affect the performance or operation of the memory device 540 or the host device 510. In some examples, the footprint recovery technique may have harmful effects, such as accelerated fatigue or other wear mechanisms, which need to be balanced with the presence or sensitivity of the footprint. Therefore, for these and other reasons, the recovery procedure may be selectively performed for the presence of a detected or inferred footprint, or selectively blocked based on the absence of a detected or inferred footprint. Therefore, the footprint detection component 560 can be configured to support determining when to perform the recovery procedure, which can provide efficiency and reliability benefits, as well as other benefits that can be appreciated by those skilled in the art.

[0151] In some examples, the footprint detection component 560 may execute or manage (e.g., cause the memory device 540 to execute, cause the footprint detection component 560 to execute) one or more footprint detection procedures to determine whether the memory array 555 and / or the memory cells of the memory array 555 are operating within one or more specifications (e.g., whether a recovery operation is performed). In some cases, the footprint detection component 560 may determine that the memory array 555 is operating within one or more specifications and send an indication to another component of the memory device 540 or to the host device 510 that the memory device 540 is operating properly. In other cases, the footprint detection component 560 may determine that the memory array 555 is not or may not be operating within one or more specifications (e.g., footprint has occurred, footprint has been detected, footprint has been predicted), and a recovery procedure may be initiated. The footprint detection component 560 may execute the footprint detection procedure (e.g., autonomously, or in response to a command from the host device 510) on a scheduled (e.g., periodic) or event-driven basis (e.g., in response to detecting one or more triggering events).

[0152] In some examples, the footprint detection component 560 can detect various conditions that can be associated with possible imprinting of the memory array 555 (e.g., temperature, time, failure of the memory device 540, access patterns that can produce footprints accidentally or maliciously). In response to such detection, the footprint detection component 560 can issue a command to the footprint recovery component 565 to initiate a recovery operation, or can trigger other (e.g., more deterministic, more complex) aspects of footprint detection performed by the footprint detection component. In some examples, such a command or trigger can be accompanied by information for initiating or adjusting the operation, an indication of the severity detected in the condition, an indication of the condition that the footprint recovery component 565 can use to select a footprint recovery procedure, or an indication of how aggressively the footprint recovery should be performed. In some examples, the footprint detection component 560 can indicate (e.g., to the footprint recovery component 565, to the memory controller 550) one or more sections of the memory array 555 on which to perform the footprint detection procedure.

[0153] In some examples, footprint detection component 560 can support footprint recovery component 565 in selecting a footprint recovery method based on system status, user requirements, or other parameters, such as providing information to footprint recovery component 565 so that footprint recovery component 565 can make such a selection. In some examples, footprint detection component 560 can provide such information to footprint manager 525 so that footprint manager 525 can make such a selection.

[0154] In some examples, footprint detection component 560 can signal to host device 510 the presence or prediction of a footprint in memory array 555, which can indicate or otherwise be interpreted as a request for host device 510 to initiate a recovery operation, a request for host device 510 to approve a recovery operation (e.g., a signaling approval for footprint recovery component 565 to proceed with footprint recovery), an indication that memory device 540 will or is in the process of performing a recovery operation, an indication that memory device 540 may or will be temporarily unavailable for access operations or may be used for access operations at a reduced rate or performance, and other interpretations.

[0155] In some cases, footprint detection component 560 may autonomously (e.g., unilaterally, without explicit commands from host device 510) determine to perform a footprint detection procedure, which may be associated with memory device 540 actively or preemptively performing a detection or recovery operation (e.g., in a set of operations that is transparent to host device 510). In some examples, footprint detection component 560 may determine to perform a footprint detection procedure in response to a command received from host device 510 (e.g., from footprint manager 525). In some cases, the command may be received by memory device 540 as part of a boot procedure (e.g., as part of boot or initialization signaling).

[0156] In some examples, footprint detection component 560 may perform detection operations as part of a boot process (e.g., as part of a power-on self-test (POST)), initialization of memory device 540 (e.g., first power-on of memory device 540), or other operating conditions. In some examples, footprint detection component 560 may perform such operations before data is loaded into memory array 555 (e.g., before an operating system is loaded), which may include inhibiting or caching access commands from host device 510. In some examples, footprint detection component 560 may perform detection operations while data is stored in memory array 555, and footprint detection component 560 may support various coordination with host device 510 or other components of memory device 540 to support various data retention, redundancy, or integrity techniques described herein.

[0157] The footprint detection component 560 can support various techniques for determining the presence or likelihood of footprints in the memory array 555. For example, the footprint detection component 560 can know that the memory array 555 is storing logic states that may be imprinted, and detect or monitor a temperature or duration that may indicate a static bake. In another example, the footprint detection component can monitor access operations (e.g., performed by the memory controller 550), and can be configured to detect inadvertent or malicious access conditions that can produce footprints, such as adverse access patterns, adverse biases, or other conditions that may be associated with asymmetrically altering memory cells in the memory array 555 relative to different logic states. Thus, the footprint detection component 560 can be configured to support initiating or triggering various operations in the system 500 based on the prediction of footprints or other adverse conditions, without having to directly detect the footprints themselves.

[0158] Additionally or alternatively, the imprint detection component 560 may perform various operations intended to directly detect the presence or extent of imprints in the memory array 555. In one example, an imprint detection procedure that may be performed or managed by the imprint detection component 560 may include writing a first set of logic states to a subset of memory cells of the memory array 555. In some cases, prior to writing the first set of logic states, the memory device 540 may write a specific (e.g., known, configured, forced) pattern of logic states to the subset of memory cells, and the pattern may be configured to support subsequent operation of the imprint detection procedure. In other cases, the logic states stored by the subset of memory cells may not be a priori forced and, therefore, may be random (e.g., unknown, not specifically configured to support the imprint detection procedure) from the perspective of the imprint detection procedure.

[0159] The memory device 540 may be configured (e.g., via operation of an imprint detection component) to read the subset of memory cells to obtain a second set of logic states and determine a first number of mismatches or errors associated with the second set of logic states. In some cases, the memory device may compare the logic state read from each memory cell (e.g., from the second set of logic states, the read or detected logic state) with the logic state that has been written to each respective memory cell (e.g., from the first set of logic states, the target logic state of a previous write operation). For each instance in which the read or detected logic state is different from the target logic state of a previous write operation, a mismatch or error may be counted. In one example, an imprinted memory cell may remain in a first state (e.g., corresponding to a detected logic 1) even after an attempt is made to write the memory cell to a different state (e.g., corresponding to a target logic 0). Based on such differences, the memory device 540 (e.g., the imprint detection component 560) may determine or infer that imprinting has occurred or may have occurred on the memory cell. When the presence, number, or rate of mismatches or errors meets the threshold, the memory device 540 may proceed with a recovery operation (e.g., a recovery operation of the footprint recovery component 565, such as triggered or initiated by the footprint detection component 560) based on the mismatch or error between the second set of logic states and the first set of logic states.

[0160] The footprint detection component 560 may employ various techniques to determine and evaluate the number of mismatches or errors in such operations. For example, the memory device 540 (e.g., a sensing component of the memory device 540) may be configured with a default or operating reference voltage for determining the logic state of the memory cells under normal operating conditions, such as when reading application data from the memory array 555. As an example, the memory device 540 (e.g., the footprint detection component 560) may obtain a second set of logic states by reading the memory cells using the default reference voltage and comparing the resulting number of mismatches or errors to a threshold value.

[0161] Additionally or alternatively, the memory device 540 (e.g., the footprint detection component 560) may obtain a second set of logic states by reading the memory cells using a reference voltage that is lower or higher than a default reference voltage, which may be referred to as an offset reference voltage. In some cases, the offset reference voltage may be associated with an expected number of mismatches or errors (e.g., an expected number of errors that occur due to reading using a reference voltage that is lower or higher than the default reference voltage, even if there is no footprint). The memory device 540 (e.g., the footprint detection component 560) may compare the measured number of errors observed when reading the subset of memory cells using the offset reference voltage and the expected number of errors associated with the offset reference voltage. In some cases, the footprint detection component 560 may determine whether to perform a recovery procedure based on this comparison. In some cases, two offset reference voltages may be used to obtain two sets of logic states. For example, the first offset reference voltage may be lower than the default reference voltage, and the second offset reference voltage may be higher than the default reference voltage.

[0162] Additionally or alternatively, the memory device 540 (e.g., the footprint detection component 560) may use the difference between the number of mismatches or errors observed when reading using two different reference voltages to determine whether a recovery procedure should be performed. For example, the second set of logic states and the third set of logic states may be obtained by reading the memory cells using two corresponding offset reference voltages that are both higher or both lower than the default reference voltage. The measured difference (e.g., subtraction), slope, or other type of gradient (e.g., linear gradient, nonlinear gradient such as nonlinear regression) may be determined based on a first number of mismatches or errors associated with reading the subset of memory cells at a first offset reference voltage and a second number of errors associated with reading the subset of memory cells at a second offset reference voltage. An expected difference, slope, or other corresponding type of gradient may be defined based on a first expected number of errors resulting from reading using the first offset reference voltage and a second expected number of errors resulting from reading using the second offset reference voltage. The measured difference, slope, or other type of gradient may be compared to an expected counterpart to determine whether a footprint has occurred or whether a recovery procedure should be performed.

[0163] These examples are for illustrative purposes, and the footprint detection component 560 may perform one or more additional analyses based on the number of mismatches or errors (e.g., comparing the number of mismatches or errors to a threshold, comparing or otherwise analyzing the number of mismatches or errors relative to another number of mismatches or errors determined using another reference voltage) to determine whether to perform a recovery operation.

[0164] The memory device 540 may also include an ECC component 570 configured to support one or more ECC operations at the memory device 540. In various examples, the ECC component 570 may be configured to correct single bits per word or page, double bit errors of a word or page, or other configurations. In some examples, the footprint detection component 560 may be coupled to the ECC component 570, and the footprint detection component 560 may use information from the ECC component 570 to determine whether to perform a recovery procedure. For example, the footprint detection component 560 may determine to perform a footprint detection procedure when the number of mismatches or errors between the written and read logical states fails to meet a threshold, and in some cases, the threshold may be based on the number of errors that can be corrected by the ECC component 570, or the rate at which errors can be corrected by the ECC component 570. In this regard, the footprint detection component 560 may set a threshold for initiating a recovery operation to be at or above the number of errors that can be corrected by the ECC component 570 (e.g., indicating a relatively severe condition). In some cases, the threshold for initiating a recovery operation may be zero errors (e.g., a recovery operation may be initiated as soon as a mismatch is detected).

[0165] In some examples, footprint detection component 560 may be configured to set a threshold for initiating a recovery operation below the number of errors that can be corrected by ECC component 570, which may indicate a less severe or moderately severe condition. For example, it may be assumed that ECC component 570 handles some failures according to the capabilities of the employed ECC scheme, but if the number of errors or the rate at which ECC component 570 handles errors reaches a threshold level within this capability, then footprint detection component 560 may be configured to preemptively initiate a recovery operation (e.g., before the ECC component has caught up with the errors), which may include triggering a relatively less severe or moderate level of recovery operation.

[0166] In some instances, multiple error thresholds or error rate thresholds at the ECC component 570 may be used as part of the recovery decision. For ECC correction rates below a minimum threshold, a recovery operation may not be initiated. For ECC correction rates above a low threshold, there may be a "low severity" recovery operation, such as recovery during operation (e.g., background recovery, maintenance recovery). For ECC correction rates above a high threshold, or for functional failures that exceed the ECC correction capability, there may be a "high severity" recovery operation, such as a discrete recovery event. In some instances, such techniques may be supported by a state machine method (e.g., of the memory controller 550, of the footprint detection component 560), where if a counter exceeds a threshold, various transitions may be initiated. In some instances, such techniques may include real-time rate determination in operation based on combinatorial logic techniques (e.g., chip-level or array-level techniques applied at the memory device 540).

[0167] In one example, the ECC rate can be defined as the number of correctable ECC errors divided by the access count (e.g., time derivative, count derivative), taking into account the capabilities or errors at the ECC component. In some examples, the ECC rate can be calculated or otherwise considered in absolute terms, such as directly dividing the determined number of ECC errors by the access count. In some examples, the ECC rate can be calculated or otherwise considered as an approximate derivative (e.g., a counter right shift after overflow) to be incorporated into the combinatorial logic. In some examples, the memory device 540 may not be configured to perform an interrupt and terminate the system. Therefore, the techniques described in consideration of the ECC rate can use actual (e.g., determined) ECC counts or rates, and the actual ECC counts or rates can be added to the background counts or rates (e.g., nominal ECC counts or rates, threshold ECC counts or rates, or normalized ECC counts or rates) that the ECC component 570 can detect. When such addition causes a counter overflow, the corresponding rollback of the counter can be used as an indication of a difference relative to an expected characteristic (e.g., detection or prediction of a memory cell footprint).

[0168] In an illustrative example, the expected or threshold number of failures may be 10 words corrected over a certain number of access operations (e.g., one million starts, one billion starts, ten billion starts). In the case where the ECC component 570 corrects 35 words over the same number of access operations, the errors may be within the capabilities of the ECC component, but the drift or increase beyond the expected may be used (e.g., by the imprint detection component 560) to take preventive measures (e.g., initiate a recovery operation) to reduce the correction load of the ECC component 570.

[0169] In various examples, the number of errors or error rate at the ECC component 570 can include the total amount or rate of corrections, the number or rate of corrections associated with a logical state (e.g., errors of a logical 0, errors of a logical 1) considered independently, or the number or rate of corrections associated with a logical state (e.g., errors of a logical 0, errors of a logical 1) considered in isolation. In other words, the ECC component 570 can support information related to the directionality of the number or rate of errors (e.g., relative to different logical states). Thus, according to various examples of the described techniques, the footprint detection component 560, the footprint recovery component 565, the footprint manager 525, or various combinations thereof can consider error or mismatch directionality to determine one or more parameters related to footprint management.

[0170] The footprint recovery component 565 may be configured to perform various operations to equalize or normalize the memory cells of the memory array 555 (e.g., recover from actual or possible memory cell footprint, mitigate the effects of conditions associated with memory cell footprint). For example, when one or more of the memory array 555 employs a ferroelectric memory architecture, the footprint recovery component 565 may perform or control operations configured to shift the memory cells from the imprinted hysteresis curve 440 to or toward the removed hysteresis curve 430. In some examples, the footprint recovery component 565 may operate independently of or in the absence of the footprint manager 525 to support various techniques for footprint recovery within the memory device 540. For example, the footprint recovery component 565 may operate autonomously without coordinating footprint recovery techniques with the host device 510 (e.g., using processing capabilities on a die or other integrated circuit system or memory device 540). In some examples, this approach can facilitate footprint recovery techniques that benefit from a deeper understanding of chip-level conditions or other relatively direct understanding of operating conditions (e.g., without the need to express such understanding to the host device), and can support memory device 540 being agnostic to different host devices of different types or capabilities. In other examples, footprint recovery component 565 can operate based on signaling exchanged with footprint manager 525 in a coordinated footprint management system, which can support footprint management coordination between host device 510 and memory devices. In some examples, this approach can support offloading aspects of footprint management from memory device 540 to host device 510, which can support relatively lean memory architectures (e.g., with relatively limited onboard processing power or performance), enabling relatively complex technologies to be supported by enhancing the capabilities of host device 510, among other benefits.

[0171] In some examples (e.g., in response to a trigger or other information from the imprint detection component 560 or the imprint manager 525, intended to recover memory cells of the memory array 555), the imprint recovery component 565 can be configured to apply or otherwise control various biasing techniques, such as applying one or more voltages or voltage pulses on the memory cells, or performing multiple access operations (e.g., multiple read operations, multiple write operations, multiple read and write operations) on the memory cells of the memory array 555. In various examples, such biasing can be performed in a maintenance or recovery mode that may or may not be associated with a particular data access (e.g., as requested or commanded by the host device 510, on a scheduled basis, based on detection or prediction that imprinting has occurred), or in an imprint maintenance or recovery mode that modifies parameters of access operations (e.g., read operations, write operations, refresh operations) while supporting data transfer in the imprint maintenance or recovery mode. In some cases, the parameters can be permanently or indefinitely modified to support imprint recovery or prevention (e.g., the duration or magnitude of the access voltage can be modified).

[0172] The operation of the footprint recovery component 565 can be initiated, triggered, adjusted, or otherwise controlled or modified by various signaling (e.g., from the footprint detection component 560, from the footprint manager 525). For example, the footprint recovery component 565 can start the recovery operation based on the initialization, permission, authorization signaling that can be generated within the memory device 540 or within the host device 510. In some examples, various footprint management components (e.g., of the memory device 540, of the host device 510) can detect various conditions related to the recovery operation, and the footprint recovery component 565 can adjust or adjust the recovery operation for different environmental (e.g., system or product) conditions or constraints, different unit technology sensitivities, and other factors. Additionally or alternatively, the footprint recovery component 565 can perform footprint recovery operations that are adjusted or selected based on the characterized severity or direction of the imprint, the specific operating conditions of the memory device 540, the host device 510, or the entire system 500, or based on various operating modes, permissions, approvals, or prohibitions.

[0173] In some examples, footprint recovery component 565 can initiate operation based on memory device 540 powering on or initializing for a boot operation of host device 510. In some examples, the operation of footprint recovery component itself can be part of a boot cycle, and if the recovery operation is unsuccessful, memory device 540 can signal host device 510 to try another memory device (e.g., auxiliary memory device 590) for supporting the ongoing operation. Additionally or alternatively, memory device 540 can provide signaling to the host device indicating that memory device 540 needs to be replaced (e.g., a fault signal, a fault indicator light).

[0174] In some examples, footprint recovery component 565 can send one or more indications related to a footprint recovery procedure (e.g., indicating the start of a footprint recovery operation or the end of a recovery operation) to host device 510. In some examples, footprint recovery component 565 can otherwise provide signaling that memory device 540 or one or more memory arrays 555 of memory device 540 is unavailable for access operations.

[0175] In some examples, the system 500 (e.g., the host device interface 515, the memory interface 545) may be configured for signaling between the host device 510 and the memory device 540 to support various operations or modes of operation. In some examples, such system or controller signals may be set external to the memory device 540 or external to the memory array 555 and may control certain aspects of the recovery process. For example, a "recovery required" signal may be configured (e.g., by the host device 510, by the memory device 540) to signal, request, or otherwise trigger various footprint recovery operations described herein. In some examples, the "recovery required" signal may be enabled as a default or initial configuration or pre-configuration so that footprint recovery operations are preemptively performed at the initial startup of the system 500 or prior to shipment to a consumer (e.g., according to an early life recovery or "wake-up" operation). In another example, when footprint detection is performed by the host device 510, a "controller specified recovery" signal may be configured by the host device 510 to schedule footprint recovery operations to be performed by the memory device 540.

[0176] Additionally or alternatively, other signaling may be provided to refine various aspects of footprint management in system 500. In some instances, a "disable resume" signal may be configured (e.g., by host device 510, by memory device 540) to override internal resume monitoring (e.g., of memory device 540, memory array 555) and prevent resume operations, such as when memory device 540 requires specific performance. In some instances, a "force resume" signal may be configured (e.g., by host device 510, by memory device 540) to override or otherwise override internal resume monitoring and initiate resume operations. In some instances, a "pause resume" signal may be configured (e.g., by host device 510, by memory device 540) to temporarily override internal resume operations, such as to support temporary high-bandwidth data transfer situations, a temporary desire to reduce power consumption (e.g., low battery), or other conditions. In some examples, a "resume time" signal may be configured (eg, by host device 510, by memory device 540) to specify a time available for a resume operation (eg, for a discrete resume event on memory array 555 or a subset thereof).

[0177] System 500 may be configured to support a variety of footprint recovery techniques, which may be generally characterized as discrete recovery events across the entire memory array 555, recovery operations during operation, or modifying other operations on the memory array 555 for the purpose of footprint recovery. Although certain examples may be described in the context of one of these characterizations, such descriptions are provided as non-limiting examples for illustrative purposes, and various other examples or combinations may also be used in accordance with the described techniques.

[0178] In a first set of examples, footprint management can include various techniques for performing discrete footprint recovery across the entire memory array 555. For example, some aspects of footprint management can be included in monitoring that is run when the system 500 or host device 510 is booted or powered on. In some examples, a flag can be set before or when the memory device 540 is powered off as an indication that a footprint may have occurred or should trigger the footprint management techniques described herein. Thus, the system 500 can be configured to actively attempt to recover from or mitigate the effects of a footprint.

[0179] In some examples, techniques for performing discrete footprint recovery may operate on the entire memory array 555 or a limited subset of the memory array 555 (e.g., in response to a trigger). Some techniques may interfere with normal operation of the system 500 and may include signaling or other operational understandings between the host device 510 and the memory device 540 (e.g., "suspend" signaling, operation inhibition signaling, suspend start operation). Thus, in some examples, performing discrete footprint recovery may be performed before the system 500 regains normal functionality, but including such operations (e.g., in a preventative manner) may prevent the system 500 from malfunctioning solely due to the effects of the footprint.

[0180] In some examples, discrete footprint management techniques may include assessing whether memory array 555 or a subset of memory array 555 passes or fails a monitoring step, such as a retest operation following a footprint restore bias or access. The retest operation may include or be associated with the option of initiating additional footprint restore bias or access, signaling of status from memory device 540 to host device 510 (e.g., to footprint manager 525), or both.

[0181] In one example, a full array recovery may be triggered or initiated by a boot sequence imprint monitoring or other functional failure (e.g., a boot failure, a blue screen event, a high severity imprint monitoring failure). In another example, a full array recovery may be triggered or initiated by an inability to correct non-volatile data using ECC during recovery, in which case the memory device 540 or the host device 510 (e.g., the imprint manager 525) may generate a signal to the system 500 that the data in the memory array 555 needs to be replaced from a storage device (e.g., the auxiliary memory device 590) and initiate a clean restart.

[0182] When the system 500 is configured to select from a variety of options for imprint recovery methods, in some cases, the option of performing discrete restore events across the entire memory array 555 may be preferred or advantageous. For example, discrete restore events may be configured to provide relatively strong restores in a relatively short amount of time. However, such techniques may be associated with relatively greater power consumption, may suspend certain aspects of memory operations while restore is performed, may be associated with causing fatigue or accelerating other degradation, or may have other tradeoffs. Therefore, in some cases, certain aspects of discrete restore across the entire memory array 555 may be reserved for medium or high severity imprints (e.g., when a low severity imprint is detected or inferred, discrete restore events across the entire memory array 555 are disabled).

[0183] In some cases, when it is determined that the operating temperature of the memory device 540 or the host device 510 is relatively low (e.g., at or below a temperature threshold), discrete restore events across the entire memory array 555 may be applied, as less aggressive imprint restoration may be ineffective under these conditions where charge mobility or other responses to imprint restoration are impaired. In other words, when the operating temperature of the host device 510 or the memory device 540 is higher, less aggressive imprint restoration techniques may be appropriately effective in normalizing or equalizing memory cells. The selection of such restoration techniques may also take into account power supply or power availability, as discrete restore operations across the entire memory array 555 may only be selected, available for selection, or enabled under certain power conditions (e.g., battery charge is at or above a threshold, power consumption of the system 500 is at or below a threshold, the host device 510 or the system 500 is plugged in).

[0184] In some examples, the described techniques for discrete footprint recovery across the entire memory array 555 may be supported by various signaling between the host device 510 and the memory device 540. For example, by being supported by such signaling, components of the system 500 may understand that operations should be suspended or inhibited during footprint recovery. In some examples, the signaling may include or be accompanied by negotiation of available time (e.g., requested by the memory device 540, granted by the host device 510, or otherwise signaled). In some examples, such recovery techniques may include or be triggered by relatively complex footprint detection techniques, such as detection at the memory array 555 using multiple reference voltages, performing slope or gradient calculations or analysis, or other techniques that provide greater observability of footprint conditions at the memory array 555.

[0185] In a second set of examples, footprint management may include various techniques for performing footprint recovery during operation of the memory device 540 or memory array 555 (e.g., in a maintenance mode). The memory array 555 may continue to operate during such techniques, but various aspects of cell characteristics may be detected (e.g., detected or inferred presence of footprints, detection of inadvertent or malicious access operations that may cause footprints or other cell-level degradation or failures) so that recovery operations may be performed during operation to mitigate, mitigate, or prevent footprints. In some examples, performing footprint recovery during operation may reduce performance (e.g., increase power consumption, reduce bandwidth, increase latency), but such reduction may be within allowed specifications. Thus, footprint recovery during operation of the memory device 540 may be used to provide recovery when a low to moderate amount of recovery is needed but requires normal operation of the device and reduced performance of the memory device 540 or host device 510 is acceptable.

[0186] In some examples, footprint recovery during operation can be associated with a monitoring scheme having multiple thresholds, thereby supporting relatively less aggressive recovery techniques in some cases (e.g., relatively less aggressive than discrete recovery events across the entire memory array 555). For example, if a low-severity footprint is detected or inferred, a low-level footprint recovery can be performed without stopping certain operations of the system 500 (e.g., footprint recovery can be performed while allowing some data exchange between the memory device 540 and the host device 510). In some cases, footprint recovery during operation can be viewed as a maintenance mode or operation to equalize or normalize the memory array 555 before a footprint causes such access errors, compared to other recovery techniques that can be performed based on the detection of a fault that can be associated with an access error (e.g., full fuse recovery of a failed memory array 555).

[0187] In some examples, thresholds associated with footprint recovery during operation may be based on a detection scheme that utilizes different reference voltages when reading the memory array 555 (e.g., reference Figure 7 8). For example, conditions associated with each of a set of reference voltages or some combination thereof can be used to individually indicate the severity of a footprint detection or prediction. When performing footprint detection at multiple reference voltages, if the condition at the memory array 555 fails a threshold at one or more reference voltages but passes a threshold at one or more other reference voltages, then the system 500 can proceed with maintenance-type footprint recovery. If the condition at the memory array 555 fails a threshold at all reference voltages, then the system 500 can proceed with a full recovery mode (e.g., discrete recovery events across the entire memory array 555). In some examples, such techniques can be supported by chip-level analog thresholds at the memory array, where different thresholds are configured for each of a set of applied reference voltages.

[0188] Footprint recovery during operation can be triggered or adjusted based on various operating conditions in system 500. For example, such techniques can be triggered or adjusted based on data load between host device 510 and memory device 540 or based on processor load of host device 510, where higher loads can correspond to performing less disruptive footprint recovery maintenance. In other examples, system 500 can be configured to detect non-functional or reduced functionality modes (e.g., when system 500 or host device 510 is plugged in overnight), and techniques for footprint recovery during operation can be initiated based on such detection to support maintenance mode. In some examples, footprint recovery during operation can take into account handshaking or other signaling between host device 510 and memory device 540, and various aspects can be initiated or adjusted based on various requirements, operating modes, or other considerations.

[0189] In one example, footprint recovery during operation can utilize a self-refresh configuration at the memory device 540. For example, refresh can be applied (e.g., uniformly) to the entire memory array 555, and refresh operations can be performed more frequently at the memory device 540 based on a footprint detection trigger (e.g., increasing the rate or frequency of self-refresh operations). The increased rate or frequency of refresh operations can provide bias to the memory cells to mitigate the effects of footprinting. In various examples, the modified refresh operation can include an extension, one or more temporary modifications that change voltages, or include state swaps / inversions, which may or may not affect normal operation. Although such techniques may slow down the operation of the memory device 540 or increase power consumption, such techniques may otherwise be transparent to the operation of the interfacing components (e.g., the host device 510) and may not require signaling or negotiation between the memory device 540 and the host device. In other examples, such extensions may be associated with commands or signaling with the host device 510, such as signaling to indicate or approve (e.g., authorize execution) a relatively low-performance mode of operation.

[0190] In some examples, footprint recovery during operation may be based on, included in, or otherwise associated with ECC or wear leveling operations at the memory device 540, where the associated operations may be modified based on relatively lower severity triggers. For example, a relatively small amount of recovery (e.g., bias or access with relatively lower amplitude or relatively shorter duration) may be applied to each page refreshed in accordance with ECC scrubbing or wear leveling. In other words, operations or algorithms associated with ECC or wear leveling may be modified for the purpose of footprint recovery (e.g., based at least in part on the detection or inference of memory cell footprint). Such techniques may be applied to the entire memory array 555 over time while still supporting access operations of the memory array 555.

[0191] In one example, an ECC correction count at the ECC component 570 may be monitored (e.g., by state, by transition), and if the monitored count exceeds or otherwise satisfies a threshold, footprint maintenance may be triggered or initiated. In another example, aspects of wear leveling may include an offset of a physical to logical pointer associated with an offset of data to a new page. Before or after such an offset, recovery processing may be applied to unused physical pages. In various examples, the pages in transition may be offset with a certain number (e.g., 1,000) of rapid cycles or a certain number (e.g., 10) of extended pulses.

[0192] Such techniques may be applied to other memory management methods including rotating data or any other refresh. For example, footprint recovery during operation may include adding recovery cycles or biases to refreshed pages, increasing the number of self-refreshes, reducing the number of system refreshes that are skipped (e.g., where the memory device 540 is configured to skip system refreshes), and the like. In some instances, reducing the number of skipped system refreshes may not require any system knowledge (assuming partial skip refreshes), and accordingly, may be supported without specific signaling between the host device 510 and the memory device 540. When performing a fast recovery (e.g., based on discrete restore events), the voltage may be higher, while a slow recovery for a less severe footprint may have a lower voltage.

[0193] According to various examples, the described techniques may correspond to a permanent or one-way change in operation or may correspond to a change that may be reset back to normal operation after a set time, a set number of passes through the entire array, or in response to operating conditions such as being in idle mode and being plugged in (e.g., a battery charging overnight condition). In some examples, footprint recovery during operation may be performed on a subset of the memory array 555 to restore the operating window for the particular subset.

[0194] When the system 500 is configured to select from various options for footprint recovery methods, in some cases, the option of performing recovery during operation may be preferred or advantageous. For example, recovery during operation may be performed to provide recovery by spreading recovery cycles across multiple operations when power consumption is an issue. In some instances, such techniques may be triggered or adjusted at relatively high operating temperatures of the memory device 540 or host device, because such techniques may be more effective at high temperatures than at low temperatures. Additionally or alternatively, such techniques may be triggered or adjusted at relatively early operating life (e.g., early or mid-life of the memory device), because such techniques may be relatively gentler on the memory device 540 (e.g., compared to discrete recovery events), and accordingly, may be less prone to accelerating fatigue or other degradation of the memory array 555. Additionally or alternatively, such techniques may be triggered or adjusted based on the available time for recovery operations.

[0195] In a third set of examples, footprint management may include various techniques for performing footprint recovery by modifying the operation of memory device 540 or memory array 555. Footprint recovery by modifying operation may refer to various changes in the normal operation of memory device 540 or memory array 555 that are intended to facilitate recovery and may be associated with a reduction in performance (e.g., increased power consumption, reduced bandwidth, increased latency) within permitted specifications. In some examples, the described techniques for footprint recovery by modifying operation may differ from footprint recovery during operation because there may not be additional operations or programs to be performed on a subset of memory array 555 subsequently. Conversely, footprint recovery by modifying operation may refer to various techniques that change how standard operation works. Thus, application of the described recovery to the entire memory array 555 may be implied by normal use of the memory array 555 rather than explicit cycling of the memory array 555. In some examples, such techniques may be intended to be relatively permanent changes in the operation of memory device 540 or memory array 555, or at least unidirectional changes (e.g., a series of changes in parameters in the same direction, not a return to a previous state or configuration of operation).

[0196] In some examples, footprint recovery by modifying operation can take advantage of the flexibility of pulse width or amplitude at the memory device 540. For example, normal operation of the memory device can begin with relatively short pulses (e.g., read pulses, write pulses, refresh pulses), such as shorter bias durations, or pulses with relatively low amplitudes, which can be advantageous for early life operation (e.g., lower power consumption, lower fatigue or other degradation rates). Based on detected or inferred footprint conditions, pulse width, pulse amplitude, or both can be increased (e.g., later in life) to improve footprint recovery or robustness. In some examples, such techniques can be applied near the end of life (e.g., of the memory device 540, of the host device 510), where increased resistance to footprinting may be worth the corresponding higher power consumption or corresponding accelerated degradation of the memory array.

[0197] One example of such a technique may include selective modification of a read pulse (e.g., a cell bias applied during a read operation, a cell bias after issuing an ACT or ACT command), such as an increased read pulse duration, an increased read pulse amplitude, or both. In some examples, such a modification may support restoration of normalized or equalized performance of the memory array 555, or otherwise compensate for changes in memory cell characteristics that may be caused by footprinting. Another example of such a technique may include selective modification (e.g., in response to footprint detection or prediction) of a write pulse (e.g., a cell bias applied during a write operation or a write-back operation, a cell bias after issuing a precharge or PRE command), such as an increased write pulse duration, an increased write pulse amplitude, or both.

[0198] In another example, the "open page" time can be modified, which can refer to various techniques for modifying the voltage or duration of the applied bias during the time between the startup page and the precharge page, which can be alternatively referred to as the time between the open page and the closed page. In some examples, such techniques may include modifying the duration of the period between the startup page and the precharge page, which may correspond to an increase in the row activity time (tRAS) or other timing parameters. In some examples, the open page time may not be part of a read operation, nor part of a write or rewrite operation. On the contrary, at least from the perspective of some memory cells of the memory array 555, the open time may refer to a waiting state, and modifications during this state may not affect other timing specifications. Accordingly, the bias during the open page time can be adjusted for various considerations without necessarily affecting the timing performance. Applying a bias during this period may help to reduce imprinting, but may cause problems for other reasons (e.g., degradation, fatigue, power consumption). Thus, changes to the open page time for imprint management may be enabled relatively late in the operational life of the host device 510 or memory device 540, or during certain operating modes or conditions.

[0199] Another example may include various modifications of the cycles at which the memory device 540 is refreshed. For example, while a typical refresh pulse may have a relatively short duration (e.g., 15-25 nanoseconds), modifications made in response to the detection or inference of a footprint may include extending the refresh to a longer duration (e.g., 200 nanoseconds). In one example, a refresh operation may include various multiples of cycles (e.g., performing two refresh cycles for each triggered refresh), which may effectively double the bias time during the refresh operation. Thus, some modifications to the operation for footprint recovery may include extending the per-page refresh time to include recovery processing of the page being refreshed.

[0200] In another example, for a memory device 540 that has an ECC scrubbing feature enabled (eg, passing ECC code through an ECC engine to correct errors and then writing the corrected data back to the array), scrubbing frequency may be selectively increased in response to a low severity footprint monitor alert.

[0201] Techniques for performing imprint recovery by modifying operations may be selected or adjusted based on various criteria. For example, various techniques may be selected or adjusted based on the operating temperature of the memory device 540 or the host device 510. In one example, because other operating or bias modes may effectively mitigate imprints at higher temperatures, imprint recovery techniques by modifying operations are turned off or disabled at higher operating temperatures. In another example, various techniques may be selected or adjusted based on the age of the component. For example, imprint recovery techniques by modifying operations may be disabled or disabled when the detected age or wear of the host device 510 or the memory device 540 is below or otherwise meets a threshold that reduces wear or fatigue acceleration that may be associated with such techniques, or enabled when the detected age or wear of the host device 510 or the memory device 540 exceeds or otherwise meets a threshold because such wear or fatigue acceleration may be masked by the benefits of imprint management.

[0202] When the system 500 is configured to select from a variety of options for footprint recovery methods, in some cases, the option of performing footprint recovery by modifying the operation of one or more of the memory device 540 or the memory array 555 may be preferred or advantageous. In some instances, performing footprint recovery by modifying the operation may be used to provide a relatively gentle, relatively slow, or relatively weak recovery, such as when a relatively small amount of recovery is required, when normal operation and near-optimal performance are required, or when power availability is relatively low or limited. In some instances, performing footprint recovery by modifying the operation may be preferably applied at low severity or during the early life of the host device 510 or the memory device 540, but such techniques may be beneficial later in the life. In some instances, performing footprint recovery by modifying the operation may be preferably applied when power is limited or when the time available for recovery is relatively limited. In some instances, such techniques may not require signaling between the memory device 540 and the host device, in which case such techniques may be preferably applied in embedded applications.

[0203] In other examples, recovery operations may be disabled in certain circumstances. For example, if a footprint is detected or predicted, but the corresponding severity is determined to be low, the system 500 may be configured to disable or otherwise not perform a recovery operation, which may reduce unnecessary fatigue on the unit. In other examples, avoiding or disabling recovery operations may be preferred depending on the age of the device, which may prevent or mitigate early-life failures that may be caused or exacerbated by recovery methods. For example, if the memory device 540 or one or more memory arrays 555 are relatively old or at the end of their operating life, it may be advantageous to disable recovery operations until absolutely necessary (e.g., with a relatively high threshold for performing recovery operations) to reduce fatigue and stress-induced leakage current on the memory cells of the memory array 555. In another example, if the system 500 is unable to recover a portion of the memory array 555 after multiple attempts to recover (e.g., indicating that a portion of the memory array 555 is at or near the end of its useful life), recovery on that portion of the memory array 555 may be disabled to allow operations on the still-operating portion of the memory array 555. In some examples, recovery operations may be avoided or disabled based on power supply or power availability. For example, if available power or power storage is relatively low (e.g., unplugged mode, battery-only mode, low battery condition), then the recovery operation can be disabled or reduced to reduce power consumption. In some examples, the power state of system 500 can change (e.g., host device 510 can be plugged into a wired power source), and host device 510 can respond by indicating availability for maintenance operations so that memory device 540 can continue with footprint recovery operations.

[0204] In some instances, the system 500 may be configured to take into account the severity of the detected footprint as part of the described footprint recovery operation. For example, various footprint monitoring techniques may be configured to detect or predict the severity of the footprint, and responses may be initiated or configured based on different severity thresholds. In one instance, if the severity monitoring exceeds a relatively low threshold, where the memory array 555 is still in operation, then a "low severity" recovery response may be triggered, such as recovery during operation or recovery by modifying the operation. In some instances, this may include or refer to the use of recovery as a maintenance mode before functional failures are prevalent. In another instance, if the severity monitoring exceeds a relatively high threshold, where the memory array 555 is not in operation, or the errors exceed the ECC correction, then a "high severity" recovery response may be triggered, such as a discrete recovery event across the entire memory array 555. In some instances, this may include or refer to the restoration of the functional capabilities of the memory array 555.

[0205] In some examples, system 500 may be configured to take into account the directionality of detected traces as part of the described trace recovery operations. For example, some trace detection techniques are able to discern whether the presence or severity of a trace is associated with a failure in one logic state or another logic state. Additionally or alternatively, the tendency of a trace in one direction or another may be known or predicted in other ways (e.g., based on known or predicted trace phenomena associated with one logic state or another logic state). The predominance of traces associated with a particular logic state may therefore be used to select a recovery method or bias a recovery method toward offsetting traces in that logic state.

[0206] In some examples, system 500 may be configured to take temperature (e.g., operating temperature of host device 510, operating temperature of memory device 540, operating temperature of memory array 555) into account as part of the described footprint recovery operation. For example, regardless of which recovery method is used, parameters such as bias value, bias time, or number of cycles may change due to the current temperature of the device. In some examples, recovery may be faster or easier at higher temperatures, such that lower bias or fewer cycles may be required to support a given recovery. Relatedly, recovery may be slower or more difficult at low temperatures, such that higher bias or more cycles may be required to support a given recovery. In some examples, recovery may be constrained by low temperature, such that when host device 510 or memory device 540 is operating at relatively low temperatures, it may be necessary to select a particular recovery technique.

[0207] In some examples, system 500 can be configured to take into account power conditions (e.g., power source or power availability of host device 510 or memory device 540) as part of the described footprint recovery operations. For example, the selection of footprint recovery methods can depend on available power, such as whether host device 510 or memory device 540 is operating in a low power state, on battery, or plugged in (e.g., to mains power). In another example, the degree of parallelism (e.g., the number of rows or pages restored simultaneously) can be based on power conditions, such as when plugged in, the degree of parallelism of footprint recovery is increased. In various examples, such techniques can correspond to or otherwise take into account the performance mode of host device 510, the power state of host device 510, or other detected or inferred input power conditions.

[0208] In some examples, system 500 can be configured to consider the age of memory device 540, the age of memory array 555, or the age of host device 510 as part of the described footprint recovery operations. For example, devices can generally be viewed as going through three age ranges, referred to as early life, mid-life, and late life, which can correspond to a bathtub curve. In various examples, such descriptions or characterizations or other monitoring of device life can be tracked by memory device 540, host device 510, or both, to select or adjust various footprint recovery techniques.

[0209] During early-life conditions (e.g., of memory device 540, of host device 510, of system 500), recovery methods may be used to induce a "wake-up" in memory array 555. For example, early-life recovery may be a system-triggered maintenance response to defined thermal stresses of the assembly or packaging process (e.g., manufacturing operations during installation, mounting, soldering on board, curing of laminate package molding compound, soldering), or by tracking the state of a usage counter. In some examples, early-life recovery techniques may selectively tend to relatively few cycles with symmetrical, low-bias extended pulse widths to gently wake up memory array 555.

[0210] During mid-life conditions (e.g., of the memory device 540, of the host device 510, of the system 500), recovery methods may be used to recover from more significant or unexpected thermal stress events. For example, during mid-life conditions (e.g., of the memory device 540, of the host device 510, of the system 500), the device may experience multiple failure mechanisms, such as footprinting, fatigue, leakage, etc. Without the benefit of using counters or system triggers, these events may be difficult to separate from mid-life failures. Mid-life recovery techniques may be triggered by the memory device 540 or the host device 510, and may include pre-configured techniques or selection among discrete recovery events across the memory array 555, recovery during operation, or recovery by modifying operations. In some examples, mid-life may be defined as "not early-life" (e.g., as a binary flag) or defined by using counters (e.g., access operation counters, odometers), both of which may be applied to the selection or adjustment of recovery methods.

[0211] During end-of-life conditions (e.g., of memory device 540, host device 510, system 500), recovery methods may tend to be more extreme and may emphasize modifications to standard operations, such as increasing write bias or read bias. In some instances, end-of-life recovery may be characterized as an "all or nothing" response, where host device 510 or memory device 540 may not have much useful life remaining, and the benefits of footprint recovery may outweigh any corresponding degradation in useful life. In some instances, end-of-life may be defined as an "end-of-life" flag (e.g., as a binary flag), or defined by the use of counters (e.g., access operation counters, odometers), both of which may apply to the selection or adjustment of recovery methods.

[0212] Age or wear assessment may be supported by various techniques in system 500. For example, memory device 540 may include an on-die usage counter that may be compared (e.g., at memory device 540, at host device 510) to a set of predefined life usage thresholds to identify whether memory device 540 meets an early-life, mid-life, or late-life condition. In another example, host device 510 or memory device 540 may include a controller that sets a flag or another indication corresponding to an early-life, mid-life, or late-life condition. For example, an early-life flag may be set after final system assembly or board soldering or after initial startup and system testing, and toggled after a certain duration or another threshold of operation.

[0213] In some examples, footprint management techniques may also consider aspects of data retention of the memory array 555, which may include various examples of static configuration or selective operation with respect to whether to attempt to retain data stored by memory cells to which footprint recovery is applied.

[0214] In one example, a footprint recovery method may attempt to preserve data stored in the memory array 555 by copying the data from a subset of the memory array 555 that will receive the recovery process to an alternate location (e.g., another memory address of the same memory array 555, a different memory array 555, or an auxiliary memory device 590). For example, the footprint recovery process may include copying the data to a different subset of the memory array 555 and remapping the logical to physical address scrambling, wherein the recovery process may be performed immediately after entering the idle state or when entering the idle state. In another example, the data may be retained locally by performing a certain number of repeated cycles of the reverse write-back operation, thereby substantially flipping the data state of the array subset for a given number of cycles. In some examples, if the footprint detection or evaluation operation has delivered a low severity warning, then such data retention may be enabled, and data may still be read from and written to the array without having an unrecoverable error. In other words, if the memory array 555 has not experienced an unrecoverable error, then the system 500 may be configured to attempt data retention.

[0215] In another example, in bypass mode, data can be read into a sense amplifier or latch (e.g., of the sensing component 250) and held at the sense amplifier or latch without being overwritten by biasing or cycling of the memory array 555. In various examples, after a restore operation, data from the restored memory cells can be returned or latched to the same location from the sense amplifier, or data from the restored memory cells can be moved or latched to a different location from the sense amplifier and the restored memory cells can be made available for other data.

[0216] In some instances, the recovery method may not attempt to preserve data. For example, if a footprint failure is known, the system 500 may be configured to avoid spending time on data preservation (e.g., data preservation may be disabled), which may speed up certain aspects of footprint recovery. When data cannot be read from or written to the memory array 555 without errors, or when the user does not expect data preservation to occur (e.g., during startup operations when the memory device 540 or memory array 555 is configured in a volatile mode or is otherwise not expected to store required information), such operations may be selectively performed or disabled in response to a high severity footprint monitoring fault.

[0217] In some instances, in applications where the memory device 540 is expected to support a certain degree of non-volatility (e.g., when the memory device 540 is configured to function as a non-volatile RAM), particular consideration may be given to aspects of data retention during footprint recovery. For example, the system 500 may be configured with a data hierarchy or other storage hierarchy where the purpose of the memory device 540 may be to provide relatively fast storage. In one instance, the memory device 540 may be configured to provide virtual memory functionality that is faster than other secondary memory devices 590. In some instances, this may include operating the memory array 555 of the memory device 540 in a non-volatile mode to initialize quickly (e.g., wake up from a sleep mode where the memory device 540 is powered down). In these cases, prior to entering a low power mode, the system 500 may be configured to cause the data in the virtual memory to be refreshed (e.g., copied) to the secondary memory device 590, where the secondary memory device may support or be expected to support a higher degree of non-volatility or footprint resistance than the memory device 540. In other words, memory device 540 may be configured to support fast booting (e.g., taking advantage of the probability that stored information is still present), but may not explicitly or purely rely on the presence of such data at memory device 540. For example, system 500 may be configured to attempt initialization using information from memory device 540, and in the event of a failure (e.g., a boot failure), footprint management techniques (e.g., detection operations, recovery operations) may be performed on memory device 540 before, during, or after the attempted initialization using information copied to secondary memory device 590.

[0218] Refresh, copy or other redundancy techniques may additionally or alternatively include refresh by address space identifier (ASID), refresh of program and operating system data, refresh by user, refresh according to program compared to data, or refresh or copy by other configuration or initiation, and various operation management schemes may be configured accordingly. For example, when an error in accessing memory device 540 is not recoverable by normal ECC operation, data can be pulled back during error recovery using a page table or mapping (e.g., virtual memory mapping, data redundancy mapping), which may include data stored at a different memory array 555 or auxiliary memory device 590 (e.g., flash memory, hard disk, or another storage device). In other words, according to these and other techniques, system 500 can be configured to determine whether to pull data from memory array 555 or pull a copy from another memory (e.g., another memory array 555 or auxiliary memory device 590), which may have a different (e.g., higher) degree of non-volatility or another difference in the degree of footprint. Such techniques for determining the location of access data copies can be combined with various footprint management techniques described herein.

[0219] In another example of applying the described techniques in a memory hierarchy, the system 500 may be configured to copy information from the memory device 540 to the secondary memory device 590 during imprint detection or imprint recovery. For example, the system 500 may be configured to apply such techniques as an attempt to back up or recover information (e.g., back up data to the secondary memory device 590) that would otherwise be lost when writing the information back to the imprinted memory cells of the memory device 540. Such techniques may preferably be applied with a secondary memory device 590 configured for relatively fast operation, such as a secondary memory device 590 employing a DRAM or FeRAM architecture.

[0220] In some examples, the system 500 may be configured to selectively enable or configure various aspects of data retention based on various considerations. For example, if an ECC correction at a memory device 540 fails, the system 500 may be configured to understand that the data in the memory device 540 may be damaged, so that the data in the memory device 540 or a particular memory array 555 does not need to be retained during imprint recovery (e.g., relying on data stored in another location). In another example, the system 500 may be configured to perform various operations based on system or product constraints, such as the configuration of the volatility or non-volatility of the memory device 540. For example, if the system 500 is configured to use the memory device 540 in a non-volatile mode, or the memory device 540 is otherwise not configured as non-volatile, the system 500 (e.g., the host device 510, the memory device 540) may set a flag or mode register that identifies the memory device 540 or its operation as non-volatile, and perform imprint management techniques accordingly. In some examples, if imprint recovery is being performed after power-up or during operation of the memory device 540, data may need to be preserved unless the system 500 provides an indication that data preservation is not required for a given subset of the memory array 555. In another example, the various imprint recovery techniques described herein may be selectively enabled or configured based on detecting whether a backup location is available in another memory array 555 or in the secondary memory device 590. For example, an imprint detection limit or threshold may be set based on whether such a detection is present, or various recovery types may be selected based on whether such a detection is present.

[0221] In some examples, one or more of the techniques described may be utilized to mitigate or address aspects of security vulnerabilities, malicious attacks, or inadvertently adverse access patterns. For example, as non-volatility in a memory device is moved closer to the processor (e.g., in terms of a memory hierarchy), the configuration of the system architecture may need to consider the likelihood of data retention failures in the memory device, as well as the mechanisms that may cause such failures (e.g., whether due to imprinting or some other phenomenon). In some examples, imprints in the memory device 540 may be associated with certain vulnerabilities, and thus, the host device 510, the memory device 540, or the entire system 500 may be configured to address such vulnerabilities or to increase immunity or robustness to such vulnerabilities.

[0222] In one example, a memory device may have a security or operational vulnerability in an access mode, such as row hammering, where row hammering can be used to gain access to different portions of the memory device. In some cases, memory cells that have been imprinted or otherwise degraded may be attacked. For example, if a host device 510 (e.g., a CPU of host device 510) conducts a speculative event in response to an error in memory device 540, then an imprint or other fault or phenomenon of memory device 540 may be the source that triggers such an event. To increase robustness and security, system 500 may be configured with a level of handoff between memory device 540 (e.g., imprint detection component 560, imprint recovery component 565, memory controller 550) and host device 510 (e.g., imprint manager 525, host device controller 520) to mitigate such vulnerabilities. In some examples, imprint detection techniques such as those described herein may be configured in a manner that causes such attacks to be interrupted.

[0223] In one example, unrecoverable data errors (e.g., one or more failed bits) may be identified during a startup event or a maintenance or recovery event (e.g., a stamp detection event, a stamp recovery procedure). In various examples, unrecoverable ECC errors may be the result of intentional design, unintentional adverse access patterns, or random failures. For example, with respect to an intentional attack, a bad actor may intentionally stamp a bit at a critical location in the memory array 555, or identify memory cells in the array that have an imprinted bias direction or other relative weakness related to data retention, and design errors to occur at these memory cells (e.g., writing critical data to a location in the memory array 555 that is known to have an imprinted or another degraded ability to store data). Additionally or alternatively, a random attack may be generated by intentionally cutting power to the memory device 540, the host device 510, or the system 500 to design for retention failures, or by bombarding the memory device 540 configured for non-volatile operation with radiation. In some examples, when host device 510 (e.g., a CPU of host device 510) receives corrupted data or code, host device 510 may branch unpredictably. In benign situations, such branching may simply cause host device 510 or system 500 to crash. Avoiding such crashes may be beneficial (e.g., to avoid inconvenience), but such crashes may not be relevant to other downstream. However, under hostile conditions, branching may represent a security issue.

[0224] According to aspects of the present disclosure, when system 500 (e.g., memory device 540, host device 510) identifies an error (e.g., an uncorrectable ECC error), whether or not related to imprinting or some other cause, system 500 can be configured to continue various operations and communications to mitigate or address the security vulnerability.

[0225] According to various examples, the memory device 540 may detect data errors (e.g., uncorrectable errors) or access patterns (e.g., one or more read commands, one or more write commands) that may adversely affect the storage characteristics of the memory device 540, such as access patterns that may reduce the ability of memory cells in the memory array 555 to be written or otherwise store data. For example, such detection may be performed during a startup operation or during normal operation of the system 500 (e.g., of the memory device 540). In some examples, the memory device 540 may detect access patterns that may cause the host device 510 to initiate or otherwise perform speculative branches. In some examples, the memory device 540 may identify footprint attacks or identify forced footprints, which may be associated with conditions that may result in footprints of ferroelectric capacitors (e.g., in FeRAM applications), footprints of another type of capacitor (e.g., in DRAM applications), footprints of material memory elements, or other types of footprints. In some examples, the memory device 540 may determine that the data errors exceed the correction capabilities of the memory device 540 (e.g., of the ECC program).

[0226] In response to such detection, the memory device 540 may determine to cease normal operation (e.g., at least temporarily), which may be associated with a violation of an assumption or configuration of non-volatility. In some examples, this may include the memory device 540 entering a secure mode, entering a maintenance mode, or entering a recovery mode, or some combination thereof. In some examples, the memory device 540 may initiate a recovery operation on the memory array 555, such as a footprint recovery operation, and in some examples, recover data from another portion of the system 500 (e.g., from a different memory array 555, from an auxiliary memory device 590). In some examples, the memory device 540 may determine to cease operation entirely, or at least to cease until a subsequent initialization or boot operation (e.g., initiated by the host device 510).

[0227] Additionally or alternatively, the memory device 540 may be configured to indicate an error to the host device 510 through implicit signaling or its absence or through explicit signaling. In some examples, the memory device 540 may lock or deactivate an address decoder of the memory device 540 (e.g., of the memory controller 550), or lock certain addresses of the memory device 540 (e.g., of the one or more memory arrays 555). In some examples, the memory device 540 may be configured to return random data (e.g., instead of the requested data), which the host device 510 may interpret as an error indication. In some examples, the memory device 540 may be configured to prevent or prohibit responding to the host device 510 (e.g., ignoring commands from the host device 510), so that the memory device 540 may be considered to be completely locked (e.g., from the perspective of the host device 510), at least temporarily. In some examples, the memory device 540 may be configured to send a message to the host device 510 that an exception has occurred, placing the responsibility for responding on the host device 510. In some examples, the response of memory device 540 may be configured to intentionally cause a failure at host device 510, such as a deliberately designed blue screen event (eg, rather than attempting to recover from an error, which could open a security hole or permit malicious access).

[0228] In some examples, the memory device 540 may be configured to transfer or grant (e.g., switch to) a maintenance mode, thereby avoiding or prohibiting access or other operations from generating malicious imprints. In some examples, such a transfer may be accompanied by the memory device 540 sending a message or other signaling to the host device 510, which may generate an exception at the host device 510. In some examples, such signaling may be accompanied by the memory device 540 indicating to the host device 510 an address with an ECC error.

[0229] In some examples, the host device 510 may be configured to recognize errors of the memory device 540 and attempt to recover data from another location, such as another memory array 555 or an auxiliary memory device 590. In other words, the host device 510 may attempt to perform an access operation with the memory device 540, and based on detecting an unrecoverable error of the memory device 540 (e.g., implicitly, based on a characteristic of a response or lack of a response from the memory device 540, or explicitly, based on specifically configured signaling from the memory device 540, based on a detection or prediction or imprint or another degradation at the memory device 540), the host device 510 may attempt to recover data (e.g., backup data, redundant data) based at least in part on the auxiliary memory device 590. In one example, such data recovery may be facilitated by the memory device 540 signaling the address of such errors or returning an ECC error when accessing an address with an error. In some examples, such signaling may include the memory device 540 signaling a failure instead of or in place of the data requested for the read operation. Therefore, host device 510 may attempt to pull the originally requested data from the backup location.

[0230] The system 500 may be configured to recover from such conditions according to various procedures. For example, the host device 510 may perform recovery by using an address table, such as a translation lookaside buffer (TLB), a cache table, or any other logical or virtual mapping of an address. Using such a table or another lookup resource, the host device may attempt to retrieve data from an alternative storage device to replace the potentially damaged data. In some instances, such methods may prevent other failures from occurring at the host device, such as preventing a blue screen event from occurring. In some instances, this method may enable the host device 510 to recover from an ECC error at the memory device 540. In some instances, the exception may be passed to a processor (e.g., a CPU) at the host device, which may initiate a new boot operation, wherein the host device 510 may be configured to retry using the memory device 540 (e.g., for a preconfigured number of retries), or use an auxiliary memory device 590.

[0231] In one example of such recovery, the system 500 may be configured such that parity bits are stored elsewhere in the system 500 (e.g., separate from the memory device 540). In other words, when data is written to the memory device 540, parity bits associated with the data may be written to the auxiliary memory device 590. In such an example, the system 500 may be configured such that the host device 510 may attempt to correct data errors at the memory device 540 using multiple memory devices (e.g., at least one auxiliary memory device 590), which may include performing a more complex error correction scheme (e.g., as coordinated at the host device 510) than the scheme performed or supported at the memory device 540 (e.g., a chip-level or on-die ECC scheme).

[0232] In some examples, such schemes may be supported or enhanced by the bit flippers of the memory device 540, which may improve the robustness of the memory device 540 to certain types of malicious attacks. For example, the bit flipper functionality including reverse writeback may inherently improve the robustness to malicious imprints because the reverse writeback itself may disable or restore certain aspects of the imprint. However, the described techniques may prevent other malicious attacks, or attacks where reverse writeback is not sufficient to disable or prevent the imprint. In addition, the described techniques are beneficial to systems 500 or memory devices 540 that are not configured with certain reverse writeback techniques or another inherent resistance to imprints or another memory degradation that may be attacked.

[0233] Figure 6 An example of a process flow 600 for supporting footprint management of a memory system according to examples disclosed herein is shown. Features of the process flow 600 may be implemented by a memory device (e.g., reference Figures 1 to 5 10, memory die 160, memory die 200, or memory device 540) described herein implements or performs or one or more components of a memory device (e.g., reference Figures 1 to 5 In some examples, one or more of the described techniques may be offloaded to a host device (e.g., by a host computer). Figure 5 510 or footprint manager 525 as described herein).

[0234] In some cases, when a footprint detection procedure is performed on a memory cell of a memory array, the logical state stored by the memory cell may be random from the perspective of the footprint detection procedure. For example, the logical state stored by the memory cell may be unknown or otherwise not specifically configured to support the footprint detection procedure. In other words, in some cases, the memory device may perform the footprint detection procedure at 615 on a memory cell in which the previously stored data is not related to the footprint detection procedure (e.g., not affected by it, not specific to the footprint detection procedure). For example, before the footprint detection procedure (e.g., before the conditions associated with imprinting), the memory cell of the memory array on which the footprint detection procedure is performed may have been used to store application data. In these cases, the memory device may use any data that will be stored to the memory cell as potential imprinted data or potential imprinted logical state before starting the footprint detection procedure at 615. In these cases, the memory device may or may not rely on the degree of randomness of the stored data to support the mixing of logical states of the evaluated memory cells or portions thereof throughout the memory array for the footprint detection procedure at 615.

[0235] In other cases, the memory device may write forcing (e.g., known, preconfigured) data to the memory cells to be evaluated (e.g., a subset of the array) at 605, prior to performing the imprint detection procedure at 615, so that in the event of a subsequent imprint detection procedure, the memory device may perform the imprint detection procedure on these memory cells and treat the forcing data as a potential imprinted logic state. Prior to determining to initiate the imprint detection procedure (e.g., prior to the shutdown and subsequent restart at 610), the memory device may actively write the forcing data according to various techniques. Writing the forcing data may include the memory device writing all memory cells (e.g., of the subset of cells for imprint evaluation) to the same logic state (e.g., writing "solid" forcing data), a desired mix of logic states (e.g., writing "mixed" forcing data, writing different logic states in known or preconfigured proportions), or a known logic state pattern (e.g., alternating logic states, a "checkerboard" pattern).

[0236] As an example, the memory device may use one or more replica word lines or pages (e.g., memory cells, memory pages, or memory segments made available by wear leveling or another procedure) as a subset of memory cells to which the forced data will be written at 605. In some examples, based on a wear leveling procedure or algorithm, the memory controller may transfer data between one or more memory cells in the memory array, or transfer data with an auxiliary memory device. Wear leveling may include, for example, transferring application data from one physical location to another within or across or between memory arrays, which may prevent one memory cell or subset of the memory array from being written to or read more (e.g., much more) than another memory cell or subset. Excessive access may shorten the useful life of overused memory cells compared to less frequently accessed memory cells, so wear leveling may protect individual memory cells of the memory device from being overused, causing the memory cells to fail prematurely.

[0237] In some cases, a memory array may include additional (e.g., spare) memory cells, rows, or pages that may support the transfer or otherwise offset of application data within the memory array. In some instances, such space in the memory array or such offset of application data may be part of wear leveling functionality. In some instances, such spare memory cells may be referred to as gap memory cells and may also be associated with one or more gap word lines or gap pages. Thus, due to these and other aspects of operation or configuration, at any given time, some memory cells of the memory array may not be actively storing application data, or such data may not be important to the memory device or host device.

[0238] In some cases, spare memory cells may be available and may be used to store known or forced data that may be used in a subsequent footprint detection procedure. When the physical location of the application data is shifted according to the wear leveling procedure, the known or forced data used in the subsequent footprint detection procedure may also be shifted (e.g., to the latest available row or page that is not actively used for application data). In some cases, the wear leveling operation may be performed on a word line basis, and the word lines coupled to the memory cells that are not currently used for application data may be referred to as replica word lines or offset word lines. Thus, a first set of logic states (e.g., in a known or forced pattern) may be written to the memory cells coupled to one or more replica word lines available through the wear leveling operation. Upon initiation of the memory device or another triggering of the memory device, the memory controller may perform a footprint detection procedure using a known or forced pattern of logic states written to the memory cells of the memory array that are available through the wear leveling procedure (e.g., the memory cells coupled to the replica word lines).

[0239] In some cases, the known or forced data may be continuously updated (e.g., refreshed) at the memory array. In these cases, the known or forced data may be present at the memory array in the event of a sudden or unexpected deactivation event (e.g., power outage, crash) or other standby event in which the host device or memory device may not be actively monitoring or otherwise operating. In some cases, the memory controller may enforce a set of logical states at the memory array as part of one or more deactivation procedures, which may be included when initiating a shutdown or standby mode. For example, when a host device or the like initiates a deactivation procedure, the host device controller 520, the footprint manager 525, the memory controller 550, or the footprint detection component 560 may identify one or more portions of the memory array 555 for enforcing data conditions, and the memory device may write the forced data to the identified portions of the memory array.

[0240] In some examples, the memory device (e.g., footprint detection component 560) may record or otherwise track the forced logic state so that subsequent access operations (e.g., read operations, write operations) of the same subset of memory cells can be compared to the forced logic state or otherwise based on the forced logic state (e.g., when determining an evaluation data condition based on the imprinted data condition). In some examples, the footprint detection component 560 or the memory controller 550 may write a data pattern as the forced logic state. For example, the forced data may include an alternating pattern of logic zeros and logic ones that may be referred to as a checkerboard pattern, a solid pattern of all logic zeros or all logic ones, or various other combinations or distributions of logic zeros and logic ones. In some examples, enforcing a known data condition may include reading and recording a set of logic states that have been written to the subset of memory cells. In this regard, the record of the written or stored data may serve as a forced or known logic state.

[0241] In some cases, the memory device or the host device may perform a footprint detection procedure in response to the deactivation and restart of the memory device. For example, at 610, the memory device may be deactivated (e.g., as part of a power-off procedure of a device associated with the memory device, as part of entering a standby mode). While deactivated, the memory device may be exposed to various environmental conditions (e.g., increased temperature), which may be related to whether the memory cells of the memory device are imprinted. Whether due to adverse environmental conditions or otherwise, footprints may occur in some cases when the memory device is deactivated or in a standby state. In the deactivated state or the standby state, the memory device may not track or sense the environmental conditions to which it is exposed or the duration for which it is deactivated. Subsequently at 610 (e.g., before 615), the memory device may be activated.

[0242] After booting up, the memory device or host device may not have data or information that can be used to determine whether to perform an imprint recovery procedure (e.g., related to the probability of imprinting when the memory device is de-booted). In some cases, after booting up, the host device may initiate, or the memory device may otherwise perform (e.g., autonomously), one or more evaluations. For example, as part of a power-on self-test (POST) process, the host device may instruct the memory device to perform, or the memory device may otherwise initiate or perform, one or more tests to determine whether the memory device is operating within one or more specifications (e.g., specifications related to memory cell equalization or normalization), which may include an imprint detection procedure.

[0243] At 615, the memory device or host device may perform a footprint detection procedure. In some cases, the memory device may perform a footprint detection procedure based on the deactivation and activation at 610 or another basis as described herein. In various examples, the operation of 615 may be triggered at the startup of the memory device (e.g., triggered by it), or based on a footprint evaluation performed during other operations of the memory device or host device. In some examples, the operation of 615 may continue until the presence of a footprint is detected, or may be initiated based on some other indication of a footprint (e.g., static bake conditions, identification of an unintentional or malicious access pattern that may cause a footprint). In some examples, the footprint detection procedure may include identifying a subset of memory cells of the memory array 555 for performing one or more steps of a footprint detection process.

[0244] In some cases, the subset of memory cells used for the footprint detection procedure may be based on the location of the memory that has been written to force the logic state. For example, the subset of cells may be based on or correspond to the portion of the memory array 555 written at step 605. In the event that the memory device has not previously forced the data, the memory device may select a subset of memory cells to perform the footprint detection procedure at 615. The subset of memory cells may be predefined, randomly selected, or selected based on one or more other configurations or boot procedures. In some examples, the subset of memory cells selected for the footprint detection procedure may include one or more memory arrays 555 or different sections of the memory device.

[0245] As part of the footprint detection procedure, at 615, the memory device may write a first set of logic states to the subset of memory cells. In some instances, the first set of logic states may include a known (e.g., preconfigured, predefined, forced) pattern. For example, the memory device may write solid data of all logic 0s or logic 1s to the subset of memory cells. In some instances, the memory device may write the opposite logic state to each memory cell in the subset, for example, by reading the current data state of the memory cell (e.g., using a default reference voltage) and then writing the opposite state to the corresponding memory cell, which may be referred to as a read inversion write-back procedure. In some instances, the memory device may write a mix of logic states as the first set of logic states. This may include writing a pattern, such as an alternating pattern of logic 1s and logic 0s, a set of random logic states, or any other combination of logic states.

[0246] In the event that the forcing data has been written to the memory array prior to the suspected imprinting event (e.g., prior to deactivation of the memory device, prior to the memory device entering a standby state), the first set of logic states may be based on the forcing data. For example, if a set of solid logic states (e.g., all logic 0s) is forced prior to deactivation, the memory device may write an opposite set of solid logic states (e.g., all logic 1s), the same logic states (e.g., all logic 0s), or another logic pattern as described herein. In some cases, the memory device may write a data pattern to a subset of memory cells prior to deactivation.

[0247] As another part of the footprint detection procedure, the memory device may perform one or more read operations on the one or more portions of the subset of memory cells (e.g., the memory cells). The read operations on the subset of memory cells may produce another set of logic states (e.g., a second set of logic states), which the memory device may compare to the first set of logic states (e.g., written at 615). In some cases, as part of the footprint detection analysis, the memory device may perform additional read or write operations on the subset of memory cells to obtain additional sets of logic states.

[0248] In some cases, based on reading the evaluated memory cells using one or more different reference voltages, the memory device or host device may obtain a second set of logic states or other additional sets of logic states. For example, the memory device may be configured with a default or operating reference voltage for use when reading the logic state of the memory array (e.g., under normal operation). The default or operating reference voltage may be set to reduce or minimize the number of read errors that occur during a read operation, during normal operation (e.g., when the memory array 555 is in an access mode or a normal operating mode). In some cases, the memory device or host device may obtain the second set of logic states by reading the evaluated memory cells using the default reference voltage. In some examples, the memory device or host device may obtain the second set of logic states by reading the evaluated memory cells using one or more offset reference voltages. In these cases, the offset reference voltage may be associated with an expected number of errors or mismatches, as discussed herein (e.g., according to a probabilistic distribution of memory cell characteristics).

[0249] The memory device may determine one or more numbers of errors based on a mismatch or difference between a written logical state (e.g., a first set of logical states, one or more target logical states of a previous write operation) and a read logical state (e.g., a second set of logical states). In some cases, the memory device or host device may compare the logical state read from each memory cell to a known, recorded, or forced value of the logical state that has been previously written to the memory cell. If the logical states are different, the memory device or host device may determine an error or mismatch, and if the logical states are the same, the memory device or host device may determine that no error or mismatch has occurred. The memory device or host device may count the number of errors for one or more portions of a subset of memory cells to determine the number of errors.

[0250] At 620, the memory device or host device may determine whether a recovery operation should be performed (e.g., based at least in part on the footprint detection procedure performed at 615). In some instances (e.g., when the footprint detection procedure at 615 includes identifying a number of errors or mismatches), such a determination of whether a recovery operation should be performed may be based on the identified number of errors or mismatches, such as by comparing the identified number of errors or mismatches to a threshold. For example, if the second set of logic states is obtained by reading the memory cells using a default reference voltage, then the threshold may be relatively low (e.g., zero errors or near zero errors, based on the ECC operation or capabilities of the ECC component 570). In some cases, if the second set of logic states is obtained by reading the memory cells using an offset reference voltage (e.g., a reference voltage that is higher or lower than the default reference voltage), then the threshold may be relatively high (e.g., based on an expected or probabilistic number of errors that may occur when reading at the offset voltage, as described herein, for example, with respect to Figure 7 described).

[0251] In some cases, a memory device or a host device may determine a first number of errors (e.g., resulting from reading using a first threshold voltage) and a second number of errors (e.g., resulting from reading using a second threshold voltage), and determine whether a recovery operation should be performed based on the first and second number of errors. This may include determining a gradient parameter (e.g., a difference, a linear slope, a nonlinear regression) between the first number of errors and the second number of errors, examples of which are described herein (e.g., with respect to Figure 7 ) is further described. In some cases, the memory device or the host device may determine to perform a recovery operation, for example, based on determining that a threshold is met. For example, the threshold may be related to the number of errors, the gradient parameter, or other parameters.

[0252] In some examples, the memory device may indicate to the host device that a recovery operation is required, and the memory device may wait to receive instructions from the host device (e.g., a command to perform a recovery operation or to enter an access, or another operating mode, approval to proceed with the recovery procedure). Thus, in some cases, the host device may determine whether or when the memory device should perform a repair procedure in response to signaling from the memory device. In the event that the memory device determines that a repair operation is not required (e.g., a threshold is not met), the memory device may indicate to the host device that it is ready to complete the boot procedure or otherwise enter an access, or another operating mode (e.g., by indicating through the memory device 540, based at least in part on determining that the memory array 555 is not stamped or is not stamped to a level greater than a threshold, the memory device 540 is available for access operations).

[0253] At 625, the memory device or host device may perform a recovery operation, which may include cycling memory cells of the memory array one or more times (e.g., according to a bias mode, according to an access operation mode). For example, the memory device may perform multiple access operations (e.g., read and write operations) on one or more memory arrays of the memory device. In some cases, the write operation may include an inverted write-back operation, in which a corresponding memory cell is read (e.g., using a default reference voltage) and a complementary or opposite logic state of the determined (e.g., read) logic state is written back to the corresponding memory cell. In some examples, the recovery operation of 620 may include performing multiple write operations on all or substantially all memory cells in a subset of memory cells of the memory array based on analyzing data from a subset of memory cells of the same memory array or a different memory array.

[0254] In some examples, the memory device may determine that the recovery operation has completed and send one or more relevant indications to the host device. In some cases, the memory device may perform a loop operation and then send an indication to the host device that the memory device can be started and used by the host device, or an indication that the memory device can enter an access or another operating mode. In some cases, after completing the recovery operation, the memory device may perform a subsequent or second footprint detection procedure to determine or otherwise evaluate whether the repair operation was successful (e.g., to confirm that the recovery operation was successful before indicating availability to the host device or transitioning to a normal operating mode).

[0255] At 630, the memory device of the host device may enter an operating mode (e.g., normal operating mode, access mode) after determining at 620 not to perform a recovery operation or after completing the recovery operation at 625. In various examples, this may include resuming an access mode or a normal operating mode, or completing a boot process.

[0256] Although the example of process flow 600 illustrates footprint detection utilizing written and read logical states of a memory array (e.g., based on direct detection or assessment of the presence of footprints), other examples of process flow 600 may utilize other footprint detection techniques, or may make decisions regarding recovery operations (e.g., at 620) based on predictions or inferences regarding memory cell footprints, such as detecting or identifying conditions that may be associated with or otherwise accompany another memory cell asymmetry of memory cell imprinting or failure (e.g., high temperature, duration of inactivity, detection of inadvertent or malicious access operations or patterns that may cause footprints or other skew, asymmetry, or other adverse memory cell characteristics).

[0257] Figure 7 Graph 700 illustrates footprint detection conditions that may support footprint management of a memory system according to examples disclosed herein. Graph 700 may illustrate the number of mismatches between a target logic state (e.g., a written logic state, an attempted written logic state, an expected logic state) and a detected logic state (e.g., a read logic state) as a function of a reference voltage used to detect a stored logic state (e.g., by sensing component 250, via reference line 255). As part of a footprint detection procedure, one or more of the illustrated footprint detection conditions may be detected by a memory device (e.g., a reference line 255). Figures 1 to 5 10, memory die 160, memory die 200, or memory device 540) or one or more components of a memory device (e.g., reference Figures 1 to 5 The described device memory controller 155, local memory controller 165, local memory controller 265, memory controller 550 or footprint detection component 560) is implemented or executed.

[0258] In the example of curve 700, the unimprinted feature 740 can show the expected number of mismatches when reading a group of representative memory cells 205 at different reference voltages without imprinting (e.g., when the group of representative memory cells 205 is equalized or normalized). For example, the expected number of mismatches can be related to the random or probabilistic relationship of the read voltage and the corresponding reference voltage generated by the read operation. According to the illustrated example of curve 700, a read signal (e.g., of digit line 215) above the reference voltage (e.g., of reference line 255) can indicate a logical 1, and a read signal below the reference voltage can indicate a logical 0. In an intermediate voltage region (e.g., near a default reference voltage), the expected number of mismatches for a given reference voltage can be zero. In some examples, the expected number of mismatches can be zero in the entire reference voltage range corresponding to the read window. When the reference voltage increases or decreases beyond such an intermediate region, the expected mismatch or error can increase along the slope according to the probabilistic or random relationship.

[0259] In the example of curve 700, the imprinted feature 750 can show the number of mismatches when reading the same group of representative memory cells 205 at different reference voltages, when the group of representative memory cells has been imprinted with one or more logic states. Compared to the unimprinted feature 740, the imprinted feature 750 can have a kink slope associated with the imprint of multiple or mixed logic states. For example, on either side of the central region (e.g., around the default reference voltage 702), one side of the kink can be associated with the characteristics of the memory cells imprinted in one logic state, and the other side of the kink can be associated with the characteristics of the memory cells imprinted in another different logic state. In some examples, such kink characteristics can be utilized as part of an imprint detection operation.

[0260] In other examples, a group of representative memory cells may be imprinted with a single logic state (not shown), and the imprinted features 750 may have the same or similar slope as the unimprinted features 740, but the imprinted features 750 may be offset along the reference voltage axis. In such examples, the offset of the features may be utilized as part of a footprint detection operation (e.g., based on detecting or identifying an asymmetry relative to a default reference voltage 702, based on a detected mismatch being higher than expected on one side of the default reference voltage 702 but not higher than on the other side).

[0261] In some examples, the footprint detection procedure can include reading a subset of memory cells at one or more reference voltages (e.g., a default reference voltage 702, one or more offset reference voltages 705), and determining the number of mismatches (e.g., errors, differences) between a logic state that has been read using the respective reference voltages and a previously written logic state or a target logic state, as described herein. Curve 700 shows an example relationship between different reference voltages 702 and 705 for reading logic states, an expected number of mismatches 715 (e.g., failures, errors, or differences expected for a normalized or equalized memory array 555, according to a probabilistic or random relationship) when reading at the respective reference voltages 702 or 705, and a measured number of mismatches 720 (e.g., failures, errors, or differences) for an example of an imprinted memory array 555 when reading at the respective reference voltages 702 or 705.

[0262] The default reference voltage 702 may be a default or operating reference voltage for a memory device. Read operations using the default reference voltage 702 may be expected to produce zero errors (e.g., where the expected number of mismatches 715-a is equal to zero), a statistically insignificant number of errors, or a number that is less than the number of errors that can be corrected by ECC operations when the memory cells of the memory array are operating properly (e.g., when no imprinting occurs, in an equalized or normalized memory array 555). In some cases, the default reference voltage 702 may be a reference voltage used by the memory device during normal operating procedures when performing access operations, such as data access associated with application data. Although in some instances, the default reference voltage 702 may be fixed at the memory device, in other instances, the default reference voltage 702 (e.g., for normal operation, for default operation) may be adjusted at the memory device during operation of the memory device (e.g., adjusted to an adaptive reference voltage, adjusted to a configurable reference voltage to compensate for changes in memory device or memory cell characteristics applicable to normalized or equalized operations) for reasons unrelated to imprinting.

[0263] As part of the footprint detection procedure, the memory device may read the memory cells using one or more offset reference voltages 705, which may be less than the default reference voltage 702 (e.g., offset reference voltages 705-b or 705-c) or greater than the default reference voltage 702 (e.g., offset reference voltages 705-d or 705-e). In some cases, as part of the footprint detection procedure, the measured number of mismatches 720 detected at different offset reference voltages 705 may deviate from the expected number of mismatches 715, which may be associated with the memory cells being imprinted in different logic states.

[0264] In some cases, a memory device may determine a logic state stored at a memory cell to be evaluated for imprinting using an offset reference voltage 705 that is higher or lower than the default reference voltage 702, and as part of the footprint evaluation, a measured number of mismatches 720 at the offset reference voltage 705 may be compared to an expected number of mismatches 715 at the offset reference voltage. For example, offset reference voltage 705-b may be associated with an expected number of mismatches 715-b when reading a normally operating memory cell (e.g., unimprinted, undegraded, equalized, normalized), offset reference voltage 705-c may be associated with an expected number of mismatches 715-c when reading a normally operating memory cell, offset reference voltage 705-d may be associated with an expected number of mismatches 715-d when reading a normally operating memory cell, and offset reference voltage 705-e may be associated with an expected number of mismatches 715-e when reading a normally operating memory cell.

[0265] In some cases, as part of a footprint detection procedure, a memory device may read a subset of memory cells using an offset reference voltage 705-b. The memory device may determine the measured number of mismatches 720-b resulting from reading the subset of memory cells using the offset reference voltage 705-b, and if at least a portion of the memory cells are imprinted, the measured number of mismatches 720-b may be greater than or equal to the expected number of mismatches 715-b. In some cases, reading the subset of memory cells using the offset reference voltage 705-b may indicate or determine whether a cell that was written to a logic 0 state (e.g., a target logic state) was imprinted in a logic 1 state. For example, if the footprint detection procedure determines that a memory cell was intended to store a logic 0 state but was imprinted in a logic 1 state, the measured number of mismatches 720-b may be greater than the expected number of mismatches 715-b.

[0266] In some cases, as part of a footprint detection procedure, a memory device may read a subset of memory cells using an offset reference voltage 705-c. The memory device may determine the measured number of mismatches 720-c resulting from reading the subset of memory cells using the offset reference voltage 705-c, and if at least a portion of the memory cells are imprinted, the measured number of mismatches 720-c may be less than or equal to the expected number of mismatches 715-c. In some cases, reading the subset of memory cells using the offset reference voltage 705-c may indicate or determine whether cells that have been written to a logic 0 state (e.g., a target logic state) are also imprinted in a logic 0 state. For example, if the footprint detection procedure determines that a memory cell intended to store a logic 0 state is also imprinted in a logic 0 state, the measured number of mismatches 720-c may be less than the expected number of mismatches 715-c.

[0267] In some cases, a memory device may read a subset of memory cells using an offset reference voltage 705-d. The memory device may determine the measured number of mismatches 720-d resulting from reading the subset of memory cells using the offset reference voltage 705-d, and if at least a portion of the memory cells are imprinted, the measured number of mismatches 720-d may be greater than or equal to the expected number of mismatches 715-d. In some cases, reading the subset of memory cells using the offset reference voltage 705-d may indicate or determine whether a cell that was written to a logic 1 state (e.g., a target logic state) was imprinted in a logic 0 state. For example, if an imprint detection procedure determines that a memory cell was intended to store a logic 1 state but was imprinted in a logic 0 state, the measured number of mismatches 720-d may be greater than the expected number of mismatches 715-d.

[0268] In some cases, as part of a footprint detection procedure, a memory device may read a subset of memory cells using an offset reference voltage 705-e. The memory device may determine the measured number of mismatches 720-e resulting from reading the subset of memory cells using the offset reference voltage 705-e, and if at least a portion of the memory cells are imprinted, the measured number of mismatches 720-e may be less than or equal to the expected number of mismatches 715-e. In some cases, reading the subset of memory cells using the offset reference voltage 705-e may indicate or determine whether cells that have been written to a logic 1 state (e.g., a target logic state) are also imprinted in a logic 1 state. For example, if the footprint detection procedure determines that a memory cell intended to store a logic 1 state is also imprinted in a logic 1 state, the measured number of mismatches 720-e may be less than the expected number of mismatches 715-e.

[0269] In some cases, the ability to detect footprints in a memory array based on memory cells intended to store logic states that may be imprinted in the same logic state or in different logic states may depend on an initial distribution of imprinted memory cells (e.g., a number or proportion of memory cells imprinted in a logic 0 state and a number or proportion of memory cells imprinted in a logic 1 state), a set of logic states written to a subset of memory cells (e.g., a set of imprinted logic states, a first set of logic states), a number of imprinted memory cells, or a combination thereof. Thus, to support various examples of footprint assessment, a memory device may be configured to read memory cells according to a default reference voltage 702, one or more offset reference voltages 705, or various combinations thereof, where such conditions may be preconfigured or selected or indicated by a memory device or a host device.

[0270] Fig. 8AAn example of a footprint evaluation process 800-a for supporting footprint management of a memory system according to examples disclosed herein is shown. The operations of the footprint evaluation process 800-a may be performed by a memory device (e.g., referring to Figures 1 to 5 10, memory die 160, memory die 200, or memory device 540) or one or more components of a memory device (e.g., reference Figures 1 to 5 The described device memory controller 155, local memory controller 165, local memory controller 265, memory controller 550, or footprint detection component 560) is implemented or performed. In some examples, one or more of the described techniques can be offloaded to a host device (e.g., by a reference Figure 5 In other words, a system (e.g., system 500) may be configured to perform footprint evaluation process 800-a according to various distributions of operations between memory devices and host devices. The operations of footprint evaluation process 800-a may include reference to Figures 1 to 7 In some examples, the footprint evaluation process 800-a may be configured to evaluate whether one or more memory cells of a memory array have shifted from a de-imprinted hysteresis curve 430 to an imprinted hysteresis curve 440, or any other change in hysteresis or charge mobility characteristics that may be caused by memory cell footprinting.

[0271] The footprint evaluation process 800-a illustrates an example of operations that can be combined in different ways to support multiple possible implementations of a footprint detection procedure, where the logic states of the memory cells used to execute the procedure are unknown at the start of the program (e.g., not enforced before the program starts). For example, before deactivating a footprint detection procedure or evaluation mode triggered by a startup event, a standby event, or otherwise, a footprint detection circuit (e.g., footprint detection component 560, footprint manager 525) or a controller (e.g., memory controller 550, host device controller 520) may not have written to or read data from a memory array for subsequent use in the footprint detection procedure. In some instances, as part of a startup sequence, a footprint detection procedure may be executed, and the memory device may not have stored a record of which logic states are stored at the corresponding memory cells. In some instances, the memory device may not have performed a read operation to determine the logic state of the memory cell after deactivation. The footprint detection procedure can be triggered or initiated based on various criteria, such as powering on the memory device or host device, initializing the memory device or host device, waking up the memory device or host device from a sleep or standby state, based on operational criteria, such as the number or rate of errors (e.g., corrected by an ECC component or algorithm) exceeding or otherwise meeting a threshold, or entering a diagnostic mode or maintenance mode, as well as other criteria.

[0272] At 805, a memory device or host device may identify one or more subsets of memory cells for performing a footprint detection procedure that may store unforced logic states (e.g., unknown logic states, logic states that may not be specific to a footprint detection operation, a set of logic states that may or may not have been imprinted). The subset of memory cells may include a portion of memory cells, such as a portion of a memory array 555, may span more than one array, may be distributed in different portions of one or more memory arrays 555, or a combination thereof. The subset of memory cells may be determined by the memory device or host device after initiating a footprint detection procedure, or may be specifically used (e.g., preconfigured for use) in performing a footprint detection procedure.

[0273] At 810, a memory device or host device may write a set of logic states (e.g., a first set of logic states) to a subset of memory cells of a memory array. The logic states written to the subset of memory cells may be referred to as a set of footprint evaluation logic states, written evaluation logic states, or more generally, footprint evaluation data. The footprint evaluation process 800-a illustrates three examples of writing a set of logic states to support footprint detection evaluation, one or more of which may be selected or performed by a memory device or host device based on various criteria (e.g., configuration of the memory device or host device, pre-configuration of the memory device or host device, selection and command of the memory device by the host device, operating conditions of the host device or memory device, data type, distribution of logic states that may be imprinted, etc.).

[0274] As a first example, at 810-a, the memory device or host device may write a set of solid (e.g., same, equal, identical) logic states to all memory cells in a subset of memory cells. In some cases, this may include writing each cell to represent a logical 0. In other cases, the memory device or host device may write each cell to represent a logical 1. In various examples, the memory device or host device may write a set of solid logic states without reading or determining the current (e.g., imprinted, potentially imprinted) logic state written to each cell.

[0275] As a second example, at 810-b, the memory device or host device may write a set of opposite logic states to the subset of memory cells. In some examples, writing the set of opposite logic states may include performing a read-invert write-back procedure for each cell. For example, for each of the subset of memory cells, the memory device or host device may read the current logic state of the corresponding memory cell (e.g., using the default reference voltage 702), invert the logic state (e.g., determine an opposite or complementary logic state to the read logic state), and write the inverted or opposite logic state back to the corresponding memory cell. In some examples, such techniques may assume or rely on that, at 810-b, a certain amount of charge or other characteristic is stored in the corresponding memory cell that will indicate a potential imprinted logic state.

[0276] As a third example, at 810-c, the memory device or host device may write a mixed set of data to the subset of memory cells. In some cases, writing the mixed set of data may include writing a pattern (e.g., a checkerboard pattern, alternating logic states), writing random data, writing a distribution or ratio of multiple logic states, reading and writing back the same logic state (e.g., a read logic state, an uninverted logic state, based on reading the subset of memory cells using the default reference voltage 702), or other logic states to the memory array subset.

[0277] In some examples, the memory device or host device may record or track which logic states are written to the respective memory cells.The memory device or host device may record or track the first set of logic states for comparison at a later time in a footprint detection procedure (eg, during an evaluation operation).

[0278] In some cases, different portions of one or more memory arrays may be used to perform different portions (e.g., sub-operations) of the footprint evaluation process 800-a. For example, a memory device or host device may write a first portion of a first set of logical states to a first portion of a subset of memory cells, and write a second (e.g., remaining) portion of the first set of logical states to a second portion of the subset of memory cells. In some examples, a memory device or host device may write the same pattern or the same set of logical states to multiple portions of a subset of memory cells. For example, a subset of memory cells may contain multiple sets of repeating logical states. In this regard, a memory device or host device may use different sets of logical states written to different portions of the array to perform different portions of a subsequent read operation (e.g., at 815).

[0279] At 815, the memory device or host device may read the subset of memory cells, which may include reading the logic states that it had written (e.g., test data, evaluation data) or attempted to write to the subset of memory cells at step 810 to obtain a second set of logic states. In some cases, the memory device or host device may write an entire set of test data at 810 and then perform a read operation on the subset of memory cells at 815. In some cases, the memory device or host device may wait for a defined or predetermined duration or delay between writing the test data and reading the test data (e.g., between the write of 810 and the read of 815).

[0280] The memory device or host device may read test data (e.g., read memory cells in a subset) one or more times using one or more reference voltages (e.g., default reference voltage 702 or one or more offset reference voltages 705). In some cases, the reference voltage used to read test data written to a subset of memory cells may depend on (e.g., be selected or determined at least in part based on) an analysis method used to assess whether imprinting has occurred or whether the memory device should perform a recovery procedure.

[0281] At 820, the memory device or host device may perform a footprint assessment method (e.g., to determine whether to perform footprint recovery) based at least in part on the test data read or determined at 815. The footprint assessment process 800-a illustrates three examples for performing footprint detection assessments, one or more of which may be selected and performed based on various criteria (e.g., configuration of the memory device or host device, pre-configuration of the memory device or host device, selection and command of the memory device by the host device, operating conditions of the host device or memory device, data type, distribution of logic states that may be imprinted, etc.).

[0282] At 820-a, the memory device or host device may perform a first analysis method (e.g., method 1), which may include reading a subset of memory cells at two offset reference voltages. For example, the memory device or host device may evaluate or compare data (e.g., a measured number of mismatches 720 or errors) obtained using the first offset reference voltage 705 with data (e.g., a measured number of mismatches 720 or errors) obtained using the second offset reference voltage 705. In some cases, the first and second offset reference voltages 705 may both be lower than or both be higher than the default reference voltage 702. For example, the memory device or host device may obtain a second set of logic states by reading a subset of memory cells using a first offset reference voltage 705 (e.g., offset reference voltage 705-b) that is lower than the default reference voltage 702. The memory device or host device may obtain a third set of logic states by reading a subset of memory cells using a second offset reference voltage 705 (e.g., offset reference voltage 705-c) that is also lower than the default reference voltage.

[0283] In some cases, the first and second offset reference voltages 705 may both be less than the default reference voltage 702, and the second offset reference voltage 705 (e.g., offset reference voltage 705-c) may be less than the first offset reference voltage 705 (e.g., offset reference voltage 705-b, an offset reference voltage 705 that differs more from the default reference voltage 702 than the first offset reference voltage 705). Before obtaining the third set of logic states by reading using the second offset reference voltage 705, the memory device or the host device may obtain the second set of logic states by reading using the first offset reference voltage 705. In these cases, the memory device or host device may not need to rewrite the first set of logic states to the subset of memory cells because the expected number of mismatches 715 resulting from reading at the second offset reference voltage 705 may be greater than the expected number of mismatches 715 resulting from reading at the first offset reference voltage 705, or because applying the first offset reference voltage 705 may be associated with a smaller change in charge state or polarization state than applying the second offset reference voltage 705 (e.g., the first offset reference voltage is associated with a non-destructive read operation and the first offset reference voltage is associated with a read operation that may not adversely affect the results of a read operation using the second offset reference voltage). In such examples, the memory device may or may not perform a rewrite operation between a read at the first offset reference voltage 705 and a read at the second offset reference voltage 705.

[0284] In some cases, the memory device or host device may read at the second offset reference voltage 705 (e.g., an offset reference voltage 705 that differs more from the default reference voltage 702 than the first offset reference voltage) and then read at the first offset reference voltage 705. In these cases, the memory device may or may not rewrite the first set of logic states to the subset of memory cells after reading using the second offset reference voltage 705 and before reading using the first offset reference voltage 705 (e.g., depending on whether the logic states stored by the subset of memory cells have been disturbed by the read at the second offset reference voltage 705). For example, if reading using the second offset reference voltage 705 may introduce a greater number of mismatches or errors due to reading at an offset reference voltage 705 that is significantly different from the default reference voltage 702, or if reading using the second offset reference voltage 705 is associated with a change in the charge state or polarization state of the memory cells (e.g., when reading at the second offset reference voltage 705 is associated with a decrease in polarization of one or more of the memory cells, when reading using the second offset reference voltage may affect the results of reading using the first offset reference voltage), then the memory device may rewrite the first set of logic states. In some examples, different subsets of memory cells may be used for reading at different offset reference voltages 705 (e.g., a first subset of memory cells is used for reading at a first offset reference voltage 705 and a second subset of memory cells is used for reading at a second offset reference voltage 705, where the first and second subsets are different or non-overlapping), which may resolve any issues associated with reading the same memory cells at different reference voltages.

[0285] In some cases, first and second offset reference voltages 705 may both be greater than default reference voltage 702, and second offset reference voltage 705 (e.g., offset reference voltage 705-e) may be greater than first offset reference voltage 705 (e.g., offset reference voltage 705-d, an offset reference voltage 705 that differs more from default reference voltage 702 than first offset reference voltage 705). Before obtaining a third set of logic states by reading using second offset reference voltage 705, a memory device or a host device may obtain a second set of logic states by reading using first offset reference voltage 705. In these cases, the memory device or host device may not need to rewrite the first set of logic states to the subset of memory cells because the expected number of mismatches 715 resulting from reading at the second offset reference voltage 705 may be greater than the expected number of mismatches 715 resulting from reading at the first offset reference voltage 705, or because applying the first offset reference voltage 705 may be associated with a smaller change in charge state or polarization state than applying the second offset reference voltage 705 (e.g., the first offset reference voltage is associated with a non-destructive read operation and the first offset reference voltage is associated with a read operation that may not adversely affect the results of a read operation using the second offset reference voltage). In such examples, the memory device may or may not perform a rewrite operation between reading at the first offset reference voltage 705 and reading at the second offset reference voltage 705.

[0286] In some cases, the memory device or host device may read at the second offset reference voltage 705 (e.g., an offset reference voltage 705 that differs more from the default reference voltage 702 than the first offset reference voltage) and then read at the first offset reference voltage 705. In these cases, the memory device may or may not rewrite the first set of logic states to the subset of memory cells after reading using the second offset reference voltage 705 and before reading using the first offset reference voltage 705 (e.g., depending on whether the logic states stored by the subset of memory cells have been disturbed by the read at the second offset reference voltage 705). For example, if reading using the second offset reference voltage 705 may introduce a greater number of mismatches or errors due to reading at an offset reference voltage 705 that is significantly different from the default reference voltage 702, or if reading using the second offset reference voltage 705 is associated with a change in the charge state or polarization state of the memory cells (e.g., when reading at the second offset reference voltage 705 is associated with a decrease in polarization of one or more of the memory cells, when reading using the second offset reference voltage may affect the results of reading using the first offset reference voltage), then the memory device may rewrite the first set of logic states. In some examples, different subsets of memory cells may be used for reading at different offset reference voltages 705 (e.g., a first subset of memory cells is used for reading at a first offset reference voltage 705 and a second subset of memory cells is used for reading at a second offset reference voltage 705, where the first and second subsets are different or non-overlapping), which may resolve any issues associated with reading the same memory cells at different reference voltages.

[0287] The memory device or host device may determine a first number of mismatches or errors (e.g., a first measured number of mismatches 720) by comparing the second set of logic states to the first set of logic states. For example, when the logic state read from the memory cell at 815 does not match the logic state written to the memory cell at 810 (e.g., a target written logic state, a target logic state), a mismatch or error may be counted. Such a mismatch may indicate that the memory cell has been imprinted (e.g., subjected to a change from the unimprinted hysteresis curve 430 to the imprinted hysteresis curve, prior to the write operation at 810), and in response to the write operation at 810, failed to change to the written logic state, or changed back or flipped back to the imprinted logic state. Similarly, the memory device or host device may determine a second number of mismatches or errors (e.g., a second measured number of mismatches 720) by comparing the third set of logic states to the first set of logic states (e.g., written at 810 or rewritten after determining the second set of logic states).

[0288] In some cases, the memory device or host device may determine a difference between the first number of mismatches or errors and the second set of mismatches or errors (e.g., a difference between a first measured number of mismatches 720 and a second expected number of mismatches 720), and compare this determined or measured difference to an expected difference between mismatches or errors associated with reads at the first and second offset reference voltages 705 (e.g., a difference between a corresponding first expected number of mismatches 715 and a corresponding second expected number of mismatches 715). For example, the memory device or host device may store or otherwise identify a first expected number of mismatches or errors associated with reads at the first offset reference voltage 705 (e.g., an expected number of mismatches 715-b or an expected number of mismatches 715-d) and a second expected number of mismatches or errors associated with reads at the second offset reference voltage 705 (e.g., an expected number of mismatches 715-c or an expected number of mismatches 715-e). Thus, the memory device or host device can determine an expected difference based on comparing a first expected number of mismatches or errors with a second expected number of mismatches or errors (e.g., the difference between the expected number of mismatches 715-c and the expected number of mismatches 715-b, the difference between the expected number of mismatches 715-e and the expected number of mismatches 715-d).

[0289] The memory device or host device may determine to perform a recovery operation based on comparing the difference of the measured conditions of the two offset reference voltages 705 to the difference of the expected conditions of the two offset reference voltages 705. If the measured difference deviates (e.g., is above or below) the expected difference by a defined amount or otherwise satisfies a threshold, then a footprint recovery operation will be initiated or performed. In one example, if the difference between the measured number of mismatches 720-c and the measured number of mismatches 720-b is less than the difference between the expected number of mismatches 715-c and the expected number of mismatches 715-b or is less than the difference between the expected number of mismatches 715-c and the expected number of mismatches 715-b by a certain threshold amount, then a footprint recovery operation will be performed.

[0290] In some cases, the memory device or host device may determine a measured gradient (e.g., a slope or another gradient, whether linear or not, such as a nonlinear regression) based on the first number of mismatches or errors and the second set of mismatches or errors (e.g., the slope between the first measured number of mismatches 720 and the second measured number of mismatches 720), and compare this determined or measured gradient to an expected gradient between mismatches or errors associated with reads at the first and second offset reference voltages 705 (e.g., the slope between the corresponding first expected number of mismatches 715 and the corresponding second expected number of mismatches 715).

[0291] For example, the memory device or host device may store or otherwise identify an expected gradient between mismatches or errors at two offset reference voltages 705 (e.g., the slope between the expected number of mismatches 715-c and 715-b, respectively, at offset reference voltages 705-c and 705-b), and the memory device or host device may determine whether to perform a recovery operation based on comparing a measured gradient between mismatches or errors at the two offset reference voltages 705 (e.g., the slope between the measured number of mismatches 720-c and 720-b, respectively, at offset reference voltages 705-c and 705-b) to the expected gradient. In one example, if the slope between the measured number of mismatches 720-c and the measured number of mismatches 720-b is lower than the slope between the expected number of mismatches 715-c and the expected number of mismatches 715-b or lower than the slope between the expected number of mismatches 715-c and the expected number of mismatches 715-b by a certain threshold amount, then a footprint recovery operation is to be performed. In some examples, such techniques may be beneficial during a startup sequence because the slope or gradient may provide good observability of possible footprint characteristics, and memory devices may be particularly sensitive to footprint when powered down or otherwise maintaining logic states or charge states in a memory array.

[0292] In another example, the expected number of mismatches 715 can be calculated or otherwise determined (e.g., dynamically) based on the measured number of mismatches 720 and the expected slope. Such a technique may illustrate extrapolating from a set of measured mismatches to identify an expected number of mismatches based on a known slope and a known difference between an evaluated reference voltage, where another measured number of mismatches can be compared to the calculated expected value. If the second measured number of mismatches 720 and the extrapolated expected number of mismatches 715 differ by a certain threshold amount (e.g., 16x), then a recovery operation can be initiated. Such a technique may be less computationally intensive than direct slope calculation or comparison, and may be beneficial when the slope is easily understood or characterized, which may support hard-coding or otherwise configuring various aspects of footprint detection.

[0293] At 820-b, the memory device or host device may perform a second analysis method (e.g., Method 2), which may include reading a subset of memory cells using a default or operational reference voltage (e.g., default reference voltage 702). The memory device or host device may compare data obtained by reading at the default reference voltage (e.g., the measured number of mismatches 720-a) to a threshold, where the threshold may be related to an expected number of errors (e.g., related to an expected number of mismatches 715-a). In some cases, reading the subset of memory cells using the default reference voltage may be expected to produce no mismatch errors, or may be expected to produce substantially zero errors.

[0294] In these examples, the memory device or host device may set the threshold to zero or substantially zero mismatches or errors, and in the event that this threshold is satisfied (e.g., met or exceeded), it may be determined that a footprint has occurred or a recovery operation is to be performed. In some examples, the memory device or host device may set the threshold based on a tolerance for performing read operations using the default reference voltage 702. For example, if the tolerance associated with the default reference voltage 702 specifies an allowed or expected number of read errors that occur when reading a defined number of cells, then the threshold may be set based on this tolerance (e.g., higher, lower, equal, etc.). In this regard, the memory device or host device may determine that a footprint has occurred when the number of errors generated by reading using the default reference voltage exceeds the tolerance.

[0295] In some cases, the associated threshold (e.g., associated with the difference between the expected number of mismatches 715 and the measured number of mismatches 720) may be based on the ECC operation performed by the memory device. In this regard, the threshold may be at or above the number of errors that can be corrected by the ECC operation for the subset of memory cells. For example, if the ECC operation uses a single error correction (SEC) codeword, then the threshold may be set to one error. In other examples, the threshold may be set to a level below the number of errors that can be corrected by the ECC operation for the subset of memory cells.

[0296] At 820-c, the memory device or host device may perform a third analysis method (e.g., Method 3), which may include reading a subset of memory cells using one or more offset reference voltages 705. The memory device or host device may compare data obtained using the one or more offset reference voltages 705 (e.g., a measured number of mismatches 720) to an expected number of mismatches 715 associated with reading using the same one or more offset reference voltages 705. In some cases, the memory device or host device may obtain a second set of logic states by reading using a first reference voltage (e.g., one of the offset reference voltages 705) and determine the number of errors or mismatches between the second set of logic states and the first set of logic states (e.g., a measured number of mismatches 720). The memory device or host device may compare the measured number of mismatches 720 to an expected number of mismatches 715 (e.g., for a corresponding offset reference voltage 705), and determine, based on the comparison, whether a footprint has occurred or whether a recovery operation is to be performed. For example, if for one or more of the evaluated offset reference voltages 705, the measured number of mismatches 720 is greater or less than the corresponding expected number of mismatches 715 by a defined multiple or threshold amount, the memory device may determine that a footprint has occurred or to perform a recovery procedure.

[0297] In some cases, the memory device or host device may only determine the measured number of mismatches 720 at a single offset reference voltage 705. For example, when the subset of memory cells already contained a random or mixed distribution of logic states prior to initiating the footprint detection procedure (e.g., prior to 810), and when writing the first set of logic states (e.g., at 810) already included writing a random or mixed data distribution to the subset of memory cells, determining errors at a single offset reference voltage 705 may be performed (e.g., selected by the memory device or host device).

[0298] In some cases (e.g., when footprint evaluation is performed at multiple offset reference voltages 705), the memory device or host device may determine a second measured number of mismatches 720 using a second offset reference voltage 705, which may use a different subset of memory cells than the first measured number used to determine the mismatch 720, or the same subset of memory cells (e.g., when performing an overwrite operation, such as a footprint evaluation overwrite, between evaluations at different offset reference voltages 705). For example, the memory device or host device may write a third set of logic states to a second subset of memory cells of the memory array, and obtain a fourth set of logic states by reading the third set of logic states using the second offset reference voltage 705. This may include using one offset reference voltage 705 that is less than the default reference voltage 702 and one offset reference voltage 705 that is greater than the default reference voltage 702. For example, the first offset reference voltage 705 may be less than the default reference voltage 702 (e.g., the offset reference voltage 705-b or the offset reference voltage 705-c), and the second offset reference voltage 705 may be greater than the default reference voltage 702 (e.g., the offset reference voltage 705-d or the offset reference voltage 705-e). Thus, a first measured number of mismatches 720 may be obtained by reading the first subset of memory cells using the first offset reference voltage 705, and a second measured number of mismatches 720 may be obtained by reading the second subset of memory cells using the second offset reference voltage 705.

[0299] The memory device or host device may determine whether an imprint has occurred, or whether to perform a recovery operation, based on comparing the first measured number of mismatches 720 to the first expected number of mismatches 715, based on comparing the second measured number of mismatches 720 to the second expected number of mismatches 715, or a combination thereof. For example, if the first or second measured number of mismatches 720 is greater or less than the corresponding expected number of mismatches 715 by a defined multiple, the memory device or host device may determine that an imprint has occurred, or perform or trigger a recovery procedure.

[0300] Figure 8BAn example of a footprint evaluation process 800-b for supporting footprint management of a memory system according to examples disclosed herein is shown. The footprint evaluation process 800-b may implement or execute reference Fig. 8A The features of the footprint evaluation process 800-b may be stored in a memory device (e.g., a reference Figures 1 to 5 10, memory die 160, memory die 200, or memory device 540) or one or more components of a memory device (e.g., reference Figures 1 to 5 In some examples, one or more of the described techniques may be offloaded to a host device (e.g., a host computer). Figure 5 In other words, a system (e.g., system 500) may be configured to perform footprint evaluation process 800-b according to various distributions of operations between memory devices and host devices. The operations of footprint evaluation process 800-b may include reference to Figures 1 to 8A In some examples, the footprint evaluation process 800-b may be configured to evaluate whether one or more memory cells of a memory array have shifted from a de-imprinted hysteresis curve 430 to an imprinted hysteresis curve 440, or any other change in hysteresis or charge mobility characteristics that may be caused by memory cell footprinting.

[0301] The footprint evaluation process 800-b illustrates an example of operations that may be combined in various ways to support multiple possible implementations of a footprint detection procedure, wherein the logic states of the memory cells used to execute the procedure are known at the start of the procedure (e.g., enforced or otherwise configured prior to the start of the procedure). For example, prior to deactivating a footprint detection procedure or evaluation mode triggered by a startup event, a standby event, or otherwise, a footprint detection circuit (e.g., footprint detection component 560, footprint manager 525) or a controller (e.g., memory controller 550, host device controller 520) may have specifically written or enforced data on the memory array for subsequent use in the footprint detection procedure, as described herein. The footprint detection procedure may be triggered or initiated based on various criteria, such as powering on a memory device or host device, initializing a memory device or host device, waking up a memory device or host device from a sleep or standby state, based on operating criteria, such as the number or rate of errors (e.g., corrected by an ECC component or algorithm) exceeding or otherwise satisfying a threshold, or entering a diagnostic mode or maintenance mode, and other criteria.

[0302] At 850, a memory device or host device may identify one or more subsets of memory cells for performing a footprint detection procedure that may be storing forced or otherwise known logic states (e.g., a set of logic states that may or may not have been imprinted). The subset of memory cells may include a portion of memory cells, such as a portion of an array, may span more than one array, may be distributed in different portions of one or more arrays, or a combination thereof. The subset of memory cells may have stored logic states that were forced by the memory device prior to initiating the footprint detection procedure. For example, to support the footprint detection procedure, the memory device or host device may have written a recoded or tracked set of logic states to the subset of memory cells (e.g., prior to deactivation, or otherwise prior to initiating the footprint detection procedure), as described herein. Thus, in the example of 800-b, the memory device may have a known data background that may or may not have been imprinted, which may facilitate certain aspects of footprint detection, including those described herein.

[0303] In one example, wear leveling can be continuously operated on the memory device, which can be used to implement a known data pattern. For example, in each blank row or page that is opened or available, the wear leveling operation can include or otherwise enable writing a checkerboard logic pattern to the blank row or page. The memory device can track which rows or pages have been written with the checkerboard pattern, so that blank rows or pages can be selected for imprint evaluation with the understanding that the blank rows or pages have been written with the checkerboard pattern. In other examples, available rows or pages can be written with solid data patterns or other patterns or ratios of data states. In other examples, the known data pattern can be enforced in a dedicated portion of the memory array, which can be overwritten or reversed over time to avoid non-representative imprints or other conditions in the dedicated portion of the memory array.

[0304] At 855, the memory device or host device may write a set of logic states (e.g., a first set of logic states) to a subset of memory cells of the memory array. The logic states written to the subset of memory cells may be referred to as a set of footprint evaluation logic states, written evaluation logic states, or more generally, footprint evaluation data. The footprint evaluation process 800-b illustrates three examples of writing a set of logic states to support footprint detection evaluation, one or more of which may be selected or performed by the memory device or host device based on various criteria (e.g., configuration of the memory device or host device, pre-configuration of the memory device or host device, selection and command of the memory device by the host device, operating conditions of the host device or memory device, data type, distribution of logic states that may be imprinted, etc.).

[0305] As a first example, at 855-a, the memory device may write a set of opposite solid logical states to the subset of memory cells. This may be done if, prior to deactivation, the memory device or host device had already written a first set of solid or identical logical states to the subset of memory cells. For example, if a set of all logical zeros had been written to the subset of memory cells prior to deactivation, then at 855-a, the memory device or host device may write all logical ones to the same subset of memory cells. In various examples, the write of 855-a may or may not include reading the initial state of the subset of memory cells, as the subset of memory cells may have remained in a forced data mode.

[0306] As a second example, at 855-b, the memory device or host device may write a set of identical solid logical states to the subset of memory cells. This may be done if, prior to deactivation, the memory device or host device had written a first set of solid or identical logical states to the subset of memory cells. For example, if a set of all logical zeros had been written to the subset of memory cells prior to deactivation, then at 855-a, the memory device may rewrite all logical zeros to the same subset of memory cells. In some cases, because the memory cells are evaluated in the same logical state that may be imprinted, use of this approach may be associated with initiating or triggering a recovery operation after fewer mismatches than expected are identified.

[0307] As a third example, at 855-c, the memory device or host device may write a defined (e.g., mixed) set of data to the subset of memory cells. In some cases, writing the mixed set of data may include writing a certain pattern (e.g., a checkerboard pattern, alternating logic states), writing random data, writing a certain distribution or ratio of multiple logic states, reading and writing back the same logic state (e.g., the read logic state, the uninverted logic state, based on reading the subset of memory cells using the default reference voltage 702), or other logic states to the subset of the memory array.

[0308] As a fourth example, at 855-d, the memory device or host device may write a set of solid logical states to a subset of memory cells. In some cases, this may include writing each cell to represent a logical 0. In other cases, the memory device or host device may write each cell to represent a logical 1. The memory device or host device may write a set of solid logical states without reading or determining the current logical state written to each cell.

[0309] In some examples, the memory device or host device may record or track which logic states are written to the respective memory cells.The memory device or host device may record or track the first set of logic states for comparison at a later time in a footprint detection procedure (eg, during an evaluation operation).

[0310] In some cases, different portions of one or more memory arrays may be used to perform different portions (e.g., sub-operations) of the footprint evaluation process 800-b. For example, a memory device or host device may write a first portion of a first set of logical states to a first portion of a subset of memory cells, and write a second (e.g., remaining) portion of the first set of logical states to a second portion of the subset of memory cells. In some examples, a memory device or host device may write the same pattern or the same set of logical states to multiple portions of a subset of memory cells. For example, a subset of memory cells may contain multiple sets of repeating logical states. In this regard, a memory device or host device may use different sets of logical states written to different portions of the array to perform different portions of a subsequent read operation (e.g., at 815).

[0311] At 860, the memory device or host device may read the subset of memory cells, which may include reading the logic states that it had written (e.g., test data, evaluation data) or attempted to write to the subset of memory cells at step 850 to obtain a second set of logic states. In some cases, the memory device or host device may write an entire set of test data at 850 and then perform a read operation on the subset of memory cells at 860. In some cases, the memory device or host device may wait for a defined or predetermined duration or delay between writing the test data and reading the test data (e.g., between the write of 855 and the read of 860).

[0312] The memory device or host device may read test data (e.g., read memory cells in a subset) one or more times using one or more reference voltages (e.g., default reference voltage 702 or one or more offset reference voltages 705). In some cases, the reference voltage used to read test data written to a subset of memory cells may depend on (e.g., be selected or determined at least in part based on) an analysis method used to assess whether imprinting has occurred or whether the memory device should perform a recovery procedure.

[0313] At 865, the memory device or host device may perform a footprint assessment method (e.g., to determine whether to perform footprint recovery) based at least in part on the test data read or determined at 860. Footprint assessment process 800-b illustrates three examples for performing footprint detection assessment (e.g., method 1, method 2, and method 3, which may include reference to Fig. 8A), one or more of which may be selected and executed based on various criteria (e.g., configuration of the memory device or host device, pre-configuration of the memory device or host device, selection and command of the memory device by the host device, operating conditions of the host device or memory device, data type, distribution of logical states that may be imprinted, etc.). For example, step 865-a may include one or more of the techniques described with reference to step 820-a, step 865-b may include one or more of the techniques described with reference to step 820-b, and step 865-c may include one or more of the techniques described with reference to step 820-c. As described herein, any functionality associated with any of Method 1, Method 2, or Method 3 may be recombined with any other functionality described as being associated with any other method.

[0314]

[0315]

[0316] Table 1 - Array Imprinting and Blotting Evaluation Scenarios

[0317] Table 1 shows scenarios anticipated by combining the imprinted data conditions, imprinted data distributions, evaluation data conditions, and selection schemes for evaluation methods described with reference to footprint evaluation processes 800-a and 800-b, any of which may be supported by operations at a memory device, operations at a host device, or coordinated operations at a memory device. Each of the described scenarios may have various advantages or other considerations for implementing footprint management in a memory system.

[0318] With respect to the examples described for imprinted data conditions, in some cases, forced data can support improved imprint detection because known or otherwise assumed imprint conditions can support a good understanding of potential imprinted conditions. However, unforced data conditions (e.g., random data, data not specifically configured for imprint management) can be relatively faster or more power efficient because the system may not be required to perform a forced write operation. In some examples, forced data conditions can be applied in limited circumstances (e.g., during shutdown or idle periods of the memory device), which can mitigate the slowdown or power consumption associated with forced data patterns. Furthermore, in some cases, unforced data conditions can be random enough to support appropriate observability of imprint conditions. For example, for n pages, the variance of a "worst case" condition compared to a solid data pattern can be equal to 1 / 2 nWhen the data condition is associated with a wear leveling operation using (32 x 8) pages, the probability of more than 70% of the data being in the same state is roughly 1 / 257, or almost zero. Therefore, in some cases of 256 pages, it may be reasonable to assume random data regardless of what is actually written. Therefore, while the described techniques may support a solid unforced imprinted data condition, such a condition is unlikely.

[0319] With respect to the examples described for the imprinted data distribution, the mixed data distribution may support relatively greater observability under conditions where the imprint phenomenon may have relatively consistent probabilities for different logic states or when the imprint detection method relies on different offset reference voltages 705 on either side of the default reference voltage (e.g., according to the example of evaluation method 3). In some examples, solid data may provide advantages when the imprint phenomenon or occurrence rate is relatively biased toward one logic state, or when the evaluation method does not rely on different offset reference voltages 705 on either side of the default reference voltage (e.g., according to the examples of evaluation methods 1, 2, or 3). In some cases, under a solid imprinted data distribution or an opposite state or same state evaluation data distribution, evaluation method 2 or 3 may be more appropriate than evaluation method 1 because the solid imprinted data distribution may not be associated with a kink feature 740, and therefore may not be associated with a detectable change in slope after imprinting (e.g., may not support detection of method 1).

[0320] With respect to the examples described for evaluation data conditions, in some cases, a solid evaluation data pattern may support relatively greater or deeper observability for both solid and mixed embossed data distributions, depending on the evaluation method used. In some cases, it may be advantageous to match a solid embossed data pattern with an opposite solid evaluation pattern, such as when performing a single-sided configuration of evaluation method 3. In some cases, when evaluating an embossment of multiple states, a mixed evaluation data pattern may be preferred, and the mixed data may be preconfigured or selectively configured to be the same state, different states, or unforced (e.g., random). In some cases, the embossed logic state may not be known when it is not enforced (e.g., when the embossment itself causes the stored logic state to be lost), in which case it may be preferred to apply a forced data condition when relying on an opposite state evaluation data condition.

[0321] With respect to the examples described for the evaluation methods, by performing various evaluations related to slope or gradient (e.g., between conditions at different reference voltages), the evaluation method 1 can provide relatively powerful observability of footprint features (e.g., related to kinked imprinted features 740), which can support distinguishing memory cell imprints from other faults or phenomena. Such methods can be supported by relatively complex curve fitting or chip-level evaluations between measured slopes and expected slopes, or expected number of mismatches identified at least in part based on the measured number of mismatches and expected slopes (e.g., for different reference voltages).

[0322] In some instances, if both logic states have similar sensitivity to imprint, or if a relatively robust calculation is desired, then evaluation method 1 may be configured with slope or gradient calculations on both sides of default reference voltage 702. In some instances, if one logic state is more sensitive to imprint than the other logic state, or if a single slope or gradient calculation provides suitable observability, then evaluation method 1 may be configured with slope or gradient calculations on one side of default reference voltage 702. In some cases, evaluation method 3 may be preconfigured to be performed with a single slope or gradient calculation, or may be selectively performed with a single slope or gradient calculation based on imprint data (e.g., when only one side of default reference voltage 702 is read to indicate whether imprinting has occurred, when only one condition of an imprinted logic state or an evaluated logic state is expected).

[0323] In some examples, Assessment Method 2 may be used with a mismatch threshold that is below a lower limit of ECC correction (e.g., below the fault correction capability of the ECC algorithm or a threshold within the fault correction capability of the ECC algorithm), and the system may be configured to permit a certain non-zero level or rate of mismatch or ECC correction before initiating a print recovery operation. Although such techniques may have relatively low visibility or observability to specific failure modes associated with prints (e.g., because Assessment Method 2 may not be able to distinguish between hard faults and print faults), such techniques may be relatively fast and effective. In some cases, Method 2 may have unmeasured results or otherwise lack sensitivity, but a recovery operation may be triggered after any mismatch is detected using Assessment Method 2. In other words, using Assessment Method 2 may be relatively conservative for imprints (e.g., it may be possible to trigger or initiate print recovery more frequently than necessary).

[0324] In some instances, evaluation method 3 may be associated with margining the reference voltage level to a level of a non-zero number of expected mismatches. In some instances, the calculations for evaluation method 3 may be similar to those of evaluation method 2, but the use of an offset reference voltage 705 may provide better visibility or observability of the footprint compared to the use of a default reference voltage in evaluation method 2. In some cases, if the memory device 540 degrades during its operation, then the expected number of mismatches may be expected to increase accordingly, which may not have a clear relationship to the footprint. Therefore, later in the operational life, it may be expected that performing evaluation method 3 will have false positives regarding the footprint (e.g., erroneously detecting a read window collapse due to wear), which may trigger or initiate footprint recovery more frequently than desired. However, in some instances, the various thresholds for evaluat...

Claims

1. A memory system, comprising: one or more memory arrays comprising a group of memory cells; as well as A circuit system is coupled to the one or more memory arrays and is configured to cause the memory system to: receiving a command to execute a footprint recovery procedure configured to mitigate a tendency of the group of memory cells to store a respective first logic state instead of a respective second logic state; initiating the footprint recovery procedure based at least in part on receiving the command; transmitting an indication of a status of the footprint recovery procedure based at least in part on initiating the footprint recovery procedure; receiving an instruction to suspend the footprint recovery procedure after initiating the footprint recovery procedure; pausing the footprint recovery procedure based at least in part on receiving the indication; as well as The footprint recovery procedure is resumed after pausing the footprint recovery procedure.

2. The memory system of claim 1 , wherein the circuit system is further configured to cause the memory system to: detecting the propensity of the group of memory cells to store a corresponding first logic state instead of a corresponding second logic state; and An indication of the tendency is transmitted, wherein the command is received based at least in part on transmitting the indication of the tendency. 3 . The memory system of claim 1 , wherein the indication of the status of the footprint recovery procedure comprises an indication that the footprint recovery procedure is started or that the footprint recovery procedure is ended. 4 . The memory system of claim 1 , wherein the indication of the status of the footprint recovery procedure comprises an indication of whether the footprint recovery procedure was successful.

5. The memory system of claim 1, wherein the circuit system is further configured to cause the memory system to: An error correction failure is determined based at least in part on initiating the footprint recovery procedure, wherein the indication of the status of the footprint recovery procedure includes an indication to perform replacement of data associated with the set of memory cells based at least in part on the error correction failure.

6. The memory system of claim 1, wherein the indication of the status of the footprint recovery procedure comprises an indication that the one or more memory arrays are unavailable for access operations during the footprint recovery procedure.

7. The memory system of claim 1, wherein the circuit system is further configured to cause the memory system to: receiving an indication of a duration available for performing the footprint recovery procedure; and The footprint recovery procedure is performed based at least in part on the available duration.

8. A method comprising: detecting, at a host device, a condition indicative of a propensity of a memory cell of a memory device to store a corresponding first logic state instead of a corresponding second logic state; transmitting from the host device to the memory device a command for the memory device to perform a footprint recovery procedure for alleviating a tendency of the memory cell to store a corresponding first logic state instead of a corresponding second logic state; receiving, at the host device, an indication of a status of the footprint recovery procedure based at least in part on transmitting the command; Based at least in part on the indication of the status, transmitting an indication to suspend the footprint recovery procedure; and One or more access commands are transmitted to the memory device based at least in part on transmitting the indication to suspend the footprint recovery procedure.

9. The method according to claim 8, further comprising: A duration, temperature, or access pattern of storing a logic state is detected, wherein the condition indicative of the tendency to store the corresponding first logic state instead of the corresponding second logic state is detected based at least in part on the duration, temperature, or access pattern of storing the logic state.

10. The method according to claim 8, further comprising: An indication of an initial startup of the memory device is detected, wherein the condition indicative of the tendency to store the respective first logic state instead of the respective second logic state is detected based at least in part on the indication of the initial startup of the memory device.

11. The method of claim 8, wherein detecting the condition indicating the tendency to store the respective first logic state instead of the respective second logic state comprises: An indication of the tendency is received from the memory device.

12. The method of claim 8, wherein the indication of the status of the footprint recovery procedure comprises an indication that the memory device is executing the footprint recovery procedure, the method further comprising: Access operations of the memory device are suspended based at least in part on the indication that the memory device is executing the footprint recovery procedure.

13. The method of claim 8, wherein the indication of the status of the footprint recovery procedure comprises an indication that the memory device is executing the footprint recovery procedure, the method further comprising: Access operations of the memory device are performed at a slower rate based at least in part on the indication that the memory device is performing the footprint recovery procedure.

14. The method of claim 8, wherein the indication of the status of the footprint recovery procedure comprises an indication of a failure of the footprint recovery procedure, the method further comprising: An access operation of a second memory device is performed based at least in part on the indication of a failure of the footprint recovery procedure.

15. The method of claim 8, wherein the indication of the status of the footprint recovery procedure comprises an indication that the footprint recovery procedure was successful, the method further comprising: One or more access commands are transmitted to the memory device based at least in part on the indication that the footprint recovery procedure was successful.

16. A method comprising: receiving a command to execute a footprint recovery procedure for mitigating a tendency of a group of memory cells to store a corresponding first logic state instead of a corresponding second logic state; initiating the footprint recovery procedure based at least in part on receiving the command; transmitting an indication of a status of the footprint recovery procedure based at least in part on initiating the footprint recovery procedure; receiving an instruction to suspend the footprint recovery procedure after initiating the footprint recovery procedure; pausing the footprint recovery procedure based at least in part on receiving the indication; as well as The footprint recovery procedure is resumed after pausing the footprint recovery procedure.

17. The method according to claim 16, further comprising: detecting the tendency of the group of memory cells to store a corresponding first logic state instead of a corresponding second logic state; as well as An indication of the tendency is transmitted, wherein the command is received based at least in part on transmitting the indication of the tendency.

18. A method comprising: Determining improving the ability of a group of memory cells to switch between storing different logical states; modifying an operating parameter of the set of memory cells based at least in part on determining that the ability of the set of memory cells to switch between storing different logical states is improved; as well as The set of memory cells is operated based at least in part on the modified operating parameters.

19. The method according to claim 18, further comprising: The group of memory cells is determined to be imprinted in respective first logic states, wherein determining to improve the ability of the group of memory cells to switch between storing different logic states is based at least in part on determining the group of memory cells to be imprinted.

20. The method of claim 18, wherein: The operating parameters include a temporal frequency of refresh operations for the set of memory cells; and Modifying the operating parameters includes increasing the temporal frequency of refresh operations for the group of memory cells.

21. The method of claim 18, wherein: The refresh procedure of the group of memory cells includes at least one refresh operation of each memory cell in the group of memory cells; The operating parameters include a number of refresh operations for each refresh procedure for the set of memory cells; and Modifying the operating parameters includes increasing the number of refresh operations for each refresh procedure for the set of memory cells.

22. The method of claim 21, further comprising: The number of refresh operations are performed by reading respective first logic states from the group of memory cells and writing respective second logic states to the group of memory cells.

23. The method of claim 18, wherein: The operating parameters include a number of commanded refresh operations that the memory device can skip for the set of memory cells; and Modifying the operating parameters includes reducing the number of commanded refresh operations that the memory device can skip for the set of memory cells.

24. The method of claim 18, wherein: The operating parameters include a magnitude of a voltage used to perform a read operation, a write operation, or a refresh on the set of memory cells; and Modifying the operating parameter includes changing the magnitude of the voltage used to perform a read operation, a write operation, or a refresh operation on the group of memory cells.

25. The method of claim 18, wherein: An access procedure of a memory cell in the group of memory cells includes a read operation and a write operation; The operating parameters include a magnitude of a voltage applied to the memory cell at a time between the read operation and the write operation; and Modifying the operating parameter includes changing the magnitude of the voltage applied to the memory cell at the time between the read operation and the write operation.

26. The method of claim 18, wherein: The operating parameters include a temporal frequency of an error correction procedure for the set of memory cells; and Modifying the operating parameters includes increasing the temporal frequency of the error correction procedure for the group of memory cells.

27. The method of claim 18, further comprising: after modifying the value of the operating parameter, determining that the group of memory cells have been operated at least in part based on the modified value of the operating parameter for a duration that satisfies a threshold amount of time; based at least in part on determining that the duration satisfies the threshold amount of time, changing the value of the operating parameter to a second value; and Based at least in part on the second value of the operating parameter, the set of memory cells is operated.

28. The method of claim 18, further comprising: after modifying the value of the operating parameter, determining that a number of refresh operations performed on the group of memory cells satisfies a threshold; changing the value of the operating parameter to a second value based at least in part on determining that the number of refresh operations satisfies the threshold; as well as Based at least in part on the second value of the operating parameter, the set of memory cells is operated.

29. The method of claim 18, further comprising: determining to operate a memory device including the set of memory cells in a maintenance mode, wherein: determining to increase the ability of the set of memory cells to switch between storing different logical states is based at least in part on determining to operate the memory device in the maintenance mode; and Operating the memory device in the maintenance mode includes operating the set of memory cells based at least in part on the modified operating parameters.

30. The method of claim 18, wherein: The operating parameters include a duration of a refresh operation of the set of memory cells; and Modifying the operating parameters includes increasing the duration of a refresh operation of the group of memory cells, the method further comprising: During a refresh operation of a memory cell in the group of memory cells, a set of voltage pulses is applied to the memory cell.

31. The method of claim 30, wherein: A first subset of the set of voltage pulses has a first polarity; and A second subset of the set of voltage pulses has a second polarity.

32. A memory system comprising: one or more memory arrays comprising a group of memory cells; as well as A circuit system is coupled to the one or more memory arrays and is configured to cause the memory system to: Determining improving the ability of a group of memory cells to switch between storing different logical states; modifying an operating parameter of the set of memory cells based at least in part on determining that the ability of the set of memory cells to switch between storing different logical states is improved; as well as The set of memory cells is operated based at least in part on the modified operating parameters.

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