DMA transmission system, method and device, storage medium and program product

Abstract

The embodiment of the invention provides a DMA transmission system, method and device, a storage medium and a program product. The method comprises the steps that DMA configuration information of a target task is read and analyzed through a DMA processor, a transmission rule corresponding to the target task is determined according to information obtained after analysis, if it is determined that the transmission rule corresponding to the target task is in a preset list, a single-time transmission strategy of the target task is determined according to information indicated by the transmission rule, and otherwise, the single-time transmission strategy of the target task is determined. And determining a multiple transmission strategy of the target task according to the information indicated by the transmission rule, and sending the obtained transmission strategy to a DMA execution unit through a DMA processor, so that the DMA execution unit reads data of the target task from the source address based on the transmission strategy, and writes the data into the target address. The method is used for improving data transmission efficiency, reliability of data transmission and expansibility of a data transmission scene.

Description

Technical Field

[0001] The present application relates to the field of big data technology, and in particular to a DMA transmission system, method, device, storage medium and program product. Background Art

[0002] DMA (Direct Memory Access) is a computer system technology that enables external devices to directly exchange data with memory.

[0003] The prior art integrates the functions corresponding to the DMA technology into a DMA hardware chip. When a user needs to transfer data between an external device and a system memory, the system processor initiates a request to the DMA hardware chip so that the DMA hardware chip immediately writes each batch of a preset number of data read from the indicated source address to the target address until the data to be transmitted is completed.

[0004] However, with the increase in data transmission requirements, current DMA hardware chips are difficult to flexibly adapt to more read functions, thus affecting the performance of system data transmission. Summary of the invention

[0005] The embodiments of the present application provide a DMA transmission system, method, device, storage medium and program product to improve data transmission efficiency, improve data transmission reliability and scalability of data transmission scenarios.

[0006] In a first aspect, an embodiment of the present application provides a DMA transmission system, including:

[0007] A DMA processor is used to read the DMA configuration information of the target task, determine the transmission rule corresponding to the target task according to the DMA configuration information, determine the transmission strategy corresponding to the target task according to the transmission rule and send it to the DMA execution unit; the transmission strategy includes a single transmission strategy and a multiple transmission strategy, wherein, if the transmission rule corresponding to the target task is in a preset list, the corresponding transmission strategy is a single transmission strategy, otherwise, the corresponding transmission strategy is a multiple transmission strategy, and the DMA configuration information is written by the system processor;

[0008] The DMA execution unit is used to receive a transmission strategy, read data of a target task from a corresponding source address based on the transmission strategy, and write the data to a corresponding target address.

[0009] Optionally, the DMA configuration information includes a data width and a data distribution characteristic of a source address corresponding to the target task, and a data width and a data distribution characteristic of a target address;

[0010] The single transfer strategy includes a single read strategy and a single write strategy;

[0011] When the DMA execution unit reads the data of the target task from the corresponding source address based on the transmission strategy and writes the data to the corresponding target address, it is specifically used to:

[0012] Based on the single read strategy, all data is read from the source address. The single read strategy includes the number of reads and the number of reads each time. The number of reads each time is determined according to the data width of the source address, and the number of reads is determined according to the number of reads each time.

[0013] Based on a single write strategy, all data is written to the target address. The single write strategy includes the number of writes and the number of writes each time. The number of writes each time is determined according to the data width of the target address, and the number of writes is determined according to the number of writes each time.

[0014] Optionally, the DMA execution unit is further configured to:

[0015] Based on multiple transmission strategies, determine the target amount of data to be transmitted each time;

[0016] The target amount of data is read from the source address, and after obtaining the currently read target amount of data, the target amount of data is written to the target address until all the data of the target task are written to the target address.

[0017] Optionally, the DMA processor is further configured to:

[0018] When it is determined that the target task includes multiple subtasks with the same DMA configuration information, a transmission rule corresponding to the subtask is determined according to the configuration information of any subtask;

[0019] When the transmission rule corresponding to the subtask is in the preset transmission rule list, the transmission strategy of the target task is determined to be a single transmission strategy; otherwise, the transmission strategy corresponding to the target task is determined to be a multiple transmission strategy.

[0020] Optionally, the DMA execution unit is further configured to:

[0021] Before writing the read data to the target address each time, a corresponding read error correction code is determined according to the data; and after writing the data to the target address, the data is read a second time based on the target address, and a corresponding write error correction code is determined according to the data read a second time;

[0022] Determine whether the written error correction code is consistent with the read error correction code; if they are consistent, determine that the data transmission is successful; otherwise, rewrite the data to the target address based on the corresponding transmission strategy;

[0023] When it is determined that all data of the target task are successfully transmitted, a transmission status of successful transmission is generated and fed back to the system processor.

[0024] In a second aspect, an embodiment of the present application provides a data transmission method, applied to a DMA processor, comprising:

[0025] Read the DMA configuration information of the target task, and determine the transmission rule corresponding to the target task according to the DMA configuration information; the DMA configuration information is written by the system processor;

[0026] Determine the transmission strategy corresponding to the target task according to the transmission rule and send it to the DMA execution unit; so that the DMA execution unit reads the data of the target task from the corresponding source address based on the transmission strategy, and writes the data to the corresponding target address; the transmission strategy includes a single transmission strategy and a multiple transmission strategy, wherein, if the transmission rule corresponding to the target task is in the preset list, the corresponding transmission strategy is a single transmission strategy, otherwise, the corresponding transmission strategy is a multiple transmission strategy.

[0027] Optionally, when it is determined that the target task includes multiple subtasks with the same DMA configuration information, a transmission rule corresponding to the subtask is determined according to the configuration information of any subtask;

[0028] When the transmission rule corresponding to the subtask is in the preset transmission rule list, the transmission strategy of the target task is determined to be a single transmission strategy; otherwise, the transmission strategy corresponding to the target task is determined to be a multiple transmission strategy.

[0029] In a third aspect, an embodiment of the present application provides a data transmission method, which is applied to a DMA execution unit, comprising:

[0030] Receive a transmission strategy corresponding to a target task; the transmission strategy is determined by a DMA processor according to a transmission rule corresponding to the target task, the transmission rule is determined according to the read DMA configuration information of the target task, and the DMA configuration information is written into the DMA processor by a system processor; the transmission strategy includes a single transmission strategy and a multiple transmission strategy, wherein, if the transmission rule corresponding to the target task is in a preset list, the corresponding transmission strategy is a single transmission strategy, otherwise, the corresponding transmission strategy is a multiple transmission strategy;

[0031] Based on the transmission strategy, the data of the target task is read from the corresponding source address and the data is written to the corresponding target address.

[0032] Optionally, the DMA configuration information includes a data width and a data distribution characteristic of a source address corresponding to the target task, and a data width and a data distribution characteristic of a target address;

[0033] The single transfer strategy includes a single read strategy and a single write strategy;

[0034] Based on the single read strategy, all data is read from the source address. The single read strategy includes the number of reads and the number of reads each time. The number of reads each time is determined according to the data width of the source address, and the number of reads is determined according to the number of reads each time.

[0035] Based on a single write strategy, all data is written to the target address. The single write strategy includes the number of writes and the number of writes each time. The number of writes each time is determined according to the data width of the target address, and the number of writes is determined according to the number of writes each time.

[0036] Optionally, based on the multiple transmission strategy, determining a target amount of data to be transmitted each time;

[0037] The target amount of data is read from the source address, and after obtaining the currently read target amount of data, the target amount of data is written to the target address until all the data of the target task are written to the target address.

[0038] Optionally, before writing the read data to the target address each time, a corresponding read error correction code is determined according to the data; and after writing the data to the target address, the data is read a second time based on the target address, and a corresponding write error correction code is determined according to the data read a second time;

[0039] Determine whether the written error correction code is consistent with the read error correction code; if they are consistent, determine that the data transmission is successful; otherwise, rewrite the data to the target address based on the corresponding transmission strategy;

[0040] When it is determined that all data of the target task are successfully transmitted, a transmission status of successful transmission is generated and fed back to the system processor.

[0041] In a fourth aspect, an embodiment of the present application provides a data transmission device, applied to a DMA processor, comprising:

[0042] A determination module, used for reading DMA configuration information of a target task, and determining a transmission rule corresponding to the target task according to the DMA configuration information; the DMA configuration information is written by a system processor;

[0043] The first processing module is used to determine the transmission strategy corresponding to the target task according to the transmission rule and send it to the DMA execution unit; so that the DMA execution unit reads the data of the target task from the corresponding source address based on the transmission strategy, and writes the data to the corresponding target address; the transmission strategy includes a single transmission strategy and a multiple transmission strategy, wherein, if the transmission rule corresponding to the target task is in a preset list, the corresponding transmission strategy is a single transmission strategy, otherwise, the corresponding transmission strategy is a multiple transmission strategy.

[0044] Optionally, the first processing module is further configured to determine a transmission rule corresponding to a subtask according to configuration information of any subtask when it is determined that the target task includes multiple subtasks with the same DMA configuration information;

[0045] When the transmission rule corresponding to the subtask is in the preset transmission rule list, the transmission strategy of the target task is determined to be a single transmission strategy; otherwise, the transmission strategy corresponding to the target task is determined to be a multiple transmission strategy.

[0046] In a fifth aspect, an embodiment of the present application provides a data transmission device, applied to a DMA execution unit, comprising:

[0047] A receiving module, used for receiving a transmission strategy corresponding to a target task; the transmission strategy is determined by a DMA processor according to a transmission rule corresponding to the target task, the transmission rule is determined according to the read DMA configuration information of the target task, the DMA configuration information is written into the DMA processor by a system processor; the transmission strategy includes a single transmission strategy and a multiple transmission strategy, wherein, if the transmission rule corresponding to the target task is in a preset list, the corresponding transmission strategy is a single transmission strategy, otherwise, the corresponding transmission strategy is a multiple transmission strategy;

[0048] The second processing module is used to read the data of the target task from the corresponding source address based on the transmission strategy, and write the data into the corresponding target address.

[0049] Optionally, the DMA configuration information includes a data width and a data distribution characteristic of a source address corresponding to the target task, and a data width and a data distribution characteristic of a target address;

[0050] The single transfer strategy includes a single read strategy and a single write strategy;

[0051] The second processing module is further used to read all data from the source address based on a single read strategy, the single read strategy includes a read count and a read quantity each time; the read quantity each time is determined according to the data width of the source address, and the read count is determined according to the read quantity each time;

[0052] Based on a single write strategy, all data is written to the target address. The single write strategy includes the number of writes and the number of writes each time. The number of writes each time is determined according to the data width of the target address, and the number of writes is determined according to the number of writes each time.

[0053] Optionally, the second processing module is further used to determine a target amount of data to be transmitted each time based on the multiple transmission strategy;

[0054] The target amount of data is read from the source address, and after obtaining the currently read target amount of data, the target amount of data is written to the target address until all the data of the target task are written to the target address.

[0055] Optionally, the second processing module is further used to determine a corresponding read error correction code according to the data before writing the read data to the target address each time; and after writing the data to the target address, read the data a second time based on the target address, and determine a corresponding write error correction code according to the data read a second time;

[0056] Determine whether the written error correction code is consistent with the read error correction code; if they are consistent, determine that the data transmission is successful; otherwise, rewrite the data to the target address based on the corresponding transmission strategy;

[0057] When it is determined that all data of the target task are successfully transmitted, a transmission status of successful transmission is generated and fed back to the system processor.

[0058] In a sixth aspect, an embodiment of the present application provides an electronic device, including: a memory, a processor;

[0059] Memory stores computer-executable instructions;

[0060] The processor executes the computer-executable instructions stored in the memory, so that the processor executes various possible implementations of the second aspect and / or the third aspect as described above.

[0061] In the seventh aspect, an embodiment of the present application provides a computer-readable storage medium, in which computer-readable storage medium is stored computer execution instructions, which, when executed by a processor, are used to implement various possible implementations of the second aspect and / or the third aspect as described above.

[0062] In an eighth aspect, an embodiment of the present application provides a computer program product, including a computer program, which, when executed by a processor, implements various possible implementations of the second aspect and / or the third aspect as described above.

[0063] The DMA transmission system, method, device, storage medium and program product provided by the embodiment of the present application write the DMA configuration information of the target task into the DMA processor through the system processor, and read and parse the DMA configuration information through the DMA processor, determine the transmission rule corresponding to the target task according to the information obtained after parsing, if it is determined that the transmission rule corresponding to the target task is in the preset list, then determine the single transmission strategy corresponding to the target task according to the information indicated by the transmission rule, otherwise, determine the multiple transmission strategy corresponding to the target task according to the information indicated by the transmission rule. The obtained transmission strategy is sent to the DMA execution unit by the DMA processor, so that the DMA execution unit reads the data of the target task from the corresponding source address based on the transmission strategy, and writes the data to the corresponding target address. The embodiment of the present application improves the data transmission efficiency, the reliability of data transmission and the scalability of data transmission scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0065] Figure 1 A schematic diagram of an application scenario of the prior art provided for this application;

[0066] Figure 2 A schematic diagram of the structure of the chip system provided in this application;

[0067] Figure 3 A schematic diagram of the structure of the DMA processor provided in this application;

[0068] Figure 4 A flowchart of the data transmission method provided by this application;

[0069] Figure 5 A schematic diagram of the structure of the data transmission device provided in this application Figure 1 ;

[0070] Figure 6 A schematic diagram of the structure of the data transmission device provided in this application Figure 2 ;

[0071] Figure 7 A schematic diagram of the structure of the electronic device provided in this application.

[0072] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0073] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0074] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant laws, regulations and standards in the relevant regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0075] First, the terms involved in this application are explained:

[0076] DMA (Direct Memory Access) is a computer system technology that allows efficient data transfer between external devices and computer motherboard memory without the intervention of the computer processor.

[0077] Figure 1 The application scenario diagram of the prior art provided for this application is as follows: Figure 1 As shown, the application scenario of the prior art includes a chip system, which includes a system processor, memory, system bus, external devices and DMA hardware, wherein DMA hardware refers to hardware designed based on DMA technology. For the transmission task of transferring target data from an external device to the memory, the system processor transmits the configuration information corresponding to the transmission task to the DMA hardware, so that the DMA hardware transmits the corresponding target data through the bus, while releasing the resources of the system processor for processing other tasks, thereby improving the overall performance of the system while improving the data transmission efficiency of the system.

[0078] However, with the continuous increase in system complexity, the system's demand for data transmission based on DMA technology is also increasing. In order to adapt to the needs of data transmission, the existing technology has continuously improved and developed DMA hardware, resulting in an increasingly complex DMA hardware structure. When transmission anomalies occur during the data transmission process, it is difficult to troubleshoot the problem, and the development cycle of DMA hardware is relatively long. Therefore, the existing technology is difficult to meet the current system's high demand for data transmission and diversified application scenarios, reducing the stability and efficiency of data transmission and affecting the overall performance and scalability of the system.

[0079] The data transmission method provided in the present application writes the DMA configuration information of the target task into the DMA processor through the system processor, and determines the transmission rule of the target task after reading the DMA configuration information through the DMA processor. If it is determined that the transmission rule is in a preset list, the transmission strategy corresponding to the target task is determined to be a single transmission strategy. Otherwise, the transmission strategy corresponding to the target task is determined to be a multiple transmission strategy. Based on the above transmission rules, the transmission strategy corresponding to the DMA configuration information of the target task is obtained and sent to the DMA execution unit, so that when the DMA execution unit determines that the transmission strategy is a single transmission strategy, based on the instruction of the single transmission strategy, all the data of the target task is read from the source address, and all the data is written to the target address after reading all the data; if the transmission strategy is determined to be a multiple transmission strategy, based on the instruction of the multiple transmission strategy, a certain amount of data is read from the source address, and the data is written to the target address after reading a certain amount of data, and then the steps of data reading and data writing are repeated until all data transmission is completed. The present application adopts different transmission strategies for tasks with different transmission rules, adopts multiple transmission strategies for tasks whose transmission rules are not preset rules, and adopts a single transmission strategy for tasks whose transmission rules are preset rules, thereby improving the transmission efficiency of tasks corresponding to each transmission rule, improving the scalability and reliability of the DMA transmission system for data transmission, realizing the diversification of application scenarios, and further improving the overall performance of the DMA transmission system. The error correction code of the currently transmitted data is calculated before and after each data writing, and the transmission status of the target task is determined based on the error correction code corresponding to each data transmission, thereby ensuring transmission efficiency while improving the convenience of troubleshooting when transmission fails.

[0080] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0081] The DMA transmission system provided in the present application can be applied to various chip systems, including but not limited to: embedded microcontrollers, embedded systems on chip, computer CPU systems, etc.

[0082] Figure 2 The schematic diagram of the chip system provided in this application is as follows: Figure 2As shown, the chip system includes: a system processor, a memory, an external device module, a bus and a DMA transmission system, and the DMA transmission system includes a DMA processor and a DMA execution unit. The DMA processor is used to read the DMA configuration information of the target task, determine the transmission rule corresponding to the target task according to the DMA configuration information, determine the transmission strategy corresponding to the target task according to the transmission rule and send it to the DMA execution unit; the transmission strategy includes a single transmission strategy and a multiple transmission strategy, wherein if the transmission rule corresponding to the target task is in the preset list, the corresponding transmission strategy is a single transmission strategy, otherwise, the corresponding transmission strategy is a multiple transmission strategy, and the DMA configuration information is written by the system processor; the DMA execution unit is used to receive the transmission strategy, read the data of the target task from the corresponding source address based on the transmission strategy, and write the data to the corresponding target address.

[0083] Exemplarily, the external device module includes but is not limited to: storage device, network interface, image processing device, audio device, etc., the memory includes but is not limited to: SRAM, DRAM, Flash, etc., the memory is used to store data and programs, the system bus is the bus of the chip system, and data is exchanged with the DMA transmission system through the system bus. The DMA execution unit is a high-speed data transmission device, which performs various data transmission tasks within the chip system based on the control of the DMA processor.

[0084] For example, data transmission between memory A and memory B, data transmission between memory A and external device A, and data transmission between external device A and external device B are performed.

[0085] Optionally, the DMA configuration information includes a data width and a data distribution feature of a source address corresponding to the target task, and a data width and a data distribution feature of a target address. The data distribution feature includes continuous and non-continuous. The preset list includes n preset rules, where n is a positive integer.

[0086] Optionally, Figure 3 The structural diagram of the DMA processor provided in this application is as follows: Figure 3 As shown, the DMA processor includes a processor core, an instruction memory, a data memory, an external device handshake module and a configuration register, wherein the processor core is a high-performance, low-power RiscV processor core, and RiscV is an open standard instruction architecture.

[0087] In a possible embodiment, the system processor writes the DMA configuration information corresponding to the target task into the configuration register of the DMA processor through the bus. After the writing is completed, the RiscV processor core of the DMA processor reads the DMA configuration information in the configuration register and parses it to obtain the source address information, the target address information, the transmission data length and the transmission priority. After the external device has prepared all the data to be transmitted, a transmission instruction is sent to the RiscV processor core through the external handshake module, so that the RiscV processor core determines the transmission rule corresponding to the target task based on the transmission instruction and the parsed DMA configuration information, and determines the transmission strategy corresponding to the target task according to the transmission rule, wherein when the transmission rule is in the preset list, the obtained transmission strategy is a single transmission strategy, otherwise, the obtained transmission strategy is a multiple transmission strategy. The transmission strategy is sent to the DMA execution unit through the RiscV processor core, so that the DMA execution unit reads the data of the source address through the system bus, and writes the read data to the target address through the system bus.

[0088] In a possible embodiment, based on a single transfer strategy, according to the source address, data width of the source address, data distribution characteristics of the source address, target address, data width of the target address, data distribution characteristics of the target address and transfer data length indicated by the DMA configuration information, the number of reads, the number of bytes read each time and the reading method before writing all the data, as well as the number of writes, the number of bytes written each time and the writing method after reading all the data are determined to obtain the transfer strategy corresponding to the target task.

[0089] In a possible embodiment, based on multiple transmission strategies, according to the source address, data width of the source address, data distribution characteristics of the source address, target address, data width of the target address, data distribution characteristics of the target address and transmission data length indicated by the DMA configuration information, the number of reads before each data write, the number of bytes read each time and the reading method, as well as the number of writes, the number of bytes written each time and the writing method after each data read are determined to obtain the transmission strategy corresponding to the target task.

[0090] Optionally, the instruction memory is used to store instructions executed during the operation of the DMA processor. The implementation principle and technical effect of the instruction memory of this embodiment are similar to those of the instruction memory of the prior art, and are not described in detail in this embodiment.

[0091] The embodiment of the present application determines the transmission rules corresponding to each task through the DMA processor, so as to determine the transmission strategy corresponding to the target task in the transmission scenario based on the transmission rules, thereby controlling the DMA execution unit to complete the data reading and data writing of the target task according to the obtained transmission strategy, thereby improving the data transmission efficiency and reliability of the DMA transmission system. And by using the above-mentioned DMA processor to control and manage data transmission, the DMA control unit executes the data transmission method, which reduces the complexity of realizing the data transmission function in the chip system, improves the convenience of configuring and upgrading the DMA transmission system, reduces the development cost of the DMA transmission system, improves the flexibility and scalability of the DMA transmission system, and further improves the response time and overall performance of the chip system.

[0092] Optionally, the single transfer strategy includes a single read strategy and a single write strategy; the DMA execution unit reads all data from the source address based on the single read strategy, and the single read strategy includes the number of reads and the number of reads each time; the number of reads each time is determined according to the data width of the source address, and the number of reads is determined according to the number of reads each time; based on the single write strategy, all data is written to the target address, and the single write strategy includes the number of writes and the number of writes each time; the number of writes each time is determined according to the data width of the target address, and the number of writes is determined according to the number of writes each time.

[0093] Optionally, the DMA configuration information also includes the transmission data length.

[0094] In a possible embodiment, the RiscV processor core parses the DMA configuration information of the target task and obtains that the data width of the source address is 32 bits (4 bytes), the data distribution characteristics of the source address are discrete characteristics, the data width of the target address is 32 bits (4 bytes), the data distribution characteristics of the target address are continuous characteristics, and the transmission data length is 128 bytes.

[0095] With respect to the above DMA configuration information, in the prior art, DMA hardware non-continuously reads 4 bytes of data from the source address to the system bus once (corresponding to 3 bus cycles), and then non-continuously writes 4 bytes of data to the target address once (corresponding to 3 bus cycles) through the system bus, and repeats the above steps 32 times until the 128-byte data transmission is completed. When the 128-byte transmission is completed, a total of 192 bus cycles of the chip system are spent.

[0096] In the embodiment of the present application, the RiscV processor core determines the transmission rule of the target task based on the above DMA configuration information: the data width of the source address and the target address match, but the data distribution characteristics are different. At this time, if the transmission rule is determined to be the preset rule 2 in the preset list, the single transmission strategy corresponding to the target task is generated and transmitted to the DMA control unit. The DMA control unit reads 32 4-byte data (corresponding to 96 bus cycles) from the source address non-continuously to the system bus according to the single read strategy in the single transmission strategy, and sorts the data read each time to obtain the sorted 128-byte data based on the transmission protocol of the system bus. Based on the single write strategy in the single transmission strategy, the sorted 128-byte data is continuously written to the target address 32 times 4-byte data (corresponding to 33 bus cycles). In the embodiment of the present application, it takes 129 bus cycles to complete the transmission of the above 128 bytes of data. It can be seen that the number of bus cycles spent in the embodiment of the present application is less than the number of bus cycles in the prior art.

[0097] The embodiment of the present application determines that the transmission rule of the target task is in a preset list, obtains the single transmission strategy corresponding to the target task, and based on the single transmission strategy, writes all the data of the target task to the target address after reading all the data of the target task, thereby improving the transmission efficiency and transmission reliability of the tasks whose transmission rules are in the preset list, realizing efficient transmission under multiple transmission rules, expanding the data transmission scenarios of the DMA transmission system, and improving the data transmission efficiency and reliability in different scenarios.

[0098] Optionally, when the DMA processor determines that the target task includes multiple subtasks with the same DMA configuration information, it determines the transmission rule corresponding to the subtask based on the configuration information of any subtask; when the transmission rule corresponding to the subtask is in the preset transmission rule list, the transmission strategy of the target task is determined to be a single transmission strategy; otherwise, the transmission strategy corresponding to the target task is determined to be a multiple transmission strategy.

[0099] In a possible embodiment, when the target task includes two subtasks (such as task 1 and task 2), the RiscV processor core parses the DMA configuration information corresponding to the two subtasks of the target task, and obtains that the data width of the source addresses of task 1 and task 2 is 32 bits (4 bytes), the data distribution characteristics of the source addresses of task 1 and task 2 are both continuous characteristics, the data width of the target addresses of task 1 and task 2 is 32 bits (4 bytes), the data distribution characteristics of the target addresses of task 1 and task 2 are both continuous characteristics, and the transmission data length of task 1 and task 2 is 128 bytes.

[0100] With respect to the above DMA configuration information, in the prior art, DMA hardware is used to non-continuously read 4 bytes of data from the source address of task 1 to the system bus (corresponding to 3 bus cycles), and then non-continuously write 4 bytes of data to the target address of task 1 through the system bus (corresponding to 3 bus cycles), and the above steps are repeated 32 times until the 128-byte data transmission of task 1 is completed. After the 128-byte transmission of task 1 is completed, 4 bytes of data are non-continuously read from the source address of task 2 to the system bus (corresponding to 3 bus cycles), and then non-continuously write 4 bytes of data to the target address of task 2 through the system bus (corresponding to 3 bus cycles), and after the writing is completed, it is determined that the transmission of the above 4 bytes of data is completed, and then the above steps are repeated 32 times until the 128-byte data transmission of task 2 is completed. The transmission of a total of 256 bytes of data for task 1 and task 2 corresponds to a total of 384 bus cycles of the chip system.

[0101] In the embodiment of the present application, the RiscV processor core determines the transmission rule of the target task based on the above DMA configuration information: the data width of the source address and the target address of the two subtasks match and the data distribution characteristics are the same. At this time, if the transmission rule is determined to be the preset rule 3 in the preset list, the single transmission strategy corresponding to the target task is generated and transmitted to the DMA control unit. The DMA control unit continuously reads 64 4-byte data (corresponding to 65 bus cycles) from the source address of task 1 and the source address of task 2 to the system bus according to the single read strategy in the single transmission strategy, and sorts the data read each time based on the transmission protocol of the system bus to obtain the sorted 128-byte data. Based on the single write strategy in the single transmission strategy, 32 4-byte data (corresponding to 33 bus cycles) are continuously written to the target address of task 1, and 32 4-byte data (corresponding to 33 bus cycles) are continuously written to the target address of task 2, so all the data written to the target task corresponds to 66 bus cycles. In the embodiment of the present application, 131 bus cycles are required to complete the transmission of 256 bytes of data of the target task. The number of bus cycles required to transmit all the data of the target task in the embodiment of the present application is less than the number of bus cycles in the prior art.

[0102] The embodiment of the present application determines that the DMA configuration information of the target task includes the DMA configuration information of multiple identical subtasks, and determines that the transmission rule of the subtask is in a preset list, that is, a single transmission strategy corresponding to the target task is obtained, and based on the single transmission strategy, all the data of the multiple subtasks are read and then all the data are written into the target addresses corresponding to each subtask, thereby improving the transmission efficiency and transmission reliability of the tasks whose transmission rules of multiple subtasks are in the preset list, realizing efficient transmission of multiple tasks, expanding the data transmission scenarios of the DMA transmission system, improving the scalability of the data transmission system, and improving the data transmission efficiency and reliability in different scenarios.

[0103] Exemplarily, each system bus request to read data once requires three bus cycles, non-continuous reading of 1-byte data four times means reading 1-byte data four times based on four system bus requests, and continuous writing of 4-byte data 32 times means writing 4-byte data 32 times based on one system bus request.

[0104] Optionally, the DMA execution unit determines a corresponding read error correction code based on the data before writing the read data to the target address each time; and after writing the data to the target address, reads the data a second time based on the target address, and determines a corresponding write error correction code based on the data read the second time; determines whether the write error correction code is consistent with the read error correction code; when they are consistent, determines that the data transmission is successful, otherwise, based on the corresponding transmission strategy, rewrites the data to the target address; when it is determined that all data transmission of the target task is successful, generates a transmission status of successful transmission and feeds it back to the system processor.

[0105] Optionally, the transmission strategy also includes a secondary reading strategy, and the DMA execution unit performs secondary reading based on the secondary reading strategy. The secondary reading strategy is generated by the DMA processor according to the data width of the target address, the data distribution characteristics of the target address, and the transmission data length when the data verification function is turned on in the configuration register according to the parsed DMA configuration information.

[0106] Optionally, the DMA execution unit includes a data buffer.

[0107] In a possible embodiment, for a single transfer strategy, after the DMA control unit non-continuously reads 4-byte data 32 times from the source address according to the single read strategy in the single transfer strategy, and obtains 128 bytes of data, the 128 bytes of data are sent to the data memory of the DMA processor (or the data buffer of the DMA execution unit), so as to process the 128 bytes of data through the data memory to obtain a read error correction code corresponding to the 128 bytes of data. After obtaining the read error correction code, the DMA control unit continuously writes the above 128 bytes of data to the target address for 32 times of 4-byte data according to the single write strategy in the single transfer strategy. After the writing is completed, the DMA control unit continuously reads 4-byte data 32 times from the target address based on the secondary read strategy in the single transfer strategy, obtains the secondary read 128 bytes of data and sends it to the data memory of the DMA processor (or the data buffer of the DMA execution unit), so as to process the secondary read 128 bytes of data through the data memory to obtain a write error correction code corresponding to the secondary read 128 bytes of data. The read error correction code and the write error correction code are compared. If the comparison is consistent, it is determined that all data of the target task are successfully transmitted, and a transmission status of successful transmission is generated. If the comparison is inconsistent, the 128-byte data read from the source address and stored in the data storage device is rewritten to the target address according to the single write strategy.

[0108] Exemplarily, the read error correction code refers to the error correction code corresponding to the data read from the source address of the target task, and the write error correction code refers to the error correction code corresponding to the data read from the target address of the target task. Among them, the method of calculating the error correction code corresponding to the data is similar to the implementation principle of calculating the error correction code in the prior art, and is not elaborated in the embodiments of this application.

[0109] In a possible embodiment, the DMA processor records the amount of data transferred in real time, and when it is determined that the amount of data transferred at the current moment reaches the transfer data length corresponding to the target task, it determines that the data transfer is completed, and sends a transfer completion notification to the system processor. The system processor sends a status read instruction to the DMA execution unit based on the transfer completion notification, so that the DMA execution unit feeds back the transfer status of the target task to the system processor when receiving the status read instruction.

[0110] The embodiment of the present application performs consistency verification on the data before and after writing, so that when it is determined based on the verification result that the data before and after writing are inconsistent, the corresponding data is rewritten in time to improve the accuracy and reliability of data transmission.

[0111] Optionally, the DMA execution unit determines the target quantity of data for each transmission based on a multiple transmission strategy; reads the target quantity of data from the source address, and after obtaining the target quantity of data currently read, writes the target quantity of data to the target address until all data of the target task are written to the target address.

[0112] In a possible embodiment, the RiscV processor core parses the DMA configuration information of the target task and obtains that the data width of the source address is 32 bits (4 bytes), the data distribution characteristics of the source address are continuous characteristics, the data width of the target address is 32 bits (4 bytes), the data distribution characteristics of the target address are continuous characteristics, and the transmission data length is 128 bytes.

[0113] For the above DMA configuration information, the RiscV processor core determines the transmission rule of the target task based on the above DMA configuration information: the data width of the source address and the target address match and the data distribution characteristics are the same. At this time, it is determined that the transmission rule is not in the preset list, and a multiple transmission strategy corresponding to the target task is generated and transmitted to the DMA control unit. The DMA control unit determines that the target number of data to be transmitted each time is 4 bytes of data according to the multiple transmission strategy, reads 4 bytes of data from the source address non-continuously to the system bus based on the target number indicated by the multiple transmission strategy, and sends the read 4 bytes of data to the data memory of the DMA processor (or the data buffer of the DMA execution unit), so as to process the 4 bytes of data through the data memory to obtain the read error correction code corresponding to the 4 bytes of data. After obtaining the read error correction code, the DMA control unit writes 4 bytes of data to the target address non-continuously once according to the multiple transmission strategy. After the writing is completed, the 4 bytes of data are read non-continuously from the target address once based on the secondary reading strategy in the multiple transmission strategy, and the 4 bytes of data read twice are obtained and sent to the data memory of the DMA processor (or the data buffer of the DMA execution unit), so as to process the 4 bytes of data read twice through the data memory, and obtain the write error correction code corresponding to the 4 bytes of data read twice. The read error correction code and the write error correction code are compared. If the comparison is inconsistent, the 4-byte data read from the source address and stored in the data storage device is rewritten to the target address according to the single write strategy.

[0114] In a possible embodiment, the DMA control unit rewrites the 4-byte data corresponding to the read error correction code to the target address, and based on the secondary read strategy in the multiple transmission strategies, reads the 4-byte data non-continuously to the target address again and calculates the corresponding write error correction code. If the write error correction code is still inconsistent with the read error correction code, the transmission status of the 4-byte data is determined to be transmission failure.

[0115] In a possible embodiment, when the DMA control unit determines that the comparison is consistent, it determines that the transmission status of the 4-byte data is a successful transmission, and repeats the next reading and writing steps after determining that the transmission is successful, until the above steps are repeated 32 times to obtain multiple transmission statuses, and the transmission status of the target task is determined according to the multiple transmission statuses. If all the transmission statuses obtained are successful transmissions, a transmission status of successful transmission of the target task is generated and fed back to the system processor. If it is determined that there is at least one transmission failure status among the transmission statuses corresponding to the obtained data, a transmission status of failed transmission of the target task is generated, and the transmission status of the failed transmission of the target task and the data of the failed retransmission of the target task are fed back to the system processor, so that the system processor can perform troubleshooting based on the data information of the failed transmission.

[0116] When performing data transmission based on a multiple transmission strategy, the embodiment of the present application performs consistency verification on the data written each time to obtain a corresponding transmission status. When the target task transmission fails, troubleshooting is performed based on the transmission status corresponding to the data written each time, thereby improving the efficiency and accuracy of troubleshooting and further improving the reliability of data transmission.

[0117] Optionally, the DMA transmission system provided in the embodiment of the present application is based on a programmable DMA processor and a programmable DMA execution unit. The DMA processor in the DMA transmission system can realize various logic controls of the data transmission process and dynamic upgrade functions for different needs, and the DMA execution unit is used to perform efficient data transmission actions according to the transmission strategy transmitted by the DMA processor.

[0118] In a possible embodiment, the DMA execution unit includes a high-speed data transmission interface and a flow control module, wherein the high-speed data transmission interface supports multiple data widths and transmission protocols, and is used to transmit data between addresses of different data widths, and the flow control module is used to read and write data according to the transmission strategy. The DMA transmission system provided in this embodiment improves the reliability and stability of data transmission, improves the scalability of the chip system, and realizes diversified application scenarios of the DMA transmission system.

[0119] Figure 4 A flow chart of the data transmission method provided in this application, such as Figure 4 As shown, in this embodiment Figure 2 Based on the embodiment, a data transmission method is described in detail, and the method includes:

[0120] S401: The system processor writes DMA configuration information to the DMA processor.

[0121] More specifically, the system processor writes DMA configuration information corresponding to the target task to the DMA processor.

[0122] S402: The DMA processor parses the DMA configuration information to obtain a transmission rule.

[0123] More specifically, the DMA processor reads and parses the written DMA configuration information, and obtains that the data width of the source address is 8 bits (1 byte), the data distribution feature of the source address is continuous, the data width of the target address is 32 bits (4 bytes), the data distribution feature of the target address is continuous, and the transmission data length is 128 bytes. Based on the above DMA configuration information, the transmission rule of the target task is determined as follows: the data widths of the source address and the target address do not match and are both continuous. The transmission rule corresponding to the target task is determined based on the information obtained after parsing.

[0124] S403: The DMA processor determines a transmission strategy for the target task based on the transmission rule.

[0125] More specifically, the DMA processor determines that the transmission rule of the target task is in the preset list. If the transmission rule is determined to be in the preset list, a single transmission strategy corresponding to the target task is generated according to the source address, the data width of the source address, the data distribution characteristics of the source address, the transmission data length, the target address, the data width of the target address, and the data distribution characteristics of the target address indicated by the transmission rule. The single transmission strategy includes a single write strategy, a single read strategy, and a double read strategy.

[0126] S404: The DMA processor sends a transmission strategy to the DMA execution unit.

[0127] More specifically, the DMA processor sends a single transfer policy to the DMA execution unit.

[0128] S405 , the DMA execution unit reads data of the source address of the target task based on the transmission strategy.

[0129] More specifically, the DMA control unit continuously reads 1-byte data 128 times (corresponding to 129 bus cycles) from the source address of the target task according to the single read strategy in the single transfer strategy, obtains 128 bytes of data to the system bus, and sorts the data read each time based on the transmission protocol of the system bus to obtain the sorted 128 bytes of data.

[0130] S406 , the DMA execution unit determines a read error correction code corresponding to the read data.

[0131] More specifically, the DMA execution unit stores the sorted 128-byte data in a data buffer of the DMA execution unit, and calculates a corresponding read error correction code for the 128-byte data through the data buffer.

[0132] S407 , the DMA execution unit writes data to the target address of the target task based on the transmission strategy.

[0133] More specifically, the DMA execution unit continuously writes 32 times of 4-byte data (corresponding to 33 bus cycles) of the sorted 128-byte data to the target address based on the single write strategy in the single transfer strategy.

[0134] S408 , the DMA execution unit reads the data written to the target address for a second time, and determines a corresponding write error correction code.

[0135] More specifically, after the DMA execution unit completes writing the 128-byte data, it continuously reads 4-byte data 32 times from the target address according to the secondary read strategy in the single read strategy, obtains the secondary read 128-byte data and stores it in the data buffer of the DMA execution unit. The write error correction code corresponding to the secondary read 128-byte data is calculated through the data buffer.

[0136] S409 , when the DMA execution unit determines that the target task transmission is completed, it generates the transmission status of the target task according to the read error correction code and the write error correction code.

[0137] More specifically, when determining that the 128-byte data transmission of the target task is completed, the DMA execution unit determines whether the read error correction code and the write error correction code corresponding to the target task are consistent. When it is determined that they are consistent, a transmission status indicating that the target task transmission is successful is generated.

[0138] S410: The DMA processor sends a transfer completion notification to the system processor.

[0139] More specifically, the DMA processor records the amount of data transmitted in real time, determines when the target task transmission is completed based on the transmission data length corresponding to the target task, generates a transmission completion notification and sends it to the system processor.

[0140] S411 . The system processor sends a status read instruction to the DMA execution unit.

[0141] More specifically, after receiving the transfer completion notification, the system processor sends a status read instruction to the DMA execution unit.

[0142] S412: The DMA execution unit sends a transfer status to the system processor.

[0143] More specifically, after receiving the status read instruction, the DMA execution unit sends a transfer status indicating that the target task has been successfully transferred to the system processor.

[0144] Optionally, for the DMA configuration information obtained in step S402, the prior art non-continuously reads 1-byte data from the source address to the system bus 4 times (corresponding to 12 bus cycles) through the DMA hardware, and non-continuously writes 4-byte data to the target address once (corresponding to 3 bus cycles) through the system bus, and repeats the above steps 32 times until the 128-byte data transmission is completed. When the 128-byte transmission is completed, a total of 480 bus cycles of the chip system are spent. The DMA execution unit in this embodiment needs 162 bus cycles to transmit the 128-byte data to complete the target task. Therefore, the number of bus cycles required in this embodiment is less than the number of bus cycles required in the prior art.

[0145] The data transmission method provided in the embodiment of the present application determines the transmission rule corresponding to the target task through a DMA processor, determines the transmission strategy of the target task according to the transmission rule and sends it to the DMA transmission unit, so that data is transmitted based on the transmission strategy through the DMA transmission unit, thereby improving the diversity of data transmission application scenarios, improving the data transmission efficiency in various scenarios, and improving the reliability and accuracy of data transmission.

[0146] Figure 5 A schematic diagram of the structure of the data transmission device provided in this application Figure 1 ,like Figure 5 As shown, applied to a DMA processor, the data transmission device 50 provided in this embodiment includes:

[0147] The determination module 501 is used to read the DMA configuration information of the target task and determine the transmission rule corresponding to the target task according to the DMA configuration information; the DMA configuration information is written by the system processor;

[0148] The first processing module 502 is used to determine the transmission strategy corresponding to the target task according to the transmission rule and send it to the DMA execution unit; so that the DMA execution unit reads the data of the target task from the corresponding source address based on the transmission strategy, and writes the data to the corresponding target address; the transmission strategy includes a single transmission strategy and a multiple transmission strategy, wherein, if the transmission rule corresponding to the target task is in the preset list, the corresponding transmission strategy is a single transmission strategy, otherwise, the corresponding transmission strategy is a multiple transmission strategy.

[0149] Optionally, the first processing module 502 is further configured to determine a transmission rule corresponding to a subtask according to configuration information of any subtask when it is determined that the target task includes multiple subtasks with the same DMA configuration information;

[0150] When the transmission rule corresponding to the subtask is in the preset transmission rule list, the transmission strategy of the target task is determined to be a single transmission strategy; otherwise, the transmission strategy corresponding to the target task is determined to be a multiple transmission strategy.

[0151] The data transmission device provided in this embodiment is applied to a DMA processor and can execute the method provided in the above method embodiment and applied to a DMA processor. The implementation principle and technical effect are similar and will not be described in detail in this embodiment.

[0152] Figure 6 A schematic diagram of the structure of the data transmission device provided in this application Figure 2 ,like Figure 6 As shown, the data transmission device 60 provided in this embodiment is applied to a DMA execution unit and includes:

[0153] The receiving module 601 is used to receive the transmission strategy corresponding to the target task; the transmission strategy is determined by the DMA processor according to the transmission rule corresponding to the target task, and the transmission rule is determined according to the DMA configuration information of the target task read, and the DMA configuration information is written into the DMA processor by the system processor; the transmission strategy includes a single transmission strategy and a multiple transmission strategy, wherein, if the transmission rule corresponding to the target task is in the preset list, the corresponding transmission strategy is a single transmission strategy, otherwise, the corresponding transmission strategy is a multiple transmission strategy;

[0154] The second processing module 602 is used to read the data of the target task from the corresponding source address based on the transmission strategy, and write the data to the corresponding target address.

[0155] Optionally, the DMA configuration information includes a data width and a data distribution characteristic of a source address corresponding to the target task, and a data width and a data distribution characteristic of a target address;

[0156] The single transfer strategy includes a single read strategy and a single write strategy;

[0157] The second processing module 602 is further used to read all data from the source address based on a single read strategy, where the single read strategy includes a read count and a read quantity each time; the read quantity each time is determined according to the data width of the source address, and the read count is determined according to the read quantity each time;

[0158] Based on a single write strategy, all data is written to the target address. The single write strategy includes the number of writes and the number of writes each time. The number of writes each time is determined according to the data width of the target address, and the number of writes is determined according to the number of writes each time.

[0159] Optionally, the second processing module 602 is further configured to determine a target amount of data to be transmitted each time based on a multiple transmission strategy;

[0160] The target amount of data is read from the source address, and after obtaining the currently read target amount of data, the target amount of data is written to the target address until all the data of the target task are written to the target address.

[0161] Optionally, the second processing module 602 is further configured to determine a corresponding read error correction code according to the data before writing the read data to the target address each time; and after writing the data to the target address, read the data a second time based on the target address, and determine a corresponding write error correction code according to the data read a second time;

[0162] Determine whether the written error correction code is consistent with the read error correction code; if they are consistent, determine that the data transmission is successful; otherwise, rewrite the data to the target address based on the corresponding transmission strategy;

[0163] When it is determined that all data of the target task are successfully transmitted, a transmission status of successful transmission is generated and fed back to the system processor.

[0164] The data transmission device provided in this embodiment is applied to a DMA execution unit and can execute the method provided in the above method embodiment and applied to a DMA execution unit. The implementation principle and technical effects are similar and will not be described in detail in this embodiment.

[0165] Figure 7 This is a schematic diagram of the structure of the electronic device provided in this application. Figure 7 As shown, the electronic device 70 provided in this embodiment includes: at least one processor 701 and a memory 702. Optionally, the device 70 further includes a communication component 703. The processor 701, the memory 702 and the communication component 703 are connected via a bus 704.

[0166] In a specific implementation process, at least one processor 701 executes the computer-executable instructions stored in the memory 702, so that at least one processor 701 executes the above method.

[0167] The specific implementation process of the processor 701 can be found in the above method embodiment, and its implementation principle and technical effect are similar, so this embodiment will not be repeated here.

[0168] In the above embodiments, it should be understood that the processor can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), etc. A general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the invention can be directly implemented as a hardware processor, or can be implemented by a combination of hardware and software modules in the processor.

[0169] The memory may include a high-speed memory (Random Access Memory, RAM), and may also include a non-volatile memory (NVM), such as at least one disk storage.

[0170] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, the bus in the drawings of this application is not limited to only one bus or one type of bus.

[0171] The present application also provides a computer program product, including a computer program, which implements the above method when executed by a processor.

[0172] The present application also provides a computer-readable storage medium, in which computer-executable instructions are stored. When a processor executes the computer-executable instructions, the above method is implemented.

[0173] The above-mentioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk. The readable storage medium can be any available medium that can be accessed by a general or special-purpose computer.

[0174] An exemplary readable storage medium is coupled to a processor so that the processor can read information from the readable storage medium and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can be located in an application specific integrated circuit (Application Specific Integrated Circuits, referred to as: ASIC). Of course, the processor and the readable storage medium can also exist in the device as discrete components.

[0175] The division of units is only a logical function division, and there may be other divisions in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interface, device or unit, which can be electrical, mechanical or other forms.

[0176] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0177] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0178] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods of each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0179] Those skilled in the art can understand that all or part of the steps of implementing the above-mentioned method embodiments can be completed by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, the steps of the above-mentioned method embodiments are executed; and the aforementioned storage medium includes: ROM, RAM, disk or optical disk and other media that can store program codes.

[0180] Finally, it should be noted that those skilled in the art will readily conceive of other embodiments of the present invention after considering the specification and practicing the invention disclosed herein. The present invention is intended to cover any variations, uses or adaptations of the present invention, which follow the general principles of the present invention and include common knowledge or customary technical means in the art not disclosed by the present invention, are not limited to the precise structure described above and shown in the drawings, and may be modified and changed in various ways without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.

Claims

1. A DMA transmission system, characterized in that: include: A DMA processor is used to read the DMA configuration information of the target task, determine the transmission rule corresponding to the target task according to the DMA configuration information, determine the transmission strategy corresponding to the target task according to the transmission rule and send it to the DMA execution unit; the transmission strategy includes a single transmission strategy and a multiple transmission strategy, wherein if the transmission rule corresponding to the target task is in a preset list, the corresponding transmission strategy is a single transmission strategy, otherwise, the corresponding transmission strategy is a multiple transmission strategy, and the DMA configuration information is written by the system processor; The DMA execution unit is used to receive the transmission strategy, read the data of the target task from the corresponding source address based on the transmission strategy, and write the data to the corresponding target address.

2. The system according to claim 1, characterized in that The DMA configuration information includes the data width and data distribution characteristics of the source address corresponding to the target task, and the data width and data distribution characteristics of the target address; The single transmission strategy includes a single read strategy and a single write strategy; When the DMA execution unit reads the data of the target task from the corresponding source address based on the transmission strategy and writes the data to the corresponding target address, it is specifically used to: Based on the single read strategy, all data are read from the source address, the single read strategy includes the number of reads and the number of reads each time; the number of reads each time is determined according to the data width of the source address, and the number of reads is determined according to the number of reads each time; Based on the single write strategy, all data are written to the target address, and the single write strategy includes the number of writes and the number of writes each time; the number of writes each time is determined according to the data width of the target address, and the number of writes is determined according to the number of writes each time.

3. The system according to claim 2, characterized in that The DMA execution unit is further used for: Based on the multiple transmission strategies, determining a target amount of data to be transmitted each time; The target amount of data is read from the source address, and after obtaining the currently read target amount of data, the target amount of data is written into the target address until all the data of the target task are written into the target address.

4. The system according to claim 3, characterized in that The DMA processor is further configured to: When it is determined that the target task includes a plurality of subtasks having the same DMA configuration information, determining a transmission rule corresponding to the subtask according to the configuration information of any subtask; When the transmission rule corresponding to the subtask is in the preset transmission rule list, the transmission strategy of the target task is determined to be a single transmission strategy; otherwise, the transmission strategy corresponding to the target task is determined to be a multiple transmission strategy.

5. The system according to any one of claims 1 to 4, characterized in that: The DMA execution unit is further used for: Before writing the read data to the target address each time, determining a corresponding read error correction code according to the data; and after writing the data to the target address, reading the data a second time based on the target address, and determining a corresponding write error correction code according to the data read a second time; Determining whether the write error correction code is consistent with the read error correction code; When the data are consistent, the data transmission is determined to be successful; otherwise, based on the corresponding transmission strategy, the data is rewritten into the target address; When it is determined that all data of the target task are transmitted successfully, a transmission status of successful transmission is generated and fed back to the system processor.

6. A data transmission method, characterized in that: Applicable to DMA processors, including: Reading DMA configuration information of a target task, and determining a transmission rule corresponding to the target task according to the DMA configuration information; the DMA configuration information is written by a system processor; The transmission strategy corresponding to the target task is determined according to the transmission rule and sent to the DMA execution unit; so that the DMA execution unit reads the data of the target task from the corresponding source address based on the transmission strategy, and writes the data to the corresponding target address; the transmission strategy includes a single transmission strategy and a multiple transmission strategy, wherein, if the transmission rule corresponding to the target task is in a preset list, the corresponding transmission strategy is a single transmission strategy, otherwise, the corresponding transmission strategy is a multiple transmission strategy.

7. A data transmission method, characterized in that: Applicable to DMA execution unit, including: Receive a transmission strategy corresponding to a target task; the transmission strategy is determined by a DMA processor according to a transmission rule corresponding to the target task, the transmission rule is determined according to DMA configuration information of the target task read, and the DMA configuration information is written into the DMA processor by a system processor; the transmission strategy includes a single transmission strategy and a multiple transmission strategy, wherein if the transmission rule corresponding to the target task is in a preset list, the corresponding transmission strategy is a single transmission strategy, otherwise, the corresponding transmission strategy is a multiple transmission strategy; The data of the target task is read from the corresponding source address based on the transmission strategy, and the data is written to the corresponding target address.

8. An electronic device, characterized in that: include: Memory, processor; The memory stores computer-executable instructions; The processor executes the computer-executable instructions stored in the memory, so that the processor performs the method according to claim 6 or 7.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, which are used to implement the method according to claim 6 or 7 when executed by a processor.

10. A computer program product, characterized in that The invention comprises a computer program, which implements the method according to claim 6 or 7 when being executed by a processor.

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