Level conversion circuit, driving method, display panel, circuit board and display device

Abstract

The invention discloses a level conversion circuit, a driving method, a display panel, a circuit board and a display device. The level conversion circuit is electrically connected between the driving chip and the gate driving circuit and used for converting a first driving signal of the driving chip into a second driving signal, the second driving signal is used for driving the gate driving circuit, the difference value between the high level and the low level of the first driving signal is a first difference value, and the difference value is a second difference value; the difference value between the high level and the low level of the second driving signal is a second difference value, and the second difference value is larger than the first difference value. According to the embodiment of the invention, the level conversion circuit is introduced, so that the difference value between the high level and the low level of the driving signal output by the display driving chip is increased, the effective utilization of the existing display driving chip is realized, and the resource waste can be reduced while the larger cross-voltage requirement is met.

Description

Technical Field

[0001] The present application belongs to the field of display technology, and in particular relates to a level conversion circuit and driving method, a display panel, a circuit board and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and flat panel display devices based on technologies such as Light Emitting Diode (LED) have been widely used in various consumer electronic products such as mobile phones, televisions, laptops, desktop computers, etc. due to their advantages such as high image quality, power saving, thin body and wide application range, becoming the mainstream in display devices.

[0003] However, the display performance of current OLED display products needs to be improved. Summary of the invention

[0004] The embodiments of the present application provide a level conversion circuit and a driving method, a display panel, a circuit board, and a display device. By introducing a level conversion circuit, the difference between the high level and the low level of the driving signal output by the display driver chip is increased, thereby achieving effective utilization of the existing display driver chip, and reducing the waste of resources while meeting a greater cross-voltage requirement.

[0005] In a first aspect, an embodiment of the present application provides a level conversion circuit, which is electrically connected between a driver chip and a gate driver circuit, and is used to convert a first drive signal of the driver chip into a second drive signal, the second drive signal is used to drive the gate driver circuit, the difference between the high level and the low level of the first drive signal is a first difference, the difference between the high level and the low level of the second drive signal is a second difference, and the second difference is greater than the first difference.

[0006] In a possible embodiment of the first aspect, at the same moment, a high potential of the second driving signal corresponds to a low potential of the first driving signal; or, at the same moment, a low potential of the second driving signal corresponds to a high potential of the first driving signal.

[0007] In a possible embodiment of the first aspect, a high level of the second drive signal is equal to a high level of the first drive signal, and a low level of the second drive signal is less than a low level of the first drive signal;

[0008] Alternatively, the high level of the second driving signal is greater than the high level of the first driving signal, and the low level of the second driving signal is equal to the low level of the first driving signal.

[0009] In a possible embodiment of the first aspect, the level conversion circuit includes:

[0010] A first output module, a first end of which is electrically connected to the first power supply end, and a second end of which is electrically connected to the gate drive circuit;

[0011] A second output module, a first end of which is electrically connected to the second power supply end, a second end of which is electrically connected to the gate drive circuit, and a control end of which is connected to the first drive signal;

[0012] An output control module, a first end of which is electrically connected to the reference power supply end, a second end of which is electrically connected to the control end of the first output module, and a control end of which is connected to the first driving signal;

[0013] Wherein, under the control of the output control module and the first driving signal, the first output module and the second output module are alternately turned on;

[0014] One of the first power supply terminal and the second power supply terminal is at a high level, and the other is at a low level. When the first power supply terminal is at a low level, the low level of the first power supply terminal is less than the low level of the first drive signal; when the first power supply terminal is at a high level, the high level of the first power supply terminal is greater than the high level of the first drive signal.

[0015] In a possible embodiment of the first aspect, when the first power supply terminal is at a low level, the high level of the second power supply terminal is equal to the high level of the first drive signal; when the first power supply terminal is at a high level, the low level of the second power supply terminal is equal to the low level of the first drive signal.

[0016] In a possible embodiment of the first aspect, the first output module includes a first transistor, a first electrode of the first transistor serves as a first end of the first output module, a second electrode of the first transistor serves as a second end of the first output module, and a gate of the first transistor serves as a control end of the first output module;

[0017] The second output module includes a second transistor, the first electrode of the second transistor serves as the first end of the second output module, the second electrode of the second transistor serves as the second end of the second output module, and the gate of the second transistor serves as the control end of the second output module;

[0018] The output control module includes a third transistor, the first electrode of the third transistor serves as the first end of the third output module, the second electrode of the third transistor serves as the second end of the third output module, and the gate of the third transistor serves as the control end of the third output module;

[0019] In a possible embodiment of the first aspect, when the first power supply terminal is at a low level, the second transistor is a P-type transistor, and the first transistor and the third transistor are N-type transistors;

[0020] In a possible embodiment of the first aspect, when the first power supply terminal is at a low level, the reference voltage configured at the reference power supply terminal is 0V or less than 0V;

[0021] Alternatively, when the first power supply terminal is at a high level, the first transistor and the third transistor are P-type transistors, and the second transistor is an N-type transistor;

[0022] In a possible embodiment of the first aspect, when the first power supply terminal is at a high level, the reference voltage configured at the reference power supply terminal is 0V or greater than 0V.

[0023] In a possible embodiment of the first aspect, a coupling module is further included, and the coupling module is electrically connected between the driving chip and the control end of the first output module;

[0024] In a possible embodiment of the first aspect, the coupling module includes a first capacitor, a first electrode of the first capacitor is electrically connected to the driving chip, and a second electrode of the first capacitor is electrically connected to the first output module.

[0025] Based on the same inventive concept, in a second aspect, an embodiment of the present application further provides a driving method of a level conversion circuit, which is applied to the level conversion circuit as described in any embodiment of the first aspect, and the method includes:

[0026] Using a driving chip to invert the original driving signal to obtain a first driving signal and output the first driving signal;

[0027] The control level conversion circuit converts the first driving signal into a second driving signal to drive the gate driving circuit.

[0028] Based on the same inventive concept, in a third aspect, an embodiment of the present application further provides a display panel, including:

[0029] Gate drive circuit;

[0030] And, in the level conversion circuit as described in any embodiment of the first aspect, the level conversion circuit is used to output a second drive signal, and the second drive signal is used to drive the gate drive circuit.

[0031] In a possible embodiment of the third aspect, the driving chip is used to output N first driving signals, the timing of the N first driving signals is different, the display panel includes N level conversion circuits, the N level conversion circuits correspond one-to-one to the N first driving signals, and N is an integer greater than or equal to 2.

[0032] Based on the same inventive concept, in a fourth aspect, an embodiment of the present application further provides a circuit board, the circuit board is used to drive a display panel, and the display panel includes a gate driving circuit;

[0033] The circuit board includes the level conversion circuit as described in any embodiment of the first aspect;

[0034] In a possible embodiment of the third aspect, the circuit board includes a printed circuit board or a flexible circuit board;

[0035] In a possible embodiment of the third aspect, the transistors of the level conversion circuit include an N-type metal oxide semiconductor field effect transistor and a P-type metal oxide semiconductor field effect transistor.

[0036] Based on the same inventive concept, in a fifth aspect, an embodiment of the present application further provides a display device, including:

[0037] A display panel including a gate drive circuit;

[0038] A driving chip, used for providing a first driving signal;

[0039] And, in the level conversion circuit as described in any embodiment of the first aspect, the level conversion circuit is used to convert the first drive signal into a second drive signal, and the second drive signal is used to drive the gate drive circuit.

[0040] In a possible embodiment of the fifth aspect, the level conversion circuit is disposed on the display panel.

[0041] In a possible embodiment of the fifth aspect, when the display device further includes a circuit board, the level conversion circuit is disposed on the circuit board.

[0042] In a possible embodiment of the fifth aspect, the second power supply terminal is provided by a driver chip, and the second power supply terminal is also electrically connected to the gate drive circuit;

[0043] In a possible embodiment of the fifth aspect, the first power supply terminal is provided by a power supply or circuit outside the driving chip, and the first power supply terminal is also electrically connected to the gate driving circuit.

[0044] The level conversion circuit and driving method, display panel, circuit board and display device of the embodiments of the present application, wherein the level conversion circuit is electrically connected between the driving chip and the gate driving circuit, and is used to convert the first driving signal of the driving chip into a second driving signal, the second driving signal is used to drive the gate driving circuit, and the second difference between the high level and the low level of the second driving signal is greater than the first difference between the high level and the low level of the first driving signal. Therefore, by introducing the level conversion circuit, the difference between the high level and the low level of the driving signal output by the display driving chip is increased, thereby achieving effective utilization of the existing display driving chip, and reducing waste of resources while meeting greater cross-voltage requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Other features, objects and advantages of the present application will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals represent the same or similar features and the accompanying drawings are not drawn to scale.

[0046] Figure 1 This is a schematic diagram of a connection relationship of a level conversion circuit provided in an embodiment of the present application;

[0047] Figure 2 is a signal timing diagram of the input signal and the output signal of the level conversion circuit provided in an embodiment of the present application;

[0048] Figure 3 is another signal timing diagram of the input signal and the output signal of the level conversion circuit provided in the embodiment of the present application;

[0049] Figure 4 is a structural schematic diagram of a level conversion circuit provided in an embodiment of the present application;

[0050] Figure 5 is another structural schematic diagram of the level conversion circuit provided in an embodiment of the present application;

[0051] Figure 6-a is a structural schematic diagram of a level conversion circuit 20 that can meet lower voltage requirements provided in an embodiment of the present application;

[0052] Figure 6-b It is a structural schematic diagram of a level conversion circuit 20 that can meet higher voltage requirements provided in an embodiment of the present application;

[0053] Figure 7 It is a flow chart of a driving method of a level conversion circuit provided in an embodiment of the present application;

[0054] Figure 8-a is a structural schematic diagram of a display panel provided in an embodiment of the present application;

[0055] Figure 8-b is another structural schematic diagram of a display panel provided in an embodiment of the present application;

[0056] Figure 9-a This is a schematic diagram of a power connection of a gate driving circuit in a display device provided in an embodiment of the present application;

[0057] Figure 9-b This is another power connection schematic diagram of the gate driving circuit in the display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0058] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application and are not configured to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0059] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0060] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0061] It is obvious to those skilled in the art that various modifications and changes can be made in the present application without departing from the spirit or scope of the present application. Therefore, the present application is intended to cover modifications and changes of the present application that fall within the scope of the corresponding claims (technical solutions for protection) and their equivalents. It should be noted that the implementation methods provided in the embodiments of the present application can be combined with each other without contradiction.

[0062] Before describing the technical solutions provided by the embodiments of the present application, in order to facilitate the understanding of the embodiments of the present application, the present application first specifically describes the problems existing in the related art:

[0063] In the related art, a display driver chip (DDIC) may provide a driving signal to a gate drive circuit (Gate In Panel, GIP). The driving signal may include a power signal (such as a fixed high power voltage and a fixed low power voltage), a trigger signal (STV signal) and a clock signal (CLK signal), so that the gate drive circuit operates under the control of the driving signal.

[0064] The voltage of the driving signal that the display driver chip can provide usually includes a high voltage VGH (VGH greater than 0) and a low voltage VGL (VGL less than 0). VGH and VHL together determine the voltage range of the driving signal that the display driver chip can output, that is, the maximum voltage range of the driving signal is the difference between VGH and VGL.

[0065] However, with the continuous advancement of display technology and the emergence of new display devices, the demand for gate drive circuits on cross-voltage is also gradually increasing. When the cross-voltage required by the gate drive circuit exceeds the output capacity of the display driver chip, even if the existing display driver chip is still intact in performance, it cannot meet the needs of the gate drive circuit, resulting in idleness and waste of resources.

[0066] Based on this, the embodiments of the present application provide a level conversion circuit and driving method, a display panel, a circuit board and a display device. By introducing the level conversion circuit, the difference between the high level and the low level of the driving signal output by the display driver chip is increased, thereby achieving effective utilization of the existing display driver chip, and reducing the waste of resources while meeting greater cross-voltage requirements.

[0067] The level conversion circuit and driving method, display panel, circuit board and display device provided in the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0068] Figure 1 It is a schematic diagram of a connection relationship of a level conversion circuit provided in an embodiment of the present application.

[0069] like Figure 1 As shown, the level conversion circuit 20 is electrically connected between the driving chip 10 and the gate driving circuit 30 .

[0070] The level conversion circuit 20 may be used to convert a first driving signal of the driving chip 10 into a second driving signal.

[0071] The second driving signal may be used to drive the gate driving circuit 30 .

[0072] The gate driving circuit 30 is used to generate a gate driving signal, and the gate driving circuit 30 is electrically connected to the sub-pixels in the display panel. The sub-pixels can write data signals, emit light, etc. under the control of the gate driving signal.

[0073] It should be noted that both the first driving signal and the second driving signal are pulse signals. In the embodiment of the present application, a relatively high potential level in the pulse signal can be called a high level, and a relatively low potential level can be called a low level.

[0074] The difference between the high level and the low level of the first drive signal is a first difference ΔU1, the difference between the high level and the low level of the second drive signal is a second difference ΔU2, and ΔU2>ΔU1. In other words, the level conversion circuit 20 can increase the first difference ΔU1 between the high level and the low level of the input signal (the first drive signal) to the second difference ΔU2.

[0075] According to the level conversion circuit 20 provided in the embodiment of the present application, the level conversion circuit 20 is electrically connected between the driver chip 10 and the gate driver circuit 30, and is used to convert the first drive signal of the driver chip 10 into a second drive signal, and the second drive signal is used to drive the gate driver circuit 30. The second difference ΔU2 between the high level and the low level of the second drive signal is greater than the first difference ΔU1 between the high level and the low level of the first drive signal. Therefore, by introducing the level conversion circuit 20, the difference between the high level and the low level of the first drive signal output by the driver chip 10 is increased, and the existing driver chip 10 is effectively utilized. It can meet the greater cross-voltage requirements of the gate driver circuit 30 while reducing the waste of resources.

[0076] In some embodiments, Figure 2 As shown, at the same time, the high potential of the second drive signal corresponds to the low potential of the first drive signal; or, at the same time, the low potential of the second drive signal corresponds to the high potential of the first drive signal. In other words, when one of the second drive signal and the first drive signal reaches a high level, the other reaches a low level, which can be simply understood as the first drive signal and the second drive signal have opposite phases but different cross-voltage ranges. For example, when the first drive signal is at a high level, the second drive signal is at a low level; when the first drive signal is at a low level, the second drive signal is at a high level. In the embodiment of the present application, the driver chip 10 can output the original gate circuit drive signal in an inverted manner, and the output first drive signal is transmitted to the level conversion circuit 20. Since the level conversion circuit 20 can convert the first drive signal into a second drive signal, the second drive signal has an opposite phase to the first drive signal. Therefore, the second drive signal after two inversions has the same phase as the original gate circuit drive signal, and the cross-voltage range of the original gate circuit drive signal can be increased on the basis of the unchanged control logic, which can meet the larger cross-voltage requirements of the gate drive circuit 30, and realize the effective use of the existing driver chip 10, which can meet the larger cross-voltage requirements while reducing the waste of resources.

[0077] Figure 31 is a signal timing diagram of an input signal (first drive signal) and an output signal (second drive signal) of the level conversion circuit 20 provided in an embodiment of the present application.

[0078] like Figure 3 The second driving signal (1), the second driving signal (2), and the second driving signal (3) shown correspond to different cross-voltage requirements of the gate driving circuit 30 respectively.

[0079] In one embodiment, the gate drive circuit 30 has a lower voltage requirement, see Figure 3 In the signal waveform of the second drive signal (1), the high level of the second drive signal is equal to the high level of the first drive signal, and the low level of the second drive signal is less than the low level of the first drive signal. In the embodiment of the present application, the high level of the first drive signal is used as a reference, and the level conversion circuit 20 can be used to reduce the low level of the first drive signal, which can meet the lower voltage requirement of the gate drive circuit 30.

[0080] In yet another embodiment, the gate drive circuit 30 has a higher voltage requirement, see Figure 3 In the signal waveform of the second drive signal (2), the high level of the second drive signal is greater than the high level of the first drive signal, and the low level of the second drive signal is equal to the low level of the first drive signal. In the embodiment of the present application, the high level of the first drive signal can be increased by using the level conversion circuit 20 based on the low level of the first drive signal, so as to meet the higher voltage requirement of the gate drive circuit 30.

[0081] In yet another embodiment, the gate drive circuit 30 has higher and lower voltage requirements, see Figure 3 In the signal waveform of the second drive signal (3), the high level of the second drive signal is greater than the high level of the first drive signal, and the low level of the second drive signal is less than the low level of the first drive signal. In the embodiment of the present application, by using the level conversion circuit 20 to increase the high level of the first drive signal while reducing the low level of the first drive signal, the voltage range of the first drive signal can be flexibly increased, and the requirements of the lower voltage and the higher voltage of the gate drive circuit 30 can be met at the same time.

[0082] Some exemplary structures of the level conversion circuit 20 are introduced below. It should be noted that the following are only some examples and are not intended to limit the present application. As long as the circuit structure can convert the first drive signal with a small difference into the second drive signal with a large difference, it can be applied to the level conversion circuit.

[0083] Figure 4 Schematic diagram of a structure of a level conversion circuit 20 provided in an embodiment of the present application.

[0084] As an example, Figure 4 As shown, the level conversion circuit 20 may include a first output module 21 and a second output module 22. The first output module 21 and the second output module 22 may alternately transmit power signals of the first power terminal and the second power terminal to the gate driving circuit 30.

[0085] It should be noted that if Figure 3 The second driving signals (1), (2), and (3) shown in the figure can correspond to different cross-voltage requirements of the gate driving circuit. In order to achieve the cross-voltage requirements of the gate driving circuit 30, the cross-voltage requirements can be flexibly adjusted. Figure 4 The magnitude of the power supply voltage configured at the first power supply terminal and the second power supply terminal in the embodiment can generate Figure 3 Any one of the second driving signals.

[0086] In one example, you can continue to refer to Figure 4 , the first output module 21 and the second output module 22 may include triggers, and the trigger conditions are different, one of which is a high level trigger and the other is a low level trigger, so that the first output module 21 and the second output module 22 can alternately reach the trigger condition. When the first output module 21 meets the trigger condition, it can output the power signal of the first power supply end; when the second output module 22 meets the trigger condition, it can output the power signal of the second power supply end. Therefore, the power signals of the first power supply end and the second power supply end can be alternately transmitted to the gate drive circuit 30, and by adjusting the size of the power supply voltage configured for the first power supply end and the second power supply end, it can generate Figure 3 Any one of the second driving signals.

[0087] Figure 5 2 is another structural diagram of the level conversion circuit 20 provided in an embodiment of the present application.

[0088] like Figure 5 As shown, the level conversion circuit 20 may include a first output module 21 , a second output module 22 and an output control module 23 .

[0089] A first end of the first output module 21 is electrically connected to the first power supply end, and a second end of the first output module 21 is electrically connected to the gate driving circuit 30 .

[0090] The first end of the second output module 22 is electrically connected to the second power supply end, the second end of the second output module 22 is electrically connected to the gate drive circuit 30, and the control end of the second output module 22 can be connected to the first drive signal. The second output module 22 can output the power signal of the second power supply end to the gate drive circuit 30 in response to the first drive signal.

[0091] A first end of the output control module 23 is electrically connected to the reference power supply end, a second end of the output control module 23 is electrically connected to the control end of the first output module 21 , and the control end of the output control module 23 is connected to the first driving signal.

[0092] Under the control of the output control module 23 and the first driving signal, the first output module 21 and the second output module 22 can be turned on alternately, so that the power signals of the first power supply end and the second power supply end can be alternately transmitted to the gate driving circuit 30.

[0093] Among them, one of the first power supply terminal and the second power supply terminal is at a high level, and the other is at a low level, which are used to generate a high level and a low level of the second driving signal.

[0094] When the first power supply terminal is at a low level, the low level of the first power supply terminal may be lower than the low level of the first driving signal, so as to meet a lower voltage requirement of the gate driving circuit 30 .

[0095] When the first power supply terminal is at a high level, the high level of the first power supply terminal may be greater than the high level of the first driving signal, so as to meet a higher voltage requirement of the gate driving circuit 30 .

[0096] In the embodiment of the present application, the level conversion circuit 20 can alternately transmit the power signals of the first power supply end and the second power supply end to the gate drive circuit 30 through the coordinated work of the first output module 21, the second output module 22 and the output control module 23, and can drive the gate drive circuit 30 with a larger cross-voltage requirement.

[0097] In one embodiment, when the first power supply terminal is at a low level VGL2, the low level VGL2 of the first power supply terminal is less than the low level VGL1 of the first drive signal, and the high level VGH of the second power supply terminal is equal to the high level VGH of the first drive signal, which can be used to output Figure 3 The second drive signal (1) is shown.

[0098] In another embodiment, when the first power supply terminal is at a high level VGH2, the high level VGH2 of the first power supply terminal is greater than the high level VGH1 of the first drive signal, and the low level VGL of the second power supply terminal is equal to the low level VGL of the first drive signal, which can be used to output Figure 3 The second drive signal (2) is shown.

[0099] In one embodiment, the second power supply terminal is a power supply terminal of the driver chip 10. In the embodiment of the present application, the driver chip 10 provides a power signal to the second power supply terminal, so that a level of the second drive signal is equal to a level of the first drive signal, and the following can be generated: Figure 3The second driving signal (1) or the second driving signal (2) shown can effectively utilize the existing pin functions of the driving chip 10, thereby saving resources and costs.

[0100] In another embodiment, the second power supply terminal may also be a power supply terminal of other power supplies, and the voltage of the power supply signal of other power supplies may be configured according to the actual cross-voltage requirement of the gate drive circuit 30, which is more flexible and can generate Figure 3 Any one of the second drive signal (1), the second drive signal (2) and the second drive signal (3) shown.

[0101] In some embodiments, see Figure 6-a or Figure 6-b The first output module 21 may include a first transistor T1. The first electrode of the first transistor T1 may serve as the first end of the first output module 21, the second electrode of the first transistor T1 may serve as the second end of the first output module 21, and the gate of the first transistor T1 may serve as the control end of the first output module 21.

[0102] The second output module 22 may include a second transistor T2. The first electrode of the second transistor T2 may serve as the first end of the second output module 22, the second electrode of the second transistor T2 may serve as the second end of the second output module 22, and the gate of the second transistor T2 may serve as the control end of the second output module 22.

[0103] The output control module 23 may include a third transistor T3. The first electrode of the third transistor T3 may serve as the first end of the output control module 23, the second electrode of the third transistor T3 may serve as the second end of the output control module 23, and the gate of the third transistor T3 may serve as the control end of the output control module 23.

[0104] In the embodiment of the present application, by controlling the conduction and cutoff of each transistor, power signals of different levels can be alternately output from the first power supply end and the second power supply end, thereby generating a second drive signal with a wider voltage range, providing a more stable drive signal for the gate drive circuit 30.

[0105] Figure 6-a is a schematic diagram of a structure of a level conversion circuit 20 that can meet lower voltage requirements provided by an embodiment of the present application, and can generate Figure 3 The second drive signal (1) is shown.

[0106] In one embodiment, Figure 6-aAs shown, when the first power supply terminal is at a low level, the second transistor T2 is a P-type transistor, and the first transistor T1 and the third transistor T3 are N-type transistors. In the embodiment of the present application, the first transistor T1 and the third transistor T3 can transmit the power signal VGL2 of the first power supply terminal to the gate drive circuit 30 in response to the high level VGH of the first drive signal; the second transistor T2 can transmit the power signal VGH of the second power supply terminal to the gate drive circuit 30 in response to the low level VGL of the first drive signal, so that VGH and VGL2 can be transmitted to the gate drive circuit 30 alternately to meet the lower voltage requirement of the gate drive circuit 30, thereby generating Figure 2 The second drive signal (1) is shown.

[0107] In yet another embodiment, see Figure 6-a , when the first power supply terminal is at a low level, the reference voltage Vref1 configured at the reference power supply terminal is 0V or <0V. In the embodiment of the present application, the magnitude of the reference voltage Vref1 determines the gate voltage of the first transistor T1, and the source voltage of the first transistor T1 is VGL2, so the on or off state of the first transistor T1 can be accurately controlled by adjusting the voltage magnitude of Vref1 under different values ​​of VGL2.

[0108] Figure 6-b is a schematic diagram of a structure of a level conversion circuit 20 provided in an embodiment of the present application that can meet higher voltage requirements and can generate Figure 3 The second drive signal (2) is shown.

[0109] In one embodiment, Figure 6-b As shown, when the first power supply terminal is at a high level, the first transistor T1 and the third transistor T3 are P-type transistors, and the second transistor T2 is an N-type transistor. In the embodiment of the present application, the first transistor T1 and the third transistor T3 can transmit the power signal VGH2 of the first power supply terminal to the gate drive circuit 30 in response to the low level VGL of the first drive signal; the second transistor T2 can transmit the power signal VGH2 of the second power supply terminal to the gate drive circuit 30 in response to the high level VGH1 of the first drive signal, so that VGH2 and VGL can be transmitted to the gate drive circuit 30 alternately to meet the higher voltage requirements of the gate drive circuit 30, thereby generating a voltage as shown in FIG. Figure 3 The second drive signal (2) is shown.

[0110] In yet another embodiment, see Figure 6-b, when the first power supply terminal is at a high level, the reference voltage Vref2 configured at the reference power supply terminal is 0V or > 0V. In the embodiment of the present application, the magnitude of the reference voltage Vref2 determines the gate voltage of the first transistor T1, and the source voltage of the first transistor T1 is VGH2, so the on or off state of the first transistor T1 can be accurately controlled by adjusting the voltage magnitude of Vref2 under different values ​​of VGH2.

[0111] It should be noted that the inventors have found that the source of the second transistor T2 is connected to VGH or VGL, and the gate of the second transistor T2 is connected to VGH or VGL, so the state of the second transistor T2 is simple and controllable, and there is no need to introduce the output control module 23. Since the source of the first transistor T1 is connected to VGL2 or VGH2, VGL2 or VGH2 is determined according to the cross-voltage requirement of the gate drive circuit 30, it is necessary to introduce the output control module 23 to effectively control the on and off state of the first transistor T1.

[0112] The inventors further discovered that when controlling the second transistor T2 to be turned on, the first transistor T1 needs to be effectively turned off. Figure 6-a and Figure 6-b In the case where the coupling module 24 is not included, the third transistor T3 is turned off first, so that the gate of the first transistor T1 is suspended, so that the first transistor T1 does not meet the conduction condition. However, the suspension of the gate of the first transistor T1 will make the Vgs of the first transistor T1 uncertain, resulting in the problem that the first transistor T1 cannot be effectively turned off. Therefore, the coupling module can be introduced to ensure that the gate of the first transistor T1 is always connected to a certain voltage, so that the Vgs of the first transistor T1 is a certain value, thereby ensuring that the first transistor T1 can be effectively turned off.

[0113] In some embodiments, you may continue to refer to Figure 6-a or Figure 6-b The level conversion circuit 20 may further include a coupling module 24, which is electrically connected between the driving chip 10 and the control end of the first output module 21. The coupling module 24 can ensure that the gate of the first transistor T1 is always connected to a certain voltage, and the voltage can effectively control the conduction and shutdown of the first transistor T1.

[0114] In one embodiment, you can continue to refer to Figure 6-a or Figure 6-b The coupling module 24 may include a first capacitor C1 , a first electrode of the first capacitor C1 is electrically connected to the driving chip 10 , and a second electrode of the first capacitor C1 is electrically connected to the first output module 21 .

[0115] The following is a detailed description of Vref1=0V as an example Figure 6-a The working process of the level conversion circuit 20 shown in FIG.

[0116] 1) The driver chip 10 inverts the original gate circuit drive signal and outputs the obtained first drive signal, whose levels are VGH and VGL1, and transmits it to the level conversion circuit 20;

[0117] 2) When the first driving signal is at a high level VGH, the second transistor T2 of the level conversion circuit 20 is turned off, and the third transistor T3 is turned on, so the gate of the first transistor T1 is Vref1 = 0V.

[0118] The voltage difference Vgs between the gate and the source of the first transistor T1 is 0-VGL2>the threshold voltage Vth_N of the first transistor T1, and the first transistor T1 is turned on, so the second driving signal is at a low level VGL2 at this time.

[0119] At this time, the left plate potential of capacitor C1 is VGH, and the right plate potential is 0V.

[0120] 3) When the first driving signal is at a low level VGL1, the second transistor T2 is turned on and the third transistor T3 is turned off. The second transistor T2 is turned on, so the second driving signal is at a high level VGH at this time.

[0121] It should be noted that, at this time, if the coupling module 24 is not connected, since the third transistor T3 is disconnected, the gate of the first transistor T1 is in a suspended state, so that the first transistor T1 is not turned on, but it cannot be ensured to be turned off quickly and effectively, so it cannot be ensured that the second drive signal is a pure high level VGH at this time, which will affect the output quality of the second drive signal. Therefore, the coupling module 24 can be connected to output a high-quality second drive signal.

[0122] According to the capacitor bootstrap effect (the voltage difference stored on the left and right plates of the capacitor cannot change suddenly), since the voltage change of the left plate of capacitor C1 is VGL1-VGH, the potential of the right plate of capacitor C1 is 0+(VGL1-VGH), so the gate potential of the first transistor T1 is 0+(VGL1-VGH). The voltage difference Vgs between the gate and the source of the first transistor T1 is 0+(VGL1-VGH)-VGL2<the threshold voltage Vth_N of the first transistor T1 (this voltage relationship is the prerequisite of the scheme), which meets the turn-off condition of the first transistor T1, and the first transistor T1 can be quickly disconnected.

[0123] In the embodiment of the present application, by introducing the coupling module 24, the level conversion circuit 20 can achieve the output of the high-quality second drive signal when processing the first drive signal output by the driver chip 10. Specifically, when the first drive signal becomes a low level VGL1, due to the bootstrap effect of the capacitor C1, the Vgs of the first transistor T1 is lower than its threshold voltage Vth_N, thereby ensuring that the first transistor T1 can be quickly and effectively turned off, so that the second drive signal can quickly reach the high level VGH. The problem of being unable to turn off quickly due to the gate of the first transistor T1 being suspended when the third transistor T3 is disconnected is effectively solved, thereby improving the output quality and stability of the second drive signal, and ensuring the quality and reliability of the output signal.

[0124] It should be noted that Figure 6-a The power signal VGL1 generated by the driver chip 10 shown does not need to be connected to the gate drive circuit 30. The power signal VGH generated by the driver chip 10 can be connected to the gate drive circuit to provide a power signal for the gate drive circuit 30, thereby improving the utilization rate of the chip pins and saving resources and costs. In addition, other circuits can be used to generate VGL2 power to power the gate drive circuit 30 and the level conversion circuit 20.

[0125] In another embodiment, see Figure 6-a , since VGL2 is determined by the specific cross-voltage requirement of the gate drive circuit 30, there is a situation where the turn-off condition of the first transistor T1 is not met when Vref1 = 0V, resulting in the first transistor T1 not being able to be turned off quickly and effectively when it needs to be turned off. That is, when Vref1 = 0V, the turn-off condition of the first transistor T1 "the voltage difference between the gate and the source of the first transistor T1 0 + (VGL1-VGH) - VGL2 < the threshold voltage Vth_N of the first transistor T1" is not met, so the setting of Vref1 needs to be < 0V and also needs to meet:

[0126]

[0127] Wherein, VGH is the high level of the first driving signal, VGL1 is the low level of the first driving signal, VGL2 is the signal of the first power supply terminal, Vth_T1 is the threshold voltage of the first switch tube T1, and Vth_T3 is the threshold voltage of the third switch tube T3. Figure 6-a The voltage magnitude of the reference voltage Vref1 at the reference power supply end can accurately control the rapid on and off of the first output module 21, thereby quickly and accurately alternately outputting the power signals of the first power supply end and the second power supply end, and quickly and accurately generating the second driving signal.

[0128] In the embodiment of the present application, the first output module 21 (specifically the first transistor T1) can be precisely controlled to turn on and off quickly by adjusting the voltage of the reference voltage Vref1 at the reference power supply terminal. When Vref1 = 0V, since the turn-off condition of the first transistor T1 is not met, the first transistor T1 cannot be turned off quickly and effectively when it needs to be turned off.

[0129] The following is a detailed description of Vref2 = 0V as an example Figure 6-b The working process of the level conversion circuit 20 shown in FIG.

[0130] 1) When the first drive signal is at a low level VGL, the second transistor T2 is turned off and the third transistor T3 is turned on, so the gate of the first transistor T1 is Vref2 = 0 V. The voltage difference Vgs between the gate and the source of the first transistor T1 is 0-VGH2 < the threshold voltage Vth_P of the first transistor T1, and the first transistor T1 is turned on, so the second drive signal outputs a high level VGH2.

[0131] At this time, the left plate potential of capacitor C1 is VGL, and the right plate potential is 0V.

[0132] 2) When the first drive signal is at a high level VGH1, the second transistor T2 is turned on and the third transistor T3 is turned off. Since the voltage on the left plate of capacitor C1 is VGH1-VGL and the original voltage on the right plate is 0V, the potential on the right plate is approximately changed to 0+(VGH1-VGL) by using the capacitor bootstrap effect, so the gate of the first transistor T1 is approximately 0+(VGH1-VGL). The voltage difference Vgs between the gate and the source of the first transistor T1 is approximately 0+(VGH1-VGL)-VGH2>the threshold voltage Vth_P of the first transistor T1 (this voltage relationship is a prerequisite for the scheme), and the first transistor T1 is turned off, so the second drive signal outputs a low level VGL.

[0133] In the embodiment of the present application, a coupling module 24 is introduced, and the level conversion circuit 20 can realize the output of a high-quality second drive signal when processing the first drive signal output by the driver chip 10. Specifically, when the first drive signal becomes a high level VGH1, due to the bootstrap effect of the capacitor C1, the Vgs of the first transistor T1 is higher than its threshold voltage Vth_P, thereby ensuring that the first transistor T1 can be quickly and effectively turned off, so that the second drive signal can quickly reach the low level VGL. The problem of being unable to turn off quickly due to the gate of the first transistor T1 being suspended when the third transistor T3 is disconnected is effectively solved, thereby improving the output quality and stability of the second drive signal, and ensuring the quality and reliability of the output signal.

[0134] It should be noted that when the display screen sets a higher ELVDD, the gate drive circuit 30 requires a higher VGH voltage. When the driver chip 10 cannot output such a high VGH power supply and corresponding drive signal, it can be used. Figure 6-b The level conversion circuit 20 is shown.

[0135] In another embodiment, see Figure 6-a , since VGH2 is determined by the specific cross-voltage requirement of the gate drive circuit 30, there is a situation where the turn-off condition of the first transistor T1 is not met when Vref2 = 0V, resulting in the first transistor T1 not being able to be turned off quickly and effectively when it needs to be turned off. That is, when Vref2 = 0V, the turn-off condition of the first transistor T1 "the voltage difference between the gate and the source of the first transistor T1 0 + (VGH1-VGL) - VGH2> the threshold voltage Vth_P of the first transistor T1" is not met, so the setting of Vref2 needs to be > 0V and needs to meet:

[0136]

[0137] Wherein, VGL is the low level of the first driving signal, VGH1 is the high level of the first driving signal, VGH2 is the signal of the second power supply terminal, Vth_T1 is the threshold voltage of the first switch tube T1, and Vth_T3 is the threshold voltage of the third switch tube T3. Figure 6-b The voltage of the power signal Vref2 at the reference power end can meet the requirement of accurately controlling the rapid on and off of the first transistor T1, thereby quickly and accurately outputting the power signals of the first power end and the second power end alternately, ensuring the quality and reliability of the output signal.

[0138] It should be noted that the threshold voltage Vth_P of the P-type transistor is a negative value, for example, Vth_P=-1V, and the threshold voltage Vth_N of the N-type device is a positive value, for example, Vth_N=+1V.

[0139] Based on the same inventive concept, Figure 7 As shown, an embodiment of the present application further provides a driving method of a level conversion circuit, which is applied to the level conversion circuit described in any of the above embodiments. The driving method of the level conversion circuit includes steps S110 and S120.

[0140] S110, using the driving chip 10 to perform inversion processing on the original driving signal to obtain a first driving signal and output the first driving signal.

[0141] The original driving signal is the gate circuit driving signal that the driving chip 10 should originally output, and the voltage range of the original driving signal cannot meet the larger voltage requirement of the gate driving circuit 30 .

[0142] Specifically, the driving chip 10 can be used to invert the original driving signal and then output a first driving signal, where the first driving signal is opposite to the original driving signal in phase and the cross-voltage range remains unchanged.

[0143] S120 , controlling the level conversion circuit 20 to convert the first driving signal into a second driving signal to drive the gate driving circuit 30 .

[0144] Specifically, the level conversion circuit 20 can be controlled to convert the first drive signal into a second drive signal. The second drive signal has a phase opposite to the first drive signal but a different voltage range. The voltage range of the second drive signal is greater than the voltage range of the first drive signal. Thus, the second drive signal can be used to drive the gate drive circuit, thereby meeting the greater voltage requirement of the gate drive circuit.

[0145] In the embodiment of the present application, the driver chip 10 can output the original gate circuit drive signal in an inverted manner, and the output first drive signal is transmitted to the level conversion circuit 20. Since the level conversion circuit 20 can convert the first drive signal into a second drive signal, the second drive signal has a phase opposite to the first drive signal and a different voltage range. Therefore, the second drive signal after two inversions has the same phase as the original gate circuit drive signal, and the voltage range of the original gate circuit drive signal can be increased on the basis of unchanged control logic, which can meet the larger voltage requirement of the gate drive circuit 30, thereby realizing effective utilization of the existing driver chip 10 and reducing resource waste while meeting the larger voltage requirement.

[0146] Based on the same inventive concept, Figure 8-a As shown, the embodiment of the present application also provides a display panel 100, which may include a gate driving circuit 30 and a level conversion circuit 20 as described in any of the above embodiments, wherein the level conversion circuit 20 is used to output a second driving signal, and the second driving signal is used to drive the gate driving circuit 30.

[0147] In the embodiment of the present application, the level conversion circuit 20 may be located on the display panel, which can greatly improve the integration level and reduce the overall volume and weight.

[0148] It should be noted that, since the display panel 100 includes the level conversion circuit 20 provided by any one of the above embodiments, the display panel 100 has all the beneficial effects of the above level conversion circuit 20 .

[0149] In some embodiments, you may continue to refer to Figure 8-aThe driver chip 10 is used to output N first drive signals (STV1, CLK1, CLK2, etc.), and the timing of the N first drive signals is different. The display panel 100 may include N level conversion circuits 20, and the N level conversion circuits 20 correspond to the N first drive signals one by one, where N is an integer greater than or equal to 2. In the embodiment of the present application, each level conversion circuit 20 performs level conversion for a specific first drive signal, which helps to improve the stability and accuracy of the signal.

[0150] In one embodiment, the transistor of the level conversion circuit 20 is a thin film transistor (TFT). In the embodiment of the present application, the transistor of the level conversion circuit 20 located on the display panel 100 can be a thin film transistor (TFT), which can achieve more accurate and reliable control and improve the response speed.

[0151] Based on the same inventive concept, Figure 8-b As shown, the embodiment of the present application further provides a circuit board 200 , which is used to drive the display panel 100 . The display panel 100 may include a gate driving circuit 30 .

[0152] The circuit board 200 may include the level conversion circuit 20 described in any one of the above embodiments.

[0153] In some embodiments, the circuit board 200 may include a printed circuit board or a flexible circuit board.

[0154] In some embodiments, the transistors of the level conversion circuit 20 include two types of transistors: N-type metal oxide semiconductor field effect transistor (NMOS-FET) and P-type metal oxide semiconductor field effect transistor (PMOS-FET).

[0155] In the embodiment of the present application, the level conversion circuit 20 can be located on a printed circuit board PCB or a flexible circuit board FPC outside the screen body, so the level conversion circuit 20 can be disassembled for easy maintenance. In addition, it can be determined whether the existing driver chip 10 can be directly used according to whether the gate drive circuit 30 has a higher cross-voltage requirement, thereby determining whether to connect the level conversion circuit 20, and if the gate drive circuit 30 has a higher cross-voltage requirement, it can be determined according to the following example. Figure 2 Different high voltage requirements shown in the figure can be connected to different level conversion circuits 20, which is more flexible.

[0156] It should be noted that, since the circuit board 200 includes the level conversion circuit 20 provided by any one of the above embodiments, the circuit board 200 has all the beneficial effects of the above level conversion circuit 20 .

[0157] Based on the same inventive concept, the embodiment of the present application further provides a display device 1000, including:

[0158] The display panel 100 includes a gate driving circuit 30;

[0159] A driving chip 10, used for providing a first driving signal;

[0160] And, as in any of the above-mentioned embodiments, the level conversion circuit 20 is used to convert the first driving signal into a second driving signal, and the second driving signal is used to drive the gate driving circuit.

[0161] The display device 1000 includes the level conversion circuit 20 provided by any one of the above embodiments, so the display device 1000 has all the beneficial effects of the above level conversion circuit 20 .

[0162] In some embodiments, the level conversion circuit 20 is disposed on the display panel 100. In the embodiment of the present application, the level conversion circuit 10 is disposed on the display panel 100, which can improve the integration of the entire display device 1000, simplify the assembly process, and improve the overall reliability of the product.

[0163] In one embodiment, when the display device further includes a circuit board 200, the level conversion circuit 10 can also be disposed on the circuit board 200. In the embodiment of the present application, the level conversion circuit 10 is disposed on the circuit board 200, which can flexibly cope with different cross-voltage requirements of the gate driving circuit 30.

[0164] In one embodiment, Figure 9-a or Figure 9-b As shown, the second power supply terminal is provided by the driver chip 10, and the second power supply terminal is also electrically connected to the gate driving circuit 30. In the embodiment of the present application, the driver chip 10 provides the second power supply terminal, which helps to effectively utilize resources, reduce the number of external power supplies, and reduce costs.

[0165] In one embodiment, continue to see Figure 9-a or Figure 9-b The first power supply terminal is provided by a power supply or circuit outside the driver chip, and the first power supply terminal is also electrically connected to the gate drive circuit 30, so as to provide the gate drive circuit 30 with a larger cross-voltage requirement while providing it with a matching power supply signal, making full use of existing resources and saving costs.

[0166] It should be noted that the display device 1000 may be at least one of a wearable device, a camera, a mobile phone, a tablet computer, a display screen, a television, and a vehicle-mounted display terminal. Since the display device 1000 includes the level conversion circuit 20 provided by any of the above embodiments, the display device 1000 has all the beneficial effects of the above level conversion circuit 20.

[0167] It should be understood that in the embodiment of the present application, "B corresponding to A" means that B is associated with A, and B can be determined according to A. However, it should also be understood that determining B according to A does not mean determining B only according to A, and B can also be determined according to A and / or other information.

[0168] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A level conversion circuit, characterized in that: The level conversion circuit is electrically connected between the driving chip and the gate driving circuit, and is used to convert the first driving signal of the driving chip into a second driving signal, the second driving signal is used to drive the gate driving circuit, the difference between the high level and the low level of the first driving signal is a first difference, the difference between the high level and the low level of the second driving signal is a second difference, and the second difference is greater than the first difference.

2. The level conversion circuit according to claim 1, characterized in that: At the same time, the high potential of the second driving signal corresponds to the low potential of the first driving signal; or, at the same time, the low potential of the second driving signal corresponds to the high potential of the first driving signal; Preferably, the high level of the second driving signal is equal to the high level of the first driving signal, and the low level of the second driving signal is lower than the low level of the first driving signal; Alternatively, the high level of the second driving signal is greater than the high level of the first driving signal, and the low level of the second driving signal is equal to the low level of the first driving signal.

3. The level conversion circuit according to claim 1, characterized in that: The level conversion circuit comprises: A first output module, a first end of which is electrically connected to the first power supply end, and a second end of which is electrically connected to the gate drive circuit; A second output module, a first end of which is electrically connected to the second power supply end, a second end of which is electrically connected to the gate drive circuit, and a control end of which is connected to the first drive signal; An output control module, a first end of which is electrically connected to a reference power supply end, a second end of which is electrically connected to a control end of the first output module, and a control end of which is connected to the first drive signal; Wherein, under the control of the output control module and the first driving signal, the first output module and the second output module are alternately turned on; One of the first power supply terminal and the second power supply terminal is at a high level, and the other is at a low level. When the first power supply terminal is at a low level, the low level of the first power supply terminal is less than the low level of the first drive signal; when the first power supply terminal is at a high level, the high level of the first power supply terminal is greater than the high level of the first drive signal; Preferably, when the first power supply terminal is at a low level, the high level of the second power supply terminal is equal to the high level of the first drive signal; when the first power supply terminal is at a high level, the low level of the second power supply terminal is equal to the low level of the first drive signal.

4. The level conversion circuit according to claim 3, characterized in that: The first output module comprises a first transistor, a first electrode of the first transistor serves as a first end of the first output module, a second electrode of the first transistor serves as a second end of the first output module, and a gate of the first transistor serves as a control end of the first output module; The second output module comprises a second transistor, the first electrode of the second transistor serves as the first end of the second output module, the second electrode of the second transistor serves as the second end of the second output module, and the gate of the second transistor serves as the control end of the second output module; The output control module comprises a third transistor, the first electrode of the third transistor serves as the first end of the third output module, the second electrode of the third transistor serves as the second end of the third output module, and the gate of the third transistor serves as the control end of the third output module; Preferably, when the first power supply terminal is at a low level, the second transistor is a P-type transistor, and the first transistor and the third transistor are N-type transistors; Preferably, when the first power supply terminal is at a low level, the reference voltage configured at the reference power supply terminal is 0V or less than 0V; Alternatively, when the first power supply terminal is at a high level, the first transistor and the third transistor are P-type transistors, and the second transistor is an N-type transistor; Preferably, when the first power supply terminal is at a high level, the reference voltage configured at the reference power supply terminal is 0V or greater than 0V.

5. The level conversion circuit according to claim 3 or 4, characterized in that: It also includes a coupling module, wherein the coupling module is electrically connected between the driving chip and the control end of the first output module; Preferably, the coupling module comprises a first capacitor, a first electrode of the first capacitor is electrically connected to the driving chip, and a second electrode of the first capacitor is electrically connected to the first output module.

6. A driving method for a level conversion circuit, characterized in that: Applied to the level conversion circuit according to any one of claims 1 to 5, the method comprising: Using a driving chip to invert the original driving signal to obtain a first driving signal and output the first driving signal; The level conversion circuit is controlled to convert the first driving signal into a second driving signal to drive the gate driving circuit.

7. A display panel, characterized in that: include: Gate drive circuit; And, according to any one of claims 1 to 5, the level conversion circuit is used to output a second drive signal, and the second drive signal is used to drive the gate drive circuit. Preferably, the driving chip is used to output N of the first driving signals, the timing of the N first driving signals is different, the display panel includes N of the level conversion circuits, the N level conversion circuits correspond one-to-one to the N first driving signals, and N is an integer greater than or equal to 2.

8. A circuit board, characterized in that: The circuit board is used to drive a display panel, and the display panel includes a gate driving circuit; The circuit board comprises the level conversion circuit according to any one of claims 1 to 5; Preferably, the circuit board comprises a printed circuit board or a flexible circuit board; Preferably, the transistors of the level conversion circuit include N-type metal oxide semiconductor field effect transistors and P-type metal oxide semiconductor field effect transistors.

9. A display device, characterized in that: include: A display panel including a gate drive circuit; A driving chip, used for providing a first driving signal; And, according to any one of claims 1 to 5, the level conversion circuit is used to convert the first drive signal into a second drive signal, and the second drive signal is used to drive the gate drive circuit.

10. The display device according to claim 9, characterized in that: The level conversion circuit is arranged on the display panel; Preferably, when the display device further includes a circuit board, the level conversion circuit is arranged on the circuit board; Preferably, the second power supply terminal is provided by the driving chip, and the second power supply terminal is also electrically connected to the gate driving circuit; Preferably, the first power supply terminal is provided by a power supply or circuit outside the driving chip, and the first power supply terminal is also electrically connected to the gate driving circuit.

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