Gate driving circuit and driving method of display panel and display device

Abstract

The invention provides a gate driving circuit and driving method of a display panel and a display device, and belongs to the technical field of display. In multiple stages of driving units included in the gate driving circuit, a first input control circuit of each stage of driving unit can control the input end of the current stage of driving unit to be conducted with the input ends of other stages of driving units under the control of a synchronous light-emitting control signal, so that a light-emitting signal is transmitted into the multiple stages of driving units at the same time; moreover, the second input control circuit of each stage of driving unit can control the output end of the current stage of driving unit to be conducted with the input ends of the other stages of driving units under the control of the sequential light-emitting control signal, so that the light-emitting signal is transmitted into the multi-stage driving unit stage by stage. Therefore, the gate drive circuit not only can simultaneously output the light-emitting signals to the multiple rows of pixels to drive the multiple rows of pixels to emit light synchronously, but also can sequentially output the light-emitting signals to the multiple rows of pixels to drive the multiple rows of pixels to emit light sequentially. The driving modes of the gate driving circuit are diversified, and the driving effect is good.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a gate driving circuit and driving method of a display panel, and a display device. Background Art

[0002] The gate driving circuit is a circuit used to transmit a gate driving signal such as a light emitting signal to pixels in a display panel to drive the pixels to emit light, and is an indispensable part of the display device.

[0003] In the related art, the gate driving circuit generally includes a plurality of cascaded driving units, which are connected one-to-one with the plurality of rows of pixels in the display panel and are used to output luminous signals to the plurality of rows of pixels row by row to drive the plurality of rows of pixels to emit light row by row, that is, to realize row-by-row scanning.

[0004] However, the current gate driving circuit has a relatively simple driving mode and a relatively poor driving effect. Summary of the invention

[0005] Provided are a gate drive circuit and a drive method for a display panel, and a display device, which can solve the problem that the gate drive circuit in the related art has a relatively single drive mode and a poor drive effect. The technical solution is as follows:

[0006] In one aspect, a gate driving circuit of a display panel is provided, the gate driving circuit comprising: a cascaded multi-stage driving unit, the driving unit comprising: a first input control circuit, a second input control circuit and an output circuit;

[0007] The first input control circuit is respectively connected to the synchronous light-emitting control terminal, the input terminal of the output circuit and the input terminals of other stage driving units of the cascade, and is used to control the on-off of the input terminal of the output circuit and the input terminals of other stage driving units in response to the synchronous light-emitting control signal provided by the synchronous light-emitting control terminal, so that the signal received by the input terminal of the output circuit is transmitted to the input terminal of the other stage driving unit;

[0008] The second input control circuit is connected to the sequential light emitting control terminal, the output terminal of the output circuit and the input terminal of the other stage driving unit respectively, and is used to control the on-off of the output terminal of the output circuit and the input terminal of the other stage driving unit in response to the sequential light emitting control signal provided by the sequential light emitting control terminal, so that the signal output by the output terminal of the output circuit is transmitted to the input terminal of the other stage driving unit, wherein, in the same time period, the potential of the sequential light emitting control signal is opposite to the potential of the synchronous light emitting control signal;

[0009] The input end of the output circuit is used to receive a luminous signal, the clock end of the output circuit is used to receive a clock signal, the output end of the output circuit is used to connect to a pixel in the display panel, and the output circuit is used to sample the luminous signal based on the clock signal and output it to the pixel via the output end.

[0010] Optionally, the output circuit includes: a trigger;

[0011] The output circuit is used for sampling the luminous signal based on the transition edge of the clock signal and outputting the sample to the pixel via the output terminal.

[0012] Optionally, the trigger is a double-edge-triggered D trigger; the second input control circuit is connected to the middle state end of the double-edge-triggered D trigger; the driving unit further includes: a logic circuit;

[0013] The logic circuit is used to be connected between the output end of the double-edge D trigger and the pixel, and the logic circuit is also connected to the intermediate state end of the double-edge D trigger. The logic circuit is used to perform logical operations on the signals output from the output end and the intermediate state end of the double-edge D trigger and then output them to the pixel.

[0014] Optionally, the logic operation processing is an AND processing, and the logic circuit includes: an AND gate;

[0015] The two input terminals of the AND gate are respectively connected to the output terminal and the intermediate state terminal of the double-edge D flip-flop, and the output terminal of the AND gate is used to be connected to the pixel.

[0016] Optionally, the driving unit further includes: a third input control circuit, a first forward scan control circuit and a first reverse scan control circuit;

[0017] The first input control circuit is connected to the input end of the other stage driving unit via the third input control circuit, and the third input control circuit is also connected to the synchronous light emitting control end, and the first input control circuit and the third input control circuit are used to control the on-off of the input end of the output circuit and the input end of the other stage driving unit in response to the synchronous light emitting control signal, so that the signal received by the input end of the output circuit is transmitted to the input end of the other stage driving unit, or the signal received by the input end of the other stage driving unit is transmitted to the input end of the output circuit;

[0018] The first forward scan control circuit and the first reverse scan control circuit are both connected between the first input control circuit and the third input control circuit, and the first forward scan control circuit is also connected to the forward scan control terminal, and the first reverse scan control circuit is also connected to the reverse scan control terminal, the first forward scan control circuit is used to control the on-off of the first input control circuit and the third input control circuit in response to the forward scan control signal provided by the forward scan control terminal, so that the signal received by the input terminal of the output circuit is sequentially transmitted to the input terminal of the other stage driving unit through the first input control circuit and the third input control circuit, and the first reverse scan control circuit is used to control the on-off of the first input control circuit and the third input control circuit in response to the reverse scan control signal provided by the reverse scan control terminal, so that the signal received by the input terminal of the other stage driving unit is sequentially transmitted to the input terminal of the output circuit through the third input control circuit and the first input control circuit;

[0019] Wherein, in the same time period, the potential of the reverse scan control signal is opposite to the potential of the forward scan control signal.

[0020] Optionally, the first input control circuit and the third input control circuit are further connected to the sequential light emitting control terminal, and are used to control the on / off of the input terminal of the output circuit and the input terminals of the other stage driving units in response to the synchronous light emitting control signal and the sequential light emitting control signal;

[0021] The first forward scan control circuit is also connected to the reverse scan control terminal, and is used to control the on / off of the first input control circuit and the third input control circuit in response to the forward scan control signal and the reverse scan control signal;

[0022] The first reverse scan control circuit is also connected to the forward scan control terminal, and is used to control the on / off of the first input control circuit and the third input control circuit in response to the forward scan control signal and the reverse scan control signal.

[0023] Optionally, the first input control circuit includes: a first transmission gate; the third input control circuit includes: a second transmission gate; the first forward scan control circuit includes: a third transmission gate and a fourth transmission gate; the first reverse scan control circuit includes: a fifth transmission gate and a sixth transmission gate;

[0024] The control end of the first transmission gate and the control end of the second transmission gate are respectively connected to the synchronous light-emitting control end and the sequential light-emitting control end, the control end of the third transmission gate to the control end of the sixth transmission gate are respectively connected to the forward scanning control end and the reverse scanning control end, the input end of the first transmission gate is connected to the input end of the output circuit, the output end of the first transmission gate is connected to the input end of the third transmission gate and the output end of the fifth transmission gate, the output end of the third transmission gate is connected to the input end of the fourth transmission gate, the input end of the fifth transmission gate is connected to the output end of the sixth transmission gate, the output end of the fourth transmission gate and the input end of the sixth transmission gate are both connected to the output end of the second transmission gate, and the input end of the second transmission gate is connected to the input end of the other stage driving unit.

[0025] Optionally, the driving unit further includes: a first enhancement circuit and / or a second enhancement circuit;

[0026] The first enhancement circuit is connected between the third transmission gate and the fourth transmission gate, and is used to enhance the signal output by the third transmission gate and then transmit it to the fourth transmission gate;

[0027] The second enhancement circuit is connected between the fifth transmission gate and the sixth transmission gate, and is used for enhancing the signal output by the sixth transmission gate and then transmitting the signal to the fifth transmission gate.

[0028] Optionally, the first enhancement circuit comprises: an even number of first inverters connected in series; the second enhancement circuit comprises: an even number of second inverters connected in series;

[0029] The input ends of the even number of first inverters connected in series are connected to the output end of the third transmission gate, and the output ends of the even number of first inverters connected in series are connected to the input end of the fourth transmission gate;

[0030] The input ends of the even number of second inverters connected in series are connected to the output end of the sixth transmission gate, and the output ends of the even number of second inverters connected in series are connected to the input end of the fifth transmission gate.

[0031] Optionally, the driving unit further includes: a fourth input control circuit, a second forward scan control circuit and a second reverse scan control circuit;

[0032] The fourth input control circuit is connected to the sequential light emitting control terminal, the input terminal of the output circuit and the output terminal of the other stage driving unit respectively, and is used to control the on-off of the output terminal of the other stage driving unit and the input terminal of the output circuit in response to the sequential light emitting control signal, so that the signal output by the output terminal of the other stage driving unit is transmitted to the input terminal of the output circuit;

[0033] The second positive scan control circuit is connected between the output end of the output circuit and the second input control circuit, and is also connected to the positive scan control end, and is used to control the on-off of the output end of the output circuit and the second input control circuit in response to the positive scan control signal provided by the positive scan control end, so that the signal output by the output end of the output circuit is transmitted to the input end of the other stage driving unit through the second input control circuit;

[0034] The second reverse sweep control circuit is connected between the input end of the output circuit and the fourth input control circuit, and is also connected to the reverse sweep control end, and is used to control the on-off between the input end of the output circuit and the fourth input control circuit in response to the reverse sweep control signal provided by the reverse sweep control end, so that the signal output by the output end of the other stage driving unit is transmitted to the input end of the output circuit via the fourth input control circuit;

[0035] Wherein, in the same time period, the potential of the reverse scan control signal is opposite to the potential of the forward scan control signal.

[0036] Optionally, the second input control circuit and the fourth input control circuit are both connected to the sequential light emitting control terminal, the second input control circuit is used to control the on-off of the output terminal of the output circuit and the input terminal of the other stage driving unit in response to the synchronous light emitting control signal and the sequential light emitting control signal, and the fourth input control circuit is used to control the on-off of the output terminal of the other stage driving unit and the input terminal of the output circuit in response to the synchronous light emitting control signal and the sequential light emitting control signal;

[0037] The second forward scan control circuit is also connected to the reverse scan control terminal, and is used to control the on / off connection between the output terminal of the output circuit and the second input control circuit in response to the forward scan control signal and the reverse scan control signal;

[0038] The second reverse scan control circuit is also connected to the forward scan control terminal, and is used to control the on / off of the input terminal of the output circuit and the fourth input control circuit in response to the forward scan control signal and the reverse scan control signal.

[0039] Optionally, the second input control circuit includes: a seventh transmission gate; the fourth input control circuit includes: an eighth transmission gate; the second forward scan control circuit includes: a ninth transmission gate; the second reverse scan control circuit includes: a tenth transmission gate;

[0040] The control end of the seventh transmission gate and the control end of the eighth transmission gate are respectively connected to the synchronous light-emitting control end and the sequential light-emitting control end, the control end of the ninth transmission gate to the control end of the tenth transmission gate are respectively connected to the forward scanning control end and the reverse scanning control end, the input end of the seventh transmission gate is connected to the output end of the ninth transmission gate, the output end of the seventh transmission gate is connected to the input end of the other-stage driving unit, the input end of the ninth transmission gate is connected to the output end of the output circuit, the input end of the eighth transmission gate is connected to the output end of the other-stage driving unit, the output end of the eighth transmission gate is connected to the input end of the tenth transmission gate, and the output end of the tenth transmission gate is connected to the input end of the output circuit.

[0041] Optionally, the driving unit further includes: an inverting circuit;

[0042] The inverting circuit is used to be connected between the output end of the output circuit and the pixel, and is used to invert the signal output from the output end of the output circuit and then transmit it to the pixel.

[0043] Optionally, the inverting circuit comprises: a third inverter;

[0044] The input end of the third inverter is connected to the output end of the output circuit, and the output end of the third inverter is used to be connected to the pixel.

[0045] On the other hand, a method for driving a display panel is provided, which is applied to the gate driving circuit as described in the above aspect; the method comprises:

[0046] In response to the synchronous light-emitting instruction, the first input control circuit controls the input end of the output circuit to be connected with the input end of the other stage driving unit in response to the synchronous light-emitting control signal provided by the synchronous light-emitting control end, so that the signal received by the input end of the output circuit is transmitted to the input end of the other stage driving unit, and the output circuit in each stage driving unit samples the received light-emitting signal based on the received clock signal and synchronously outputs it to the multiple rows of pixels in the display panel through the output end, so as to synchronously light up the multiple rows of pixels;

[0047] In response to a sequential light-emitting instruction, the second input control circuit controls the on-off connection between the output end of the output circuit and the input end of the other-stage driving unit in response to a sequential light-emitting control signal provided by the sequential light-emitting control end, so that the signal output by the output end of the output circuit is transmitted to the input end of the other-stage driving unit, and the output circuit in each stage of the driving unit samples the received light-emitting signal based on the received clock signal and outputs it sequentially to the multiple rows of pixels in the display panel through the output end, so as to light up the multiple rows of pixels in sequence.

[0048] In another aspect, a display device is provided, the display device comprising: a display panel, and the gate driving circuit as described in the above aspect;

[0049] The display panel includes a plurality of rows of pixels. The gate driving circuit is connected to the plurality of rows of pixels and is used to drive the plurality of rows of pixels to emit light.

[0050] In summary, the beneficial effects brought about by the technical solution provided by this application may at least include:

[0051] A gate drive circuit and a drive method for a display panel and a display device are provided. In the multi-stage drive unit included in the gate drive circuit, the first input control circuit of each stage drive unit can control the input end of the current stage drive unit to be connected with the input end of other stage drive units under the control of a synchronous light-emitting control signal, so that the light-emitting signal is transmitted to the multi-stage drive unit at the same time; and the second input control circuit of each stage drive unit can control the output end of the current stage drive unit to be connected with the input end of other stage drive units under the control of a sequential light-emitting control signal, so that the light-emitting signal is transmitted to the multi-stage drive unit step by step. Therefore, the gate drive circuit can not only output light-emitting signals to multiple rows of pixels at the same time to drive multiple rows of pixels to emit light synchronously, but also output light-emitting signals to multiple rows of pixels in sequence to drive multiple rows of pixels to emit light in sequence. The gate drive circuit has diversified driving modes and good driving effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0053] Figure 1 is a schematic structural diagram of a gate drive circuit provided in an embodiment of the present application;

[0054] Figure 2 is a schematic structural diagram of a driving unit provided in an embodiment of the present application;

[0055] Figure 3 is a schematic diagram of the structure of another driving unit provided in an embodiment of the present application;

[0056] Figure 4 is a structural schematic diagram of another driving unit provided in an embodiment of the present application;

[0057] Figure 5 is a partial structural schematic diagram of a driving unit provided in an embodiment of the present application;

[0058] Figure 6 is a partial structural schematic diagram of another driving unit provided in an embodiment of the present application;

[0059] Figure 7 is a partial structural schematic diagram of another driving unit provided in an embodiment of the present application;

[0060] Figure 8 is a partial structural diagram of another driving unit provided in an embodiment of the present application;

[0061] Fig. 9 is a partial structural diagram of another driving unit provided in an embodiment of the present application;

[0062] Fig.10 is a partial structural diagram of another driving unit provided in an embodiment of the present application;

[0063] Fig.11 is a partial structural diagram of another driving unit provided in an embodiment of the present application;

[0064] Fig.12 is a schematic diagram of the overall circuit structure of a driving unit provided in an embodiment of the present application;

[0065] Fig.13 is a schematic diagram of a circuit structure of a plurality of cascaded drive units provided in an embodiment of the present application;

[0066] Fig.14 It is a driving timing diagram of a gate driving circuit provided in an embodiment of the present application;

[0067] Fig.15 is a schematic flow chart of a method for driving a display panel provided in an embodiment of the present application;

[0068] Fig.16 It is a structural schematic diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0069] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0070] It is understandable that the transistors used in the embodiments of the present application can be thin film transistors (TFT) or field effect transistors or other devices with the same characteristics. The field effect transistor example can be a metal oxide semiconductor (MOS) field effect transistor, also known as a MOS tube. According to the role in the circuit, the transistors used in the embodiments of the present application are mainly switching transistors. Since the source and drain of the switching transistor used here are symmetrical, the source and drain are interchangeable. In the embodiments of the present application, the source is called the first pole and the drain is called the second pole. According to the form in the accompanying drawings, the middle end of the transistor is defined as the control pole, which can also be called the gate, the signal input end is the source, and the signal output end is the drain. In addition, the switching transistor used in the embodiments of the present application can include any one of a P-type switching transistor and an N-type switching transistor, wherein the P-type switching transistor is turned on when the gate is low and turned off when the gate is high, and the N-type switching transistor is turned on when the gate is high and turned off when the gate is low. In addition, multiple signals in each embodiment of the present application correspond to a first potential and a second potential. The first potential and the second potential only represent that the potential of the signal has two state quantities, and do not mean that the first potential or the second potential has a specific value in the full text.

[0071] With the development of display technology, various types of displays have emerged. Among them, the more typical one is the silicon-based organic light emitting diode (OLED) microdisplay. Silicon-based OLED microdisplay is an active organic light emitting diode display device made by combining complementary metal-oxide-semiconductor (CMOS) technology and OLED technology, using single-crystal silicon as the active driving backplane. Silicon-based OLED microdisplays are widely used in augmented reality (AR), virtual reality (VR), mixed reality (MR), electronic viewfinder (EVF), first-person view (FPV), drones, thermal imagers, night vision devices, infrared cameras and / or medical devices due to their many advantages such as high resolution, high PPI, high contrast, high brightness, low power consumption, small size and light weight. Among them, PPI refers to the number of pixels contained in the display per inch (pixels per inch), which reflects the pixel density of the display.

[0072] From a structural point of view, the display driver integrated circuit (DDIC) and silicon backplane (Si-BP) of the silicon-based OLED microdisplay can be integrated on the same IC. Among them, Si-BP generally includes a pixel driver circuit array (active area), a gate driver on array (GOA) circuit and a source driver (source driver) circuit, and the GOA circuit is also called a GOA control circuit. The embodiment of the present application mainly studies the GOA circuit in Si-BP, which is mainly implemented by a digital circuit and is intended to provide a control signal for the row drive of the pixel circuit array. For example, an emission signal (EM_SIGNAL), referred to as an EM signal.

[0073] It is understandable that the EM signal is generally transmitted to the light-emitting control transistor connected between the pull-up power line VDD (or, the light-emitting element OLED) and the driving transistor in the pixel circuit array to control the light-emitting control transistor to turn on or off. When the light-emitting control transistor is turned on, a path can be formed from the pull-up power line VDD to the pull-down power line VSS connected to the light-emitting element OLED, thereby driving the light-emitting element OLED to emit light, so that the silicon-based OLED microdisplay displays a picture.

[0074] In some embodiments, the GOA circuit generally includes a plurality of cascaded driving units (also called shift register GOA units), and the plurality of GOA units are connected one-to-one with the plurality of rows of pixels, and output luminous signals to the plurality of rows of pixels row by row to drive the plurality of rows of pixels to emit light row by row. The light-emitting element in the pixel generally refers to the self-luminous OLED mentioned above. That is, for the OLED, in this embodiment, it will not be like a liquid crystal display (LCD) where all pixels emit light at the same time, that is, the entire LCD is lit up. This will cause the working time of each pixel in the OLED to be different.

[0075] For example, in an example where pixels are capable of displaying the three primary colors of red, green, and blue, some pixels display blue for a relatively long time. As a result, the blue attenuation of this pixel will be greater than that of other pixels. When blue is displayed again in the future, the blue displayed by this pixel will be lighter than that displayed by other pixels. The same problem occurs when displaying red and green. As a result, the display effect is poor.

[0076] Based on this, for OLED display products such as silicon-based OLED microdisplays, the embodiment of the present application proposes a new GOA circuit. The GOA circuit can not only output luminous signals EM to multiple rows of pixels row by row to drive multiple rows of pixels to emit light row by row; it can also output luminous signals EM to multiple rows of pixels at the same time to drive multiple rows of pixels to emit light synchronously, that is, the display panel of the display can display synchronously on the entire surface (Global Emission). In this way, not only can the driving mode of the gate drive circuit be enriched, but also the driving effect of the gate drive circuit can be improved, so that the gate drive circuit can drive the display panel to display reliably and improve the display effect of the display panel. Of course, it is not limited to application in silicon-based OLED microdisplays.

[0077] Figure 1 A gate drive circuit (also called a GOA circuit or a GOA control circuit) of a display panel provided in an embodiment of the present application. Figure 1 As shown, the gate driving circuit includes: a cascaded multi-stage driving unit 00 (also called a GOA unit).

[0078] Optionally, the nth level driving unit 00 may be cascaded with the n+ith level driving unit 00. Wherein, 1≤n≤Mi, M is the total number of levels of the multi-level driving unit 00, M≥1, and i is a positive integer greater than or equal to 1. For example, referring to Figure 1 In the gate driving circuit shown therein, every two adjacent driving units 00 are cascaded, that is, i=1.

[0079] exist Figure 1 Based on this, taking the nth level driving unit 00 in the multi-level driving unit 00 as an example, Figure 2 FIG. 1 shows a schematic diagram of the structure of a driving unit 00. Figure 1 and Figure 2 It can be seen that the driving unit 00 includes: a first input control circuit 01 , a second input control circuit 02 and an output circuit 03 .

[0080] The first input control circuit 01 is respectively connected to the synchronous light emitting control terminal EN_GLOBAL, the input terminal D of the output circuit 03 and the input terminals of other stage driving units 00 in cascade. In addition, the first input control circuit 01 is used to control the connection and disconnection between the input terminal D of the output circuit 03 and the input terminals of other stage driving units 00 in response to the synchronous light emitting control signal provided by the synchronous light emitting control terminal EN_GLOBAL, so that the signal received by the input terminal D of the output circuit 03 is transmitted to the input terminals of other stage driving units 00.

[0081] It is understandable that, combined with Figure 2, the input end of the other stage driving unit 00 recorded in the embodiment of the present application may refer to: the input end D of the output circuit 03 in the other stage driving unit 00. On this basis, for example, when the potential of the synchronous light emitting control signal provided by the synchronous light emitting control end EN_GLOBAL is the first potential, the first input control circuit 01 can control the input end D of the output circuit 03 in the current stage driving unit 00 to be connected with the input end D of the output circuit 03 in the other stage driving unit 00, so that the signal received by the input end D of the output circuit 03 in the current stage driving unit 00 can be transmitted to the input end D of the output circuit 03 in the other stage driving unit 00; and when the potential of the synchronous light emitting control signal provided by the synchronous light emitting control end EN_GLOBAL is the second potential, the first input control circuit 01 can control the input end D of the output circuit 03 in the current stage driving unit 00 to be disconnected from the input end D of the output circuit 03 in the other stage driving unit 00, at which time, the signal received by the input end D of the output circuit 03 in the current stage driving unit 00 cannot be transmitted to the input end D of the output circuit 03 in the other stage driving unit 00.

[0082] That is, for each level of driving unit 00, the first input control circuit 01 in the driving unit 00 of the level can control the input end D of the output circuit 03 in the driving unit 00 of the level to be directly connected with the input end D of the output circuit 03 in other levels of driving units 00 under the control of the synchronous light emitting control signal, so that the signal is directly transmitted to the input end of each level of driving unit 00 without passing through the output circuit 03. In this way, the input end D of the output circuit 03 in each level of driving unit 00 can simultaneously receive the signal input to the input end D of the output circuit 03 in the driving unit 00 of the level. That is, the input end D of the output circuit 03 in each level of driving unit 00 can simultaneously receive the same signal.

[0083] Optionally, the first potential may be an effective potential, the second potential may be an invalid potential, and the first potential may be a high potential relative to the second potential. That is, the first potential may be a high potential, and the second potential may be a low potential. Of course, in some embodiments, the first potential may also be a low potential relative to the second potential. Moreover, for an N-type transistor, the effective potential (i.e., the first potential) may be a high potential, and the invalid potential (i.e., the second potential) may be a low potential. For a P-type transistor, the effective potential (i.e., the first potential) may be a low potential, and the invalid potential (i.e., the second potential) may be a high potential.

[0084] The second input control circuit 02 is respectively connected to the sequential light emitting control terminal EN_GLOBAL', the output terminal Q of the output circuit 03 and the input terminal of the other stage driving unit 00. In addition, the second input control circuit 02 is used to control the on-off of the output terminal Q of the output circuit 03 and the input terminal of the other stage driving unit 00 in response to the sequential light emitting control signal provided by the sequential light emitting control terminal EN_GLOBAL', so that the signal output by the output terminal Q of the output circuit 03 is transmitted to the input terminal of the other stage driving unit 00.

[0085] As described above, the input end of the other stage driving unit 00 may refer to the input end D of the output circuit 03 included in the other stage driving unit 00. On this basis, for example, when the potential of the sequential light emitting control signal provided by the sequential light emitting control end EN_GLOBAL' is the first potential, the second input control circuit 02 can control the output end Q of the output circuit 03 in the current stage driving unit 00 to be connected with the input end D of the output circuit 03 in the other stage driving unit 00, so that the signal output by the output end Q of the output circuit 03 in the current stage driving unit 00 can be transmitted to the input end D of the output circuit 03 in the other stage driving unit 00; and when the potential of the sequential light emitting control signal provided by the sequential light emitting control end EN_GLOBAL' is the second potential, the second input control circuit 02 can control the output end Q of the output circuit 03 in the current stage driving unit 00 to be disconnected from the input end D of the output circuit 03 in the other stage driving unit 00, at which time, the signal output by the output end Q of the output circuit 03 in the current stage driving unit 00 cannot be transmitted to the input end D of the output circuit 03 in the other stage driving unit 00. In the figure, the output terminal Q of the current n-th stage driving unit 00 is marked as Qn.

[0086] That is, for each level of driving unit 00, the second input control circuit 02 in the driving unit 00 of the level can control the output terminal Q of the output circuit 03 in the driving unit 00 of the level to be connected with the input terminal D of the output circuit 03 in other levels of driving unit 00 under the control of the sequential light emission control signal, so that the signal is transmitted to the input terminal of other levels of driving unit 00 after passing through the output circuit 03. In this way, the input terminal D of the output circuit 03 in each level of driving unit 00 can sequentially receive the signal outputted by the output terminal Q of the output circuit 03 in the driving unit 00 of the level. That is, the input terminal D of the output circuit 03 in each level of driving unit 00 can sequentially receive the same signal. For example, in a scenario where two adjacent stages of driving units 00 are cascaded, the input end D of the output circuit 03 in the second stage driving unit 00 can first receive a signal output by the output end Q of the output circuit 03 in the cascaded first stage driving unit 00, and then the input end D of the output circuit 03 in the third stage driving unit 00 can receive a signal output by the output end Q of the output circuit 03 in the cascaded second stage driving unit 00, and so on, to achieve cascade transmission of signals.

[0087] In the same period, the potential of the sequential light emitting control signal is opposite to the potential of the synchronous light emitting control signal. That is, when the potential of the synchronous light emitting control signal is the first potential, the potential of the sequential light emitting control signal may be the second potential; conversely, when the potential of the synchronous light emitting control signal is the second potential, the potential of the sequential light emitting control signal may be the first potential. The first potential may be, for example, a high potential, and the second potential may be, for example, a low potential.

[0088] Thus, in combination with the above example records, it can be known that when the first input control circuit 01 controls the input terminal D of the output circuit 03 to be connected to the input terminals of other stage driving units 00, so that the signal is transmitted to the input terminals of each stage driving units 00 at the same time, the second input control circuit 02 can control the output terminal Q of the output circuit 03 to be disconnected from the input terminals of other stage driving units 00; when the second input control circuit 02 controls the output terminal Q of the output circuit 03 to be connected to the input terminals of other stage driving units 00, so that the signal is sequentially cascaded and transmitted to the input terminals of each stage driving units 00, the first input control circuit 01 can control the input terminal D of the output circuit 03 to be disconnected from the input terminals of other stage driving units 00. That is, in a period of time, the input terminals of each stage driving units 00 can either receive signals simultaneously or sequentially.

[0089] The input terminal D of the output circuit 03 is used to receive the luminous signal EM, the clock terminal CK of the output circuit 03 is used to receive the clock signal CLK, and the output terminal Q of the output circuit 03 is used to connect to the pixel (not shown in the figure) in the display panel. In addition, the output circuit 03 is used to sample the luminous signal EM based on the clock signal CLK and output it to the pixel through the output terminal Q. That is, the output circuit 03 can sample the luminous signal EM received at the input terminal D and output it to the pixel through the output terminal Q under the control of the clock signal CLK.

[0090] Optionally, combined Figure 1 and Figure 2 It can be seen that in each stage of the driving unit 00, the input terminal D of the output circuit 03 can also be connected to the luminous signal line Dn to receive the luminous signal EM provided by the luminous signal line Dn. Here, Dn can refer to the luminous signal line connected to the input terminal D of the output circuit 03 in the n-th stage of the driving unit 00. Correspondingly, Dn+1 can refer to the luminous signal line connected to the input terminal D of the output circuit 03 in the n+1-th stage of the driving unit 00.

[0091] Correspondingly, the cascade connection of the n-th level driving unit 00 and the n+1-th level driving unit 00 may refer to: the output terminal Q of the output circuit 03 in the n-th level driving unit 00 is connected to the input terminal D of the output circuit 03 in the n+1-th level driving unit 00. In the embodiment of the present application, the output terminal Q of the output circuit 03 in the n-th level driving unit 00 may be connected to the input terminal D of the output circuit 03 in the n+1-th level driving unit 00 via the second input control circuit 02. The figure only schematically shows the light-emitting signal line Dn+1 connected to the input terminal D of the output circuit 03 in the n+1-th level driving unit 00. Of course, the input terminal D of the output circuit 03 in the first-level driving unit 00 may be connected to a separate start signal line STV to receive a start signal provided by the start signal line STV, and the start signal is a light-emitting signal EM. Of course, the start signal line STV may be connected to a DDIC to receive the light-emitting signal EM provided by the DDIC.

[0092] Furthermore, the output terminal Q of the output circuit 03 in the multi-stage driving unit 00 can be connected to multiple rows of pixels in the display panel in a one-to-one correspondence. That is, the output terminal Q of the output circuit 03 in each stage of the driving unit 00 can be connected to a row of pixels, and the output terminal Q of the output circuit 03 in each stage of the driving unit 00 can be connected to different rows of pixels. Of course, it is not limited to the one-to-one corresponding connection method. For example, in some other embodiments, the output terminal Q of the output circuit 03 in each stage of the driving unit 00 can be connected to two rows or more than two rows of pixels.

[0093] Thus, in combination with the foregoing description, it can be known that under the control of the synchronous light-emitting control signal, the first input control circuit 01 can simultaneously receive the same light-emitting signal EM that has not been transmitted by the output circuit 03 at the input end D of the output circuit 03 in each level of the driving unit 00. Therefore, the output circuit 03 in each level of the driving unit 00 can simultaneously sample the same light-emitting signal EM based on the received clock signal CLK, and then output it to multiple rows of pixels in the display panel through the output end Q at the same time, so as to drive the multiple rows of pixels to emit light at the same time. For example, the gates of the light-emitting control transistors in the multiple rows of pixels are simultaneously output, so that the light-emitting control transistors in each pixel are synchronously turned on, and then the multiple rows of pixels in the display panel are synchronously emitted for the same duration, so as to achieve the effect of global emission display.

[0094] Under the control of the second input control circuit 02 in response to the sequential light emission control signal, the input terminal D of the output circuit 03 in each level of the driving unit 00 can sequentially receive the light emission signal EM transmitted after passing through the output circuit 03. Therefore, the output circuit 03 in each level of the driving unit 00 can sequentially sample the same light emission signal EM based on the received clock signal CLK, and then sequentially output it to multiple rows of pixels in the display panel through the output terminal Q, so as to drive the multiple rows of pixels to emit light sequentially. For example, the gates of the light emission control transistors in the multiple rows of pixels are output row by row, so that the light emission control transistors in each pixel are sequentially turned on, and then the multiple rows of pixels in the display panel emit light row by row, so as to achieve the effect of sequential emission display (Sequential Emission).

[0095] That is, the gate drive circuit described in the embodiment of the present application is compatible with both global emission and sequential emission modes. Moreover, in the same period, because the potential of the sequential emission control signal is opposite to the potential of the synchronous emission control signal, it can be known that under the control of the first input control circuit 01 and the second input control circuit 02, the two emission modes can be freely switched to one of them according to display requirements, thereby achieving the purpose of adapting to a variety of usage scenarios.

[0096] In summary, the embodiment of the present application provides a gate drive circuit. Since the gate drive circuit includes a multi-stage drive unit, the first input control circuit in each stage of the drive unit can control the input end of the current stage drive unit to be connected with the input end of other stages of the drive unit under the control of the synchronous light-emitting control signal, so that the light-emitting signal is transmitted to the multi-stage drive unit at the same time; and the second input control circuit in each stage of the drive unit can control the output end of the current stage drive unit to be connected with the input end of other stages of the drive unit under the control of the sequential light-emitting control signal, so that the light-emitting signal is transmitted to the multi-stage drive unit step by step. Therefore, the gate drive circuit can not only output light-emitting signals to multiple rows of pixels at the same time to drive multiple rows of pixels to emit light synchronously at the same time, but also output light-emitting signals to multiple rows of pixels in sequence to drive multiple rows of pixels to emit light in sequence. That is, the gate drive circuit is compatible with both Global Emission and Sequential Emission light-emitting modes, and the driving mode of the gate drive circuit is diversified, and the driving effect is better.

[0097] In addition, on the basis of controlling multiple rows of pixels to emit light synchronously at the same time, the problem of poor display uniformity caused by inconsistent light emission time can also be improved. That is, it can ensure that the display effect of the display panel is better.

[0098] Optionally, in some embodiments, the output circuit 03 may include: a trigger. Accordingly, the output circuit 03 may be used to sample the luminous signal EM based on the transition edge of the clock signal CLK and output the sample to the pixel via the output terminal.

[0099] For example, the transition edge of the clock signal CLK may refer to the rising edge of the potential of the clock signal CLK changing from a low potential to a high potential. That is, the output circuit 03 may sample the luminous signal EM and output it to the pixel through the output terminal when the rising edge of the clock signal CLK comes. Accordingly, the trigger included in the output circuit 03 may be a rising edge trigger.

[0100] Of course, in some other embodiments, the trigger may also be a falling edge trigger, that is, the transition edge of the clock signal CLK may also refer to the falling edge where the potential of the clock signal CLK changes from a high potential to a low potential.

[0101] Optionally, refer to Figure 3 It can be seen from the structural schematic diagram of another driving unit 00 that the trigger is, for example, a double-edge D trigger (D Flip Flop, DFF).

[0102] Correspondingly, such as Figure 3 As shown, the second input control circuit 02 can be connected to the intermediate state terminal Q_INTER of the double edge D flip-flop DFF. In addition, the driving unit 00 can also include: a logic circuit 04.

[0103] The logic circuit 04 can be used to connect between the output terminal Q of the double edge D flip-flop DFF and the pixel, and the logic circuit 04 can also be connected to the intermediate state terminal Q_INTER of the double edge D flip-flop DFF. The logic circuit 04 can be used to perform logic operation processing on the signals output from the output terminal Q and the intermediate state terminal Q_INTER of the double edge D flip-flop DFF and then output them to the pixel.

[0104] It can be understood that a double-edge D flip-flop DFF is a D flip-flop that can sample the input signal on both the rising and falling edges of the clock signal. The use of a double-edge D flip-flop DFF can improve data processing efficiency. In a double-edge D flip-flop DFF, the intermediate state terminal Q_INTER serves as an intermediate state output terminal, which can temporarily store the input signal until the next clock signal jump edge updates the output, thereby ensuring that the output can still be stable when the potential of the clock signal changes. For example, when the rising edge of the clock signal comes, the input signal can be sampled and stored in the intermediate state terminal Q_INTER. When the falling edge of the clock signal comes, the input signal is output through the intermediate state terminal Q_INTER. In this way, two data sampling and output updates can be completed within one clock cycle. In addition, refer to Figure 3 , wherein Q' of the double edge D flip-flop DFF refers to an inverting output terminal, and the potential of the signal outputted through Q' is exactly opposite to the potential of the signal outputted through the output terminal Q. In addition, the double edge D flip-flop DFF also has a reset terminal Rn, which is used to receive a reset signal RST, so as to flexibly perform initialization under the control of the reset signal RST.

[0105] Optionally, on the basis of setting the output circuit 03 as a double-edge D flip-flop DFF, the second input control circuit 02 can be connected to the intermediate state terminal Q_INTER of the double-edge D flip-flop DFF, and is used to control the on and off of the intermediate state terminal Q_INTER and the input terminals of other stage driving units 00 under the control of a sequential light-emitting control signal.

[0106] Optionally, in some embodiments, the logic operation process may be an AND process. AND process means that the logic circuit 04 outputs a high potential signal only when the potentials of all received signals are high potentials, otherwise it outputs a low potential. Figure 4 It can be seen from the structural diagram of another driving unit 00 that the logic circuit 04 may include: an AND gate AND.

[0107] Two input terminals A&B of the AND gate AND can be connected to the output terminal Q and the intermediate state terminal Q_INTER of the double-edge D flip-flop respectively, and the output terminal OUT of the AND gate AND can be used to connect to a pixel.

[0108] Of course, it is not limited to the AND processing, and accordingly, the logic circuit 04 is not limited to the design of the AND gate. For example, in some embodiments, the logic circuit 04 may include a plurality of gate circuits combined.

[0109] Optionally, Figure 5 FIG. 1 is a schematic diagram of a partial structure of a drive unit 00 provided in an embodiment of the present application. Figure 5 As shown, the driving unit 00 may further include: a third input control circuit 05 , a first forward scan control circuit 06 and a first reverse scan control circuit 07 .

[0110] The first input control circuit 01 can be connected to the input terminal of the other stage driving unit 00 via the third input control circuit 05, and the third input control circuit 05 can also be connected to the synchronous light emitting control terminal EN_GLOBAL. The first input control circuit 01 and the third input control circuit 05 can be used to control the on / off of the input terminal D of the output circuit 03 and the input terminal of the other stage driving unit 00 in response to the synchronous light emitting control signal, so that the signal received by the input terminal D of the output circuit 03 is transmitted to the input terminal of the other stage driving unit 00, or the signal received by the input terminal of the other stage driving unit 00 is transmitted to the input terminal D of the output circuit 03.

[0111] For example, the first input control circuit 01 and the third input control circuit 05 can control the input terminal D of the output circuit 03 in the current stage driving unit 00 to be connected with the input terminal D of the output circuit 03 in other stage driving units 00 when the potential of the synchronous light emitting control signal is the first potential, so that the signal received by the input terminal D of the output circuit 03 in the current stage driving unit 00 is forwardly transmitted to the input terminal D of the output circuit 03 in other stage driving units 00, or the signal received by the input terminal D of the output circuit 03 in other stage driving units 00 is reversely transmitted to the input terminal D of the output circuit 03 in the current stage driving unit 00. The first input control circuit 01 and the third input control circuit 05 can control the input terminal D of the output circuit 03 in the current stage driving unit 00 to be disconnected from the input terminal D of the output circuit 03 in other stage driving units 00 when the potential of the synchronous light emitting control signal is the second potential. At this time, the signal received by the input terminal D of the output circuit 03 in the current stage driving unit 00 cannot be transmitted to the input terminal D of the output circuit 03 in other stage driving units 00, and the signal received by the input terminal D of the output circuit 03 in other stage driving units 00 cannot be transmitted to the input terminal D of the output circuit 03 in the current stage driving unit 00. The signals here may all refer to the luminous signal EM.

[0112] That is, the first input control circuit 01 and the third input control circuit 05 can jointly respond to the synchronous light-emitting control signal to control the forward transmission and reverse transmission of the signal (such as the light-emitting signal EM) received by the input terminal D of the output circuit 03 in the cascaded driving units 00 at each level, so as to realize Global Emission while being compatible with the forward and reverse scanning functions. The forward and reverse scanning functions include the forward scanning function and the reverse scanning function. The forward scanning function may refer to transmitting the signal in the direction from the first row of pixels to the last row of pixels to scan multiple rows of pixels, and the reverse scanning function may refer to transmitting the signal in the direction from the last row of pixels to the first row of pixels to scan multiple rows of pixels.

[0113] The first forward scan control circuit 06 and the first reverse scan control circuit 07 can be connected between the first input control circuit 01 and the third input control circuit 05, and the first forward scan control circuit 06 can also be connected to the forward scan control terminal GSD_FW, and the first reverse scan control circuit 07 can also be connected to the reverse scan control terminal GSD_BW. The first forward scan control circuit 06 can be used to respond to the forward scan control signal provided by the forward scan control terminal GSD_FW, and control the on-off of the first input control circuit 01 and the third input control circuit 05, so that the signal received by the input terminal D of the output circuit 03 is transmitted to the input terminal of the other stage driving unit 00 through the first input control circuit 01 and the third input control circuit 05 in sequence. The first reverse scan control circuit 07 can be used to respond to the reverse scan control signal provided by the reverse scan control terminal GSD_BW, and control the on-off of the first input control circuit 01 and the third input control circuit 05, so that the signal received by the input terminal of the other stage driving unit 00 is transmitted to the input terminal D of the output circuit 03 through the third input control circuit 05 and the first input control circuit 01 in sequence.

[0114] For example, the first positive scan control circuit 06 can control the first input control circuit 01 and the third input control circuit 05 to be turned on when the potential of the positive scan control signal provided by the positive scan control terminal GSD_FW is the first potential, so that the signal received by the input terminal D of the output circuit 03 in the current stage driving unit 00 is transmitted to the input terminal D of the output circuit 03 in other stages of driving unit 00 via the first input control circuit 01 and the third input control circuit 05 in sequence; and can control the first input control circuit 01 and the third input control circuit 05 to be disconnected when the potential of the positive scan control signal provided by the positive scan control terminal GSD_FW is the second potential. At this time, the signal received by the input terminal D of the output circuit 03 in the current stage driving unit 00 cannot be transmitted to the input terminal D of the output circuit 03 in other stages of driving unit 00 via the first input control circuit 01 and the third input control circuit 05 in sequence.

[0115] Similarly, the first backscan control circuit 07 can control the first input control circuit 01 and the third input control circuit 05 to be turned on when the potential of the backscan control signal provided by the backscan control terminal GSD_BW is the first potential, so that the signal received by the input terminal D of the output circuit 03 in the other stage driving unit 00 is transmitted to the input terminal D of the output circuit 03 in the current stage driving unit 00 via the third input control circuit 05 and the first input control circuit 01 in sequence; and, when the potential of the backscan control signal provided by the backscan control terminal GSD_BW is the second potential, the first input control circuit 01 can be controlled to be disconnected from the third input control circuit 05. At this time, the signal received by the input terminal D of the output circuit 03 in the other stage driving unit 00 cannot be transmitted to the input terminal D of the output circuit 03 in the current stage driving unit 00 via the third input control circuit 05 and the first input control circuit 01 in sequence.

[0116] That is, under the control of the first forward scanning control circuit 06 and the first reverse scanning control circuit 07, in cooperation with the first input control circuit 01 and the third input control circuit 05, forward scanning and reverse scanning can be realized, and the signal transmission paths under forward scanning and reverse scanning are independent of each other. Among them, the signal transmission path under forward scanning is: input through the input end D of the output circuit 03 in the current stage driving unit 00, and then sequentially transmitted through the first input control circuit 01, the first forward scanning control circuit 06 and the third input control circuit 05 to the input end D of the output circuit 03 in other stage driving units 00. The signal transmission path under reverse scanning is: input through the input end D of the output circuit 03 in other stage driving units 00, and then sequentially transmitted through the third input control circuit 05, the first reverse scanning control circuit 07 and the first input control circuit 01 to the input end D of the output circuit 03 in the current stage driving unit 00. Such a design can relatively avoid the crosstalk of the signal transmitted during forward scanning and reverse scanning from the perspective of signal transmission, thereby improving the transmission efficiency of the signal when the circuit is working.

[0117] Among them, in the same time period, the potential of the reverse scan control signal is opposite to the potential of the forward scan control signal. That is, when the potential of the forward scan control signal is the first potential, the potential of the reverse scan control signal can be the second potential; conversely, when the potential of the forward scan control signal is the second potential, the potential of the reverse scan control signal can be the first potential. In this way, combined with the above example records, it can be known that when the first forward scan control circuit 06 controls the first input control circuit 01 and the third input control circuit 05 to be turned on, and the forward scan is realized, the first reverse scan control circuit 07 can be to control the first input control circuit 01 and the third input control circuit 05 to be disconnected; when the first reverse scan control circuit 07 controls the first input control circuit 01 and the third input control circuit 05 to be turned on, and the reverse scan is realized, the first forward scan control circuit 06 can be to control the first input control circuit 01 and the third input control circuit 05 to be disconnected. That is, it can be made possible to perform either forward scan or reverse scan in a time period and while realizing Global Emission.

[0118] Optionally, continue to refer to Figure 5 It can be seen that the first input control circuit 01 and the third input control circuit 05 can also be connected to the sequential light emitting control terminal EN_GLOBAL'. In addition, the first input control circuit 01 and the third input control circuit 05 can be used to control the on / off of the input terminal D of the output circuit 03 and the input terminals of other stage driving units 00 in response to the synchronous light emitting control signal and the sequential light emitting control signal.

[0119] For example, the first input control circuit 01 and the third input control circuit 05 can control the input terminal D of the output circuit 03 in the current stage driving unit 00 to be connected to the input terminal D of the output circuit 03 in other stages driving unit 00 when the potential of the synchronous light-emitting control signal and / or the potential of the sequential light-emitting control signal is a first potential; and can control the input terminal D of the output circuit 03 in the current stage driving unit 00 to be disconnected from the input terminal D of the output circuit 03 in other stages driving unit 00 when the potential of the synchronous light-emitting control signal and the potential of the sequential light-emitting control signal are both a second potential.

[0120] That is, the first input control circuit 01 and the third input control circuit 05 can control the on / off of the input terminal D of the output circuit 03 in the current stage driving unit 00 and the input terminal D of the output circuit 03 in other stage driving units 00 under the control of the two control signals, the synchronous light emitting control signal and the sequential light emitting control signal. In this way, the control reliability and flexibility can be improved.

[0121] Optionally, in some embodiments, the potential of the synchronous light-emitting control signal and the potential of the sequential light-emitting control signal may be exactly opposite potentials. That is, assuming that the first potential (i.e., the effective potential) of the synchronous light-emitting control signal is a high potential, the first potential (i.e., the effective potential) of the sequential light-emitting control signal may be a low potential. Assuming that the first potential (i.e., the effective potential) of the synchronous light-emitting control signal is a low potential, the first potential (i.e., the effective potential) of the sequential light-emitting control signal may be a high potential. On this basis, in some embodiments, only the synchronous light-emitting control terminal EN_GLOBAL may be set, and then an inverter may be set to invert the synchronous light-emitting control signal provided by the synchronous light-emitting control terminal EN_GLOBAL to obtain the desired sequential light-emitting control signal, without the need to additionally set the sequential light-emitting control terminal EN_GLOBAL'. Alternatively, only the sequential light-emitting control terminal EN_GLOBAL' may be set, and then an inverter may be set to invert the sequential light-emitting control signal provided by the sequential light-emitting control terminal EN_GLOBAL' to obtain the desired synchronous light-emitting control signal, without the need to additionally set the synchronous light-emitting control terminal EN_GLOBAL. In this way, the number of signal terminals required to be set can be simplified, thereby facilitating wiring.

[0122] Optionally, continue to refer to Figure 5 It can be seen that the first forward scan control circuit 06 can also be connected to the reverse scan control terminal GSD_BW. In addition, the first forward scan control circuit 06 can be used to control the on and off of the first input control circuit 01 and the third input control circuit 05 in response to the forward scan control signal and the reverse scan control signal.

[0123] For example, the first forward scan control circuit 06 can control the first input control circuit 01 and the third input control circuit 05 to be turned on when the potential of the forward scan control signal and / or the potential of the reverse scan control signal is the first potential; and can control the first input control circuit 01 and the third input control circuit 05 to be disconnected when the potential of the forward scan control signal and the potential of the reverse scan control signal are both the second potential. That is, like the first input control circuit 01 and the third input control circuit 05, the first forward scan control circuit 06 can control the on and off of the first input control circuit 01 and the third input control circuit 05 under the control of the two control signals, the forward scan control signal and the reverse scan control signal. In this way, the control reliability and flexibility can be improved.

[0124] Optionally, continue to refer to Figure 5 It can be seen that the first reverse scan control circuit 07 can also be connected to the forward scan control terminal GSD_FW. In addition, the first reverse scan control circuit 07 can be used to control the on and off of the first input control circuit 01 and the third input control circuit 05 in response to the forward scan control signal and the reverse scan control signal.

[0125] For example, the first reverse scan control circuit 07 can control the first input control circuit 01 and the third input control circuit 05 to be turned on when the potential of the forward scan control signal and / or the potential of the reverse scan control signal is the first potential; and can control the first input control circuit 01 and the third input control circuit 05 to be disconnected when the potential of the forward scan control signal and the potential of the reverse scan control signal are both the second potential. That is, like the first forward scan control circuit 06, the first reverse scan control circuit 07 can also control the on and off of the first input control circuit 01 and the third input control circuit 05 under the control of the two control signals, the forward scan control signal and the reverse scan control signal. In this way, the control reliability and flexibility can be improved.

[0126] Optionally, in some embodiments, the potential of the forward scanning control signal and the potential of the reverse scanning control signal may also be just opposite potentials. That is, assuming that the first potential (i.e., effective potential) of the forward scanning control signal is a high potential, the first potential (i.e., effective potential) of the reverse scanning control signal may be a low potential. Assuming that the first potential (i.e., effective potential) of the forward scanning control signal is a low potential, the first potential (i.e., effective potential) of the reverse scanning control signal may be a high potential. On this basis, in some embodiments, only the forward scanning control terminal GSD_FW may be set, and then an inverter may be set to invert the forward scanning control signal provided by the forward scanning control terminal GSD_FW to obtain the desired reverse scanning control signal, without the need to additionally set the reverse scanning control terminal GSD_BW. Alternatively, only the reverse scanning control terminal GSD_BW may be set, and then an inverter may be set to invert the reverse scanning control signal provided by the reverse scanning control terminal GSD_BW to obtain the desired forward scanning control signal, without the need to additionally set the forward scanning control terminal GSD_FW. In this way, the number of signal terminals required to be set can be simplified, thereby facilitating wiring.

[0127] It can be understood that the potentials of the forward scanning control signals received by the first forward scanning control circuit 06 and the first reverse scanning control circuit 07 can be exactly opposite, and the potentials of the received reverse scanning control signals can also be exactly opposite. That is, assuming that the first potential of the forward scanning control signal received by the first forward scanning control circuit 06 is a high potential, and the first potential of the received reverse scanning control signal is a low potential, then the first potential of the forward scanning control signal received by the first reverse scanning control circuit 07 can be a low potential, and the first potential of the received reverse scanning control signal can be a high potential. Assuming that the second potential of the forward scanning control signal received by the first forward scanning control circuit 06 is a low potential, and the second potential of the received reverse scanning control signal is a high potential, then the second potential of the forward scanning control signal received by the first reverse scanning control circuit 07 can be a high potential, and the second potential of the received reverse scanning control signal can be a low potential. In this way, only one of the first forward scanning control circuit 06 and the first reverse scanning control circuit 07 can control the first input control circuit 01 and the third input control circuit 05 to conduct in a period of time to achieve forward scanning or reverse scanning.

[0128] For example, 1 represents a high potential, 0 represents a low potential, and the first potential of the forward scan control signal received by the first forward scan control circuit 06 is a high potential 1, and the first potential of the reverse scan control signal received is a low potential 0; the first potential of the forward scan control signal received by the first reverse scan control circuit 07 is a low potential 0, and the first potential of the reverse scan control signal received is a high potential 1. The following Table 1 schematically shows the truth table of the forward scan control signal provided by the forward scan control terminal GSD_FW and the reverse scan control signal provided by the reverse scan control terminal GSD_BW when implementing forward scan and reverse scan:

[0129] Table 1

[0130] Signal Name Value Case1 Value Case2 GSD_FW 1 0 GSD_BW 0 1 Scan State Forward Scan Backward Scan

[0131] Combining Table 1 and the above records, it can be known that when the potential of the forward scan control signal provided by the forward scan control terminal GSD_FW is a high potential 1, and the potential of the reverse scan control signal provided by the reverse scan control terminal GSD_BW is a low potential 0, the first forward scan control circuit 06 can control the first input control circuit 01 and the third input control circuit 05 to be turned on, so that the signal received by the input terminal D of the output circuit 03 in the current stage driving unit 00 is transmitted forward to the input terminal D of the output circuit 03 in other stage driving units 00 through the first input control circuit 01, the first forward scan control circuit 06 and the third input control circuit 05 in sequence, so as to realize forward scan. That is, in the first value (Value Case 1) mode: GSD_FW=1 and GSD_BW=0, the scanning mode (Scan State) can be forward scan (Forward Scan). At this time, the first reverse scan control circuit 07 can control the first input control circuit 01 and the third input control circuit 05 to disconnect.

[0132] When the potential of the forward scan control signal provided by the forward scan control terminal GSD_FW is a low potential 0, and the potential of the reverse scan control signal provided by the reverse scan control terminal GSD_BW is a high potential 1, the first reverse scan control circuit 07 can control the first input control circuit 01 and the third input control circuit 05 to be turned on, so that the signal received by the input terminal D of the output circuit 03 in the other stage driving unit 00 is reversely transmitted to the input terminal D of the output circuit 03 in the current stage driving unit 00 through the third input control circuit 05, the first reverse scan control circuit 07 and the first input control circuit 01 in sequence, so as to realize reverse scan. That is, in the second value (ValueCase2) mode: GSD_FW=0 and GSD_BW=1, the scanning mode (Scan State) can be reverse scan (BackwardScan). At this time, the first forward scan control circuit 06 can control the first input control circuit 01 and the third input control circuit 05 to be disconnected.

[0133] Optionally, in Figure 5 Based on this, continue to refer to Figure 6 It can be seen that the first input control circuit 01 may include: a first transmission gate TG1. The third input control circuit 05 may include: a second transmission gate TG2. The first forward scan control circuit 06 may include: a third transmission gate TG3 and a fourth transmission gate TG4. The first reverse scan control circuit 07 may include: a fifth transmission gate TG5 and a sixth transmission gate TG6.

[0134] Among them, the control terminal T&T' of the first transmission gate TG1 and the control terminal T&T' of the second transmission gate TG2 can be connected to the synchronous light-emitting control terminal EN_GLOBAL and the sequential light-emitting control terminal EN_GLOBAL' respectively. The control terminal T&T' of the third transmission gate TG3 to the control terminal T&T' of the sixth transmission gate TG6 can be connected to the forward scanning control terminal GSD_FW and the reverse scanning control terminal GSD_BW respectively. The input terminal IN of the first transmission gate TG1 can be connected to the input terminal D (not shown in the figure) of the output circuit 03. The output terminal OUT of the first transmission gate TG1 can be connected to the input terminal IN of the third transmission gate TG3 and the output terminal OUT of the fifth transmission gate TG5, the output terminal OUT of the third transmission gate TG3 can be connected to the input terminal IN of the fourth transmission gate TG4, the input terminal IN of the fifth transmission gate TG5 can be connected to the output terminal OUT of the sixth transmission gate TG6, the output terminal OUT of the fourth transmission gate TG4 and the input terminal IN of the sixth transmission gate TG6 can both be connected to the output terminal OUT of the second transmission gate TG2, and the input terminal IN of the second transmission gate TG2 can be connected to the input terminal (not shown in the figure) of the other stage driving unit 00.

[0135] It can be understood that the transmission gate generally includes an N-type transistor and a P-type transistor connected in parallel. On this basis, the control terminal T of the transmission gate can refer to the gate of the N-type transistor, the control terminal T' of the transmission gate can refer to the gate of the P-type transistor, the input terminal IN of the transmission gate can refer to the first electrode of the N-type transistor and the first electrode of the P-type transistor connected in parallel, and the output terminal OUT of the transmission gate can refer to the second electrode of the N-type transistor and the second electrode of the P-type transistor connected in parallel.

[0136] On this basis, combined with the above embodiment records and Figure 6 It can be known that the control terminal T of the first transmission gate TG1 and the control terminal T of the second transmission gate TG2 can both be connected to the synchronous light-emitting control terminal EN_GLOBAL, and the control terminal T' of the first transmission gate TG1 and the control terminal T' of the second transmission gate TG2 can both be connected to the sequential light-emitting control terminal EN_GLOBAL'. In the third transmission gate TG3 and the fourth transmission gate TG4 included in the first forward scanning control circuit 06, the control terminal T of each transmission gate can be connected to the forward scanning control terminal GSD_FW, and the control terminal T' of each transmission gate can be connected to the reverse scanning control terminal GSD_BW. In the fifth transmission gate TG5 and the sixth transmission gate TG6 included in the first reverse scanning control circuit 07, the control terminal T of each transmission gate can be connected to the reverse scanning control terminal GSD_BW, and the control terminal T' of each transmission gate can be connected to the forward scanning control terminal GSD_FW. In this way, in the same period of time, only one control circuit in the first forward scanning control circuit 06 and the first reverse scanning control circuit 07 can control the first input control circuit 01 and the third input control circuit 05 to be turned on, so as to realize forward scanning or reverse scanning.

[0137] Optionally, continue to refer to Figure 6 It can be seen that the driving unit 00 may further include: a first enhancing circuit 08 and / or a second enhancing circuit 09 .

[0138] The first enhancement circuit 08 can be connected between the third transmission gate TG3 and the fourth transmission gate TG4. In addition, the first enhancement circuit 08 can be used to enhance the signal output by the third transmission gate TG3 and transmit it to the fourth transmission gate TG4. In this way, the attenuation problem of the signal when it is transmitted from the third transmission gate TG3 to the fourth transmission gate TG4 can be solved, and the signal received by the current stage driving unit 00 can be reliably transmitted to other stage driving units 00 through the third transmission gate TG3.

[0139] The second enhancement circuit 09 can be connected between the fifth transmission gate TG5 and the sixth transmission gate TG6. In addition, the second enhancement circuit 09 can be used to enhance the signal output by the sixth transmission gate TG6 and transmit it to the fifth transmission gate TG5. In this way, the attenuation problem of the signal when it is transmitted to the fifth transmission gate TG5 via the sixth transmission gate TG6 can be solved, and the signal received by the other stage driving unit 00 can be reliably transmitted to the current stage driving unit 00 via the sixth transmission gate TG6.

[0140] Optionally, in Figure 6 Based on this, continue to refer to Figure 7 It can be seen that the first enhancement circuit 08 may include: an even number of first inverters F1 connected in series. The second enhancement circuit 09 may include: an even number of second inverters F2 connected in series.

[0141] The input terminal IN of the even number of first inverters F1 connected in series may be connected to the output terminal OUT of the third transmission gate TG3 , and the output terminal OUT of the even number of first inverters F1 connected in series may be connected to the input terminal IN of the fourth transmission gate TG4 .

[0142] The input terminal IN of the even number of second inverters F2 connected in series may be connected to the output terminal OUT of the sixth transmission gate TG6 , and the output terminal OUT of the even number of second inverters F2 connected in series may be connected to the input terminal IN of the fifth transmission gate TG5 .

[0143] Of course, an even number of first inverters F1 connected in series may mean that the input terminal IN of every two adjacent first inverters F1 is connected to the output terminal OUT. Similarly, an even number of second inverters F2 connected in series may mean that the input terminal IN of every two adjacent second inverters F2 is connected to the output terminal OUT.

[0144] Thus, by providing an even number of first inverters F1 connected in series and an even number of second inverters F2 connected in series, the purpose of reliably enhancing the signal can be achieved. Of course, in some other embodiments, the even number of first inverters F1 connected in series can also be replaced by a buffer, which can also achieve the purpose of signal enhancement. The even number of second inverters F2 connected in series can be replaced in the same way.

[0145] Optionally, the number of first inverters F1 included in the first enhancement circuit 08 and the number of second inverters F2 included in the second enhancement circuit 09 can be the same. In this way, it can be ensured that the enhancement effect on the transmitted signal can be consistent during forward scanning and reverse scanning, thereby achieving better display uniformity during forward scanning and reverse scanning. Of course, the number of first inverters F1 included in the first enhancement circuit 08 and the number of second inverters F2 included in the second enhancement circuit 09 can also be different. For example, Figure 7 Two first inverters F1 connected in series and two second inverters F2 connected in series are schematically shown.

[0146] Combined with the previous records, we can know that Figures 5 to 7 The partial structure shown can control the luminous signal EM to be transmitted to the input end D of the output circuit 03 (such as DFF) in the cascaded driving units 00 at the same time, without passing through the DFF in sequence. In this way, the luminous signal EM can enter the output circuit 03 in each driving unit 00 at the same time, so as to be synchronously processed by the output circuit 03 in each driving unit 00 at each level, and finally the luminous signal EM output to the pixel by the cascaded driving units 00 at each level is kept synchronous, so that the display panel can synchronously emit light on the entire surface, that is, the display panel works in the Global Emission mode. Accordingly, Figures 5 to 7 The partial structure shown may also be referred to as a data transmission control module.

[0147] Furthermore, on the basis of controlling the display panel to work in the Global Emission mode, the third input control circuit 05, the first forward scan control circuit 06 and the first reverse scan control circuit 07 (i.e., the structure composed of the transmission gate and the inverter) can also be compatible with the forward and reverse scan functions. Also, in the normal display process, there is only one state of forward scan or reverse scan.

[0148] For example, combined with Figure 7 , in the positive scanning state, the signal transmission path can be Figure 7The path (1) shown. That is, the luminous signal EM can be transmitted from the top, first through a first transmission gate TG1 controlled by EN_GLOBAL=1, then through a third transmission gate TG3 controlled by GSD_FW=1, followed by two first inverters F1 connected in series to enhance the luminous signal EM to avoid attenuation of the luminous signal EM, and finally through a fourth transmission gate TG4 controlled by GSD_FW=1 and then through a second transmission gate TG2 controlled by EN_GLOBAL=1. The setting of the fourth transmission gate TG4 can also be used to prevent the luminous signal EM from flowing back to ensure a single path for signal transmission, that is, to ensure that the luminous signal EM is either transmitted in the forward direction or in the reverse direction. In the reverse scanning state, the signal transmission path can be Figure 7 In the path (2) shown, the number of devices through which the luminous signal EM passes is the same, and the functions of the devices are the same. The difference is that the luminous signal EM is transmitted from below, and GSD_BW=1.

[0149] Among them, EN_GLOBAL=1 may mean that the first potential of the synchronous light-emitting control signal provided by the synchronous light-emitting control terminal EN_GLOBAL is a high potential 1; GSD_FW=1 may mean that the first potential of the forward scan control signal provided by the forward scan control terminal GSD_FW is a high potential 1; GSD_BW=1 may mean that the first potential of the reverse scan control signal provided by the reverse scan control terminal GSD_BW is a high potential 1.

[0150] Optionally, in some embodiments, the third transmission gate TG3, the fourth transmission gate TG4 and the even number of first inverters F1 connected in series on the forward scanning path (1) can be replaced as a tri-state buffer, which can also achieve the purpose of controlling the forward scanning. The fifth transmission gate TG5, the sixth transmission gate TG6 and the even number of second inverters F2 connected in series on the forward scanning path (1) can be replaced in the same way.

[0151] Optionally, Figure 8 FIG. 1 is a schematic diagram of the structure of another part of a driving unit 00 provided in an embodiment of the present application. Figure 8 As shown, the driving unit 00 may further include: a fourth input control circuit 10 , a second forward scan control circuit 11 , and a second reverse scan control circuit 12 .

[0152] The fourth input control circuit 10 can be respectively connected to the sequential light emitting control terminal EN_GLOBAL', the input terminal D of the output circuit 03 and the output terminal of the other stage driving unit 00. In addition, the fourth input control circuit 10 can be used to control the connection and disconnection between the output terminal of the other stage driving unit 00 and the input terminal D of the output circuit 03 in response to the sequential light emitting control signal, so that the signal output by the output terminal of the other stage driving unit 00 is transmitted to the input terminal D of the output circuit 03.

[0153] It is understandable that, combined with Figure 8 The output end of the other stage driver unit 00 recorded in the embodiment of the present application may refer to: the output end Q of the output circuit 03 in the other stage driver unit 00. Of course, on the basis that the output circuit 03 is a double-edge D flip-flop DFF, the output end of the other stage driver unit 00 here may refer to: the intermediate state end Q_INTER of the output circuit 03 in the other stage driver unit 00. Figure 8 It is identified as Q_INTERn+1, indicating that the other stage driving unit 00 is the n+1th stage driving unit 00 .

[0154] On this basis, for example, the fourth input control circuit 10 can control the output terminal Q of the output circuit 03 in the other stage driving unit 00 to be connected with the input terminal D of the output circuit 03 in the current stage driving unit 00 when the potential of the sequential light-emitting control signal is the first potential, so that the signal output by the output terminal Q of the output circuit 03 in the other stage driving unit 00 is transmitted to the input terminal D of the output circuit 03 in the current stage driving unit 00; and can control the output terminal Q of the output circuit 03 in the other stage driving unit 00 to be disconnected from the input terminal D of the output circuit 03 in the current stage driving unit 00 when the potential of the sequential light-emitting control signal is the second potential. At this time, the signal output by the output terminal Q of the output circuit 03 in the other stage driving unit 00 cannot be transmitted to the input terminal D of the output circuit 03 in the current stage driving unit 00.

[0155] That is, the second input control circuit 02 and the fourth input control circuit 10 can respectively respond to the sequential light-emitting control signal provided by the sequential light-emitting control terminal EN_GLOBAL' to control the forward transmission and reverse transmission of the signal (such as the light-emitting signal EM) output from the output terminal Q of the output circuit 03 in each level of the cascaded driving unit 00, so as to realize Sequential Emission while also being compatible with the forward and reverse scanning functions.

[0156] The second positive scan control circuit 11 can be connected between the output terminal Q (e.g., the intermediate state terminal Q_INTER) of the output circuit 03 and the second input control circuit 02, and can also be connected to the positive scan control terminal GSD_FW. The second positive scan control circuit 11 can be used to control the on-off of the output terminal Q of the output circuit 03 and the second input control circuit 02 in response to the positive scan control signal provided by the positive scan control terminal GSD_FW, so that the signal output by the output terminal Q of the output circuit 03 is transmitted to the input terminal of the other stage driving unit 00 through the second input control circuit 02.

[0157] For example, the second positive scan control circuit 11 can control the output terminal Q of the output circuit 03 in the current stage driving unit 00 to be connected with the second input control circuit 02 when the potential of the positive scan control signal provided by the positive scan control terminal GSD_FW is the first potential, so that the signal output by the output terminal Q of the output circuit 03 in the current stage driving unit 00 is transmitted to the input terminal D of the output circuit 03 in other stage driving units 00 via the second input control circuit 02; and can control the output terminal Q of the output circuit 03 in the current stage driving unit 00 to be disconnected from the second input control circuit 02 when the potential of the positive scan control signal provided by the positive scan control terminal GSD_FW is the second potential. At this time, the signal output by the output terminal Q of the output circuit 03 in the current stage driving unit 00 cannot be transmitted to the input terminal D of the output circuit 03 in other stage driving units 00 via the second input control circuit 02.

[0158] The second anti-scan control circuit 12 can be connected between the input terminal D of the output circuit 03 and the fourth input control circuit 10, and can also be connected to the anti-scan control terminal GSD_BW. The second anti-scan control circuit 12 can be used to control the on-off of the input terminal D of the output circuit 03 and the fourth input control circuit 10 in response to the anti-scan control signal provided by the anti-scan control terminal GSD_BW, so that the signal output by the output terminal of the other stage driving unit 00 is transmitted to the input terminal D of the output circuit 03 through the fourth input control circuit 10.

[0159] For example, the second back-scan control circuit 12 can control the input terminal D of the output circuit 03 in the current-stage driver unit 00 to be connected with the fourth input control circuit 10 when the potential of the back-scan control signal provided by the back-scan control terminal GSD_BW is the first potential, so that the signal output by the output terminal Q (such as the intermediate state terminal Q_INTERn+1) of the output circuit 03 in the other-stage driver unit 00 is transmitted to the input terminal D of the output circuit 03 in the current-stage driver unit 00 via the fourth input control circuit 10; and can control the input terminal D of the output circuit 03 in the current-stage driver unit 00 to be disconnected from the fourth input control circuit 10 when the potential of the back-scan control signal provided by the back-scan control terminal GSD_BW is the second potential, at which time, the signal output by the output terminal Q of the output circuit 03 in the other-stage driver unit 00 cannot be transmitted to the input terminal D of the output circuit 03 in the current-stage driver unit 00 via the fourth input control circuit 10.

[0160] That is, under the control of the second forward scanning control circuit 11 and the second reverse scanning control circuit 12, in cooperation with the second input control circuit 02 and the fourth input control circuit 10, forward scanning and reverse scanning can be realized, and the signal transmission paths under forward scanning and reverse scanning are independent of each other. Among them, the signal transmission path under forward scanning is: input through the output terminal Q of the output circuit 03 in the current stage driving unit 00, and then sequentially transmitted through the second forward scanning control circuit 11 and the second input control circuit 02 to the input terminal D of the output circuit 03 in other stage driving units 00. The signal transmission path under reverse scanning is: input through the output terminal Q of the output circuit 03 in other stage driving units 00, and then sequentially transmitted through the fourth input control circuit 10 and the second reverse scanning control circuit 12 to the input terminal D of the output circuit 03 in the current stage driving unit 00. Similarly, from the perspective of signal transmission, such a design can relatively avoid the crosstalk of the signals transmitted during forward scanning and reverse scanning, thereby improving the transmission efficiency of the signal when the circuit is working.

[0161] As described above, in the same time period, the potential of the reverse scan control signal is opposite to the potential of the forward scan control signal. Thus, in combination with the above example records, it can be known that when the second forward scan control circuit 11 controls the output terminal Q of the output circuit 03 in the current stage drive unit 00 to be turned on with the second input control circuit 02, when forward scan is realized, the second reverse scan control circuit 12 can be used to control the input terminal D of the output circuit 03 in the current stage drive unit 00 to be disconnected from the fourth input control circuit 10; when the second reverse scan control circuit 12 controls the input terminal D of the output circuit 03 in the current stage drive unit 00 to be turned on with the fourth input control circuit 10, when reverse scan is realized, the second forward scan control circuit 11 can be used to control the output terminal Q of the output circuit 03 in the current stage drive unit 00 to be disconnected from the second input control circuit 02. That is, it can be made possible to perform either forward scan or reverse scan in one time period and while realizing Sequential Emission.

[0162] Optionally, continue to refer to Figure 8 It can be seen that the second input control circuit 02 and the fourth input control circuit 10 can also be connected to the sequential light emitting control terminal EN_GLOBAL'. In addition, the second input control circuit 02 can be used to control the on-off of the output terminal Q of the output circuit 03 and the input terminal of the other stage driving unit 00 in response to the synchronous light emitting control signal and the sequential light emitting control signal. The fourth input control circuit 10 can be used to control the on-off of the output terminal of the other stage driving unit 00 and the input terminal D of the output circuit 03 in response to the synchronous light emitting control signal and the sequential light emitting control signal.

[0163] For example, the second input control circuit 02 can control the output terminal Q of the output circuit 03 in the current stage driving unit 00 to be connected to the input terminal D of the output circuit 03 in the other stage driving unit 00 when the potential of the synchronous light-emitting control signal and / or the potential of the sequential light-emitting control signal is a first potential; and can control the output terminal Q of the output circuit 03 in the current stage driving unit 00 to be disconnected from the input terminal D of the output circuit 03 in the other stage driving unit 00 when the potential of the synchronous light-emitting control signal and the potential of the sequential light-emitting control signal are both a second potential.

[0164] Similarly, the fourth input control circuit 10 can control the output terminal Q of the output circuit 03 in the other stage driving unit 00 to be connected with the input terminal D of the output circuit 03 in the current stage driving unit 00 when the potential of the synchronous light-emitting control signal and / or the potential of the sequential light-emitting control signal is the first potential; and can control the output terminal Q of the output circuit 03 in the other stage driving unit 00 to be disconnected from the input terminal D of the output circuit 03 in the current stage driving unit 00 when the potential of the synchronous light-emitting control signal and the potential of the sequential light-emitting control signal are both the second potential.

[0165] That is, like the first input control circuit 01 and the third input control circuit 05, the second input control circuit 02 and the fourth input control circuit 10 can also control the on and off of the two connected ends under the control of the synchronous light emitting control signal and the sequential light emitting control signal. In this way, the control reliability and flexibility can be improved.

[0166] It can be understood that the potential of the synchronous light-emitting control signal received by each input control circuit in the second input control circuit 02 and the fourth input control circuit 10 can be exactly opposite to the potential of the synchronous light-emitting control signal received by each input control circuit in the first input control circuit 01 and the second input control circuit 02, and the potential of the received sequential light-emitting control signal can also be exactly opposite.

[0167] That is, taking the first input control circuit 01 and the second input control circuit 02 as examples for comparison, assuming that the first potential of the synchronous light-emitting control signal received by the first input control circuit 01 is a high potential, and the first potential of the sequential light-emitting control signal received is a low potential, then the first potential of the synchronous light-emitting control signal received by the second input control circuit 02 may be a low potential, and the first potential of the sequential light-emitting control signal received may be a high potential. Assuming that the second potential of the synchronous light-emitting control signal received by the first input control circuit 01 is a low potential, and the second potential of the sequential light-emitting control signal received is a high potential, then the second potential of the synchronous light-emitting control signal received by the second input control circuit 02 may be a high potential, and the second potential of the sequential light-emitting control signal received may be a low potential. In this way, only one of the first input control circuit 01 and the second input control circuit 02 can control the two ends of the connection to be turned on within a time period, thereby realizing Global Emission or Sequential Emission.

[0168] In other words, in the embodiment of the present application, a synchronous light-emitting control terminal EN_GLOBAL can be set to provide a synchronous light-emitting control signal to switch between the global emission and sequential emission modes. For example, when EN_GLOBAL=1, it is the global emission mode, and when EN_GLOBAL=0, it is the sequential emission mode. Among them, EN_GLOBAL=1 can mean that the potential of the synchronous light-emitting control signal provided by the synchronous light-emitting control terminal EN_GLOBAL is a high potential 1; EN_GLOBAL=0 can mean that the potential of the synchronous light-emitting control signal provided by the synchronous light-emitting control terminal EN_GLOBAL is a low potential 0.

[0169] Optionally, continue to refer to Figure 8 It can be seen that the second forward scan control circuit 11 can also be connected to the reverse scan control terminal GSD_BW. In addition, the second forward scan control circuit 11 can be used to control the connection between the output terminal Q of the output circuit 03 and the second input control circuit 02 in response to the forward scan control signal and the reverse scan control signal.

[0170] For example, the second forward scan control circuit 11 can control the output terminal Q of the output circuit 03 in the current stage drive unit 00 to be connected with the second input control circuit 02 when the potential of the forward scan control signal and / or the potential of the reverse scan control signal is the first potential; and can control the output terminal Q of the output circuit 03 in the current stage drive unit 00 to be disconnected from the second input control circuit 02 when the potential of the forward scan control signal and the potential of the reverse scan control signal are both the second potential. That is, like the first forward scan control circuit 06, the second forward scan control circuit 11 can also control the output terminal Q of the output circuit 03 in the current stage drive unit 00 to be connected with the second input control circuit 02 under the control of the two control signals, the forward scan control signal and the reverse scan control signal. In this way, the control reliability and flexibility can be improved.

[0171] Optionally, continue to refer to Figure 8 It can be seen that the second reverse scan control circuit 12 can also be connected to the forward scan control terminal GSD_FW. In addition, the second reverse scan control circuit 12 can be used to control the connection between the input terminal D of the output circuit 03 and the fourth input control circuit 10 in response to the forward scan control signal and the reverse scan control signal.

[0172] For example, the second reverse scan control circuit 12 can control the input terminal D of the output circuit 03 in the current stage driving unit 00 to be connected with the fourth input control circuit 10 when the potential of the forward scan control signal and / or the potential of the reverse scan control signal is the first potential; and can control the input terminal D of the output circuit 03 in the current stage driving unit 00 to be disconnected from the fourth input control circuit 10 when the potential of the forward scan control signal and the potential of the reverse scan control signal are both the second potential. That is, like the second reverse scan circuit 07, the second reverse scan control circuit 12 can also control the input terminal D of the output circuit 03 in the current stage driving unit 00 to be connected with the fourth input control circuit 10 under the control of the two control signals of the forward scan control signal and the reverse scan control signal. In this way, the control reliability and flexibility can be improved.

[0173] It can be understood that the potentials of the forward scanning control signals received by the second forward scanning control circuit 11 and the second reverse scanning control circuit 12 can be exactly opposite, and the potentials of the received reverse scanning control signals can also be exactly opposite. In addition, the potentials of the forward scanning control signals received by the second forward scanning control circuit 11 and the first forward scanning control circuit 06 can be the same, and the potentials of the received reverse scanning control signals can be the same; the potentials of the forward scanning control signals received by the second reverse scanning control circuit 12 and the first reverse scanning control circuit 07 can be the same, and the potentials of the received reverse scanning control signals can be the same. The potential design can refer to the above-mentioned records for the first forward scanning control circuit 06 and the first reverse scanning control circuit 07, and will not be repeated here one by one. In this way, it can also be made that within a time period, only one of the control circuits in the second forward scanning control circuit 11 and the second reverse scanning control circuit 12 controls the two ends of the connection to be turned on, so as to realize forward scanning or reverse scanning.

[0174] Optionally, in Figure 8 Based on this, continue to refer to Fig. 9 It can be seen that the second input control circuit 02 may include: a seventh transmission gate TG7. The fourth input control circuit 10 may include: an eighth transmission gate TG8. The second forward scan control circuit 11 may include: a ninth transmission gate TG9. The second reverse scan control circuit 12 may include: a tenth transmission gate TG10.

[0175] Among them, the control end T&T' of the seventh transmission gate TG7 and the control end T&T' of the eighth transmission gate TG8 can be connected to the synchronous light-emitting control end EN_GLOBAL and the sequential light-emitting control end EN_GLOBAL' respectively. The control end T&T' of the ninth transmission gate TG9 to the control end T&T' of the tenth transmission gate TG10 can be connected to the forward scanning control end GSD_FW and the reverse scanning control end 'GSD_BW respectively. The input end IN of the seventh transmission gate TG7 can be connected to the output end OUT of the ninth transmission gate TG9, the output end OUT of the seventh transmission gate TG7 can be connected to the input end IN of the other stage driving unit 00, the input end IN of the ninth transmission gate TG9 can be connected to the output end OUT of the output circuit 03, the input end IN of the eighth transmission gate TG8 can be connected to the output end OUT of the other stage driving unit 00, the output end OUT of the eighth transmission gate TG8 can be connected to the input end IN of the tenth transmission gate TG10, and the output end OUT of the tenth transmission gate TG10 can be connected to the input end IN of the output circuit 03.

[0176] Moreover, combined with the above records and Fig. 9It can be seen that the control terminal T of the seventh transmission gate TG7 and the control terminal T of the eighth transmission gate TG8 can both be connected to the sequential light-emitting control terminal EN_GLOBAL', and the control terminal T' of the seventh transmission gate TG7 and the control terminal T' of the eighth transmission gate TG8 can both be connected to the synchronous light-emitting control terminal EN_GLOBAL. The control terminal T of the ninth transmission gate TG9 included in the second forward scan control circuit 11 can be connected to the forward scan control terminal GSD_FW, and the control terminal T' can be connected to the reverse scan control terminal 'GSD_BW. The control terminal T of the tenth transmission gate TG10 included in the second reverse scan control circuit 12 can be connected to the reverse scan control terminal GSD_BW, and the control terminal T' can be connected to the forward scan control terminal 'GSD_FW. In this way, not only can only one of the control circuits in the second forward scan control circuit 11 and the second reverse scan control circuit 12 control both ends of the connection to be turned on in the same period of time, so as to realize forward scan or reverse scan. Moreover, in the forward scanning scenario, only one of the first input control circuit 01 and the second input control circuit 02 can control both ends of the connection to be turned on in the same period, thereby realizing Global Emission or Sequential Emission. Similarly, in the reverse scanning scenario, only one of the first input control circuit 01 and the fourth input control circuit 04 can control both ends of the connection to be turned on in the same period, thereby realizing Global Emission or Sequential Emission.

[0177] Optionally, in Fig. 9 Based on this, continue to refer to Fig.10 It can be seen that the driving unit 00 may further include: an inverting circuit 13 .

[0178] The inverting circuit 13 can be used to connect between the output terminal Q of the output circuit 03 and the pixel (not shown in the figure). In addition, the inverting circuit 13 can be used to invert the signal output by the output terminal Q of the output circuit 03 and transmit it to the pixel. In this way, two signals with opposite potentials can be output to flexibly adapt to the potential requirements of the N-type transistor and the P-type transistor in the pixel, and the application scenarios are more abundant.

[0179] Optionally, in Fig.10 Based on this, continue to refer to Fig.11 It can be seen that the inverting circuit 13 may include: a third inverter F3.

[0180] An input terminal IN of the third inverter F3 may be connected to an output terminal Q of the output circuit 03 , and an output terminal OUT of the third inverter F3 may be used to be connected to a pixel.

[0181] Optionally, refer to Figures 3 to 11It can also be seen that in the embodiment of the present application, the double-edge-triggered D flip-flop DFF, each transmission gate and each inverter may also have a power supply terminal Vdd and a ground terminal GND. The power supply terminal Vdd can be used to receive a power supply signal, and the double-edge-triggered D flip-flop DFF, each transmission gate and each inverter can be used to work reliably under the control of the power supply signal.

[0182] It is understandable that, combined with the previous records, Figures 8 to 11 The partial structure shown can control the luminous signal EM to be transmitted sequentially to the input end D of the output circuit 03 (e.g., DFF) in the cascaded driving units 00 at various levels, and needs to be transmitted sequentially after passing through the DFF. In this way, the luminous signal EM can enter the output circuit 03 in each level of the driving unit 00 in sequence, and be processed by the output circuit 03 in each level of the driving unit 00 step by step, and finally the cascaded driving units 00 at various levels output the luminous signal EM to multiple rows of pixels in sequence (e.g., row by row), so that the multiple rows of pixels emit light in sequence, that is, the display panel works in the Sequential Emission mode. Accordingly, Figures 8 to 11 The partial structure shown can also be called a signal shift register module.

[0183] On the basis of controlling the display panel to work in the Sequential Emission mode, the fourth input control circuit 10, the second forward scanning control circuit 11 and the second reverse scanning control circuit 12 can also be compatible with the forward and reverse scanning functions. In addition, during the normal display process, there is only one state of forward scanning or reverse scanning.

[0184] For example, combined with Fig. 9 , in the positive scanning state, the signal transmission path can be Fig. 9 That is, the luminous signal EM can be transmitted from the top, first through a ninth transmission gate TG9 controlled by GSD_FW=1, and then through a seventh transmission gate TG7 controlled by EN_GLOBAL=0. In the reverse scanning state, the signal transmission path can be Fig. 9 In the path (2) shown, the number of devices through which the luminous signal EM passes is the same, and the functions of the devices are the same. The difference is that the luminous signal EM is transmitted from below, and GSD_BW=1.

[0185] Optionally, from the circuit structure of the module, the module may include a DFF, a transmission gate, an AND gate, and an inverter. The two transmission gates on the top (i.e., the ninth transmission gate TG9 and the tenth transmission gate TG10) can be used as forward and reverse scan control switches in the Sequential Emission mode, while the two transmission gates on the bottom (i.e., the seventh transmission gate TG7 and the eighth transmission gate TG8) can be used as control switches for controlling signal transmission or non-transmission in the Sequential Emission mode and the Global Emission mode. For example, in the Sequential Emission mode, EN_GLOBAL=0, the seventh transmission gate TG7 is equivalent to the on state, and the luminous signal EM can be transmitted through the DFF post-stage; in the Global Emission mode, EN_GLOBAL=1, the seventh transmission gate TG7 is equivalent to the open circuit cut-off state, and the luminous signal EM cannot be transmitted through the DFF post-stage. However, regardless of the mode, the luminous signal EM is output after passing through the AND gate AND.

[0186] Optionally, combined Figure 7 and Fig.11 , Fig.12 The overall circuit structure diagram of a driving unit 00 is schematically shown. Fig.12 As can be seen from the above description, the driving unit 00 in the gate driving circuit provided in the embodiment of the present application can mainly include two modules: a data transmission control module and a signal shift register module. Among them, under the control of the data transmission control module, the multi-level driving unit 00 can simultaneously transmit the same luminous signal EM to multiple rows of pixels in the display panel in the same period, so that the display panel can achieve the effect of synchronous luminous display of the entire surface, that is, the display panel can work in the Global Emission mode. Under the control of the signal shift register module, the multi-level driving unit 00 can sequentially transmit the luminous signal EM to multiple rows of pixels in the display panel row by row, so that multiple rows of pixels are sequentially lit, that is, the display panel can work in the Sequential Emission mode. Moreover, the display panel can be flexibly controlled to work in one of the Global Emission mode and the Sequential Emission mode in the same period. In addition, while supporting the display panel to work in the Global Emission mode and the Sequential Emission mode, the embodiment of the present application also retains the forward and reverse scanning function. The gate driving circuit can adapt to more display product requirements.

[0187] For example, Fig.12Taking the forward scan as an example, two signal transmission paths in the global emission mode and in the sequential emission mode are schematically shown. Fig.12 It can be seen that in the Global Emission mode, the signal can be transmitted via path A. That is, the signal can be input from the input terminal D of the double edge D flip-flop DFF in the current stage driver unit 00, and sequentially transmitted through the first transmission gate TG1, the third transmission gate TG3, the two first inverters F1, the fourth transmission gate TG4 and the second transmission gate TG2 to the input terminal D of the double edge D flip-flop DFF in other stage driver units 00. In the Sequential Emission mode, the signal can be transmitted via path B. That is, the signal can be input from the output terminal Q of the double edge D flip-flop DFF in the current stage driver unit 00, and sequentially transmitted through the ninth transmission gate TG9 and the seventh transmission gate TG7 to the input terminal D of the double edge D flip-flop DFF in other stage driver units 00.

[0188] As mentioned above, when the display panel is controlled to work in the Global Emission mode, the luminous time, luminous starting point and even luminous end point of multiple rows of pixels or even all rows of pixels in the display panel can be made consistent, that is, it can support the simultaneous luminous display of the entire surface of pixels. Therefore, the problem of poor display effect caused by inconsistent luminous time can be alleviated to a certain extent.

[0189] Optionally, Fig.12 Taking the structure shown as an example, two adjacent driving units 00(1) and 00(2) are cascaded, and each driving unit 00 is connected to a row of pixels. Fig.13 A schematic diagram of a cascade circuit structure is shown schematically. Fig.13 It can be seen that in the Global Emission mode, the luminous signal EM can be simultaneously transmitted to the input terminal D of the DFF in the two-stage driving unit 00 through the left data transmission control module, so that the DFF in the two-stage driving unit 00 can simultaneously output the luminous signal EM received at each input terminal D through each output terminal Q when the rising edge of the clock signal comes, and output it to the connected row of pixels at the same time after being processed by the AND gate AND logic included in each. In this way, the two rows of pixels connected to the two-stage driving unit 00 can emit light and display at the same time. Among them, Fig.13 The Line1 Output shown refers to the light emitting signal EM output by the first-stage driving unit 00 (1) to the connected first-row pixels; the Line2 Output refers to the light emitting signal EM output by the second-stage driving unit 00 (2) to the connected second-row pixels.

[0190] That is, combined with Fig.14It can be seen from the timing diagram shown that in the Global Emission mode, the luminous signal EM with the same potential can be output to multiple rows of pixels at the same time, so that the multiple rows of pixels can start emitting light and stop emitting light at the same time. Fig.14 The light emission signal EM output to 10 rows (Line 1 to Line 10) of pixels is schematically shown.

[0191] It is understandable that the gate driving circuit described in the embodiments of the present application is not limited to outputting the light emitting signal EM. For example, in some other embodiments, it can also be used to output the gate driving signal GATE.

[0192] In summary, the embodiment of the present application provides a gate drive circuit. Since the gate drive circuit includes a multi-stage drive unit, the first input control circuit in each stage of the drive unit can control the input end of the current stage drive unit to be connected with the input end of other stages of the drive unit under the control of the synchronous light-emitting control signal, so that the light-emitting signal is transmitted to the multi-stage drive unit at the same time; and the second input control circuit in each stage of the drive unit can control the output end of the current stage drive unit to be connected with the input end of other stages of the drive unit under the control of the sequential light-emitting control signal, so that the light-emitting signal is transmitted to the multi-stage drive unit step by step. Therefore, the gate drive circuit can not only output light-emitting signals to multiple rows of pixels at the same time to drive multiple rows of pixels to emit light synchronously at the same time, but also output light-emitting signals to multiple rows of pixels in sequence to drive multiple rows of pixels to emit light in sequence. That is, the gate drive circuit is compatible with both Global Emission and Sequential Emission light-emitting modes, and the driving mode of the gate drive circuit is diversified, and the driving effect is better.

[0193] In addition, on the basis of controlling multiple rows of pixels to emit light synchronously at the same time, the problem of poor display uniformity caused by inconsistent light emission time can also be improved. That is, it can ensure that the display effect of the display panel is better.

[0194] The present application also provides a method for driving a display panel, which is applied to the gate driving circuit described in the above embodiment. Fig.15 As shown, the method includes:

[0195] Step 1501, in response to a synchronous light-emitting instruction, the first input control circuit responds to a synchronous light-emitting control signal provided by a synchronous light-emitting control terminal, controls the input terminal of the output circuit to be connected with the input terminals of other stages of driving units, so that the signal received by the input terminal of the output circuit is transmitted to the input terminals of other stages of driving units, and the output circuit in each stage of driving units samples the received light-emitting signal based on the received clock signal and synchronously outputs it to multiple rows of pixels in the display panel through the output terminal, so as to synchronously light up the multiple rows of pixels.

[0196] Step 1502, in response to the sequential light-emitting instruction, the second input control circuit controls the on-off connection between the output end of the output circuit and the input end of the other stage driving unit in response to the sequential light-emitting control signal provided by the sequential light-emitting control end, so that the signal output by the output end of the output circuit is transmitted to the input end of the other stage driving unit, and the output circuit in each stage driving unit samples the received light-emitting signal based on the received clock signal and outputs it sequentially to the multiple rows of pixels in the display panel through the output end to light up the multiple rows of pixels in sequence.

[0197] Optionally, the synchronous lighting instruction and the sequential lighting instruction may be generated by DDIC. Moreover, DDIC may provide the synchronous lighting control signal and the sequential lighting control signal described above based on the above instructions to synchronously light up multiple rows of pixels or sequentially light up multiple rows of pixels.

[0198] It can be understood that since the driving method of the display panel can have basically the same implementation method and technical effects as the gate driving circuit of the display panel described in the previous embodiment, for the purpose of brevity, the implementation method and technical effects of the driving method of the display panel will not be repeated here.

[0199] The present application also provides a display device. Fig.16 As shown, the display device includes: a display panel 100, and a gate driving circuit 000 as described in the above embodiment.

[0200] The display panel 100 includes a plurality of rows of pixels. The gate driving circuit 000 is connected to the plurality of rows of pixels and is used to drive the plurality of rows of pixels to emit light. Fig.16 The display panel 100 is only schematically shown.

[0201] Optionally, the display device described in the embodiment of the present application may be any product or component with a display function, such as an organic light-emitting diode (OLED) display device or a silicon-based OLED display device. Furthermore, the display device may be any appropriate display device, including but not limited to any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, and an e-book.

[0202] Since the display device can have substantially the same technical effects as the gate driving circuit described in the previous embodiment, the technical effects of the gate driving circuit will not be repeatedly described here for the purpose of brevity.

[0203] It should be noted that the terms used in the examples of this application are only used to explain the examples and are not intended to limit this application. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of this application should be the common meanings understood by people with ordinary skills in the field to which this application belongs.

[0204] For example, the words "first", "second" or "third" and similar words used in the patent application specification and claims of this application do not indicate any order, quantity or importance, but are only used to distinguish different components.

[0205] Likewise, the words “a” or “an” and the like do not denote a limitation of quantity, but rather denote the presence of at least one.

[0206] Words such as “include” or “comprising” and the like mean that the elements or objects preceding “include” or “comprising” include the elements or objects listed after “include” or “comprising” and their equivalents, and do not exclude other elements or objects.

[0207] "Up", "down", "left" or "right" etc. are only used to indicate relative position relationship. When the absolute position of the described object changes, the relative position relationship may also change accordingly. "Connected" or "coupled" refers to electrical connection.

[0208] "And / or" indicates that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects before and after are in an "or" relationship.

[0209] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A gate driving circuit for a display panel, characterized in that: The gate driving circuit comprises: a cascaded multi-stage driving unit, wherein the driving unit comprises: a first input control circuit, a second input control circuit and an output circuit; The first input control circuit is respectively connected to the synchronous light-emitting control terminal, the input terminal of the output circuit and the input terminals of other stage driving units of the cascade, and is used to control the on-off of the input terminal of the output circuit and the input terminals of other stage driving units in response to the synchronous light-emitting control signal provided by the synchronous light-emitting control terminal, so that the signal received by the input terminal of the output circuit is transmitted to the input terminal of the other stage driving unit; The second input control circuit is connected to the sequential light emitting control terminal, the output terminal of the output circuit and the input terminal of the other stage driving unit respectively, and is used to control the on-off of the output terminal of the output circuit and the input terminal of the other stage driving unit in response to the sequential light emitting control signal provided by the sequential light emitting control terminal, so that the signal output by the output terminal of the output circuit is transmitted to the input terminal of the other stage driving unit, wherein, in the same time period, the potential of the sequential light emitting control signal is opposite to the potential of the synchronous light emitting control signal; The input end of the output circuit is used to receive a luminous signal, the clock end of the output circuit is used to receive a clock signal, the output end of the output circuit is used to connect to a pixel in the display panel, and the output circuit is used to sample the luminous signal based on the clock signal and output it to the pixel via the output end.

2. The gate driving circuit according to claim 1, characterized in that: The output circuit comprises: a trigger; The output circuit is used for sampling the luminous signal based on the transition edge of the clock signal and outputting the sample to the pixel via the output terminal.

3. The gate driving circuit according to claim 2, characterized in that: The trigger is a double edge D trigger; the second input control circuit is connected to the middle state end of the double edge D trigger; the driving unit further includes: a logic circuit; The logic circuit is used to be connected between the output end of the double-edge D trigger and the pixel, and the logic circuit is also connected to the intermediate state end of the double-edge D trigger. The logic circuit is used to perform logical operations on the signals output from the output end and the intermediate state end of the double-edge D trigger and then output them to the pixel.

4. The gate driving circuit according to claim 3, characterized in that: The logic operation process is an AND process, and the logic circuit includes: an AND gate; The two input terminals of the AND gate are respectively connected to the output terminal and the intermediate state terminal of the double-edge D flip-flop, and the output terminal of the AND gate is used to be connected to the pixel.

5. The gate drive circuit according to any one of claims 1 to 4, characterized in that: The driving unit further includes: a third input control circuit, a first forward scan control circuit and a first reverse scan control circuit; The first input control circuit is connected to the input end of the other stage driving unit via the third input control circuit, and the third input control circuit is also connected to the synchronous light emitting control end, and the first input control circuit and the third input control circuit are used to control the on-off of the input end of the output circuit and the input end of the other stage driving unit in response to the synchronous light emitting control signal, so that the signal received by the input end of the output circuit is transmitted to the input end of the other stage driving unit, or the signal received by the input end of the other stage driving unit is transmitted to the input end of the output circuit; The first forward scan control circuit and the first reverse scan control circuit are both connected between the first input control circuit and the third input control circuit, and the first forward scan control circuit is also connected to the forward scan control terminal, and the first reverse scan control circuit is also connected to the reverse scan control terminal, the first forward scan control circuit is used to control the on-off of the first input control circuit and the third input control circuit in response to the forward scan control signal provided by the forward scan control terminal, so that the signal received by the input terminal of the output circuit is sequentially transmitted to the input terminal of the other stage driving unit through the first input control circuit and the third input control circuit, and the first reverse scan control circuit is used to control the on-off of the first input control circuit and the third input control circuit in response to the reverse scan control signal provided by the reverse scan control terminal, so that the signal received by the input terminal of the other stage driving unit is sequentially transmitted to the input terminal of the output circuit through the third input control circuit and the first input control circuit; Wherein, in the same time period, the potential of the reverse scan control signal is opposite to the potential of the forward scan control signal.

6. The gate driving circuit according to claim 5, characterized in that: The first input control circuit and the third input control circuit are also connected to the sequential light emitting control terminal, and are used to control the on / off of the input terminal of the output circuit and the input terminals of the other stage driving units in response to the synchronous light emitting control signal and the sequential light emitting control signal; The first forward scan control circuit is also connected to the reverse scan control terminal, and is used to control the on / off of the first input control circuit and the third input control circuit in response to the forward scan control signal and the reverse scan control signal; The first reverse scan control circuit is also connected to the forward scan control terminal, and is used to control the on / off of the first input control circuit and the third input control circuit in response to the forward scan control signal and the reverse scan control signal.

7. The gate driving circuit according to claim 6, characterized in that: The first input control circuit includes: a first transmission gate; the third input control circuit includes: a second transmission gate; the first forward scan control circuit includes: a third transmission gate and a fourth transmission gate; the first reverse scan control circuit includes: a fifth transmission gate and a sixth transmission gate; The control end of the first transmission gate and the control end of the second transmission gate are respectively connected to the synchronous light-emitting control end and the sequential light-emitting control end, the control end of the third transmission gate to the control end of the sixth transmission gate are respectively connected to the forward scanning control end and the reverse scanning control end, the input end of the first transmission gate is connected to the input end of the output circuit, the output end of the first transmission gate is connected to the input end of the third transmission gate and the output end of the fifth transmission gate, the output end of the third transmission gate is connected to the input end of the fourth transmission gate, the input end of the fifth transmission gate is connected to the output end of the sixth transmission gate, the output end of the fourth transmission gate and the input end of the sixth transmission gate are both connected to the output end of the second transmission gate, and the input end of the second transmission gate is connected to the input end of the other stage driving unit.

8. The gate driving circuit according to claim 7, characterized in that: The driving unit further includes: a first enhancement circuit and / or a second enhancement circuit; The first enhancement circuit is connected between the third transmission gate and the fourth transmission gate, and is used to enhance the signal output by the third transmission gate and then transmit it to the fourth transmission gate; The second enhancement circuit is connected between the fifth transmission gate and the sixth transmission gate, and is used for enhancing the signal output by the sixth transmission gate and then transmitting the signal to the fifth transmission gate.

9. The gate driving circuit according to claim 8, characterized in that: The first enhancement circuit comprises: an even number of first inverters connected in series; the second enhancement circuit comprises: an even number of second inverters connected in series; The input ends of the even number of first inverters connected in series are connected to the output end of the third transmission gate, and the output ends of the even number of first inverters connected in series are connected to the input end of the fourth transmission gate; The input ends of the even number of second inverters connected in series are connected to the output end of the sixth transmission gate, and the output ends of the even number of second inverters connected in series are connected to the input end of the fifth transmission gate.

10. The gate driving circuit according to any one of claims 1 to 4, characterized in that: The driving unit further includes: a fourth input control circuit, a second forward scan control circuit and a second reverse scan control circuit; The fourth input control circuit is connected to the sequential light emitting control terminal, the input terminal of the output circuit and the output terminal of the other stage driving unit respectively, and is used to control the on-off of the output terminal of the other stage driving unit and the input terminal of the output circuit in response to the sequential light emitting control signal, so that the signal output by the output terminal of the other stage driving unit is transmitted to the input terminal of the output circuit; The second positive scan control circuit is connected between the output end of the output circuit and the second input control circuit, and is also connected to the positive scan control end, and is used to control the on-off of the output end of the output circuit and the second input control circuit in response to the positive scan control signal provided by the positive scan control end, so that the signal output by the output end of the output circuit is transmitted to the input end of the other stage driving unit through the second input control circuit; The second reverse sweep control circuit is connected between the input end of the output circuit and the fourth input control circuit, and is also connected to the reverse sweep control end, and is used to control the on-off between the input end of the output circuit and the fourth input control circuit in response to the reverse sweep control signal provided by the reverse sweep control end, so that the signal output by the output end of the other stage driving unit is transmitted to the input end of the output circuit via the fourth input control circuit; Wherein, in the same time period, the potential of the reverse scan control signal is opposite to the potential of the forward scan control signal.

11. The gate driving circuit according to claim 10, characterized in that: The second input control circuit and the fourth input control circuit are also connected to the sequential light emitting control terminal, the second input control circuit is used to control the on-off of the output terminal of the output circuit and the input terminal of the other stage driving unit in response to the synchronous light emitting control signal and the sequential light emitting control signal, and the fourth input control circuit is used to control the on-off of the output terminal of the other stage driving unit and the input terminal of the output circuit in response to the synchronous light emitting control signal and the sequential light emitting control signal; The second forward scan control circuit is also connected to the reverse scan control terminal and is used to control the on / off connection between the output terminal of the output circuit and the second input control circuit in response to the forward scan control signal and the reverse scan control signal; The second reverse scan control circuit is also connected to the forward scan control terminal, and is used to control the on / off of the input terminal of the output circuit and the fourth input control circuit in response to the forward scan control signal and the reverse scan control signal.

12. The gate driving circuit according to claim 11, characterized in that: The second input control circuit includes: a seventh transmission gate; the fourth input control circuit includes: an eighth transmission gate; the second forward scan control circuit includes: a ninth transmission gate; the second reverse scan control circuit includes: a tenth transmission gate; The control end of the seventh transmission gate and the control end of the eighth transmission gate are respectively connected to the synchronous light-emitting control end and the sequential light-emitting control end, the control end of the ninth transmission gate to the control end of the tenth transmission gate are respectively connected to the forward scanning control end and the reverse scanning control end, the input end of the seventh transmission gate is connected to the output end of the ninth transmission gate, the output end of the seventh transmission gate is connected to the input end of the other-stage driving unit, the input end of the ninth transmission gate is connected to the output end of the output circuit, the input end of the eighth transmission gate is connected to the output end of the other-stage driving unit, the output end of the eighth transmission gate is connected to the input end of the tenth transmission gate, and the output end of the tenth transmission gate is connected to the input end of the output circuit.

13. The gate driving circuit according to any one of claims 1 to 4, characterized in that: The driving unit further includes: an inverting circuit; The inverting circuit is used to be connected between the output end of the output circuit and the pixel, and is used to invert the signal output from the output end of the output circuit and then transmit it to the pixel.

14. The gate driving circuit according to claim 13, characterized in that: The inverting circuit comprises: a third inverter; The input end of the third inverter is connected to the output end of the output circuit, and the output end of the third inverter is used to be connected to the pixel.

15. A method for driving a display panel, characterized in that: Applicable to the gate drive circuit according to any one of claims 1 to 14; the method comprises: In response to the synchronous light-emitting instruction, the first input control circuit controls the input end of the output circuit to be connected with the input end of the other stage driving unit in response to the synchronous light-emitting control signal provided by the synchronous light-emitting control end, so that the signal received by the input end of the output circuit is transmitted to the input end of the other stage driving unit, and the output circuit in each stage driving unit samples the received light-emitting signal based on the received clock signal and synchronously outputs it to the multiple rows of pixels in the display panel through the output end, so as to synchronously light up the multiple rows of pixels; In response to a sequential light-emitting instruction, the second input control circuit controls the on-off connection between the output end of the output circuit and the input end of the other-stage driving unit in response to a sequential light-emitting control signal provided by the sequential light-emitting control end, so that the signal output by the output end of the output circuit is transmitted to the input end of the other-stage driving unit, and the output circuit in each stage of the driving unit samples the received light-emitting signal based on the received clock signal and outputs it sequentially to the multiple rows of pixels in the display panel through the output end, so as to light up the multiple rows of pixels in sequence.

16. A display device, characterized in that: The display device comprises: a display panel, and a gate driving circuit as claimed in any one of claims 1 to 14; The display panel includes a plurality of rows of pixels. The gate driving circuit is connected to the plurality of rows of pixels and is used to drive the plurality of rows of pixels to emit light.

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