Read assist circuit and method for memory, memory and electronic equipment

Abstract

The invention provides a read auxiliary circuit for a memory, a control method, the memory and electronic equipment. The read auxiliary circuit comprises a switching device and a negative voltage generation sub-circuit; the first end of the switching device, the first end of the negative voltage generation sub-circuit and the grounding end of the level amplification circuit are coupled to a first node, the second end of the switching device is grounded, and the control end of the switching device and the second end of the negative voltage generation sub-circuit are coupled to a second node to receive a driving signal. When the driving signal is a first electric signal, the switching device is in a conducting state, so that the voltage at the first node is a first voltage value; when the driving signal is a second electric signal, the switching device is in an off state, and the negative voltage generation sub-circuit can generate a second voltage value at the first node; the second voltage value is smaller than the first voltage value. On the premise that read delay is not increased, the amplification efficiency of the sensitive amplifier can be improved, it is guaranteed that data of a memory are successfully read, and the performance of the memory is remarkably improved.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and in particular to a read assist circuit, a control method, a memory and an electronic device for a memory. Background Art

[0002] In order to ensure that the memory can read data correctly, a sense amplifier is usually used in the memory read circuit design to amplify the weak voltage difference on BL / BLX (bit line / reference bit line) caused by the memory cell read current to obtain a logic 0 or 1 output. The read margin is the voltage difference on BL / BLX (i.e., the voltage difference between the bit line (BL) and the reference bit line (BLX)) when the sense amplifier is enabled. It is an important parameter in memory design. The larger the read margin, the higher the probability of successful amplification by the sense amplifier, and vice versa. The read margin is seriously affected by factors such as process deviation, temperature, and voltage. In order to reduce the adverse effects of process deviation on the read limit, the MOS tube used in the amplifier circuit of the sense amplifier cannot usually be of the minimum size, which restricts the amplification performance of the sense amplifier itself to a certain extent.

[0003] Moreover, under high temperature and / or low voltage conditions, the read current of the memory storage unit and the performance of the sense amplifier itself will be significantly affected, thereby affecting the read limit of the memory. In order to ensure the read function of the memory under different PVT (Process Voltage Temperature, process, voltage and temperature) conditions, taking SRAM as an example, the following two solutions are usually used in related technologies to improve the amplification function of the sense amplifier:

[0004] (1) Increasing the device size of the amplifying circuit of the sensitive amplifier: As mentioned above, the MOS tube used in the amplifying circuit of the sensitive amplifier cannot adopt the minimum size and is also restricted by the column width of the SRAM storage unit. Therefore, the adjustment space is limited.

[0005] (2) Increase the read delay: so that BL / BLX has more time to form a voltage difference, ensuring the amplification function of the sensitive amplifier under the worst conditions. However, this solution has the defect of sacrificing performance under typical working conditions.

[0006] It should be noted that the information disclosed in the background technology section of the invention is only intended to deepen the understanding of the general background technology of the invention, and should not be regarded as an admission or suggestion in any form that the information constitutes prior art already known to those skilled in the art. Summary of the invention

[0007] The purpose of the present invention is to provide a read assist circuit, a control method, a memory and an electronic device for a memory. The present invention can improve the amplification efficiency of the sensitive amplifier without increasing the read delay, ensure the successful reading of the memory data, and significantly improve the performance of the memory.

[0008] In order to achieve the above object, the present invention is implemented by the following technical scheme: a read assist circuit for a memory, the memory includes a sense amplifier, the sense amplifier includes a level amplifier circuit, the level amplifier circuit is used to amplify the voltage difference between a bit line and a reference bit line when reading the memory; the read assist circuit includes a switch device and a negative voltage generating sub-circuit; the first end of the switch device, the first end of the negative voltage generating sub-circuit and the ground end of the level amplifier circuit are coupled to a first node, the second end of the switch device is grounded, and the control end of the switch device and the second end of the negative voltage generating sub-circuit are coupled to a second node to receive a driving signal;

[0009] The read assist circuit is configured such that when the drive signal is a first electrical signal, the switch device is in an on state so that the voltage at the first node is a first voltage value; when the drive signal is a second electrical signal, the switch device is in an off state, and the negative voltage generating subcircuit is configured to generate a second voltage value at the first node; wherein the voltage of the first electrical signal is greater than the voltage of the second electrical signal, and the second voltage value is less than the first voltage value.

[0010] Optionally, the negative voltage generating sub-circuit includes a first MOS transistor, a gate of the first MOS transistor is coupled to the second node, and a source and a drain of the first MOS transistor are coupled to the first node.

[0011] Optionally, the negative voltage generating sub-circuit includes a capacitor, a first end of the capacitor is coupled to the first node, and a second end of the capacitor is coupled to the second node.

[0012] Optionally, the negative voltage generating subcircuit includes a charge pump for generating negative voltage.

[0013] Optionally, the read assist circuit also includes a negation subcircuit, a first end of the negation subcircuit is coupled to the second node, and a second end of the negation subcircuit is used to receive a read signal of the memory; the negation subcircuit is configured to set the drive signal to the first electrical signal when the read signal is at a low level, and to set the drive signal to the second electrical signal when the read signal is at a high level.

[0014] Optionally, the switch device includes a second MOS tube, a gate of the second MOS tube is used to receive the driving signal, a source / drain of the second MOS tube is coupled to the ground terminal of the level amplification circuit, and a drain / source of the second MOS tube is grounded;

[0015] The second MOS transistor is configured to be in an on state when the driving signal is a first electrical signal so that the voltage at the first node is a first voltage value; and to be in an off state when the driving signal is a second electrical signal.

[0016] Optionally, the read assist circuit is integrated into a chip.

[0017] In order to achieve the above object, the present invention further provides a control method for the read assist circuit described in any one of the above items, the control method comprising:

[0018] Determine whether to enable the read assist circuit:

[0019] If not, driving the switch device to be in an on state so that the voltage at the first node is a first voltage value;

[0020] If so, determine whether the memory is in a reading state: if so, drive the switching device to an off state and enable the negative voltage generating subcircuit to generate a second voltage value at the first node, and the second voltage value is less than the first voltage value; if not, drive the switching device to an on state so that the voltage at the first node is the first voltage value.

[0021] In order to achieve the above object, the present invention further provides a memory, which includes a sense amplifier having a level amplification circuit and any one of the above-mentioned read assist circuits for the memory.

[0022] In order to achieve the above object, the present invention further provides an electronic device, which includes any one of the read assist circuits or the memory described above.

[0023] Compared with the prior art, the read assist circuit, control method, memory and electronic device provided by the present invention for a memory have the following advantages:

[0024] The present invention provides a read assist circuit for a memory, and the present invention provides a read assist circuit for a memory, and the present invention provides a switch device and a negative voltage generating subcircuit, and when the drive signal is a first electrical signal, the switch device is in a conducting state, and when the drive signal is a second electrical signal, the switch device is in a shut-off state. Therefore, when using the read assist circuit provided by the present invention, the drive signal can be set to the second electrical signal when reading the memory data so that the switch device is in a shut-off state, thereby driving the negative voltage generating subcircuit to generate a second voltage value at the first node, thereby lowering the voltage of the ground terminal of the level amplifier circuit of the sensitive amplifier. In this way, the present invention can increase the voltage difference between the power supply terminal and the ground terminal of the level amplifier circuit without increasing the read delay, improve the amplification efficiency of the sensitive amplifier, ensure the successful reading of the memory data, and thus significantly improve the performance of the memory. After completing the read operation, the drive signal is set to the first electrical signal, so that the ground terminal of the level amplifier circuit remains at 0 level, and since the time window for the sensitive amplifier to read data is very short, it has almost no effect on power consumption.

[0025] Since the control method, memory and electronic device of the read assist circuit provided by the present invention belong to the same inventive concept as the read assist circuit for the memory provided by the present invention, the control method, memory and electronic device of the read assist circuit provided by the present invention at least have all the advantages of the read assist circuit for the memory provided by the present invention. For details on the beneficial effects of the control method, memory and electronic device of the read assist circuit provided by the present invention, please refer to the above description of the beneficial effects of the read assist circuit for the memory provided by the present invention, and no further details will be given here. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A schematic diagram of one application scenario of the read assist circuit for a memory provided by the present invention;

[0027] Figure 2 A structural block diagram of a read assist circuit for a memory provided by the present invention;

[0028] Figure 3 A schematic diagram of a circuit topology structure of a read assist circuit for a memory provided in Embodiment 1 of the present invention;

[0029] Figure 4 A schematic diagram of a circuit topology structure of a read assist circuit for a memory provided in a second embodiment of the present invention;

[0030] Figure 5 A schematic diagram of a circuit topology structure of a read assist circuit for a memory provided in a fourth embodiment of the present invention;

[0031] Figure 6 A flowchart of a control method for a read assist circuit provided in Embodiment 5 of the present invention;

[0032] Figure 7 A schematic diagram of a circuit topology structure of a memory provided in Embodiment 6 of the present invention;

[0033] Figure 8 Taking reading "0" as an example, a waveform diagram of related signals of a memory without a read assist circuit in the related art is shown;

[0034] Fig. 9 For example, read "0" Figure 8 Schematic diagram of waveforms of related signals of a memory with a read assist circuit under the same conditions;

[0035] The reference numerals are as follows:

[0036] Memory 100, sense amplifier 110, level amplifier circuit 111, latch 112, storage array 130, storage unit 131, read circuit 140, control circuit 150;

[0037] Bit line-BL, reference bit line-BLX, ground terminal-VSS, power terminal-VDD, drive signal-EN, precharge signal-PRECH, read signal-SAE, read signal-DOUT;

[0038] Read assist circuit-120, switch device-121, negative voltage generating sub-circuit-122, negation sub-circuit-123;

[0039] First node-N1, second node-N2;

[0040] The first MOS tube-Q1, the second MOS tube-Q2, and the capacitor-C. DETAILED DESCRIPTION

[0041] The following is a further detailed description of the read assist circuit, control method, memory and electronic device for memory proposed by the present invention in conjunction with the accompanying drawings. According to the following description, the advantages and features of the present invention will be more clear. It should be noted that the drawings are in a very simplified form and are not in precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In order to make the purposes, features and advantages of the present invention more obvious and easy to understand, please refer to the drawings. It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions for the implementation of the present invention. Any modification of the structure, change of the proportional relationship or adjustment of the size, under the same or similar conditions as the effects and purposes that can be achieved by the present invention, should still fall within the scope of the technical content disclosed by the present invention. The specific design features of the present invention disclosed herein include, for example, specific dimensions, directions, positions and shapes, which will be determined in part by the specific application and use environment. And, in the embodiments described below, sometimes the same figure mark is used in common between different drawings to represent the same part or part with the same function, and its repeated description is omitted. In this specification, similar reference numerals and letters are used to refer to similar items, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures. In addition, if the method described herein includes a series of steps, the order of these steps presented herein is not necessarily the only order in which these steps can be performed, and some of the steps described may be omitted and / or some other steps not described herein may be added to the method.

[0042] It should be noted that, in this article, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "includes one..." do not exclude the existence of other identical elements in the process, method, article or device including the elements. The singular forms "one", "an" and "the" include plural objects, the term "or" is usually used to include the meaning of "and / or", the term "several" is usually used to include the meaning of "at least one", and the term "at least two" is usually used to include the meaning of "two or more". In addition, the terms "first", "second" and "third" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated.

[0043] It should be understood that when an element is referred to as being "connected," "connected to," or "coupled to" another element, it can be directly connected to the other element, or there can be intervening elements. Conversely, when an element is referred to as being "directly connected" or "directly connected to" another element, there are no intervening elements.

[0044] The core idea of ​​the present invention is to provide a read assist circuit, a control method, a memory and an electronic device for a memory. The present invention can improve the amplification efficiency of the sensitive amplifier without increasing the read delay, ensure the successful reading of the memory data, and significantly improve the performance of the memory.

[0045] In order to realize the above idea, the present invention provides a read assist circuit for a memory. For example, see Figure 1 and Figure 2 ,in, Figure 1 A schematic diagram of one application scenario of the read assist circuit for a memory provided by the present invention, Figure 2 The structure block diagram of the read assist circuit for the memory provided by the present invention. Figure 1 and Figure 2 It can be seen that the memory 100 includes a sense amplifier 110, and the sense amplifier 110 includes a level amplifier circuit 111, and the level amplifier circuit 111 is used to amplify the voltage difference between the bit line BL and the reference bit line BLX when reading the memory 100. Exemplarily, the read assist circuit 120 includes a switch device 121 and a negative voltage generating sub-circuit 122; the first end of the switch device 121, the first end of the negative voltage generating sub-circuit 122, and the ground end VSS of the level amplifier circuit 111 are coupled to the first node N1, the second end of the switch device 121 is grounded, and the control end of the switch device 121 and the second end of the negative voltage generating sub-circuit 122 are coupled to the second node N2 to receive the driving signal EN. Furthermore, the read assist circuit 120 is configured such that when the drive signal EN is a first electrical signal, the switch device 121 is in an on state so that the voltage at the first node N1 is a first voltage value; when the drive signal EN is a second electrical signal, the switch device 121 is in an off state, and the negative voltage generating subcircuit 122 is configured to generate a second voltage value at the first node N1; wherein the voltage of the first electrical signal is greater than the voltage of the second electrical signal, and the second voltage value is less than the first voltage value.

[0046] The read assist circuit 120 for a memory provided by the present invention includes a switch device 121 and a negative voltage generating subcircuit 122, and when the drive signal EN is a first electrical signal, the switch device 121 is in a conducting state, and when the drive signal EN is a second electrical signal, the switch device 121 is in a shutoff state. Therefore, when using the read assist circuit 120 provided by the present invention, the drive signal EN can be set to a second electrical signal when reading data of the memory 100 so that the switch device 121 is in a shutoff state, thereby driving the negative voltage generating subcircuit 122 to generate a second voltage value at the first node N1, thereby lowering the voltage of the ground terminal VSS of the level amplifier circuit 111 of the sense amplifier 110. With such a configuration, the present invention can increase the voltage difference between the power supply terminal VDD and the ground terminal VSS of the level amplifier circuit 111 without increasing the read delay, thereby improving the amplification efficiency of the sense amplifier 110, ensuring successful reading of the data of the memory 100, and thereby significantly improving the performance of the memory 100. After the reading operation is completed, the driving signal EN is set to the first electrical signal so that the ground terminal VSS of the level amplifier circuit 111 maintains a 0 level. Since the time window for the sense amplifier 110 to read data is very short, it has almost no effect on power consumption.

[0047] It should be noted that the read assist circuit 120 for a memory provided by the present invention does not impose too many restrictions on the specific type of the memory 100. As long as the memory 100 has a sense amplifier 110 and the sense amplifier 110 has a level amplification circuit 111. For example, the memory 100 can be a non-volatile memory or a volatile memory. Further, for example, the non-volatile memory 100 can be a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM) or a flash memory. The volatile memory can be a random access memory (RAM) or an external cache memory. By way of illustration and not limitation, RAM may be any of a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct RAMbus dynamic RAM (DRDRAM), and RAM100 bus dynamic RAM (RDRAM), etc.

[0048] It should be further noted that those skilled in the art should be able to understand that the present invention does not impose too many restrictions on the specific values ​​of the first voltage value and the second voltage value. For example, the first voltage value may be 0, the second voltage value is a negative voltage value less than 0, and the second voltage value may be -400mv.

[0049] For example, in some exemplary implementations, the read assist circuit 120 is integrated into a chip.

[0050] It is understandable that the present invention does not impose any limitation on the manufacturing process, function and application field of the chip integrated with the read assist circuit 120 provided by the present invention. For example, the chip may be, but not limited to, a 7nm chip, a 14nm chip and a 28nm chip; further, the chip may be, but not limited to, a processor chip, a sensor chip and a communication chip; further, the chip may be, but not limited to, a car chip, a consumer electronics chip and a medical chip.

[0051] Next, various specific embodiments of the read assist circuit 120 for a memory provided by the present invention are described.

[0052] Embodiment 1

[0053] This embodiment provides a read assist circuit for a memory. For example, see Figure 3 , Figure 3 A schematic diagram of a circuit topology structure of a read assist circuit for a memory provided in this embodiment. Figure 3It can be seen that the negative voltage generating subcircuit 122 of the read assist circuit for the memory provided in this embodiment includes a first MOS transistor Q1, a gate of the first MOS transistor Q1 is coupled to the second node N2, and a source and a drain of the first MOS transistor Q1 are coupled to the first node N1. Thus, the source and drain of the first MOS transistor Q1 are coupled to the first node N1. At this time, the first MOS transistor Q1 is used as a negative voltage generating capacitor (BOOST CAP), which is equivalent to coupling a capacitor to the first node N1. Since the switch device 121 is in a conducting state when the drive signal EN is a first electrical signal, and the switch device 121 is in a turned-off state when the drive signal EN is a second electrical signal, the drive signal EN can be reduced from the first electrical signal to the second electrical signal when reading (the reading time window is extremely short) the memory 100, that is, the voltage of the second node N2 is reduced. Due to the coupling effect of the first MOS transistor Q1, a short negative voltage is generated at the second node N2, thereby increasing the voltage difference between the power supply terminal VDD and the ground terminal VSS of the level amplifier circuit 111, thereby improving the amplification efficiency of the sense amplifier 110, and ensuring the successful reading of the data of the memory 100. Moreover, the negative voltage generating sub-circuit 122 adopts the design method of the first MOS transistor Q1, which is simple in structure and easy to implement.

[0054] It should be noted that the present invention does not impose too many restrictions on the type of the first MOS transistor Q1. For example, the first MOS transistor Q1 may be an NMOS transistor. Further, for the relevant content about the use of the first MOS transistor Q1 as a negative voltage generating capacitor, please refer to the relevant technology known to those skilled in the art, which will not be elaborated in this article.

[0055] Preferably, in some of the exemplary embodiments, please continue to refer to Figure 3 ,from Figure 3It can be seen that the switching device 121 includes a second MOS tube Q2, a gate of the second MOS tube Q2 is used to receive the driving signal EN, a source / drain of the second MOS tube Q2 is coupled to the ground terminal VSS of the level amplification circuit 111, and a drain / source of the second MOS tube Q2 is grounded; the second MOS tube Q2 is configured to be in an on state when the driving signal EN is a first electrical signal, so that the voltage at the first node N1 is a first voltage value; and to be in an off state when the driving signal EN is a second electrical signal. Therefore, when reading the data of the memory 100, the driving signal EN can be set to the second electrical signal so that the second MOS tube Q2 is in the off state, so as to use the coupling effect of the first MOS tube Q1 to pull down the voltage of the ground terminal VSS of the level amplification circuit 111 of the sensitive amplifier 110. In this way, it is possible to increase the voltage difference between the power supply terminal VDD and the ground terminal VSS of the level amplification circuit 111 without increasing the read delay, thereby improving the amplification efficiency of the sensitive amplifier 110, ensuring the successful reading of the data of the memory 100, and thus significantly improving the performance of the memory 100.

[0056] It should be noted that, as can be understood by those skilled in the art, the present invention does not impose too many restrictions on the second MOS transistor Q2. For example, the second MOS transistor Q2 can be an NMOS transistor or a PMOS transistor. If an NMOS transistor is used as the second MOS transistor Q2, correspondingly, the source of the second MOS transistor Q2 (i.e., the first end of the second MOS transistor Q2 in this article) is coupled to the ground end VSS of the level amplification circuit 111, and the drain of the second MOS transistor Q2 (i.e., the second end of the second MOS transistor Q2 in this article) is grounded; if a PMOS transistor is used as the second MOS transistor Q2, correspondingly, the drain of the second MOS transistor Q2 (i.e., the first end of the second MOS transistor Q2 in this article) is coupled to the ground end VSS of the level amplification circuit 111, and the source of the second MOS transistor Q2 (i.e., the second end of the second MOS transistor Q2 in this article) is grounded. In particular, for more detailed information about the MOS transistor, please refer to the relevant technology about the MOS transistor known to those skilled in the art. Due to space limitations, this article will not elaborate on this.

[0057] It should be understood that the use of the second MOS tube Q2 to implement the switch device 121 is only an exemplary description of a preferred implementation, and is not a limitation of the present invention. The present invention does not impose too many restrictions on the specific implementation of the switch device 121. When implementing the present invention, other methods other than the second MOS tube Q2 can also be used to implement the switch device 121. For example, the switch device 121 can also be, but is not limited to, a switch tube, etc.

[0058] It should be further explained that the present invention does not impose too many restrictions on the driving scenarios of the read assist circuit 120. For example, in some embodiments, the drive signal EN can be set to the second electrical signal as long as the memory 100 is read, and the drive signal EN can be set to the first electrical signal in all scenarios except reading the memory 100. In other embodiments, only in the scenario where the read current of the storage unit 131 of the memory 100 or the sense amplifier 110 affects the read limit of the memory 100 (such as high temperature or low voltage scenario), the drive signal EN is set to the second electrical signal when reading the memory 100, and in other scenarios that do not affect the read limit of the memory 100, the drive signal EN is set to the first electrical signal regardless of whether the memory 100 is read.

[0059] Embodiment 2

[0060] This embodiment provides another read assist circuit for a memory. The read assist circuit provided in this embodiment is different from that in the first embodiment in that the negative voltage generating subcircuit 122 is implemented differently. To avoid redundant description, only the differences from the first embodiment are described below. For the parts not mentioned in this embodiment, please refer to the relevant description of the first embodiment for adaptive understanding. For example, please refer to Figure 4 , Figure 4 A schematic diagram of a circuit topology structure of a read assist circuit for a memory provided in this embodiment. Figure 4 It can be seen that in the read assist circuit 120 for a memory provided in this embodiment, the negative voltage generating subcircuit 122 includes a capacitor C, a first end of the capacitor C is coupled to the first node N1, and a second end of the capacitor C is coupled to the second node N2. Therefore, by using the capacitor C to implement the negative voltage generating subcircuit 122, the drive signal EN can be set to the second electrical signal when reading the data of the memory 100 so that the second MOS tube Q2 is in a turned-off state, that is, the drive signal EN is reduced from the first electrical signal to the second electrical signal of a lower voltage, so that the voltage at the second end of the capacitor C is lower than the voltage at the first end thereof, and the coupling effect of the capacitor C is used to pull down the voltage of the ground terminal VSS of the level amplifier circuit 111 of the sense amplifier 110. In this way, the voltage difference between the power supply terminal VDD and the ground terminal VSS of the level amplifier circuit 111 can be increased without increasing the read delay, thereby improving the amplification efficiency of the sense amplifier 110, ensuring the successful reading of the data of the memory 100, and thus significantly improving the performance of the memory 100.

[0061] It should be noted that the basic principle of the coupling effect of the capacitor C can be referred to the relevant technology known to those skilled in the art, which will not be elaborated in this article.

[0062] Embodiment 3

[0063] The present embodiment provides another read assist circuit for a memory. The read assist circuit provided in the present embodiment is different from that in the first embodiment in that the negative voltage generating subcircuit 120 is implemented differently. In order to avoid redundancy, only the differences from the first embodiment are described below. For the parts not mentioned in the present embodiment, please refer to the relevant description of the first embodiment for adaptive understanding. Exemplarily, the negative voltage generating subcircuit 122 includes a charge pump that generates a negative voltage. Therefore, the negative voltage generating subcircuit 122 of the read assist circuit 120 provided by the present invention is implemented by a charge pump, and a stable negative voltage can be generated by the charge pump, which can not only improve the performance of the memory 100, but also make the read data more stable and controllable. It should be understood that for more detailed content about the charge pump, please refer to the charge pump related technology known to those skilled in the art, and this article will not elaborate on this.

[0064] It is particularly important to note that those skilled in the art should be able to understand that the implementation methods of the negative voltage generating sub-circuit 122 in Example 1, Example 2 and Example 3 herein are merely illustrative descriptions of preferred implementation methods, and are not limitations of the present invention. In other implementation methods, the negative voltage generating sub-circuit 122 may also be implemented in other ways besides the first MOS tube Q1, the capacitor C and the charge pump for generating negative voltage. The negative voltage generating sub-circuit 122 only needs to be able to lower the voltage at the first node N1 when the received drive signal EN is the second signal.

[0065] Embodiment 4

[0066] This embodiment provides another read assist circuit for a memory. The read assist circuit provided in this embodiment is different from that in the first embodiment in that the read assist circuit 120 further includes a counter subcircuit. In order to avoid redundant description, only the differences from the first embodiment are described below. For the parts not mentioned in this embodiment, please refer to the relevant description of the first embodiment for adaptive understanding. For example, please refer to Figure 5 , Figure 5 A schematic diagram of a circuit topology structure of a read assist circuit for a memory provided in this embodiment. Figure 5It can be seen that the read assist circuit 120 also includes a negation subcircuit 123, a first end of the negation subcircuit 123 is coupled to the second node N2, and a second end of the negation subcircuit 123 is used to receive a read signal SAE of the memory 100; the negation subcircuit 123 is configured to set the drive signal EN to the first electrical signal when the read signal SAE is at a low level (i.e., non-read state, i.e., the level amplification circuit 111 of the sensitive amplifier 110 is in a non-amplification state), and to set the drive signal EN to the second electrical signal when the read signal SAE is at a high level (i.e., read state, i.e., the level amplification circuit 111 of the sensitive amplifier 110 is in an amplification state). Therefore, the read assist circuit 120 for the memory provided by the present invention includes a negation subcircuit 123, and the drive signal EN and the read signal SAE are associated by the negation subcircuit 123. As long as the drive signal EN is set to the second electrical signal when reading the memory 100, the negative voltage generating subcircuit 122 is driven to generate a second voltage value at the first node N1, thereby lowering the voltage of the ground terminal VSS of the level amplification circuit 111 of the sensitive amplifier 110. With such a configuration, the present invention can increase the voltage difference between the power supply terminal VDD and the ground terminal VSS of the level amplification circuit 111 without increasing the read delay, thereby improving the amplification efficiency of the sensitive amplifier 110, ensuring successful reading of the data of the memory 100, and significantly improving the performance of the memory 100.

[0067] It should be noted that the present invention does not impose too many restrictions on the specific implementation of the negation sub-circuit 123. For example, the negation sub-circuit 123 may include a NOT gate, so as to invert the level of the received read signal SAE to obtain the drive signal EN. Obviously, the inclusion of the NOT gate in the negation sub-circuit 123 is only an exemplary description of a preferred embodiment and not a limitation. In specific implementation, the negation sub-circuit 123 may also be implemented by other means besides the NOT gate, which are not listed here one by one.

[0068] Embodiment 5

[0069] Based on the same inventive concept, this embodiment provides a control method for a read assist circuit, wherein the read assist circuit includes the read assist circuit described in any embodiment of this document. Figure 6 , Figure 6 Flow chart of the control method of the read assist circuit provided in this embodiment. Figure 6 It can be seen that the control method includes:

[0070] S100: Determine whether to enable the read assist circuit 120:

[0071] S210: If not, driving the switch device 121 to be in a conducting state, so that the voltage at the first node N1 is a first voltage value;

[0072] S220: If yes, determine whether the memory 100 is in a read state:

[0073] S221: If yes, drive the switch device 121 to be in the off state and enable the negative voltage generating subcircuit 122 to generate a second voltage value at the first node N1, wherein the second voltage value is less than the first voltage value;

[0074] S222: If not, drive the switch device 121 to be in the on state, so that the voltage at the first node N1 is the first voltage value.

[0075] Since the control method for the read assist circuit provided by the present invention and the read assist circuit for the memory provided by the present invention belong to the same inventive concept, the control method for the read assist circuit provided by the present invention at least has all the advantages of the read assist circuit for the memory provided by the present invention. For details on the beneficial effects of the control method for the read assist circuit provided by the present invention, please refer to the above description of the beneficial effects of the read assist circuit for the memory provided by the present invention, which will not be repeated here.

[0076] Embodiment 6

[0077] Based on the same inventive concept, this embodiment provides a memory. For example, please continue to refer to Figure 1 and Figure 7 , Figure 7 This is a schematic diagram of the circuit topology structure of the memory provided in the sixth embodiment. Figure 1 and Figure 7 It can be seen that the memory 100 includes a sense amplifier 110 having a level amplification circuit 111 and a read assist circuit 120 for the memory 100 as described in any embodiment of the present invention.

[0078] from Figure 7 It can be seen that the memory 100 also includes a method for reading the storage unit 131 ( Figure 7 The read circuit 140 and the control circuit 150 (not shown) Figure 7 The sense amplifier 110 includes a level amplifier circuit 111 and a latch 112. For the relevant contents of the memory 100, such as the control circuit 150, the read circuit 140, and the level amplifier circuit 111 and the latch 112 of the sense amplifier 110, please refer to the relevant knowledge known to those skilled in the art. Due to space limitations, this article will not elaborate on this.

[0079] In order to better understand the present invention, please refer to Figure 7 See also Figure 8 and Fig. 9 The reading operation of the memory with the read assist circuit provided by the present invention is briefly described as follows. Figure 8 Taking reading "0" as an example, a waveform diagram of related signals of a memory 100 without a read assist circuit 120 in the related art is shown; Fig. 9 For example, read "0" Figure 8 Schematic diagram of waveforms of related signals of the memory 100 with the read assist circuit 120 under the same conditions.

[0080] First, when the read assist circuit 120 is not turned on, the drive signal EN is set to a first electrical signal, so that the second MOS tube Q2 is in a conducting state, which is equivalent to grounding the ground terminal VSS of the level amplifier circuit 111 and maintaining a first voltage value (such as 0V).

[0081] Next, if the data "0" stored in a certain storage cell 131 is read, the control circuit 150 first precharges the bit line BL to a third voltage value through the precharge signal PRECH, and then the control circuit 150 opens the corresponding storage cell 131. Since the data stored in the storage cell 131 is "0", the voltage on the bit line BL decreases, and the sensitive amplifier 110 captures the voltage change between the bit line BL and the reference bit line BLX, and drives the level amplifier circuit 111 to amplify the voltage change by enabling the read signal SAE. Figure 8 In the related solution without the read assist circuit 120, the voltage of the ground terminal VSS of the level amplifier circuit 111 is maintained at the first voltage value (for example, 0V). When reading the data "0", due to the amplification efficiency of the sense amplifier 110, the sense amplifier 110 fails to recognize the voltage change, resulting in the read signal DOUT being "1". Fig. 9 When the read signal SAE is enabled, the driving signal EN applied to the read assist circuit 120 is set from the first signal to the second signal, so that the voltage of the ground terminal VSS of the level amplifier circuit 111 is pulled down to a second voltage value (exemplarily, as Fig. 9 As shown, the second voltage value is -400mv), thereby increasing the voltage difference between the power supply terminal VDD and the ground terminal VSS of the level amplifier circuit 111, and improving its amplification capability. Therefore, when reading the data "0", the voltage change can be recognized and the read signal DOUT is successfully obtained as "0".

[0082] Finally, after the read operation is completed, the drive signal EN applied to the read assist circuit 120 can be reset to the first signal to turn on the switch device 121 so that the voltage of the ground terminal VSS of the level amplifier circuit 111 is maintained at the first voltage value (such as 0V).

[0083] It is clear that the present invention does not impose too many restrictions on the correspondence between the read assist circuit 120 and the sense amplifier 110. As can be understood by those skilled in the art, the sense amplifier 110 of the register corresponds one-to-one to the bit line BL. For example, in some embodiments, the read assist circuit 120 can correspond one-to-one to the sense amplifier 110 to improve the control accuracy; in other embodiments, since the sense amplifiers 110 corresponding to all IOs of the memory 100 work to read data at the same time, multiple sense amplifiers 110 can share one read assist circuit 120 to reduce the area of ​​the memory 100. The impact of this embodiment on the area of ​​the memory 100 is estimated to be within 0.5%.

[0084] Embodiment 7

[0085] Based on the same inventive concept, another embodiment of the present invention provides an electronic device, which includes the read assist circuit described in any embodiment of the present invention or the memory described above.

[0086] Since the electronic device provided by the present invention and the read assist circuit for the memory provided by the present invention belong to the same inventive concept, the electronic device provided by the present invention at least has all the advantages of the read assist circuit for the memory provided by the present invention. For details on the beneficial effects of the electronic device provided by the present invention, please refer to the above description of the beneficial effects of the read assist circuit for the memory provided by the present invention, which will not be repeated here.

[0087] It should be noted that those skilled in the art should be able to understand that the present invention does not impose any limitation on the electronic equipment. For example, the electronic equipment includes but is not limited to video products such as televisions, video recorders, and digital cameras, communication products such as mobile phones, communication switching equipment, and communication transmission equipment, learning assistance products such as translators, learning machines, and electronic dictionaries, and medical equipment products such as medical imaging equipment and medical testing equipment. Due to space limitations, they are not listed here one by one.

[0088] Compared with the prior art, the read assist circuit, control method, memory and electronic device provided by the present invention for a memory have the following advantages:

[0089] The present invention provides a read assist circuit for a memory, and the present invention provides a read assist circuit for a memory, and the present invention provides a switch device and a negative voltage generating subcircuit, and when the drive signal is a first electrical signal, the switch device is in a conducting state, and when the drive signal is a second electrical signal, the switch device is in a shut-off state. Therefore, when using the read assist circuit provided by the present invention, the drive signal can be set to the second electrical signal when reading the memory data so that the switch device is in a shut-off state, thereby driving the negative voltage generating subcircuit to generate a second voltage value at the first node, thereby lowering the voltage of the ground terminal of the level amplifier circuit of the sensitive amplifier. In this way, the present invention can increase the voltage difference between the power supply terminal and the ground terminal of the level amplifier circuit without increasing the read delay, improve the amplification efficiency of the sensitive amplifier, ensure the successful reading of the data of the memory, and thus significantly improve the performance of the memory. After completing the read operation, the drive signal is set to the first electrical signal, so that the ground terminal of the level amplifier circuit remains at 0 level, and since the time window for the sensitive amplifier to read data is very short, it has almost no effect on power consumption.

[0090] It should be noted that the devices and methods disclosed in the embodiments of this article can also be implemented in other ways. The device implementation described above is only schematic. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of this article. In this regard, each box in the flowchart or block diagram can represent a part of a module, program or code, and the module, program segment or part of the code contains one or more executable instructions for implementing the specified logical function, and the module, program segment or part of the code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented by a dedicated hardware-based system for performing a specified function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0091] In addition, the functional modules in the various embodiments of this document may be integrated together to form an independent part, or each module may exist independently, or two or more modules may be integrated to form an independent part.

[0092] The above description is only a description of the preferred implementation of the read assist circuit, control method, memory and electronic device for memory provided by the present invention, and is not any limitation to the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure content belong to the protection scope of the present invention. Obviously, technicians in this field can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations belong to the scope of the present invention and its equivalent technology, the present invention is also intended to include these modifications and variations.

Claims

1. A read assist circuit for a memory, wherein the memory comprises a sense amplifier, the sense amplifier comprises a level amplifier circuit, and the level amplifier circuit is used to amplify the voltage difference between a bit line and a reference bit line when reading the memory; characterized in that: The read assist circuit includes a switch device and a negative voltage generating subcircuit; a first end of the switch device, a first end of the negative voltage generating subcircuit and a ground end of the level amplifying circuit are coupled to a first node, a second end of the switch device is grounded, and a control end of the switch device and a second end of the negative voltage generating subcircuit are coupled to a second node to receive a driving signal; The read assist circuit is configured such that when the drive signal is a first electrical signal, the switch device is in a conducting state, so that the voltage at the first node is a first voltage value; When the driving signal is a second electrical signal, the switching device is in an off state, and the negative voltage generating subcircuit is configured to generate a second voltage value at the first node; wherein the voltage of the first electrical signal is greater than the voltage of the second electrical signal, and the second voltage value is less than the first voltage value.

2. The read assist circuit according to claim 1, characterized in that: The negative voltage generating sub-circuit includes a first MOS transistor, a gate of the first MOS transistor is coupled to the second node, and a source and a drain of the first MOS transistor are coupled to the first node.

3. The read assist circuit according to claim 1, characterized in that: The negative voltage generating sub-circuit includes a capacitor, a first end of the capacitor is coupled to the first node, and a second end of the capacitor is coupled to the second node.

4. The read assist circuit according to claim 1, characterized in that: The negative voltage generating subcircuit includes a charge pump for generating negative voltage.

5. The read assist circuit according to claim 1, characterized in that: The read assist circuit also includes a negation subcircuit, a first end of the negation subcircuit is coupled to the second node, and a second end of the negation subcircuit is used to receive a read signal of the memory; the negation subcircuit is configured to set the drive signal to the first electrical signal when the read signal is at a low level, and to set the drive signal to the second electrical signal when the read signal is at a high level.

6. The read assist circuit according to any one of claims 1 to 5, characterized in that: The switch device comprises a second MOS tube, the gate of the second MOS tube is used to receive the driving signal, the source / drain of the second MOS tube is coupled to the ground terminal of the level amplification circuit, and the drain / source of the second MOS tube is grounded; The second MOS transistor is configured to be in a conducting state when the driving signal is a first electrical signal, so that the voltage at the first node is a first voltage value; When the driving signal is a second electrical signal, the device is in an off state. The read assist circuit according to claim 6 , wherein the read assist circuit is integrated into a chip.

8. A control method for a read assist circuit as claimed in any one of claims 1 to 7, characterized in that: The control method comprises: Determine whether to enable the read assist circuit: If not, driving the switch device to be in an on state so that the voltage at the first node is a first voltage value; If so, determine whether the memory is in a reading state: if so, drive the switching device to an off state and enable the negative voltage generating subcircuit to generate a second voltage value at the first node, and the second voltage value is less than the first voltage value; if not, drive the switching device to an on state so that the voltage at the first node is the first voltage value.

9. A memory, characterized in that: The invention comprises a sense amplifier having a level amplification circuit and a read assist circuit for a memory as claimed in any one of claims 1 to 7.

10. An electronic device, characterized in that: The electronic device comprises the read assist circuit according to any one of claims 1 to 7 or the memory according to claim 9.

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