Manufacturing method of FDSOI device

Abstract

The invention discloses a manufacturing method of an FDSOI device. The manufacturing method comprises the following steps: step 1, growing a first germanium-silicon layer on the surface of a top silicon layer of an SOI substrate; step 2, performing first oxidation to form a top silicon oxide layer on the surface of the first germanium-silicon layer; and step 3, annealing to enable germanium to be uniformly distributed in the top silicon layer and the first germanium-silicon layer and form a top germanium-silicon layer. And 4, removing the top silicon oxide layer. And 5, performing silicon treatment to enable unsaturated Ge bonds on the top surface of the top germanium-silicon layer to be saturated and combined by Si bonds and form a silicon-rich layer on the top surface of the top germanium-silicon layer. And step 6, second oxidation is carried out to form a gate oxide layer on the top surface of the top germanium-silicon layer, and the gate oxide layer is formed by combining Si bonds and oxygen in the silicon-rich layer, so that the number of Ge-O bonds is reduced, and the interface state density is reduced. According to the invention, the germanium concentration of the channel layer formed by the germanium-silicon material can be improved, and the interface state density between the channel layer and the gate oxide layer can be reduced, so that the performance of the device can be improved.

Description

Technical Field

[0001] The invention relates to a method for manufacturing a semiconductor integrated circuit, in particular to a method for manufacturing a FDSOI device. Background Art

[0002] As the size of devices continues to shrink, the short channel effect of traditional MOSFET becomes more prominent, and a new FDSOI structure is needed to overcome this problem. In order to improve the mobility of PMOS, SiGe channel is a very promising option. However, due to the combination of Ge bond and O bond, the SiGe channel easily forms an unsaturated Ge-O bond, which increases the interface state density at the interface, resulting in a decrease in device performance due to the carrier capture effect.

[0003] like Figures 1A to 1E , which is a device structure diagram in each step of the existing FDSOI device manufacturing method; the existing FDSOI device manufacturing method includes the following steps:

[0004] Step 1: Figure 1A As shown, a SOI substrate is provided, and the SOI substrate includes a semiconductor main layer 101, an insulating buried layer 102 and a top silicon layer 103 which are stacked in sequence.

[0005] like Figure 1B As shown, a first silicon germanium layer 104 is grown on the surface of the top silicon layer 103 .

[0006] Typically, the first silicon germanium layer 104 is grown using a RPCVD process.

[0007] The doping concentration of the first silicon germanium layer 104 is uniform doping or layered doping in which the doping concentration gradually decreases from the bottom to the top. Figure 1B , it is shown that the first germanium silicon layer 104 is divided into two doping layers, namely a first doping layer 104a and a second doping layer 104b, and the doping concentration of the second doping layer 104b is greater than the doping concentration of the first doping layer 104a.

[0008] Step 2: Figure 1C As shown, a first oxidation is performed to form a top silicon oxide layer 105 on the surface of the first silicon germanium layer 104 and germanium condensation is formed at the interface between the first silicon germanium layer 104 and the top silicon oxide layer 105; after the top silicon oxide layer 105 is formed, the total thickness of the top silicon layer 103 and the first silicon germanium layer 104 is less than the germanium diffusion length.

[0009] Step 3: Figure 1D As shown, annealing is performed to make germanium uniformly distributed in the top silicon layer 103 and the first silicon germanium layer 104 and form a top silicon germanium layer 106 . The germanium concentration of the top silicon germanium layer 106 is greater than the germanium concentration of the first silicon germanium layer 104 .

[0010] like Figure 1D As shown, due to the barrier effect of the top silicon oxide layer 105 and the buried insulating layer 102 , during the annealing process, germanium will be evenly distributed in the region between the top silicon oxide layer 105 and the buried insulating layer 102 to form a top germanium silicon layer 106 .

[0011] Step 4: Figure 1E As shown, the top silicon oxide layer 105 is removed.

[0012] When the gate oxide layer is subsequently formed, the top germanium silicon layer 106 will be directly oxidized. However, since the germanium concentration of the top germanium silicon layer 106 is relatively high, unsaturated Ge-O bonds are easily formed at the interface during oxidation. Such unsaturated Ge-O bonds will lead to interface defects and increase the interface state density, thereby affecting device performance, such as the threshold voltage will shift. Summary of the invention

[0013] The technical problem to be solved by the present invention is to provide a method for manufacturing an FDSOI device, which can increase the germanium concentration of a channel layer formed of germanium silicon material while reducing the interface state density between the channel layer and the gate oxide layer, thereby improving the performance of the device.

[0014] In order to solve the above technical problems, the manufacturing method of the FDSOI device provided by the present invention comprises the following steps:

[0015] Step 1: providing an SOI substrate, wherein the SOI substrate comprises a semiconductor main layer, an insulating buried layer and a top silicon layer stacked in sequence, and growing a first germanium silicon layer on the surface of the top silicon layer.

[0016] Step 2: Perform a first oxidation to form a top silicon oxide layer on the surface of the first silicon germanium layer and form germanium condensation at the interface between the first silicon germanium layer and the top silicon oxide layer; after the top silicon oxide layer is formed, the total thickness of the top silicon layer and the first silicon germanium layer is less than the germanium diffusion length.

[0017] Step three: performing annealing to make germanium uniformly distributed in the top silicon layer and the first silicon-germanium layer to form a top silicon-germanium layer, wherein the germanium concentration of the top silicon-germanium layer is greater than the germanium concentration of the first silicon-germanium layer.

[0018] Step 4: removing the top silicon oxide layer.

[0019] Step 5: silicon-treating the Ge bonds on the top surface of the top germanium silicon layer so that the unsaturated Ge bonds on the top surface of the top germanium silicon layer are saturated with Si bonds and a silicon-rich layer is formed on the top surface of the top germanium silicon layer.

[0020] Step six: performing a second oxidation to form a gate oxide layer on the top surface of the top germanium silicon layer, wherein the gate oxide layer is formed by combining Si bonds and oxygen in the silicon-rich layer to reduce the number of Ge-O bonds and thereby reduce the interface state density.

[0021] A further improvement is that the top silicon germanium layer at the bottom of the gate oxide layer serves as a channel layer of the PMOS.

[0022] A further improvement is that in step five, the silicon treatment is achieved by dichlorosilane (DCS) treatment, and the molecular formula of DCS is SiH2Cl2.

[0023] A further improvement is that the pressure of the high-pressure atmosphere of the DCS treatment is 30 torr to 200 torr.

[0024] A further improvement is that the reaction temperature of the DCS treatment is set to ensure that the top silicon-germanium layer is not damaged during the DCS treatment.

[0025] A further improvement is that the reaction temperature of the DCS treatment is a low temperature of 620°C to 650°C.

[0026] A further improvement is that the thickness of the silicon-rich layer is adjusted by adjusting the reaction time of the DCS treatment, and the thickness range of the silicon-rich layer is: the minimum thickness of the silicon-rich layer is required to reduce the interface state density to meet the process requirements; the maximum thickness of the silicon-rich layer is required to make the carrier mobility of the channel layer of the PMOS meet the process requirements.

[0027] A further improvement is that the reaction time of the DCS treatment is 10s to 100s.

[0028] A further improvement is that the material of the semiconductor main layer includes silicon.

[0029] A further improvement is that the material of the insulating buried layer includes silicon dioxide.

[0030] A further improvement is that, in step one, the first germanium silicon layer is grown using an RPCVD process.

[0031] A further improvement is that the doping concentration of the first germanium silicon layer is uniform doping or layered doping in which the doping concentration gradually decreases from the bottom to the top.

[0032] After the concentration of the first grown germanium silicon layer is increased and a top germanium silicon layer with a higher germanium concentration is formed, the present invention does not directly perform oxidation to form a gate oxide layer, but first performs a silicidation treatment. The silicidation treatment can saturate more unsaturated germanium bonds formed in the top surface area of ​​the top germanium silicon layer due to the increase in germanium concentration through silicon bonds. In this way, in the second oxidation to form the gate oxide layer, the gate oxide layer is mainly formed by the combination of Si bonds and oxygen, so that the number of Ge-O bonds can be reduced and thus the interface state density can be reduced. Therefore, the present invention can increase the germanium concentration of the channel layer formed by the germanium silicon material while reducing the interface state density between the channel layer and the gate oxide layer, thereby improving the performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0034] Figure 1A-1E It is a device structure diagram in each step of the manufacturing method of the existing FDSOI device;

[0035] Figure 2 is a flow chart of a method for manufacturing an FDSOI device according to an embodiment of the present invention;

[0036] Figure 3A-3G It is a device structure diagram in each step of the manufacturing method of the FDSOI device in an embodiment of the present invention. DETAILED DESCRIPTION

[0037] like Figure 2 FIG. 1 is a flow chart of a method for manufacturing an FDSOI device according to an embodiment of the present invention; Figures 3A to 3G , which is a device structure diagram in each step of the method for manufacturing an FDSOI device according to an embodiment of the present invention; the method for manufacturing an FDSOI device according to an embodiment of the present invention comprises the following steps:

[0038] Step 1: Figure 3A As shown, a SOI substrate is provided, and the SOI substrate includes a semiconductor main layer 201, an insulating buried layer 202 and a top silicon layer 203 which are stacked in sequence.

[0039] In the embodiment of the present invention, the material of the semiconductor body layer 201 includes silicon.

[0040] The material of the buried insulating layer 202 includes silicon dioxide.

[0041] like Figure 3B As shown, a first silicon germanium layer 204 is grown on the surface of the top silicon layer 203 .

[0042] In the embodiment of the present invention, the first silicon germanium layer 204 is grown by using the RPCVD process.

[0043] The doping concentration of the first silicon germanium layer 204 is uniform doping or layered doping in which the doping concentration gradually decreases from the bottom to the top. Figure 3B , it is shown that the first germanium silicon layer 204 is divided into two doping layers, namely a first doping layer 204a and a second doping layer 204b, and the doping concentration of the second doping layer 204b is greater than the doping concentration of the first doping layer 204a.

[0044] Step 2: Figure 3C As shown, a first oxidation is performed to form a top silicon oxide layer 205 on the surface of the first silicon germanium layer 204 and germanium condensation is formed at the interface between the first silicon germanium layer 204 and the top silicon oxide layer 205; after the top silicon oxide layer 205 is formed, the total thickness of the top silicon layer 203 and the first silicon germanium layer 204 is less than the germanium diffusion length.

[0045] Step 3: Figure 3D As shown, annealing is performed to make germanium uniformly distributed in the top silicon layer 203 and the first silicon germanium layer 204 to form a top silicon germanium layer 206 . The germanium concentration of the top silicon germanium layer 206 is greater than the germanium concentration of the first silicon germanium layer 204 .

[0046] Step 4: Figure 3E As shown, the top silicon oxide layer 205 is removed.

[0047] Step 5: Figure 3F As shown, the Ge bonds on the top surface of the top germanium silicon layer 206 are silicon-treated so that the unsaturated Ge bonds on the top surface of the top germanium silicon layer 206 are saturated with Si bonds and a silicon-rich layer 207 is formed on the top surface of the top germanium silicon layer 206 .

[0048] In the embodiment of the present invention, the silicon processing is implemented by DCS processing.

[0049] In some embodiments, the pressure of the high-pressure atmosphere of the DCS treatment is 30 torr to 200 torr.

[0050] The reaction temperature of the DCS treatment is set to ensure that the top SiGe layer 206 is not damaged during the DCS treatment. In some embodiments, the reaction temperature of the DCS treatment is a low temperature of 620°C to 650°C.

[0051] In the embodiment of the present invention, the thickness of the silicon-rich layer 207 is adjusted by adjusting the reaction time of the DCS treatment, and the thickness range of the silicon-rich layer 207 is: the minimum thickness of the silicon-rich layer 207 is required to reduce the interface state density to meet the process requirements; the maximum thickness of the silicon-rich layer 207 is required to make the carrier mobility of the subsequent PMOS channel layer 301 meet the process requirements. In some preferred embodiments, the reaction time of the DCS treatment is 10s to 100s, and the reaction time of 10s to 100s can ensure that the interface state density meets the requirements while ensuring that the thickness of the silicon-rich layer 207 is reduced so that the carrier mobility of the channel layer 301 is not affected.

[0052] Step 6: Figure 3G As shown, a second oxidation is performed to form a gate oxide layer 302 on the top surface of the top germanium silicon layer 206. The gate oxide layer 302 is formed by combining Si bonds and oxygen in the silicon-rich layer 207 to reduce the number of Ge-O bonds and thereby reduce the interface state density.

[0053] In the embodiment of the present invention, the top silicon germanium layer 206 at the bottom of the gate oxide layer 302 serves as the channel layer 301 of the PMOS.

[0054] like Figure 3G As shown, the subsequent steps include: forming a gate conductive material layer 303 and performing patterning etching. In some embodiments, the gate conductive material layer 303 is a polysilicon gate.

[0055] Source and drain implantation is performed to form a source region 304 and a drain region 305 on both sides of the gate conductive material layer 303 in a self-aligned manner.

[0056] In the embodiment of the present invention, after the concentration of the grown first germanium silicon layer 204 is increased and a top germanium silicon layer 206 with a higher germanium concentration is formed, oxidation is not directly performed to form a gate oxide layer 302, but a silicidation treatment is first performed. The silicidation treatment can saturate the unsaturated germanium bonds in the top surface area of ​​the top germanium silicon layer 206 due to the increase in germanium concentration through silicon bonds. In this way, in the second oxidation to form the gate oxide layer 302, the gate oxide layer 302 is mainly formed by the combination of Si bonds and oxygen, which can reduce the number of Ge-O bonds and thus reduce the interface state density. Therefore, the embodiment of the present invention can increase the germanium concentration of the channel layer 301 formed by the germanium silicon material while reducing the interface state density between the channel layer 301 and the gate oxide layer 302, thereby improving the performance of the device.

[0057] Based on the existing original process, the embodiment of the present invention performs DCS treatment on the SiGe channel layer, i.e., the top germanium silicon layer 206, so that the outer Si bonds are first combined with the Ge bonds, and the Si bonds are more matched with the subsequent gate oxide layer (Gate oxide) to reduce the interface state and thus better achieve performance improvement. CV testing can verify that the interface state density between the SiGe channel layer and the gate oxide layer of the FDSOI device formed in the embodiment of the present invention is smaller.

[0058] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.

Claims

1. A method for manufacturing a FDSOI device, characterized in that: The steps include: Step 1: providing an SOI substrate, wherein the SOI substrate comprises a semiconductor main layer, an insulating buried layer and a top silicon layer stacked in sequence, and growing a first germanium silicon layer on the surface of the top silicon layer; Step 2: performing a first oxidation to form a top silicon oxide layer on the surface of the first silicon germanium layer and to form germanium condensation at the interface between the first silicon germanium layer and the top silicon oxide layer; after the top silicon oxide layer is formed, the total thickness of the top silicon layer and the first silicon germanium layer is less than the germanium diffusion length; Step 3: performing annealing to uniformly distribute germanium in the top silicon layer and the first germanium silicon layer to form a top germanium silicon layer, wherein the germanium concentration of the top germanium silicon layer is greater than the germanium concentration of the first germanium silicon layer; Step 4: removing the top silicon oxide layer; Step 5: siliconizing the Ge bonds on the top surface of the top germanium silicon layer, so that the unsaturated Ge bonds on the top surface of the top germanium silicon layer are saturated with Si bonds and a silicon-rich layer is formed on the top surface of the top germanium silicon layer; Step six: performing a second oxidation to form a gate oxide layer on the top surface of the top germanium silicon layer, wherein the gate oxide layer is formed by combining Si bonds and oxygen in the silicon-rich layer to reduce the number of Ge-O bonds and thereby reduce the interface state density.

2. The method for manufacturing a FDSOI device according to claim 1, wherein: The top silicon germanium layer at the bottom of the gate oxide layer serves as a channel layer of the PMOS.

3. The method for manufacturing a FDSOI device according to claim 2, wherein: In step five, the silicon processing is implemented by DCS processing.

4. The method for manufacturing a FDSOI device according to claim 3, wherein: The pressure of the high-pressure atmosphere in the DCS treatment is 30 torr to 200 torr.

5. The method for manufacturing a FDSOI device according to claim 4, wherein: The reaction temperature of the DCS treatment is set to ensure that the top silicon-germanium layer is not damaged during the DCS treatment.

6. The method for manufacturing a FDSOI device according to claim 5, wherein: The reaction temperature of the DCS treatment is a low temperature of 620°C to 650°C.

7. The method for manufacturing a FDSOI device according to claim 3, wherein: The thickness of the silicon-rich layer is adjusted by adjusting the reaction time of the DCS treatment, and the thickness range of the silicon-rich layer is: the minimum thickness requirement of the silicon-rich layer is to reduce the interface state density to meet the process requirements; the maximum thickness requirement of the silicon-rich layer is to make the carrier mobility of the channel layer of the PMOS meet the process requirements.

8. The method for manufacturing a FDSOI device according to claim 7, wherein: The reaction time of the DCS treatment is 10s to 100s.

9. The method for manufacturing a FDSOI device according to claim 1, wherein: The material of the semiconductor body layer includes silicon.

10. The method for manufacturing a FDSOI device according to claim 1, wherein: The material of the insulating buried layer includes silicon dioxide.

11. The method for manufacturing a FDSOI device according to claim 1, wherein: In step one, the first silicon germanium layer is grown using the RPCVD process.

12. The method for manufacturing a FDSOI device according to claim 10, characterized in that: The doping concentration of the first silicon germanium layer is uniform doping or layered doping in which the doping concentration gradually decreases from the bottom to the top.

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