Adjusting method for channel width of transistor, transistor and preparation method of transistor

Abstract

The invention discloses a transistor channel width adjusting method, a transistor and a preparation method of the transistor. According to the invention, the mask layer is etched back by adopting a wet etching process to enlarge the width of the opening of the groove above the substrate, so that the isolation structure formed in the groove can reduce the channel width of the channel region, and the purpose of adjusting the channel width of the transistor is achieved; the channel width of the channel region of the transistor can be adjusted under the conditions that a GDS layout does not need to be drawn again and a mask does not need to be additionally introduced, the flexibility is good, the adjustability is relatively high, and the time and the cost of the process are saved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor process technology, and in particular to a method for adjusting a transistor channel width, a transistor and a method for preparing the same. Background Art

[0002] Integrated circuits (ICs) and other electronic devices often include interconnected field effect transistor (FET) arrangements, also called metal oxide semiconductor field effect transistors (MOSFETs) or simply MOS transistors or devices. A typical MOS transistor includes a gate electrode as a control electrode and spaced-apart source and drain electrodes, a control voltage applied to the gate electrode controlling current flow through a controllable conductive channel between the source and drain electrodes.

[0003] Generally speaking, the transistor channel width is fixed when the layout is determined. If the channel width needs to be adjusted, especially when the adjustment is large, the GDS layout needs to be redrawn and an additional mask needs to be introduced, which leads to a long process cycle and additional costs. Among them, GDS (Graphic Data System) is a binary file format used to describe the layout and circuit connections of semiconductor chips. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a method for adjusting the channel width of a transistor, a transistor and a preparation method thereof, which can adjust the channel width of the transistor channel region without redrawing the GDS layout and without introducing an additional mask plate, has good flexibility and high adjustability, and saves process time and cost.

[0005] To solve the above problems, an embodiment of the present invention provides a method for adjusting the channel width of a transistor, the method comprising the following steps: providing an initial substrate, the initial substrate comprising a substrate, a mask layer covering the top surface of the substrate, and an initial trench penetrating the mask layer along a first direction and extending into the substrate, wherein the initial trench has a first sub-trench located in the substrate and a second sub-trench located in the mask layer, the second sub-trench has an initial opening width, and the first direction intersects perpendicularly with the top surface of the substrate; etching back the mask layer using a wet etching process to expand the opening width of the second sub-trench to form a channel having an initial width. A third sub-groove with a target opening width, the first sub-groove and the third sub-groove together constitute a target groove; and an isolation structure is formed in the target groove and the mask layer is removed to form a target substrate, the isolation structure has a first sub-isolation structure extending into the substrate along the first direction and a second sub-isolation structure protruding from the top surface of the substrate, an active area is defined in the substrate by two adjacent first sub-isolation structures, the active area includes a channel area with a target channel width, the target channel width is the gap width between two adjacent second sub-isolation structures in the second direction, and the second direction is parallel to the top surface of the substrate.

[0006] In some embodiments, in the second direction, a difference between the target opening width and the initial opening width ranges from 20 nm to 100 nm.

[0007] In some embodiments, the step of etching back the mask layer using a wet etching process specifically includes: adjusting the amount of etching back the mask layer by controlling the wet etching time.

[0008] In some embodiments, the material of the mask layer is silicon nitride, and the wet etching process uses hot phosphoric acid as a wet etching solution.

[0009] In some embodiments, the etch-back amount of the mask layer is 10 nm to 50 nm.

[0010] To solve the above problem, an embodiment of the present invention further provides a method for preparing a transistor, the method comprising the following steps: preparing a target substrate using the transistor channel width adjustment method described in the present invention, the target substrate comprising a substrate and an isolation structure, the isolation structure comprising a first sub-isolation structure extending into the substrate along a first direction and a second sub-isolation structure protruding from the top surface of the substrate, wherein an active area is defined in the substrate by two adjacent first sub-isolation structures, the active area comprising a channel area having a target channel width, the target channel width being the gap width between two adjacent second sub-isolation structures in a second direction, the first direction intersecting perpendicularly with the top surface of the substrate, and the second direction being parallel to the top surface of the substrate; and forming a gate on the surface of the substrate between two adjacent second sub-isolation structures.

[0011] In some embodiments, the gate fills up the gap between two adjacent second sub-isolation structures and partially covers the top surfaces of two adjacent second sub-isolation structures.

[0012] In some embodiments, an oxide layer is further formed on the top surface of the substrate between two adjacent second sub-isolation structures, and the gate is formed on the top surface of the oxide layer.

[0013] In some embodiments, the gate is made of polysilicon, and the oxide layer is made of silicon dioxide.

[0014] To solve the above problem, an embodiment of the present invention further provides a transistor, wherein the transistor is manufactured using the transistor manufacturing method of the present invention, and the channel region of the transistor has a target channel width.

[0015] The above technical solution adopts a wet etching process to etch back the mask layer to expand the opening width of the trench above the substrate, so that the isolation structure formed in the trench can reduce the channel width of the channel region, thereby achieving the purpose of adjusting the channel width of the transistor. The channel width of the transistor channel region can be adjusted without redrawing the GDS layout or introducing an additional mask plate. It has good flexibility and large adjustability, saving process time and cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 It is a schematic diagram of the device structure of a transistor in the prior art;

[0018] Figure 2 A schematic diagram of the steps of a method for adjusting the channel width of a transistor provided by an embodiment of the present invention;

[0019] Figure 3 A schematic diagram of a device structure of an initial substrate provided in one embodiment of the present invention;

[0020] Figure 4 A schematic diagram of a device structure after forming a target trench according to an embodiment of the present invention;

[0021] Figure 5 A schematic diagram of a device structure after forming a target substrate according to an embodiment of the present invention;

[0022] Figure 6 A schematic diagram of the steps of a method for preparing a transistor provided in one embodiment of the present invention;

[0023] Figure 7 A schematic diagram of the device structure of a transistor provided in one embodiment of the present invention. DETAILED DESCRIPTION

[0024] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0025] See also Figure 1 , which is a schematic diagram of the device structure of a transistor in the prior art. Figure 1 As shown, in the prior art, a transistor includes a substrate 10, an isolation structure 11, a gate oxide layer 12 and a gate 13. An active area 101 is defined in the substrate by two adjacent isolation structures, and the active area 101 includes a channel area 102, and a channel width W10 of the channel area 102 is the gap width between the two adjacent isolation structures 11.

[0026] In the prior art, the channel width of the transistor is fixed when the layout is determined. If the channel width needs to be adjusted, especially when the adjustment is over a larger range, the GDS layout needs to be redrawn and an additional mask needs to be introduced, which results in a long process cycle and additional costs.

[0027] An embodiment of the present invention provides a method for adjusting the channel width of a transistor. The method uses a wet etching process to back-etch a mask layer to expand the opening width of the trench above the substrate, so that the isolation structure formed in the trench can reduce the channel width of the channel region, thereby achieving the purpose of adjusting the channel width of the transistor. The method can adjust the channel width of the transistor channel region without redrawing the GDS layout or introducing an additional mask plate. The method has good flexibility and high adjustability, saving process time and cost.

[0028] Please also read Figure 2 to Figure 5 ,in, Figure 2 A schematic diagram of the steps of a method for adjusting the channel width of a transistor provided by an embodiment of the present invention; Figure 3 A schematic diagram of a device structure of an initial substrate provided in one embodiment of the present invention; Figure 4 A schematic diagram of a device structure after forming a target trench according to an embodiment of the present invention; Figure 5 A schematic diagram of a device structure after forming a target substrate provided by an embodiment of the present invention.

[0029] like Figure 2 As shown, the method for adjusting the channel width of the transistor described in this embodiment includes the following steps: S21, providing an initial substrate, wherein the initial substrate includes a substrate, a mask layer covering the top surface of the substrate, and an initial groove penetrating the mask layer along a first direction and extending into the substrate, wherein the initial groove has a first sub-groove located in the substrate and a second sub-groove located in the mask layer, and the second sub-groove has an initial opening width; S22, back-etching the mask layer using a wet etching process to expand the opening width of the second sub-groove to form a second sub-groove with a target opening width, The first sub-groove and the second sub-groove having the target opening width together constitute a target groove; and S23, forming an isolation structure in the target groove and removing the mask layer to form a target substrate, the isolation structure having a first sub-isolation structure extending into the substrate along the first direction and a second sub-isolation structure protruding from the top surface of the substrate, an active area is defined in the substrate by two adjacent first sub-isolation structures, the active area includes a channel area with a target channel width, and the target channel width is the gap width between two adjacent second sub-isolation structures in the second direction.

[0030] Please refer to step S21 and Figure 3, providing an initial substrate 30, the initial substrate 30 comprising a substrate 31, a mask layer 32 covering the top surface of the substrate 31, and an initial groove 39 penetrating the mask layer 32 along a first direction D1 and extending into the substrate 31, wherein the initial groove 39 has a first sub-groove 391 located in the substrate 31 and a second sub-groove 392 located in the mask layer 32, and the second sub-groove 392 has an initial opening width W1. Specifically, the first direction D1 is defined to be perpendicular to the top surface of the substrate 31, and the second direction D2 is defined to be parallel to the top surface of the substrate 31.

[0031] Specifically, the initial trench 39 may be formed using the GDS layout and mask determined when the layout is determined, thereby eliminating the need to redraw the GDS layout and introduce an additional mask.

[0032] In some embodiments, the substrate 31 is used to support the device structure above it, and the device structure can also be formed in the substrate. In this embodiment, the substrate 31 can include a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, etc.; the substrate 31 can also be a stacked structure, such as a silicon / germanium silicon stack, etc.

[0033] In some embodiments, an oxide layer 33 is further formed between the top surface of the substrate 31 and the mask layer 32. The material of the oxide layer 33 may be silicon dioxide (SiO2), and the silicon dioxide film layer covering the top surface of the substrate 31 may prevent subsequent processes from causing damage to the top surface of the substrate 31. The material of the mask layer 32 may be silicon nitride (SiN), and the silicon nitride film layer serves as an etching mask layer and a barrier layer to protect the surface of the substrate 31 from being damaged.

[0034] Please refer to step S22 and Figure 4 The mask layer 32 is etched back by a wet etching process to expand the opening width of the second sub-groove 392, forming a third sub-groove 393 with a target opening width W2, and the first sub-groove 391 and the third sub-groove 393 together constitute a target groove 40. By using a wet etching (WET) process to etch back (etchback) to expand the opening width of the initial groove located above the substrate, the width of the mask layer is reduced, thereby achieving the purpose of reducing the channel width of the channel region formed subsequently.

[0035] In some embodiments, the step of etching back the mask layer 32 using a wet etching process specifically includes: controlling the wet etching time to adjust the etching amount of the mask layer 32. By adjusting the etching amount of the mask layer 32, the channel width of the subsequently formed channel region can be adjusted.

[0036] In some embodiments, the material of the mask layer 32 is silicon nitride (SiN), and the wet etching process uses hot phosphoric acid as a wet etching solution. Hot phosphoric acid has good uniformity and high selectivity for etching silicon nitride.

[0037] In some embodiments, the etch-back amount A0 of the mask layer 32 is 10 nm to 50 nm. For example, according to the adjustment requirements of the transistor channel width, the etch-back amount can be 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, etc.

[0038] In some embodiments, in the second direction D2, the difference between the target opening width W2 and the initial opening width W1 ranges from 20nm to 100nm. For example, according to the adjustment requirements of the transistor channel width, the difference range can be 20nm, 30nm, 40nm, 5nm, 60nm, 70nm, 80nm, 90nm, 100nm, etc.

[0039] Compared with the method of reducing the width of the mask layer by photolithography to adjust the channel width of the channel region, the present embodiment uses a wet etching process to reduce the width of the mask layer, without the need to redraw the GDS layout or introduce an additional mask. The method of reducing the width of the mask layer by photolithography is limited. For example, at the 65nm node, the normal photolithography process and OPC can cover a range of less than 20%. If the photolithography process is adjusted too much, there will be gaps between different sizes. The wet etching process provided by the present embodiment is an isotropic process with good accuracy. It can adjust the width of the mask layer well, and then adjust the channel width of the channel region. It has good flexibility and high adjustability, which can save process time and cost.

[0040] Please refer to step S23 and Figure 5, an isolation structure 51 is formed in the target groove 40 and the mask layer 32 is removed to form a target base 50, the isolation structure 51 has a first sub-isolation structure 511 extending into the substrate 31 along the first direction D1 and a second sub-isolation structure 512 protruding from the top surface of the substrate 31, an active area 501 is defined in the substrate 31 by two adjacent first sub-isolation structures 511, the active area 501 includes a channel area 502 with a target channel width W50, and the target channel width W50 is the gap width between two adjacent second sub-isolation structures 512 in the second direction D2.

[0041] In some embodiments, the isolation structure 51 may be a shallow trench isolation (STI) structure or a local oxidation of silicon (LOCOS) structure. Compared with the local oxidation of silicon isolation structure, the shallow trench isolation structure occupies a smaller substrate area and can improve the integration of devices on a unit substrate.

[0042] In this embodiment, a wet etching process is used to etch back the mask layer to expand the opening width of the trench above the substrate, so that the isolation structure formed in the trench can reduce the channel width of the channel region, thereby achieving the purpose of adjusting the channel width of the transistor. The channel width of the transistor channel region can be adjusted without redrawing the GDS layout or introducing an additional mask plate. It has good flexibility and high adjustability, saving process time and cost.

[0043] Based on the same inventive concept, an embodiment of the present invention provides a method for preparing a transistor. By adopting the above-mentioned transistor channel width adjustment method of the present invention, a channel region with a target channel width is formed. The channel width of the transistor channel region can be adjusted without redrawing the GDS layout or introducing an additional mask plate. It has good flexibility and high adjustability, saving process time and cost.

[0044] Please also read Figure 6 , Figure 5 , Figure 7 ,in, Figure 6 A schematic diagram of the steps of a method for preparing a transistor provided in one embodiment of the present invention; Figure 7 A schematic diagram of the device structure of a transistor provided in one embodiment of the present invention.

[0045] like Figure 6As shown, the method for adjusting the transistor channel width described in this embodiment includes the following steps: S61, preparing a target substrate using the method for adjusting the transistor channel width described in the present invention, the target substrate including a substrate and an isolation structure, the isolation structure having a first sub-isolation structure extending into the substrate along a first direction and a second sub-isolation structure protruding from the top surface of the substrate, wherein an active area is defined in the substrate by two adjacent first sub-isolation structures, the active area including a channel area with a target channel width, and the target channel width is a gap width between two adjacent second sub-isolation structures in the second direction; and S62, forming a gate on the surface of the substrate between two adjacent second sub-isolation structures.

[0046] Please refer to step S61 and Figure 5 , a target substrate 50 is prepared by using the transistor channel width adjustment method of the present invention, the target substrate 50 includes a substrate 31 and an isolation structure 51, the isolation structure 51 includes a first sub-isolation structure 511 extending into the substrate 31 along a first direction D1 and a second sub-isolation structure 512 protruding from the top surface of the substrate 31; wherein an active area 501 is defined in the substrate 31 by two adjacent first sub-isolation structures 511, the active area 501 includes a channel area 502 with a target channel width W50, and the target channel width W50 is the gap width between two adjacent second sub-isolation structures 512 in the second direction D2. wherein the first direction D1 is perpendicular to the top surface of the substrate 31, and the second direction D2 is parallel to the top surface of the substrate 31.

[0047] In the target substrate 50 formed in this embodiment, the channel region has a target channel width, and this embodiment can adjust the channel width of the transistor channel region without redrawing the GDS layout or introducing an additional mask plate. It has good flexibility and high adjustability, saving process time and cost.

[0048] Please refer to step S62 and Figure 7 A gate 71 is formed on the surface of the substrate 31 between two adjacent second sub-isolation structures 512 .

[0049] In some embodiments, a maskless atomic layer deposition (ALD) method may be used to deposit and grow a gate material layer, and then the gate 71 may be obtained by photolithography and etching processes. The gate material may also be deposited using a predetermined mask to obtain the gate 71. The material of the gate 71 may be polysilicon (Poly).

[0050] In this embodiment, the gate 71 fills up the gap between two adjacent second sub-isolation structures 512 and partially covers the top surfaces of two adjacent second sub-isolation structures 512 .

[0051] In this embodiment, an oxide layer 33 is further formed on the top surface of the substrate 31 between two adjacent second sub-isolation structures 512, and the gate 71 is formed on the top surface of the oxide layer 33. Specifically, the material of the oxide layer 33 may be silicon dioxide (SiO2).

[0052] Based on the same inventive concept, an embodiment of the present invention provides a transistor, which is prepared by adopting the above-mentioned transistor preparation method of the present invention. The channel region of the transistor has a target channel width, and the channel width of the transistor channel region can be adjusted without redrawing the GDS layout and without introducing an additional mask plate. It has good flexibility and large adjustability, saving process time and cost.

[0053] See also Figure 7 The transistor described in this embodiment includes: a substrate 31, an isolation structure 51 and a gate 71. A first direction D1 is defined to be perpendicular to the top surface of the substrate 31, and a second direction D2 is defined to be parallel to the top surface of the substrate 31.

[0054] Specifically, the isolation structure 51 has a first sub-isolation structure 511 extending into the substrate 31 along the first direction D1 and a second sub-isolation structure 512 protruding from the top surface of the substrate 31; wherein, an active area 501 is defined in the substrate 31 by two adjacent first sub-isolation structures 511, and the active area 501 includes a channel area 502 having a target channel width W50, and the target channel width W50 is the gap width between two adjacent second sub-isolation structures 512 in the second direction D2.

[0055] Specifically, the gate 71 is formed on the surface of the substrate 31 between two adjacent second sub-isolation structures 512 .

[0056] In this embodiment, the gate 71 fills up the gap between two adjacent second sub-isolation structures 512 and partially covers the top surfaces of two adjacent second sub-isolation structures 512 .

[0057] In this embodiment, an oxide layer 33 is further formed on the top surface of the substrate 31 between two adjacent second sub-isolation structures 512, and the gate 71 is formed on the top surface of the oxide layer 33. Specifically, the material of the oxide layer 33 may be silicon dioxide (SiO2).

[0058] In the transistor formed in this embodiment, the channel region has a target channel width, and this embodiment can adjust the channel width of the transistor channel region without redrawing the GDS layout and without introducing an additional mask plate. It has good flexibility and high adjustability, saving process time and cost.

[0059] It should be noted that the terms "including" and "having" and their variations involved in the document of the present invention are intended to cover non-exclusive inclusions. The terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence, unless the context clearly indicates, and it should be understood that the data used in this way can be interchanged under appropriate circumstances. The term "one or more" depends at least in part on the context, and can be used to describe features, structures or characteristics in a singular sense, or can be used to describe features, structures or combinations of features in a plural sense. The term "based on" can be understood as not necessarily intended to express a set of exclusive factors, but can alternatively, also at least in part depending on the context, allow the presence of other factors that are not necessarily explicitly described. In addition, the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict. In addition, in the above description, the description of well-known components and technologies is omitted to avoid unnecessary confusion of the concept of the present invention. In the above embodiments, each embodiment focuses on the differences from other embodiments, and the same / similar parts between the embodiments can be referred to each other.

[0060] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for adjusting a transistor channel width, characterized in that: The method comprises the following steps: Providing an initial substrate, the initial substrate comprising a substrate, a mask layer covering a top surface of the substrate, and an initial groove penetrating the mask layer along a first direction and extending into the substrate, wherein the initial groove has a first sub-groove located in the substrate and a second sub-groove located in the mask layer, the second sub-groove has an initial opening width, and the first direction intersects the top surface of the substrate perpendicularly; Etching back the mask layer by a wet etching process to expand the opening width of the second sub-groove to form a third sub-groove with a target opening width, wherein the first sub-groove and the third sub-groove together constitute a target groove; and An isolation structure is formed in the target groove and the mask layer is removed to form a target base, the isolation structure having a first sub-isolation structure extending into the substrate along the first direction and a second sub-isolation structure protruding from the top surface of the substrate, an active area is defined in the substrate by two adjacent first sub-isolation structures, the active area includes a channel area with a target channel width, the target channel width is the gap width between two adjacent second sub-isolation structures in the second direction, and the second direction is parallel to the top surface of the substrate.

2. The method according to claim 1, characterized in that In the second direction, the difference between the target opening width and the initial opening width ranges from 20 nm to 100 nm.

3. The method according to claim 1, characterized in that The step of etching back the mask layer using a wet etching process specifically includes: The back etching amount of the mask layer is adjusted by controlling the wet etching time.

4. The method according to claim 1, characterized in that: The material of the mask layer is silicon nitride, and the wet etching process uses hot phosphoric acid as a wet etching solution.

5. The method according to claim 1, characterized in that: The etching back amount of the mask layer is 10nm-50nm.

6. A method for preparing a transistor, characterized in that: The method comprises the following steps: A target substrate is prepared by using the method for adjusting the channel width of a transistor according to any one of claims 1 to 5, wherein the target substrate comprises a substrate and an isolation structure, wherein the isolation structure comprises a first sub-isolation structure extending into the substrate along a first direction and a second sub-isolation structure protruding from a top surface of the substrate, wherein an active region is defined in the substrate by two adjacent first sub-isolation structures, the active region comprises a channel region having a target channel width, and the target channel width is a gap width between two adjacent second sub-isolation structures in a second direction, wherein the first direction intersects perpendicularly with the top surface of the substrate, and the second direction is parallel to the top surface of the substrate; and A gate is formed on the surface of the substrate between two adjacent second sub-isolation structures.

7. The method according to claim 6, characterized in that The gate fully fills the gap between two adjacent second sub-isolation structures and partially covers the top surfaces of two adjacent second sub-isolation structures.

8. The method according to claim 6, characterized in that An oxide layer is further formed on the top surface of the substrate between two adjacent second sub-isolation structures, and the gate is formed on the top surface of the oxide layer.

9. The method according to claim 8, characterized in that The material of the gate is polysilicon, and the material of the oxide layer is silicon dioxide.

10. A transistor, characterized in that: The transistor is manufactured by the transistor manufacturing method according to any one of claims 6 to 9, and the channel region of the transistor has a target channel width.

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