Small high-isolation up-conversion chip and frequency converter

Abstract

The invention provides a small-sized high-isolation up-conversion chip and a frequency converter, and belongs to the technical field of communication, and the small-sized high-isolation up-conversion chip comprises a local oscillator link, a frequency mixing link and a radio frequency link which are connected in sequence; wherein the local oscillator link comprises a five-stage single-power-supply power supply amplifying circuit and a frequency multiplier; the five-stage single-power-supply power supply amplification circuit comprises a two-stage single-power-supply first amplifier and a three-stage single-power-supply second amplifier. The first amplifier, the frequency multiplier and the second amplifier are connected in sequence; the radio frequency link comprises a four-stage dual-power supply amplification circuit; a part of circuit elements of the second amplifier, the first amplifier and the frequency multiplier are arranged on a transverse branch below the chip; the rest circuit elements of the second amplifier and the frequency mixing link are arranged in a transverse branch in the middle of the chip; and the radio frequency link is arranged on a transverse branch above the chip. According to the invention, the miniaturization of the up-conversion chip can be realized, and good isolation can be maintained at the same time.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a small high-isolation up-conversion chip and a frequency converter. Background Art

[0002] Frequency converter is an indispensable circuit in wireless system. Whether it is microwave communication system, radar, remote control, remote sensing, electronic reconnaissance and electronic countermeasure, as well as many microwave measurement systems, frequency converter is required to reduce microwave signal to medium and low frequency for processing. Monolithic Microwave Integrated Circuit (MMIC) system has the advantages of small size, high stability and high consistency, so the single-chip frequency converter has a wider application prospect in military and civilian electronic systems; at the same time, with the development demand of miniaturization of communication technology, it is also urgent to integrate multiple functional devices in the same semiconductor process, so the design of miniaturized and multifunctional chips is the trend. However, for multifunctional chips, it is necessary to achieve both chip miniaturization and multifunctional excellent performance. It is necessary to fully suppress the spurious and out-of-band of different functional devices in signal transmission. As the frequency increases, the wavelength of the transmission signal is comparable to the spacing of the transmission lines on the chip, and the signals of different paths will be coupled. Therefore, it is of great significance to design a miniaturized high isolation chip. Summary of the invention

[0003] The embodiments of the present application provide a small-sized high-isolation up-conversion chip and a frequency converter to solve the problem of miniaturizing the chip while maintaining a high isolation.

[0004] In a first aspect, an embodiment of the present application provides a small-sized high-isolation up-conversion chip, comprising: a local oscillator link, a mixing link, and a radio frequency link connected in sequence; Wherein, the local oscillator link comprises: a five-stage single-power supply amplifier circuit and a frequency multiplier; the five-stage single-power supply amplifier circuit comprises: a first amplifier with two stages of single power supplies and a second amplifier with three stages of single power supplies; the first amplifier, the frequency multiplier and the second amplifier are connected in sequence; The radio frequency link includes a four-stage dual-power supply amplifier circuit; Part of the circuit elements of the second amplifier, the first amplifier and the frequency multiplier are arranged in the horizontal branch below the chip; the remaining circuit elements of the second amplifier and the mixing link are arranged in the horizontal branch in the middle of the chip; and the radio frequency link is arranged in the horizontal branch above the chip.

[0005] In a possible implementation, the frequency multiplier is a 2-times frequency multiplier; The frequency multiplier comprises two diodes connected in reverse parallel; the output ends of the diodes are connected to a balun to output a combined signal.

[0006] In a possible implementation, the chip further includes: an impedance matching circuit M3; The impedance matching circuit M3 includes a series inductor L1 and a parallel capacitor C1; The series inductor L1 is connected to the output end of the diode and the balun terminal; the parallel capacitor C1 is grounded.

[0007] In a possible implementation, the operating frequency of the signal input to the first amplifier is 10-12 GHz; the operating frequency of the output signal after passing through the frequency multiplier is 20-24 GHz.

[0008] In a possible implementation, the chip further includes: a first impedance matching circuit; The first amplifier and the second amplifier include two-stage transistors and three-stage transistors, respectively; The first impedance matching circuit is connected to the third-stage transistor of the second amplifier and is used for performing optimal output power impedance matching of the transistor.

[0009] In a possible implementation, the first impedance matching circuit includes: a series capacitor, a grounding capacitor, a parallel capacitor, and a parallel resistor; One end of the parallel capacitor and the parallel resistor is connected to the series capacitor, and the other end is grounded.

[0010] In a possible implementation, the frequency mixing link includes an intermediate frequency signal input terminal, a radio frequency link connection terminal, and a local oscillator link connection terminal.

[0011] like Figure 4 As shown, the intermediate frequency signal is introduced by the PAD, connected to the balun B2 through the low-pass structure M4, and then input to the intermediate frequency signal input terminal; The low-pass structure M4 is composed of a series inductor L3 and a parallel capacitor C6.

[0012] In a possible implementation, the mixing link adopts a double-balanced mixing topology structure; The mixing core of the mixing link uses a diode with a size of 2 gate fingers, a gate width of 30 um, and a total gate width of 60 um.

[0013] In a possible implementation, the chip further includes a second impedance matching circuit connected between the frequency mixing link and the radio frequency link; The second impedance matching circuit includes: a first capacitor C7 and a second capacitor C8 connected in series, a parallel inductor L4 connected between the first capacitor C7 and the second capacitor C8, and a grounding resistor R1 connected to the parallel inductor L4.

[0014] In a possible implementation, a plurality of on-chip ground vias are added between signals of different paths, and the on-chip ground vias are connected in sequence.

[0015] In a possible implementation, the chip further includes: a high-impedance microstrip line; The high-impedance microstrip line is arranged around the diode of the mixing link, and the periphery of the high-impedance microstrip line is connected to a ground hole structure.

[0016] In a possible implementation, the small high-isolation up-conversion chip has a size of 3mm*2mm and uses a 5.0mm×5.0mm×1.1mm surface-mount leadless ceramic tube package, and the package dust and water resistance level is greater than or equal to IP66.

[0017] In a second aspect, an embodiment of the present application provides a frequency converter, comprising a small-sized high-isolation up-conversion chip as described in the first aspect or any possible implementation of the first aspect.

[0018] The embodiment of the present application provides a small high-isolation up-conversion chip and a frequency converter, and the small high-isolation up-conversion chip is composed of a local oscillator link, a mixing link and a radio frequency link connected in sequence. Among them, the local oscillator link includes: a five-stage single-power supply amplifier circuit and a frequency multiplier; the five-stage single-power supply amplifier circuit includes: a first amplifier of a two-stage single power supply and a second amplifier of a three-stage single power supply, and the first amplifier, the frequency multiplier and the second amplifier are connected in sequence to ensure the stability and amplification effect of the signal during transmission. The radio frequency link includes a four-stage dual-power supply amplifier circuit to meet the needs of radio frequency signal amplification and processing. Part of the circuit elements of the second amplifier, the first amplifier and the frequency multiplier are arranged in the horizontal branch below the chip; the remaining circuit elements of the second amplifier and the mixing link are arranged in the middle horizontal branch of the chip; the radio frequency link is arranged in the horizontal branch above the chip. This three-layer layout architecture not only maximizes the use of the chip's spatial resources, promotes the improvement of circuit integration, and realizes the miniaturization of the device, but also ensures effective isolation between the links, thereby enhancing the overall signal processing performance. This meets the dual high standards of size and performance of modern electronic equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0020] Figure 1 A schematic diagram of the structure of a small-sized high-isolation up-conversion chip provided in one embodiment of the present application; Figure 2 A simplified structural diagram of a local oscillator link provided in an embodiment of the present application; Figure 3 A schematic diagram of the structure of a first impedance matching circuit provided in an embodiment of the present application; Figure 4 A schematic diagram of a simplified filter structure at an intermediate frequency output end provided in an embodiment of the present application; Figure 5 A schematic diagram of the structure of a second impedance matching circuit provided in one embodiment of the present application; Figure 6 A schematic diagram of the layout of ground holes between different signal paths provided in an embodiment of the present application; Figure 7 A schematic diagram of the layout of ground holes around a diode provided in one embodiment of the present application; Figure 8 The measured IF port return loss provided by a specific embodiment of the present application; Fig. 9 The measured small signal gain provided by a specific embodiment of the present application; Fig.10 The measured output P1 provided in a specific embodiment of the present application; Fig.11 The measured output OIP3 provided by a specific embodiment of the present application; Fig.12 The measured 6*IF to RF leakage provided in a specific embodiment of the present application; Fig.13 The measured 2*LO to RF leakage provided by a specific embodiment of the present application; Fig.14 The measured 2*LO to IF leakage is provided for a specific embodiment of the present application. DETAILED DESCRIPTION

[0021] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0022] The terms "first", "second", etc. in the specification and claims of the embodiments of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the embodiments of the present application described here. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0023] Unless otherwise specified, the term "plurality" means two or more. The character " / " indicates that the objects before and after are in an "or" relationship. For example, A / B means: A or B. The term "and / or" is a description of the association relationship between objects, indicating that there can be three relationships. For example, A and / or B means: A or B, or, A and B.

[0024] The words used in this application are only used to describe the embodiments and are not used to limit the claims. As used in the description of the embodiments and claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include the plural forms as well. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of one or more associated listings. In addition, when used in this application, the term "comprise" and its variants "comprises" and / or including (comprising) refer to the existence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the existence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups of these. In the absence of more restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the process, method or device including the elements.

[0025] In this application, each embodiment may focus on the differences from other embodiments, and the same or similar parts between the embodiments may refer to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts may refer to the description of the method part.

[0026] GaAs broadband MMIC has a wide range of applications. The purpose of researching and developing MMIC was for military applications in the early days, mainly in the fields of radar, communication, electronic warfare, etc. Later, its main application shifted from military to civilian use. Wireless communications, mobile phones, satellite communication networks, global positioning systems (GPS), direct broadcast satellite reception (DBS), microwave automatic collision avoidance systems used in automobiles and traffic control will be huge markets for MMIC.

[0027] In modern communication systems, large-capacity and high-quality satellite communications have become one of the most important means of communication, whether strategic or tactical. The communication field, including communications, has a great demand for microwave, millimeter wave components and circuits, and has its own special requirements. Since there are extremely strict restrictions on the size and weight of the system in mobile communications, airborne communications, satellite communications and other communication systems, MMIC is the most suitable candidate for military and civilian communication applications. As a key component of ODU, the frequency converter plays the role of spectrum shifting and has a wide range of applications in many fields such as communications, radar, remote sensing, measurement, and electronic countermeasures. The performance and reliability of the frequency converter often have a great impact on the overall system, so the research and design of high-performance new frequency converters is of great significance to the research, development and application of the system.

[0028] The present application aims to provide a small high-isolation up-conversion chip. The chip integrates a variety of functional devices such as the local oscillator signal amplification link, the mixing link, and the radio frequency signal amplification link. The intermediate frequency signal, especially the local oscillator signal, is close to the radio frequency. If the intermediate frequency signal, the local oscillator signal, and the local oscillator out-of-band signal are not properly processed and amplified and output through the radio frequency link, it is easy to cause interference to the system. Under the premise of ensuring excellent performance, the present application optimizes the layout and proposes some simplified matching and filtering structures to realize a high-isolation miniaturized up-conversion multifunctional chip.

[0029] In order to make the purpose, technical solutions and advantages of the present application clearer, specific embodiments will be described below in conjunction with the accompanying drawings.

[0030] Figure 1 is a schematic diagram of the structure of a small high-isolation up-conversion chip provided in an embodiment of the present application. Figure 1 The figure includes: a local oscillator chain, a mixing chain and a radio frequency chain connected in sequence.

[0031] Among them, the local oscillator chain includes: a five-stage single-power supply amplifier circuit and a frequency multiplier; the five-stage single-power supply amplifier circuit includes: a two-stage single-power supply first amplifier M1 and a three-stage single-power supply second amplifier M2; the first amplifier M1, the frequency multiplier and the second amplifier M2 are connected in sequence.

[0032] The radio frequency link includes a four-stage dual-power supply amplifier circuit.

[0033] Part of the circuit elements of the second amplifier M2, the first amplifier M1 and the frequency multiplier are arranged in the horizontal branch below the chip; the remaining circuit elements of the second amplifier M2 and the mixing link are arranged in the horizontal branch in the middle of the chip; the radio frequency link is arranged in the horizontal branch above the chip.

[0034] The first amplifier M1 includes two-stage transistors G1 and G2, and the second amplifier M2 includes three-stage transistors G4, G5 and G6. The RF link includes four-stage transistors G6, G7, G8 and G9. The lower horizontal branch signal is transmitted from left to right, the middle horizontal branch signal is transmitted from right to left, and the upper horizontal branch signal is transmitted from left to right.

[0035] In the embodiment of the present application, a small high-isolation up-conversion chip is composed of a local oscillator link, a mixing link and a radio frequency link connected in sequence. Among them, the local oscillator link includes: a five-stage single-power supply amplifier circuit and a frequency multiplier; the five-stage single-power supply amplifier circuit includes: a first amplifier of a two-stage single power supply and a second amplifier of a three-stage single power supply, and the first amplifier, the frequency multiplier and the second amplifier are connected in sequence to ensure the stability and amplification effect of the signal during transmission. The radio frequency link includes a four-stage dual-power supply amplifier circuit to meet the needs of radio frequency signal amplification and processing. Part of the circuit elements of the second amplifier, the first amplifier and the frequency multiplier are arranged in the lateral branch below the chip; the remaining circuit elements of the second amplifier and the mixing link are arranged in the middle lateral branch of the chip; the radio frequency link is arranged in the lateral branch above the chip. This three-layer layout architecture not only maximizes the use of the chip's spatial resources, promotes the improvement of circuit integration, and realizes the miniaturization of the device, but also ensures effective isolation between the links, thereby enhancing the overall signal processing performance. This meets the dual high standards of size and performance of modern electronic equipment.

[0036] In a possible implementation, the frequency multiplier is a 2x frequency multiplier; The frequency doubler includes two diodes connected in reverse parallel; the output ends of the diodes are connected to a balun to output a combined signal.

[0037] In this embodiment, the frequency multiplier includes two anti-parallel diodes to achieve frequency multiplication of the second harmonic component.

[0038] like Figure 2 , which is a simplified structural diagram of a local oscillator link provided in an embodiment of the present application.

[0039] In a possible implementation, in order to optimize the frequency multiplication loss of the frequency multiplier, the chip further includes: an impedance matching circuit M3; The impedance matching circuit M3 includes a series inductor L1 and a parallel capacitor C1; The series inductor L1 is connected to the output end of the diode and the balun terminal; the parallel capacitor C1 is grounded.

[0040] In this embodiment, the introduction of the impedance matching circuit M3 improves the impedance matching between the diode port and the differential end impedance of the balun, and also improves the phase amplitude consistency of the balun, effectively improving the required second harmonic component, while also reducing the gain power index requirement for the first amplifier M1, thereby reducing the amplifier power consumption and the number of amplifier stages.

[0041] In a possible implementation, the operating frequency of the signal input to the first amplifier M1 is 10-12 GHz; the operating frequency of the output signal after the frequency multiplier is 20-24 GHz to meet the communication requirements of the Ka band.

[0042] In a possible implementation manner, the chip further includes: a first impedance matching circuit.

[0043] The first amplifier M1 and the second amplifier M2 include two-stage transistors and three-stage transistors, respectively.

[0044] The first impedance matching circuit is connected to the third-stage transistor G5 of the second amplifier M2 for performing impedance matching for the transistor for optimal output power.

[0045] In this embodiment, in order to enhance the out-of-band suppression effect of the local oscillator signal, a first impedance matching circuit is introduced. The introduction of the impedance matching circuit solves the problem of complex structure and cumbersome design process in the traditional design concept, that is, first design the local oscillator output matching link, and then add a bandpass filter at the connection with the frequency converter.

[0046] In one possible implementation, Figure 3 As shown, the first impedance matching circuit includes: a series capacitor, a grounding capacitor, a parallel capacitor and a parallel resistor; One end of the parallel capacitor and the parallel resistor is connected to the series capacitor, and the other end is grounded.

[0047] In this embodiment, the impedance matching circuit forms a simplified structure that integrates transistor power output matching and bandpass filter through series capacitors, grounded capacitors, parallel capacitors and parallel resistors, integrating the optimal power impedance point matching, DC isolation and filtering functions of transistor G5, ensuring the optimal amplifier power while achieving local oscillator out-of-band signal suppression, which not only ensures performance, but also simplifies the circuit architecture and further reduces the chip size.

[0048] In a possible implementation, the frequency mixing link includes an intermediate frequency signal input terminal, a radio frequency link connection terminal, and a local oscillator link connection terminal; The intermediate frequency signal is introduced by PAD, connected to balun B2 through low-pass structure M4, and then input to the intermediate frequency signal input terminal; The low-pass structure M4 is composed of a series inductor L3 and a parallel capacitor C6.

[0049] In the specific implementation process, the local oscillator signal generates two equal-amplitude and anti-phase signals through the balun B1, which are respectively input to the local oscillator input end of the mixing core; the intermediate frequency signal is introduced by the PAD, passes through the simplified low-pass structure M4, connected to the balun B2 and input to the mixing core, generating two RF signals, which are synthesized into a single RF signal output through the balun B2.

[0050] In this embodiment, the simplified low-pass structure M4 is composed of a series inductor L3 and a parallel capacitor C6, which not only optimizes the intermediate frequency port standing wave, but also improves the local oscillator-intermediate frequency and radio frequency-intermediate frequency isolation.

[0051] In a possible implementation, the mixer link adopts a double-balanced mixer topology structure; The mixer core of the mixer link uses a diode with a gate finger of 2, a gate width of 30um, and a total gate width of 60um.

[0052] In this embodiment, in order to ensure the power characteristics of the frequency converter, the mixer core of the mixer link uses a gate width of 30 um to prevent the gate width from being too large, which will lead to an increase in leakage capacitance and thus avoid degradation of the high-frequency characteristics of the diode.

[0053] In one possible implementation, Figure 5 As shown, the chip also includes a second impedance matching circuit connected between the frequency mixing link and the radio frequency link; The second impedance matching circuit includes: a first capacitor C7 and a second capacitor C8 connected in series, a parallel inductor L4 connected between the first capacitor C7 and the second capacitor C8, and a grounding resistor R1 connected to the parallel inductor L4.

[0054] In the specific implementation process, the mixing core is connected to the first-stage transistor G6 of the RF amplifier link by Figure 5 In the design process, the conventional scheme of first matching the power optimal input impedance of transistor G6 to 50 ohms and then connecting it to the inverter through a high-pass filter matching 50 ohms is no longer used. In this embodiment, a first capacitor C7, a second capacitor C8, a parallel inductor L4, and a grounding resistor R1 are used. Figure 5 The structure directly matches the optimal input impedance of transistor G6 to the impedance of the mixer core RF output, avoiding multiple designs and multiple circuit components.

[0055] In this embodiment, the first capacitor C7, the second capacitor C8, and the parallel inductor L4 can be equivalent to a T-type high-pass filter to suppress the intermediate frequency signal and reduce the leakage from the intermediate frequency to the radio frequency end; the second capacitor C8 has a DC isolation function, and the parallel inductor L4 and the grounding resistor R1 are connected in series to the ground structure, which can improve the stability of the amplifier. The second impedance matching circuit has a simple structure, a streamlined design process, and improves the intermediate frequency-radio frequency and local oscillator-radio frequency isolation.

[0056] In one possible implementation, Figure 6 As shown, multiple on-chip ground holes are added between signals of different paths, and the on-chip ground holes are connected in sequence to form a signal isolation wall.

[0057] In one possible implementation, Figure 7 As shown, the chip also includes: a high impedance microstrip line; The high impedance microstrip line surrounds the diode arrangement of the mixing link, and the periphery of the high impedance microstrip line is connected to a ground hole structure.

[0058] In the mixer core circuit, the ground hole structure cannot be placed between the two diodes due to the tight layout. Figure 7 The high impedance microstrip line shown surrounds the diode, and the periphery of the high impedance strip line is connected to a ground hole structure to form a signal isolation wall to improve isolation.

[0059] Optionally, the high impedance microstrip line is selected to have a width of 6um~10um. The selection of this width range is intended to balance the transmission efficiency of the signal with the impedance matching requirements of the circuit, ensuring that the attenuation of the signal during transmission is minimized while reducing reflection and interference.

[0060] Optionally, the high impedance microstrip line has a width of 6um, 7um, 8um, 9um or 10um, so that the most suitable width can be selected according to the requirements of the actual circuit, such as the frequency and power of the signal and the required impedance matching degree.

[0061] In a possible implementation, preferably, the high impedance microstrip line is selected to have a width of 8 um, so as to balance the signal transmission efficiency and the impedance matching requirements of the circuit while avoiding excessive chip size.

[0062] In a possible implementation, the small high-isolation up-conversion chip has a size of 3mm*2mm and uses a 5.0mm×5.0mm×1.1mm surface-mount leadless ceramic tube package, and the dust and water resistance level of the package is greater than or equal to IP66.

[0063] In this embodiment, the indicators of the small high isolation up-conversion chip are as follows: RF output frequency range: 24GHz ~ 29GHz; LO input frequency range: 10GHz ~ 12GHz, integrated 2-time frequency multiplier; Frequency conversion gain: 20dB (typical value); Output P1dB: 25dBm; Output IP3:33dBm; 6*IF spurious suppression: 75 dBc; 2*LO to RF isolation: <-5dBc; 2*LO to IF leakage: <-30dBc; 2*LO to IF leakage: <-30dBc; LO to IF leakage: <-30dBc.

[0064] Specifically, the parameters of a Ka-band miniaturized high-isolation up-conversion multifunctional chip in this embodiment are shown in Table 1: Table 1

[0065] After tape-out, the assembly test is performed. Figure 8~Figure 14 The package test curves are shown. Figure 8 It can be seen that the return loss of the intermediate frequency port of this embodiment performs well and meets the design requirements. Fig. 9 It can be seen that the small signal gain of this embodiment meets the design requirements. Fig.10 It can be seen that the fixed intermediate frequency is 4.1GHz, and the output P-1dB compression point meets the design requirements at the RF frequency of 24-29GHz; Fig.11 It can be seen that the fixed intermediate frequency is 4.1GHz, and the output OIP3 meets the design requirements at the RF frequency of 24-29GHz; Fig.12 It can be seen that the 6*IF to RF isolation is 5dBc; Fig.13 It can be seen that the 2*LO to RF isolation is greater than 30dBc; Fig.14 It can be seen that the 2*LO to IF isolation is greater than 30dBc.

[0066] An embodiment of the present application provides a frequency converter, comprising a small-sized high-isolation up-conversion chip in any possible embodiment as described above.

[0067] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A small high-isolation up-conversion chip, characterized in that: include: A local oscillator link, a mixing link and a radio frequency link connected in sequence; Wherein, the local oscillator link comprises: a five-stage single-power supply amplifier circuit and a frequency multiplier; the five-stage single-power supply amplifier circuit comprises: a first amplifier with two stages of single power supplies and a second amplifier with three stages of single power supplies; the first amplifier, the frequency multiplier and the second amplifier are connected in sequence; The radio frequency link includes a four-stage dual-power supply amplifier circuit; Part of the circuit elements of the second amplifier, the first amplifier and the frequency multiplier are arranged in the horizontal branch below the chip; the remaining circuit elements of the second amplifier and the mixing link are arranged in the horizontal branch in the middle of the chip; and the radio frequency link is arranged in the horizontal branch above the chip.

2. The small high isolation up-conversion chip according to claim 1, characterized in that: The frequency multiplier is a 2-fold frequency multiplier; The frequency multiplier comprises two diodes connected in reverse parallel; the output ends of the diodes are connected to a balun to output a combined signal.

3. The small high isolation up-conversion chip according to claim 2, characterized in that: Also includes: Impedance matching circuit; The impedance matching circuit includes a series inductor and a parallel capacitor; The series inductor is connected to the output end of the diode and the balun terminal; the parallel capacitor is grounded.

4. The small high isolation up-conversion chip according to claim 1, characterized in that: Also includes: a first impedance matching circuit; The first amplifier and the second amplifier include two-stage transistors and three-stage transistors, respectively; The first impedance matching circuit is connected to the third-stage transistor of the second amplifier and is used for performing optimal output power impedance matching of the transistor.

5. The small high isolation up-conversion chip according to claim 4, characterized in that: The first impedance matching circuit includes: a series capacitor, a grounding capacitor, a parallel capacitor and a parallel resistor; One end of the parallel capacitor and the parallel resistor is connected to the series capacitor, and the other end is grounded.

6. The small high isolation up-conversion chip according to claim 1, characterized in that: The mixing link includes an intermediate frequency signal input terminal, a radio frequency link connection terminal and a local oscillator link connection terminal; The intermediate frequency signal is introduced by the PAD, connected to the balun through a low-pass structure, and then input to the intermediate frequency signal input terminal; wherein the low-pass structure is composed of a series inductor and a parallel capacitor.

7. The small high isolation up-conversion chip according to claim 1, characterized in that: The mixing link adopts a double-balanced mixing topology structure; The mixing core of the mixing link uses a diode with a size of 2 gate fingers, a gate width of 30 um, and a total gate width of 60 um.

8. The small high isolation up-conversion chip according to claim 1, characterized in that: Also included is a second impedance matching circuit connected between the frequency mixing link and the radio frequency link; The second impedance matching circuit includes: a first capacitor and a second capacitor connected in series, a parallel inductor connected between the first capacitor and the second capacitor, and a grounding resistor connected to the parallel inductor.

9. The small high isolation up-conversion chip according to claim 1, characterized in that: Multiple on-chip ground vias are added between signals of different paths, and the on-chip ground vias are connected in sequence.

10. A frequency converter, characterized in that: The invention comprises the small-sized high-isolation up-conversion chip as described in any one of claims 1 to 9.

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