Filter, forming method thereof and electronic equipment

Abstract

The invention discloses a filter and a forming method thereof, and electronic equipment. The filter comprises a protective layer, the bonding pad is located in the interconnection window, the side wall of the bonding pad is aligned with the side wall of the interconnection window, and the bonding pad is electrically connected with the connecting part; the side wall of the bonding pad is aligned with the side wall of the interconnection window, and the interconnection window is located in the protection layer, so that the bonding pad and the interconnection window can be formed only by adopting one photomask, and compared with the scheme that the bonding pad and the interconnection window are respectively formed by adopting two photomasks, the number of the photomasks is reduced, the production cost is correspondingly reduced, and the production efficiency is improved. The alignment precision between the interconnection window and the bonding pad is also improved; besides, the protective layer covers the interdigital transducer, the connecting part and the substrate, so that the protective layer can protect the interdigital transducer, the connecting part and the substrate, the probability that the interdigital transducer, the connecting part or the substrate is damaged in the process manufacturing process is reduced, and the performance of the filter is further improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a filter and a method for forming the filter, and an electronic device. Background Art

[0002] The RF front-end chips of wireless communication equipment include power amplifiers, antenna switches, RF filters, multiplexers, and low-noise amplifiers, etc. Among them, RF filters include piezoelectric surface acoustic wave (SAW) filters, piezoelectric bulk acoustic wave (BAW) filters, micro-electro-mechanical system (MEMS) filters, integrated passive devices (IPD) filters, etc.

[0003] The quality factor (Q value) of SAW filters is relatively high, and SAW filters are used to make RF filters with low insertion loss and high out-of-band suppression. SAW filters are currently the most widely used filters in wireless communication devices. Highly reliable SAW filters can extend the service life of electronic devices and expand their scope of use.

[0004] Currently, there are still many problems in the formation method of SAW filters. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a filter and a method for forming the same, and an electronic device, which can reduce the use of photomasks and production costs while improving the performance of the filter.

[0006] To solve the above problems, an embodiment of the present invention provides a method for forming a filter, comprising: providing a substrate, on which an IDT and a connecting portion located on the side of the IDT are formed, the connecting portion being electrically connected to the IDT; forming a protective material layer on the substrate, the protective material layer covering the IDT, the connecting portion and the substrate; forming a mask layer having a mask opening on the protective material layer, the projection of the mask opening on the connecting portion covering a portion of the surface of the connecting portion; removing the protective material layer at the bottom of the mask opening using the mask layer as a mask, forming an interconnection window in the protective material layer, and the remaining protective material layer serving as a protective layer; forming a solder pad in the mask opening, the solder pad being also located in the interconnection window, the sidewall of the solder pad being aligned with the sidewall of the interconnection window, and the solder pad being electrically connected to the connecting portion.

[0007] Correspondingly, an embodiment of the present invention also provides a filter, comprising: a substrate; an IDT located on the substrate; a connecting portion located on the substrate at the side of the IDT, the connecting portion being electrically connected to the IDT; a protective layer covering the IDT, the connecting portion and the substrate, the protective layer having an interconnection window therein, the interconnection window exposing a portion of the surface of the connecting portion; a soldering pad located in the interconnection window, the side walls of the soldering pad being aligned with the side walls of the interconnection window, and the soldering pad being electrically connected to the connecting portion.

[0008] Correspondingly, the present invention further provides an electronic device, comprising the filter described in any embodiment of the present invention.

[0009] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages: In a method for forming a filter provided in an embodiment of the present invention, a protective material layer covering the interdigital transducer, the connecting portion and the substrate is formed on a substrate; a mask layer having a mask opening is formed on the protective material layer, the projection of the mask opening on the connecting portion covers a portion of the surface of the connecting portion; the protective material layer at the bottom of the mask opening is removed using the mask layer as a mask, an interconnection window is formed in the protective material layer, and the remaining protective material layer serves as a protective layer; a solder pad is formed in the mask opening, the solder pad is also located in the interconnection window, the sidewall of the solder pad is aligned with the sidewall of the interconnection window, and the solder pad is electrically connected to the connecting portion; in this embodiment, in the process of forming the solder pad, the mask layer is used as a mask to remove the A protective material layer is formed at the bottom of the mask opening, an interconnection window is formed in the protective material layer, and then a solder pad is formed in the mask opening, that is, in this embodiment, only one mask is used to form the solder pad and the interconnection window. Compared with the solution of using two masks to form the solder pad and the interconnection window respectively, the number of masks is reduced, the production cost is correspondingly reduced, and the alignment accuracy between the interconnection window and the solder pad is improved, which is beneficial to improving the performance of the filter; in addition, since the protective material layer is formed first and then the solder pad is formed, the protective material layer can protect the interdigital transducer, the connecting part and the substrate, which is beneficial to reduce the probability of the interdigital transducer, the connecting part or the substrate being damaged in the subsequent process manufacturing, thereby improving the performance of the filter.

[0010] The embodiment of the present invention further provides a filter, comprising: a substrate; an IDT located on the substrate; a connecting portion located on the substrate at the side of the IDT, the connecting portion being electrically connected to the IDT; a protective layer covering the IDT, the connecting portion and the substrate, the protective layer having an interconnection window, the interconnection window exposing a portion of the surface of the connecting portion; a pad located in the interconnection window, the side wall of the pad being aligned with the side wall of the interconnection window, and the pad being electrically connected to the connecting portion; in this embodiment, since the side wall of the pad is aligned with the side wall of the interconnection window, and the interconnection window is located on the protective layer, the side wall of the pad is aligned with the side wall of the interconnection window, and the interconnection window is located on the protective layer. In the layer, that is, in this embodiment, only one mask is used to form the pad and the interconnection window. Compared with the solution of using two masks to form the pad and the interconnection window respectively, the number of masks is reduced, and the production cost is correspondingly reduced. Moreover, this also improves the alignment accuracy between the interconnection window and the pad, which is beneficial to improving the performance of the filter. In addition, since the protective layer covers the interdigital transducer, the connecting part and the substrate, the protective layer can protect the interdigital transducer, the connecting part and the substrate, which is beneficial to reduce the probability of the interdigital transducer, the connecting part or the substrate being damaged during the manufacturing process, thereby improving the performance of the filter. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a schematic diagram of the structure of a filter; Figure 2 It is a structural diagram of another filter; Figures 3 to 9 is a schematic structural diagram corresponding to each step in the first embodiment of the method for forming a filter of the present invention; Figures 10 to 18 is a schematic structural diagram corresponding to each step in the second embodiment of the method for forming a filter of the present invention; Fig.19 is a schematic structural diagram of a first embodiment of a filter of the present invention; Fig. 20 It is a schematic structural diagram of the second embodiment of the filter of the present invention. DETAILED DESCRIPTION

[0012] At present, there are still many problems in the method of forming SAW filters. Now, combined with a structural schematic diagram of a filter, the reasons why the process of forming the filter needs to be improved are analyzed.

[0013] Figure 1 It is a structural diagram of a filter.

[0014] refer to Figure 1The filter comprises: a substrate 10; an IDT 11, located on the substrate 10; a connecting portion 12, located on the substrate 10 at the side of the IDT 11, the connecting portion 12 being electrically connected to the IDT 11; a pad 13, located on a partial surface of the connecting portion 12, the pad 13 being electrically connected to the connecting portion 12; a frequency modulation layer 14, covering the IDT 11, the pad 13, the substrate 10 and the surface of the connecting portion 12 exposed by the pad 13, the frequency modulation layer 14 having a first interconnection window 16, the first interconnection window 16 exposing a partial surface of the pad 13.

[0015] It should be noted that the pad 13 is located on a partial surface of the connecting portion 12. The process of forming the pad 13 requires the use of a photomask. In order to achieve electrical connection between the pad 13 and the external circuit, another photomask is required to form the first interconnection window 16 in the frequency modulation layer 14. This means that in the manufacturing process, two different photomasks are used to form the pad 13 and the first interconnection window 16 respectively.

[0016] Figure 2 This is a schematic diagram of the structure of another filter.

[0017] The similarities between the structure of the second filter and the structure of the first filter are not repeated here. The difference between the structure of the second filter and the structure of the first filter lies in that: the passivation layer 25 is located between the frequency modulation layer 24 and the interdigital transducer 21, and between the frequency modulation layer 24 and the connecting part 22, and the passivation layer 25 has a second interconnection window 27, and the second interconnection window 27 exposes a portion of the surface of the connecting part 22.

[0018] It should be noted that, since the passivation layer 25 is located between the frequency modulation layer 24 and the IDT 21, and between the frequency modulation layer 24 and the connecting portion 22, in order to protect the IDT 21, in order to achieve electrical connection between the connecting portion 22 and the pad 23, a photomask is required to form a second interconnection window 27 in the passivation layer 25. At the same time, in order to achieve electrical connection between the pad 23 and the external circuit, another photomask is required to form a first interconnection window 26 in the frequency modulation layer 24. This means that in the manufacturing process, three photomasks are used to form the first interconnection window 26, the second interconnection window 27 and the pad 23, respectively.

[0019] In summary, in the prior art, the above two types of filters both require the use of multiple masks to form interconnection windows and pads, which increases the number of photolithography times and increases the process cost; in addition, due to the limitations of the photolithography process conditions, overlay errors are easily generated in the process of forming pads and interconnection windows, thereby reducing the alignment accuracy between the pads and the interconnection windows, and further affecting the performance of the filter.

[0020] In order to solve the above technical problems, an embodiment of the present invention provides a method for forming a filter, comprising: providing a substrate, on which an IDT and a connecting portion located on the side of the IDT are formed, the connecting portion being electrically connected to the IDT; forming a protective material layer on the substrate, the protective material layer covering the IDT, the connecting portion and the substrate; forming a mask layer having a mask opening on the protective material layer, the projection of the mask opening on the connecting portion covering a portion of the surface of the connecting portion; removing the protective material layer at the bottom of the mask opening using the mask layer as a mask, forming an interconnection window in the protective material layer, and the remaining protective material layer serving as a protective layer; forming a solder pad in the mask opening, the solder pad being also located in the interconnection window, the side wall of the solder pad being aligned with the side wall of the interconnection window, and the solder pad being electrically connected to the connecting portion.

[0021] In the scheme disclosed in the embodiment of the present invention, in the process of forming the pad, the protective material layer at the bottom of the mask opening is removed using the mask layer as a mask, an interconnection window is formed in the protective material layer, and then a pad is formed in the mask opening, that is, in this embodiment, only one mask is used to form the pad and the interconnection window. Compared with the scheme of using two masks to form the pad and the interconnection window respectively, the number of masks is reduced, the production cost is correspondingly reduced, and the alignment accuracy between the interconnection window and the pad is improved, which is beneficial to improving the performance of the filter; in addition, since the protective material layer is formed first and then the pad is formed, the protective material layer can protect the interdigital transducer, the connecting part and the substrate, which is beneficial to reduce the probability of the interdigital transducer, the connecting part or the substrate being damaged in the subsequent process manufacturing, thereby improving the performance of the filter.

[0022] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0023] Figures 3 to 9 It is a schematic structural diagram corresponding to each step in the first embodiment of the method for forming a filter of the present invention.

[0024] refer to Figure 3 , providing a substrate 100 , on which an IDT 101 and a connecting portion 102 located at a side of the IDT 101 are formed, wherein the connecting portion 102 is electrically connected to the IDT 101 .

[0025] It should be noted that the electrical connection between the connecting portion 102 and the IDT 101 is not illustrated in the figure. In actual design, the connecting portion 102 and the IDT 101 are electrically connected in other areas of the filter.

[0026] The substrate 100 is used to provide a process platform for the subsequent formation of a surface acoustic wave (SAW) filter. The SAW filter is a special filtering device made by using the piezoelectric effect and the physical characteristics of surface acoustic wave propagation. In the SAW filter, the signal undergoes two conversions of electricity-acoustic-electricity to achieve frequency selection characteristics. The SAW filter has the advantages of high operating frequency, simple manufacturing process, low manufacturing cost, and high consistency of frequency characteristics. Therefore, it is widely used in various electronic devices.

[0027] In this embodiment, the substrate 100 is a piezoelectric substrate, so that the subsequent surface acoustic wave filter structure can perform filtering processing by using the piezoelectric effect.

[0028] The material of the substrate 100 includes lithium niobate (LiNbO3), lithium tantalate (LiTaO3), quartz or piezoelectric ceramics. As an example, the material of the substrate 100 is lithium tantalate.

[0029] In other embodiments, the substrate may also be a piezoelectric on insulator (POI), which includes a piezoelectric material layer, a low acoustic velocity layer, a high acoustic velocity layer, and a high-resistance silicon substrate stacked in sequence from top to bottom. The material of the piezoelectric material layer includes lithium tantalate or lithium niobate, the material of the low acoustic velocity layer includes silicon oxide, glass, silicon oxynitride or tantalum oxide, and the material of the high acoustic velocity layer includes polysilicon, silicon nitride, aluminum oxide, aluminum nitride or silicon carbide. As an example, the material of the piezoelectric material layer is lithium tantalate, the material of the low acoustic velocity layer is silicon oxide, and the material of the high acoustic velocity layer is polysilicon.

[0030] The interdigital transducers 101 (IDT) are used to realize the mutual conversion between electrical signals and acoustic signals, so that the surface acoustic wave filter performs filtering processing on the signal. In this embodiment, the filter formed is a SAW filter, so the interdigital transducer 101 is a corresponding interdigital electrode structure, and the interdigital transducer 101 includes a plurality of electrode fingers. Specifically, the interdigital transducer 101 is a metal interdigital transducer.

[0031] The material of the IDT 101 includes one or more of Mo, Al, Pt, W, Au, Al, Cr, Cu, Ni and Ag. In this embodiment, the material of the IDT 101 is aluminum. Specifically, the IDT 101 is formed by evaporating a metal film on the substrate 100 and patterning the metal film through photolithography and etching processes.

[0032] The connection portion 102 is used to realize electrical connection between the IDT 101 and the pad, thereby realizing electrical connection between the IDT 101 and an external circuit structure. Alternatively, the connection portion 102 can also be used to realize electrical connection between IDTs 101 in different regions.

[0033] In this embodiment, the connecting portion 102 and the IDT 101 are formed in the same step, which is beneficial to reducing the process steps and the process cost. Therefore, in this embodiment, the material of the connecting portion 102 is the same as that of the IDT 101.

[0034] In this embodiment, the connecting portion 102 includes a first electrode 103 and second electrodes 104 located on both sides of the first electrode 103 . The first electrode 103 and the second electrode 104 are electrically connected to at least one of the IDTs 101 , respectively.

[0035] The second electrode 104 is used to realize electrical connection between the IDTs 101 in different regions.

[0036] Specifically, the connection portion 102 that needs to be electrically connected to other connection portions 102 through a pad serves as the second electrode 104 .

[0037] The connecting portion 102 between the adjacent second electrodes 104 arranged at intervals serves as the first electrode 103 .

[0038] The first electrode 103 is used to realize electrical connection between the IDTs 101 in different regions; or, the first electrode 103 is used to electrically connect to one IDT 101 .

[0039] In this embodiment, the surface acoustic wave filter is a longitudinally coupled double-mode resonator type (Double Mode SAW, DMS) filter. The DMS filter utilizes the dual-mode characteristics of the surface acoustic wave and flexibly designs the stopband suppression and bandwidth indicators of the filter by adding a reflector between two interdigital transducers (IDTs). Due to its structural characteristics, the DMS filter can provide performance similar to that of the Bulk Acoustic Wave (BAW) filter at low frequencies with low losses; in addition, in the design of the DMS filter, by changing the key parameters of the circuit topology structure and introducing new transmission zeros, the out-of-band suppression characteristics in the high frequency band can be improved. Therefore, it is widely used in various electronic devices.

[0040] In other embodiments, according to actual design requirements, the surface acoustic wave filter may also be other types of filters.

[0041] In this embodiment, the connecting portion 102 further includes a third electrode 105 , and the third electrode 105 is electrically connected to at least one of the IDTs 101 .

[0042] The third electrode 105 is used as an input terminal or an output terminal of the IDT 101 .

[0043] refer to Figure 4 , a protective material layer 106 is formed on the substrate 100 , and the protective material layer 106 covers the IDT 101 , the connecting portion 102 and the substrate 100 .

[0044] The protective material layer 106 is used to form a protective layer. Moreover, the protective material layer 106 covering the IDT 101, the connecting portion 102 and the substrate 100 is first formed, so that the protective material layer 106 can protect the IDT 101, the connecting portion 102 and the substrate 100 in subsequent processes.

[0045] In this embodiment, the process of forming the protective material layer 106 on the substrate 100 includes a physical vapor deposition process.

[0046] It should be noted that the physical vapor deposition process has the characteristic of high film deposition density. Therefore, the protective material layer 106 formed by the physical vapor deposition process has a higher density, which is conducive to improving the density of the protective layer formed subsequently.

[0047] In the step of forming the protective material layer 106 , the protective material layer 106 at least includes a frequency modulation layer 107 .

[0048] In this embodiment, the protective material layer 106 is a single layer.

[0049] Specifically, the protective material layer 106 is a frequency modulation layer 107 .

[0050] The frequency modulation layer 107 can not only protect the IDT 101, the connection part 102 and the substrate 100 in the subsequent process, but also can be used to adjust the working frequency of the IDT 101. Specifically, the working frequency of the IDT 101 can be adjusted by changing the thickness of the frequency modulation layer 107.

[0051] In other embodiments, the protective material layer may be a laminate.

[0052] In this embodiment, in the step of forming the protective material layer 106 on the substrate 100 , the material of the frequency modulation layer 107 includes silicon oxide.

[0053] It should be noted that silicon oxide has relatively stable physical and chemical properties. In subsequent process steps, silicon oxide is not easily removed and can play an effective protective role.

[0054] In this embodiment, the thickness of the frequency modulation layer 107 should not be too large or too small. If the thickness of the frequency modulation layer 107 is too large or too small, it is easy to affect the frequency modulation layer 107's adjustment effect on the working frequency of the interdigital transducer 101, and accordingly it is easy to cause the working frequency of the interdigital transducer 101 after frequency modulation to still not meet the actual design requirements. Therefore, in this embodiment, the thickness of the frequency modulation layer 107 is 20 angstroms to 1000 angstroms.

[0055] refer to Figure 5 After forming the protective material layer 106 on the substrate 100 and before forming a mask layer having a mask opening on the protective material layer 106 , the method further includes: forming a dielectric layer 109 on the protective material layer 106 , wherein the dielectric layer 109 exposes the protective material layer 106 located on a portion of the surface of the connecting portion 102 .

[0056] The dielectric layer 109 has insulating properties, which is beneficial to further improve the electrical isolation effect between the connection portion 102 covered by the dielectric layer 109 and the pad.

[0057] The material of the dielectric layer 109 includes one or more of polyimide (PI), silicon oxide, silicon nitride, aluminum oxide and aluminum nitride. Polyimide, silicon oxide, silicon nitride, aluminum oxide and aluminum nitride all have good insulation properties. As an example, the material of the dielectric layer 109 is polyimide.

[0058] In this embodiment, in the step of forming the dielectric layer 109 on the protective material layer 106 , the dielectric layer 109 crosses and covers the protective material layer 106 on the first electrode 103 and exposes at least a portion of the surface of the protective material layer 106 on the second electrode 104 .

[0059] It should be noted that the dielectric layer 109 exposes part of the surface of the protective material layer 106 on the second electrode 104 , which is beneficial for the subsequent removal of the protective material layer 106 on the second electrode 104 , thereby achieving electrical connection between the pad and the second electrode 104 .

[0060] The dielectric layer 109 crosses and covers the protective material layer 106 located on the first electrode 103 , which is beneficial to improving the electrical isolation effect between the first electrode 103 and the pad.

[0061] As an example, the process of forming the dielectric layer 109 includes a spin coating process. In other embodiments, other suitable deposition processes may be used to form the dielectric layer.

[0062] refer to Figure 6 A mask layer 111 having a mask opening 110 is formed on the protective material layer 106 , and a projection of the mask opening 110 on the connecting portion 102 covers a portion of the surface of the connecting portion 102 .

[0063] The mask opening 110 is used to define the position and shape of the subsequent pad, and is also convenient for removing the protective material layer 106 at the bottom of the mask opening 110 along the mask opening 110 .

[0064] The projection of the mask opening 110 on the connecting portion 102 covers a portion of the surface of the connecting portion 102 , so that the pad can be electrically connected to the connecting portion 102 .

[0065] The mask layer 111 is used as a mask for forming a protection layer and a pad.

[0066] In this embodiment, the material of the mask layer 111 includes photoresist. Photoresist has high resolution, so the opening size of the mask opening 110 can be accurately controlled; at the same time, photoresist is easy to remove, thereby reducing process complexity and improving production efficiency. In other embodiments, the mask layer can also be made of other materials that can serve as an etching mask and are easy to remove.

[0067] In this embodiment, in the step of forming a mask layer 111 having a mask opening 110 on the protective material layer 106, the mask opening 110 exposes at least a portion of the surface of the dielectric layer 109 and a portion of the surface of the protective material layer 106 exposed by the dielectric layer 109, which is beneficial to increasing the process window for forming the pad, while also reducing the difficulty of subsequently removing the protective material layer 106 exposed by the dielectric layer 109.

[0068] In one embodiment, the dielectric layer 109 spans over the protective material layer 106 located on the first electrode 103. Therefore, in the step of forming a mask layer 111 having a mask opening 110 on the protective material layer 106, the mask opening 110 spans over the dielectric layer 109. The mask opening 110 exposes the dielectric layer 109 on the first electrode 103 and a portion of the surface of the protective material layer 106 on both sides of the first electrode 103, so that the second electrodes 104 on both sides of the first electrode 103 can be electrically connected using the same pad subsequently.

[0069] In this embodiment, the connecting portion 102 further includes a third electrode 105 , and therefore, the mask opening 110 also exposes at least a portion of the surface of the protective material layer 106 on the third electrode 105 .

[0070] In this embodiment, the materials of the dielectric layer 109 and the protective material layer 106 satisfy the following conditions: in the process of etching the protective material layer 106, since the dielectric layer 109 has a certain thickness, the dielectric layer 109 can protect the protective material layer 106 covered by it during the process of etching the protective material layer 106. As an example, the thickness of the dielectric layer 109 is 1.8 microns to 3 microns.

[0071] refer to Figure 7 The protective material layer 106 at the bottom of the mask opening 110 is removed using the mask layer 111 as a mask, an interconnection window 112 is formed in the protective material layer 106 , and the remaining protective material layer 106 serves as a protective layer 113 .

[0072] The interconnection window 112 is used to provide a space for realizing electrical connection between the pad and the connection portion 102 .

[0073] The protection layer 113 is used to protect the IDT 101 , the connecting portion 102 and the substrate 100 .

[0074] Specifically, in the step of removing the protective material layer 106 at the bottom of the mask opening 110 using the mask layer 111 as a mask, under the blocking effect of the dielectric layer 109, a first interconnection window 114 is formed in the protective material layer 106 on both sides of the first electrode 103, and the first interconnection window 114 exposes at least a portion of the surface of the second electrode 104.

[0075] The first interconnection window 114 exposes at least part of the surface of the second electrode 104 , so as to facilitate the subsequent electrical connection of the second electrodes 104 on both sides of the first electrode 103 through the pad, thereby achieving electrical connection between the IDTs 101 in different regions.

[0076] In this embodiment, in the step of removing the protective material layer 106 at the bottom of the mask opening 110 using the mask layer 111 as a mask, a second interconnection window 115 exposing at least a portion of the surface of the third electrode 105 is formed in the protective material layer 106 .

[0077] The second interconnection window 115 exposes at least a portion of the surface of the third electrode 105 , so as to facilitate subsequent electrical connection with the third electrode 105 through the pad, thereby outputting the electrical signal of the IDT 101 through the third electrode 105 .

[0078] In this embodiment, the process of removing the protective material layer 106 at the bottom of the mask opening 110 includes a dry etching process. The dry etching process has anisotropic etching characteristics, and the etching is more directional, which is conducive to improving the morphology and dimensional accuracy of the first interconnection window 114 and the second interconnection window 115. In other embodiments, a wet etching process can also be used to remove the protective material layer at the bottom of the mask opening.

[0079] refer to Figures 8 to 9 , forming a pad 116 (such as Fig. 9 As shown in FIG. 1 ), the pad 116 is also located in the interconnection window 112 , the sidewall of the pad 116 is aligned with the sidewall of the interconnection window 112 , and the pad 116 is electrically connected to the connection portion 102 .

[0080] It should be noted that in the process of forming the pad 116, the protective material layer 106 at the bottom of the mask opening 110 is removed by using the mask layer 111 as a mask, and the interconnection window 112 is formed in the protective material layer 106, and then the pad 116 is formed in the mask opening 110. That is, in this embodiment, only one mask is used to form the pad 116 and the interconnection window 112. Compared with the solution of using two masks to form the pad and the interconnection window respectively, the number of masks is reduced, the production cost is correspondingly reduced, and the interconnection window 112 is improved. The alignment accuracy between 12 and the pad 116 makes the side wall of the pad 116 aligned with the side wall of the interconnection window 112, which is beneficial to improving the performance of the filter; in addition, since the protective material layer 106 is formed first and then the pad 116 is formed, the protective material layer 106 can protect the IDT 101, the connecting portion 102 and the substrate 100, which is beneficial to reduce the probability of damage to the IDT 101, the connecting portion 102 or the substrate 100 in the subsequent manufacturing process, thereby improving the performance of the filter.

[0081] In this embodiment, the step of forming the pad 116 in the mask opening 110 includes: Figure 8 , forming a pad material layer 117 in the mask opening 110, and the pad material layer 117 also covers the mask layer 111; Fig. 9 , the mask layer 111 and the pad material layer 117 located on the top of the mask layer 111 are removed, and the remaining pad material layer 117 serves as the pad 116.

[0082] The pad material layer 117 is used to form the pad 116 .

[0083] In this embodiment, the process of removing the mask layer 111 and the pad material layer 117 located on the top of the mask layer 111 includes a lift-off process. The lift-off process omits the etching process step, which, on the one hand, helps to reduce production time and improve production efficiency; on the other hand, it is easy to avoid the problem of pattern distortion in the etching process, thereby improving the quality of the formed pad 116.

[0084] In this embodiment, in the step of forming a pad 116 in the mask opening 110 , the pad 116 includes a first pad 118 , which spans across the first electrode 103 and is electrically connected to the second electrodes 104 on both sides of the first electrode 103 via a first interconnection window 114 exposing the second electrode 104 .

[0085] The first pad 118 is used to realize electrical connection between the IDTs 101 in different regions.

[0086] In this embodiment, the dielectric layer 109 is located between the first pad 118 and the protection layer 113 .

[0087] It should be noted that, since the dielectric layer 109 has a certain thickness, it is beneficial for the first pad 118 and the connecting portion 102 to have a specific dielectric constant, thereby reducing the probability of parasitic capacitance between the first pad 118 and the connecting portion 102 .

[0088] In this embodiment, in the step of forming the pad 116 in the mask opening 110 , the pad 116 further includes a second pad 119 , and the second pad 119 is electrically connected to the third electrode 105 via a second interconnection window 115 exposing the third electrode 105 .

[0089] The second pad 119 is used to output or input the electrical signal of the IDT 101 through the third electrode 105 .

[0090] Figures 10 to 18 1 is a schematic diagram of the structure corresponding to each step in the second embodiment of the method for forming a filter of the present invention. Specifically, Fig.18 yes Fig.17 A partial enlarged view of area A.

[0091] The similarities between this embodiment and the first embodiment are not described in detail here. The difference between this embodiment and the first embodiment is that the substrate is a piezoelectric substrate on an insulator.

[0092] In this embodiment, reference Fig.10In the step of providing the substrate 200, the substrate 200 includes a chip region I' and a peripheral region II' surrounding the chip region I', and the IDT 201 and the connecting portion 202 are both located in the chip region I'.

[0093] The chip area I' refers to the device working area, and the peripheral area II' refers to the interconnection (bump) area for external power supply.

[0094] The substrate 200 is a piezoelectric substrate on an insulator, and the substrate 200 includes a piezoelectric material layer, a low acoustic velocity layer, a high acoustic velocity layer, and a high-resistance silicon substrate stacked in sequence from top to bottom. The material of the piezoelectric material layer includes lithium tantalate or lithium niobate, the material of the low acoustic velocity layer includes silicon oxide, glass, silicon oxynitride or tantalum oxide, and the material of the high acoustic velocity layer includes polysilicon, silicon nitride, aluminum oxide, aluminum nitride or silicon carbide. In this embodiment, the material of the piezoelectric material layer is lithium tantalate, the material of the low acoustic velocity layer is silicon oxide, and the material of the high acoustic velocity layer is polysilicon.

[0095] In this embodiment, an IDT 201 and a connecting portion 202 are formed on the substrate 200 . For a detailed description of the substrate 200 , the IDT 201 and the connecting portion 202 , please refer to the relevant contents of the first embodiment, which will not be described in detail here.

[0096] refer to Figure 11 to Figure 12 , forming a protective material layer 206 (such as Fig.12 As shown in FIG. 2 ), the protective material layer 206 covers the IDT 201 , the connecting portion 202 and the substrate 200 .

[0097] refer to Fig.11 In the step of forming the protective material layer 206 , the protective material layer 206 at least includes a frequency modulation layer 207 .

[0098] The frequency modulation layer 207 is used to adjust the operating frequency of the IDT 201. Specifically, by changing the thickness of the frequency modulation layer 207, the operating frequency of the IDT 201 can be adjusted.

[0099] In this embodiment, in the step of forming the protective material layer 206 on the substrate 200 , the material of the frequency modulation layer 207 includes silicon oxide.

[0100] It should be noted that silicon oxide has relatively stable physical and chemical properties. In subsequent process steps, silicon oxide is not easily removed and can play an effective protective role.

[0101] refer to Fig.12In the step of forming the protective material layer 206 , the protective material layer 206 further includes a passivation layer 208 , and the frequency modulation layer 207 is located on top of the passivation layer 208 .

[0102] The passivation layer 208 is used to protect the IDT 201, the connection part 202 and the substrate 200, so as to reduce the probability of the IDT 201, the connection part 202 or the substrate 200 being damaged in the subsequent manufacturing process, thereby improving the performance of the filter.

[0103] In this embodiment, in the step of forming the protective material layer 206 on the substrate 200 , the material of the passivation layer 208 includes silicon nitride or silicon nitride oxide.

[0104] It should be noted that silicon nitride and silicon oxynitride have relatively stable physical and chemical properties. In subsequent process steps, silicon nitride and silicon oxynitride are not easily removed and can play an effective protective role.

[0105] In this embodiment, when the protective material layer 206 includes a stack of a passivation layer 208 and a frequency modulation layer 207, the frequency modulation layer 207 is located on the top of the passivation layer 208. Therefore, before the frequency modulation layer 207 is formed, the passivation layer 208 can protect the substrate 200, the interdigital transducer 201 and the connecting portion 202, thereby further reducing the probability of the protective substrate 200, the interdigital transducer 201 and the connecting portion 202 being damaged.

[0106] In this embodiment, the step of forming the protective material layer 206 on the substrate 200 includes: Fig.11 , forming a passivation layer 208 on the substrate 200, wherein the passivation layer 208 covers the IDT 201, the connecting portion 202 and the substrate 200; Fig.12 A frequency modulation layer 207 is formed on the passivation layer 208 , and the frequency modulation layer 207 and the passivation layer 208 constitute a protective material layer 206 .

[0107] In this embodiment, the thickness of the frequency modulation layer 207 should not be too large or too small. If the thickness of the frequency modulation layer 207 is too large or too small, it is easy to affect the frequency modulation layer 207's adjustment effect on the working frequency of the interdigital transducer 201, and accordingly it is easy to make the working frequency of the interdigital transducer 201 after frequency modulation still fail to meet the actual design requirements. Therefore, in this embodiment, the thickness of the frequency modulation layer 207 is 20 angstroms to 1000 angstroms.

[0108] In this embodiment, the thickness of the passivation layer 208 should not be too large or too small. If the thickness of the passivation layer 208 is too large, the subsequent process of forming the interconnection window in the protective material layer 206 will easily increase the process time, thereby reducing the work efficiency and affecting the product performance (such as operating frequency and insertion loss); if the thickness of the passivation layer 208 is too small, it is easy for the passivation layer 208 to protect the interdigital transducer 201, the connecting part 202 and the substrate 200. Therefore, in this embodiment, the thickness of the passivation layer 208 is 30 angstroms to 200 angstroms.

[0109] refer to Fig.13 After forming the protective material layer 206 on the substrate 200 and before forming the dielectric layer on the protective material layer 206, the method further includes: removing the protective material layer 206 and a partial thickness of the substrate 200 in the peripheral area II', and retaining the protective material layer 206 in the chip area I'.

[0110] It should be noted that since the substrate 200 in this embodiment is a piezoelectric substrate on an insulator and the piezoelectric material layer is relatively thin, it is necessary to first remove the protective material layer 206 in the peripheral area II' and part of the thickness of the substrate 200 after forming the protective material layer 206 on the substrate 200. This is beneficial to reduce the probability of damage to the piezoelectric material layer in subsequent process manufacturing and is also beneficial to improving the performance of the filter.

[0111] Specifically, the substrate 200 includes a piezoelectric material layer, a low acoustic velocity layer, a high acoustic velocity layer, and a high-resistance silicon substrate stacked in sequence from top to bottom, so in the step of removing a portion of the thickness of the substrate 200 in the peripheral area II', at least the piezoelectric material layer in the peripheral area II' is removed. In a specific embodiment, the piezoelectric material layer, the low acoustic velocity layer, and the high acoustic velocity layer in the peripheral area II' are removed.

[0112] refer to Fig.14 After removing the protective material layer 206 of the peripheral area II' and a partial thickness of the substrate 200, a dielectric layer 209 is formed on the protective material layer 206, and the dielectric layer 209 exposes the protective material layer 206 located on a partial surface of the connecting portion 202. The dielectric layer 209 is used to electrically isolate the connecting portion 202 from the pad.

[0113] In this embodiment, in the step of forming the dielectric layer 209 , the dielectric layer 209 is also located on the substrate 200 in the peripheral region II′.

[0114] The material of the dielectric layer 209 includes one or more of polyimide, silicon oxide, silicon nitride, aluminum oxide and aluminum nitride. As an example, the material of the dielectric layer 209 is polyimide.

[0115] In this embodiment, since the connecting portion 202 includes a first electrode (not labeled) and second electrodes (not labeled) located on both sides of the first electrode, the dielectric layer 209 spans over and covers the protective material layer 206 located on the first electrode, and exposes at least a portion of the surface of the protective material layer 206 located on the second electrode.

[0116] It should be noted that since the process of forming the dielectric layer 209 adopts a spin coating process and the dielectric layer 209 is formed after removing the protective material layer 206 of the peripheral area II' and a partial thickness of the substrate 200, the dielectric layer 209 is also located on the substrate 200 of the peripheral area II'.

[0117] refer to Fig.15 After forming the dielectric layer 209 on the protective material layer 206 , a mask layer 211 having a mask opening 210 is formed on the protective material layer 206 , and the projection of the mask opening 210 on the connecting portion 202 covers a portion of the surface of the connecting portion 202 .

[0118] For a detailed description of the mask opening 210 and the mask layer 211 , please refer to the relevant contents of the first embodiment, which will not be described in detail here.

[0119] refer to Fig.16 The protective material layer 206 at the bottom of the mask opening 210 is removed using the mask layer 211 as a mask, an interconnection window 212 is formed in the protective material layer 206 , and the remaining protective material layer 206 serves as a protective layer 213 .

[0120] For a detailed description of the interconnection window 212 and the protection layer 213 , please refer to the relevant contents of the first embodiment, which will not be described in detail here.

[0121] refer to Figure 17 to Figure 18 A pad 216 is formed in the mask opening 210 , and the pad 216 is also located in the interconnection window 212 . The sidewall of the pad 216 is aligned with the sidewall of the interconnection window 212 , and the pad 216 is electrically connected to the connection portion 202 .

[0122] For a detailed description of the pad 216 and a method for forming the pad 216 , please refer to the relevant contents of the first embodiment, which will not be described in detail here.

[0123] Correspondingly, the present invention also provides a semiconductor structure. Fig.19 It is a schematic structural diagram of the first embodiment of the filter of the present invention.

[0124] refer to Fig.19The filter includes: a substrate 300; an IDT 301 located on the substrate 300; a connecting portion 302 located on the substrate 300 at the side of the IDT 301, the connecting portion 302 being electrically connected to the IDT 301; a protective layer 303 covering the IDT 301, the connecting portion 302 and the substrate 300, the protective layer 303 having an interconnection window 304, the interconnection window 304 exposing a portion of the surface of the connecting portion 302; a pad 305 located in the interconnection window 304, the sidewall of the pad 305 being aligned with the sidewall of the interconnection window 304, and the pad 305 being electrically connected to the connecting portion 302.

[0125] The substrate 300 is used to provide a process platform for forming a surface acoustic wave filter. SAW filter is a special filtering device made by using the piezoelectric effect and the physical characteristics of surface acoustic wave propagation. In the SAW filter, the signal undergoes two conversions of electricity-acoustic-electricity to achieve frequency selection characteristics. SAW filter has the advantages of high operating frequency, simple manufacturing process, low manufacturing cost, high consistency of frequency characteristics, etc., and therefore, is widely used in various electronic devices.

[0126] In this embodiment, the substrate 300 is a piezoelectric substrate, so that the subsequent surface acoustic wave filter structure can perform filtering processing by using the piezoelectric effect.

[0127] The material of the substrate 300 includes lithium niobate, lithium tantalate, quartz or piezoelectric ceramics. As an example, the material of the substrate 300 is lithium tantalate.

[0128] In other embodiments, the substrate may also be a piezoelectric substrate on an insulator, and the substrate includes a piezoelectric material layer, a low acoustic velocity layer, a high acoustic velocity layer, and a high-resistance silicon substrate stacked in sequence from top to bottom. The material of the piezoelectric material layer includes lithium tantalate or lithium niobate, the material of the low acoustic velocity layer includes silicon oxide, glass, silicon oxynitride or tantalum oxide, and the material of the high acoustic velocity layer includes polysilicon, silicon nitride, aluminum oxide, aluminum nitride or silicon carbide. As an example, the material of the piezoelectric material layer is lithium tantalate, the material of the low acoustic velocity layer is silicon oxide, and the material of the high acoustic velocity layer is polysilicon.

[0129] The interdigital transducer 301 is used to realize the mutual conversion between the electrical signal and the acoustic signal, so that the surface acoustic wave filter performs filtering processing on the signal. In this embodiment, the filter formed is a SAW filter, so the interdigital transducer 301 is a corresponding interdigital electrode structure, and the interdigital transducer 301 includes a plurality of electrode fingers. Specifically, the interdigital transducer 301 is a metal interdigital transducer.

[0130] The material of the IDT 301 includes one or more of Mo, Al, Pt, W, Au, Al, Cr, Cu, Ni and Ag. In this embodiment, the material of the IDT 301 is aluminum. Specifically, the IDT 301 is formed by evaporating a metal film on the substrate 300 and patterning the metal film through photolithography and etching processes.

[0131] The connection part 302 is used to realize the electrical connection between the IDT 301 and the pad 305, thereby realizing the electrical connection between the IDT 301 and the external circuit structure. Alternatively, the connection part 302 can also be used to realize the electrical connection between IDTs 301 in different regions.

[0132] In this embodiment, the connecting portion 302 and the IDT 301 are formed in the same step, which is beneficial to reducing the process steps and the process cost. Therefore, in this embodiment, the material of the connecting portion 302 is the same as that of the IDT 301.

[0133] In this embodiment, the connecting portion 302 includes a first electrode 306 and second electrodes 307 located on both sides of the first electrode 306 . The first electrode 306 and the second electrode 307 are electrically connected to at least one of the IDTs 301 , respectively.

[0134] The second electrode 307 is used to realize electrical connection between the IDTs 301 in different regions.

[0135] Specifically, the connection portion 302 electrically connected to other connection portions 302 through the pad 305 serves as the second electrode 307 .

[0136] The connecting portion 302 between the adjacent second electrodes 307 spaced apart serves as the first electrode 306 .

[0137] The first electrode 306 is used to realize electrical connection between the IDTs 301 in different regions; or, the first electrode 306 is used to electrically connect to one IDT 301 .

[0138] In this embodiment, the surface acoustic wave filter is a longitudinally coupled dual-mode resonator filter. The DMS filter utilizes the dual-mode characteristics of the surface acoustic wave and flexibly designs the stopband suppression and bandwidth indicators of the filter by adding a reflector between two interdigital transducers. Due to its structural characteristics, the DMS filter can provide performance similar to that of a bulk acoustic wave filter at low frequencies with low losses; in addition, in the design of the DMS filter, by changing the key parameters of the circuit topology and introducing new transmission zeros, the out-of-band suppression characteristics in the high frequency band can be improved, and therefore, it is widely used in various electronic devices.

[0139] In other embodiments, according to actual design requirements, the type of the surface acoustic wave filter may also be other types of filters.

[0140] In this embodiment, the connecting portion 302 further includes a third electrode 312 , and the third electrode 312 is electrically connected to at least one of the IDTs 301 .

[0141] The third electrode 312 is used as an input terminal or an output terminal of the IDT 301 .

[0142] The protection layer 303 is used to protect the IDT 301 , the connecting portion 302 and the substrate 300 .

[0143] In this embodiment, since the protective layer 303 covers the IDT 301, the connecting portion 302 and the substrate 300, the protective layer 303 can protect the IDT 301, the connecting portion 302 and the substrate 300, thereby helping to reduce the probability of the IDT 301, the connecting portion 302 or the substrate 300 being damaged during the manufacturing process, thereby improving the performance of the filter.

[0144] The protection layer 303 at least includes a frequency modulation layer 309 .

[0145] In this embodiment, the protection layer 303 is a single layer.

[0146] Specifically, the protection layer 303 is a frequency modulation layer 309 .

[0147] The frequency modulation layer 309 can not only protect the IDT 301, the connection part 302 and the substrate 300 in the subsequent process, but also can be used to adjust the working frequency of the IDT 301. Specifically, the working frequency of the IDT 301 can be adjusted by changing the thickness of the frequency modulation layer 309.

[0148] In other embodiments, the protective material layer may be a laminate.

[0149] In this embodiment, the thickness of the frequency modulation layer 309 should not be too large or too small. If the thickness of the frequency modulation layer 309 is too large or too small, it is easy to affect the frequency modulation layer 309's adjustment effect on the working frequency of the interdigital transducer 301, and accordingly it is easy to cause the working frequency of the interdigital transducer 301 after frequency modulation to still not meet the actual design requirements. Therefore, in this embodiment, the thickness of the frequency modulation layer 309 is 20 angstroms to 1000 angstroms.

[0150] In this embodiment, the material of the frequency modulation layer 309 includes silicon oxide.

[0151] It should be noted that silicon oxide has relatively stable physical and chemical properties. In subsequent process steps, silicon oxide is not easily removed and can play an effective protective role.

[0152] In this embodiment, the interconnection window 304 includes first interconnection windows 310 located on both sides of the first electrode 306 , and the first interconnection windows 310 expose at least a portion of the surface of the second electrode 307 .

[0153] The interconnection window 304 is used to provide a space for realizing electrical connection between the pad 305 and the connection portion 302 .

[0154] The first interconnection window 310 exposes at least part of the surface of the second electrode 307 , so as to facilitate electrical connection of the second electrodes 307 on both sides of the first electrode 306 through the pad 305 , thereby achieving electrical connection between the IDTs 301 in different regions.

[0155] In this embodiment, the interconnection window 304 further includes a second interconnection window 311 exposing at least a portion of the surface of the third electrode 312 .

[0156] The second interconnection window 311 exposes at least a portion of the surface of the third electrode 312 , so as to facilitate electrical connection with the third electrode 312 through the pad 305 , thereby outputting the electrical signal of the IDT 301 through the third electrode 312 .

[0157] The pad 305 is used to achieve electrical connection with the connecting portion 302 .

[0158] It should be noted that, since the side wall of the pad 305 is aligned with the side wall of the interconnection window 304, and the interconnection window 304 is located in the protective layer 303, that is, the present embodiment only uses one mask to form the pad 305 and the interconnection window 304. Compared with the solution of using two masks to form the pad and the interconnection window respectively, the number of masks is reduced, and the production cost is correspondingly reduced. Moreover, this also improves the alignment accuracy between the interconnection window 304 and the pad 305, which is beneficial to improving the performance of the filter.

[0159] In this embodiment, the pad 305 includes a first pad 313 , which spans across the first electrode 306 and is electrically connected to the second electrodes 307 on both sides of the first electrode 306 via a first interconnection window 310 exposing the second electrode 307 .

[0160] The first pad 313 is used to realize electrical connection between the IDTs 301 in different regions.

[0161] In this embodiment, the pad 305 further includes a second pad 314 , and the second pad 314 is electrically connected to the third electrode 312 via a second interconnection window 311 exposing the third electrode 312 .

[0162] The second pad 314 is used to output or input the electrical signal of the IDT 301 through the third electrode 312 .

[0163] In this embodiment, the filter further includes: a dielectric layer 315 located between the protection layer 303 and the pad 305 .

[0164] The dielectric layer 315 has insulating properties, which is beneficial to improving the electrical isolation effect between the connection portion 302 and the pad 305 covered by the dielectric layer 315 .

[0165] The material of the dielectric layer 315 includes one or more of polyimide, silicon oxide, silicon nitride, aluminum oxide and aluminum nitride. Polyimide, silicon oxide, silicon nitride, aluminum oxide and aluminum nitride all have good insulation properties. As an example, the material of the dielectric layer 315 is polyimide.

[0166] In this embodiment, the dielectric layer 315 crosses and covers the protection layer 303 located on the first electrode 306 , and exposes at least a portion of the surface of the second electrode 307 .

[0167] It should be noted that the dielectric layer 315 spans over and covers the protection layer 303 located on the first electrode 306 , which is beneficial to improving the electrical isolation effect between the first electrode 306 and the pad 305 .

[0168] In this embodiment, the dielectric layer 315 is located between the first pad 313 and the protection layer 303 .

[0169] It should be noted that, since the dielectric layer 315 has a certain thickness, it is beneficial to have a specific dielectric constant between the first pad 313 and the connecting portion 302, thereby reducing the probability of generating parasitic capacitance between the first pad 313 and the connecting portion 302. As an example, the thickness of the dielectric layer 315 is 1.8 microns to 3 microns.

[0170] Fig. 20 It is a schematic structural diagram of the second embodiment of the filter of the present invention.

[0171] The similarities between this embodiment and the above embodiment are not described in detail here. The difference between this embodiment and the above embodiment is that the substrate is a piezoelectric substrate on an insulator.

[0172] In this embodiment, the substrate 500 includes a chip region i and a peripheral region ii surrounding the chip region i. The top of the substrate 500 in the peripheral region ii is lower than the top of the substrate 500 in the chip region i.

[0173] Chip area i refers to the device working area, and peripheral area ii refers to the interconnection area, which is used for external power supply.

[0174] Correspondingly, the IDT 501 , the connecting portion 502 and the protection layer 503 are all located in the chip region i.

[0175] The substrate 500 is a piezoelectric substrate on an insulator, and the substrate 500 includes a piezoelectric material layer, a low acoustic velocity layer, a high acoustic velocity layer, and a high-resistance silicon substrate stacked in sequence from top to bottom. The material of the piezoelectric material layer includes lithium tantalate or lithium niobate, the material of the low acoustic velocity layer includes silicon oxide, glass, silicon oxynitride or tantalum oxide, and the material of the high acoustic velocity layer includes polysilicon, silicon nitride, aluminum oxide, aluminum nitride or silicon carbide. In this embodiment, the material of the piezoelectric material layer is lithium tantalate, the material of the low acoustic velocity layer is silicon oxide, and the material of the high acoustic velocity layer is polysilicon.

[0176] It should be noted that since the substrate 500 in this embodiment is a piezoelectric substrate on an insulator and the piezoelectric material layer is relatively thin, the top of the substrate 500 in the peripheral area ii is lower than the top of the substrate 500 in the chip area i, that is, there is no piezoelectric material layer in the peripheral area ii, which is beneficial to reduce the probability of damage to the piezoelectric material layer in subsequent process manufacturing and is also beneficial to improving the performance of the filter.

[0177] Specifically, in this embodiment, the substrate 500 of the chip area i includes a piezoelectric material layer, a low acoustic velocity layer, a high acoustic velocity layer and a high-resistance silicon substrate stacked in sequence from top to bottom; the substrate 500 of the peripheral area ii is a high-resistance silicon substrate.

[0178] In this embodiment, the protection layer 503 at least includes a frequency modulation layer 509 .

[0179] The frequency modulation layer 509 is used to adjust the operating frequency of the IDT 501. Specifically, by changing the thickness of the frequency modulation layer 509, the operating frequency of the IDT 501 can be adjusted.

[0180] In this embodiment, the protection layer 503 further includes a passivation layer 508 , and the frequency modulation layer 509 is located on the top of the passivation layer 508 .

[0181] In this embodiment, the thickness of the frequency modulation layer 509 should not be too large or too small. If the thickness of the frequency modulation layer 509 is too large or too small, it is easy to affect the frequency modulation layer 509's regulating effect on the working frequency of the interdigital transducer 501, and accordingly it is easy to make the working frequency of the interdigital transducer 501 after frequency modulation still fail to meet the actual design requirements. Therefore, in this embodiment, the thickness of the frequency modulation layer 509 is 20 angstroms to 1000 angstroms.

[0182] In this embodiment, the material of the frequency modulation layer 509 includes silicon oxide.

[0183] It should be noted that silicon oxide has relatively stable physical and chemical properties. In subsequent process steps, silicon oxide is not easily removed and can play an effective protective role.

[0184] The passivation layer 508 is used to protect the IDT 501, the connection portion 502 and the substrate 500, thereby reducing the probability of the IDT 501, the connection portion 502 or the substrate 500 being damaged in subsequent manufacturing processes, thereby improving the performance of the filter.

[0185] In this embodiment, the frequency modulation layer 509 is located on the top of the passivation layer 508. Therefore, before the frequency modulation layer 509 is formed, the passivation layer 508 can protect the substrate 500, the interdigital transducer 501 and the connecting portion 502, thereby further reducing the probability of the substrate 500, the interdigital transducer 501 and the connecting portion 502 being damaged.

[0186] In this embodiment, the thickness of the passivation layer 508 should not be too large or too small. If the thickness of the passivation layer 508 is too large, it is easy to increase the process time in the process of forming the interconnection window in the protective material layer (not shown), thereby reducing the work efficiency and affecting the product performance (such as operating frequency and insertion loss); if the thickness of the passivation layer 508 is too small, it is easy for the passivation layer 508 to protect the interdigital transducer 501, the connecting part 502 and the substrate 500. Therefore, in this embodiment, the thickness of the passivation layer 508 is 30 angstroms to 200 angstroms.

[0187] In this embodiment, the material of the passivation layer 508 includes silicon nitride or silicon oxynitride.

[0188] It should be noted that silicon nitride and silicon oxynitride have relatively stable physical and chemical properties. In subsequent process steps, silicon nitride and silicon oxynitride are not easily removed and can play an effective protective role.

[0189] In this embodiment, the filter further includes: a dielectric layer 515 located between the protection layer 503 and the pad 505 .

[0190] Specifically, the dielectric layer 515 is also located on the substrate 500 in the peripheral region ii.

[0191] The material of the dielectric layer 515 includes one or more of polyimide, silicon oxide, silicon nitride, aluminum oxide and aluminum nitride. As an example, the material of the dielectric layer 515 is polyimide.

[0192] In this embodiment, since the connecting portion 502 includes a first electrode (not labeled) and second electrodes (not labeled) located on both sides of the first electrode, the dielectric layer 515 spans over and covers the protective layer 503 located on the first electrode and exposes at least a portion of the surface of the second electrode.

[0193] It should be noted that, since the process for forming the dielectric layer 515 adopts a spin coating process, and the dielectric layer 515 is formed after removing the protective material layer (not shown) of the peripheral area ii and a partial thickness of the substrate 500, the dielectric layer 515 is also located on the substrate 500 of the peripheral area ii.

[0194] For the specific description of the filter described in this embodiment, reference may be made to the corresponding description in the aforementioned embodiment, which will not be repeated here.

[0195] The filter structure of the embodiment of the present invention may be formed by the method for forming the filter structure of the aforementioned embodiment, or may be formed by other methods for forming the filter structure, which will not be described in detail in this embodiment.

[0196] Correspondingly, an embodiment of the present invention further provides an electronic device, and the electronic device includes the filter described in any embodiment of the present invention.

[0197] The filter can be assembled into various electronic devices. As can be seen from the above analysis, the performance of the filter is relatively high, which can correspondingly obtain high-performance electronic devices. Among them, electronic devices can also include personal computers, mobile terminals such as smart phones, media players, navigation devices, electronic game devices, game controllers, tablet computers, wearable devices, anti-access electronic systems, POS terminals, medical equipment, flight simulators, etc.

[0198] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a filter, characterized in that: include: Providing a substrate, on which an IDT and a connecting portion located at a side of the IDT are formed, wherein the connecting portion is electrically connected to the IDT; forming a protective material layer on the substrate, wherein the protective material layer covers the interdigital transducer, the connecting portion and the substrate; forming a mask layer having a mask opening on the protective material layer, wherein a projection of the mask opening on the connecting portion covers a portion of a surface of the connecting portion; Using the mask layer as a mask to remove the protective material layer at the bottom of the mask opening, an interconnection window is formed in the protective material layer, and the remaining protective material layer serves as a protective layer; A pad is formed in the mask opening, the pad is also located in the interconnection window, a sidewall of the pad is aligned with a sidewall of the interconnection window, and the pad is electrically connected to the connection portion.

2. The method for forming a filter according to claim 1, wherein: After forming a protective material layer on the substrate and before forming a mask layer having a mask opening on the protective material layer, the method further includes: forming a dielectric layer on the protective material layer, wherein the dielectric layer exposes the protective material layer on a portion of the surface of the connecting portion; In the step of forming a mask layer having a mask opening on the protective material layer, the mask opening exposes at least a portion of the surface of the dielectric layer and a portion of the surface of the protective material layer exposed by the dielectric layer.

3. The method for forming a filter according to claim 2, wherein: The material of the dielectric layer includes one or more of polyimide, silicon oxide, silicon nitride, aluminum oxide and aluminum nitride.

4. The method for forming a filter according to claim 2, wherein: The connecting portion comprises a first electrode and second electrodes located on both sides of the first electrode, wherein the first electrode and the second electrode are electrically connected to at least one of the interdigital transducers respectively; In the step of forming the dielectric layer on the protective material layer, the dielectric layer spans and covers the protective material layer on the first electrode, and exposes at least a portion of the surface of the protective material layer on the second electrode; In the step of forming a mask layer having a mask opening on the protective material layer, the mask opening spans across the dielectric layer and exposes a portion of the surface of the dielectric layer on the first electrode and the protective material layer on both sides of the first electrode; In the step of removing the protective material layer at the bottom of the mask opening using the mask layer as a mask, first interconnection windows are formed in the protective material layer on both sides of the first electrode, and the first interconnection windows expose at least a portion of the surface of the second electrode; In the step of forming a pad in the mask opening, the pad includes a first pad, the first pad straddles the first electrode, and is electrically connected to second electrodes on both sides of the first electrode via a first interconnection window exposing the second electrode.

5. The method for forming a filter according to any one of claims 1 to 4, characterized in that: The connecting portion further comprises a third electrode, and the third electrode is electrically connected to at least one of the interdigital transducers; In the step of removing the protective material layer at the bottom of the mask opening by using the mask layer as a mask, a second interconnection window exposing at least a portion of the surface of the third electrode is formed in the protective material layer; In the step of forming a pad in the mask opening, the pad includes a second pad electrically connected to the third electrode via a second interconnection window exposing the third electrode.

6. The method for forming a filter according to claim 2, wherein: In the step of providing the substrate, the substrate comprises a chip area and a peripheral area surrounding the chip area, and the IDT and the connecting portion are both located in the chip area; After forming the protective material layer on the substrate and before forming the mask dielectric layer on the protective material layer, the method further includes: removing the protective material layer and a portion of the thickness of the substrate in the peripheral area, and retaining the protective material layer in the chip area; In the step of forming the dielectric layer, the dielectric layer is also located on the substrate in the peripheral region.

7. The method for forming a filter according to claim 1, wherein: The process of forming the protective material layer on the substrate includes a physical vapor deposition process.

8. The method for forming a filter according to claim 1, wherein: The process of removing the protective material layer at the bottom of the mask opening includes a dry etching process.

9. The method for forming a filter according to claim 1, wherein: The step of forming a pad in the mask opening includes: forming a pad material layer in the mask opening, wherein the pad material layer also covers the mask layer; The mask layer and the pad material layer located on the top of the mask layer are removed, and the remaining pad material layer is used as a pad.

10. The method for forming a filter according to claim 1, wherein: In the step of forming the protective material layer, the protective material layer at least includes a frequency modulation layer.

11. The method for forming a filter according to claim 10, wherein: In the step of forming the protective material layer, the protective material layer further includes a passivation layer, and the frequency modulation layer is located on the top of the passivation layer.

12. The method for forming a filter according to claim 11, wherein: In the step of forming a protective material layer on the substrate, the material of the frequency modulation layer includes silicon oxide, and the material of the passivation layer includes silicon nitride or silicon oxynitride.

13. The method for forming a filter according to claim 1, wherein: The material of the mask layer includes photoresist.

14. A filter, characterized in that: include: substrate; an interdigital transducer, located on the substrate; A connecting portion, located on the substrate at the side of the IDT, the connecting portion being electrically connected to the IDT; A protective layer covering the IDT, the connecting portion and the substrate, wherein the protective layer has an interconnection window, and the interconnection window exposes a portion of the surface of the connecting portion; A pad is located in the interconnection window, a side wall of the pad is aligned with a side wall of the interconnection window, and the pad is electrically connected to the connection portion.

15. The filter according to claim 14, characterized in that The filter further comprises: a dielectric layer located between the protection layer and the pad.

16. The filter according to claim 15, characterized in that The connecting portion comprises a first electrode and second electrodes located on both sides of the first electrode, wherein the first electrode and the second electrode are electrically connected to at least one of the interdigital transducers respectively; The interconnection window comprises first interconnection windows located on both sides of the first electrode, the first interconnection windows exposing at least a portion of a surface of the second electrode; The pad includes a first pad, the first pad spans across the first electrode, and is electrically connected to second electrodes on both sides of the first electrode via a first interconnection window exposing the second electrode; The dielectric layer is located between the first pad and the protection layer.

17. The filter according to any one of claims 14 to 16, characterized in that: The connecting portion further comprises a third electrode, and the third electrode is electrically connected to at least one of the interdigital transducers; The interconnection window further includes a second interconnection window exposing at least a portion of a surface of the third electrode; The pads include a second pad electrically connected to the third electrode via a second interconnection window exposing the third electrode.

18. The filter according to claim 15, characterized in that The material of the dielectric layer includes one or more of polyimide, silicon oxide, silicon nitride, aluminum oxide and aluminum nitride.

19. The filter according to claim 15, characterized in that The substrate comprises a chip region and a peripheral region surrounding the chip region, wherein a substrate top of the peripheral region is lower than a substrate top of the chip region; The interdigital transducer, the connecting portion and the protective layer are all located in the chip area; The dielectric layer is also located on the substrate in the peripheral region.

20. The filter according to claim 14, characterized in that The substrate includes a piezoelectric substrate or a piezoelectric-on-insulator substrate.

21. The filter according to claim 14, characterized in that The protection layer at least includes a frequency modulation layer.

22. The filter according to claim 21, characterized in that The protection layer further comprises a passivation layer, and the frequency modulation layer is located on the top of the passivation layer.

23. The filter according to claim 22, characterized in that The thickness of the passivation layer is 30 angstroms to 200 angstroms.

24. The filter according to claim 22, characterized in that The material of the frequency modulation layer includes silicon oxide, and the material of the passivation layer includes silicon nitride or silicon oxynitride.

25. The filter according to claim 21, characterized in that The thickness of the frequency modulation layer is 20 angstroms to 1000 angstroms.

26. An electronic device, characterized in that: Comprising a filter as claimed in any one of claims 14 to 25.

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