Digital delay phase shift circuit and phased array system

Abstract

The invention provides a digital delay phase shift circuit and a phased array system, and the circuit comprises an analog-to-digital converter which receives a target frequency band signal and converts the target frequency band signal into a digital signal; the digital local oscillator is used for generating a local oscillator signal required by orthogonal down-conversion; the decimal delay filtering branch is used for performing down-conversion processing on the digital signal based on the local oscillator signal to obtain a baseband signal, and realizing decimal part time delay of a sampling interval on the baseband signal based on a decimal time delay configuration parameter to obtain a baseband time delay signal; the local oscillator delay inverting branch is used for performing delay compensation and inverting on the local oscillator signal to obtain a compensated local oscillator signal; and the amplitude-phase adjustment branch is used for performing up-conversion processing on the baseband time delay signal based on the compensation local oscillator signal to obtain an intermediate frequency signal, and performing phase compensation on the intermediate frequency signal according to a compensation phase value determined by the digital angular frequency subjected to down-conversion processing and the decimal time delay configuration parameter and according to a configuration phase value and the compensation phase value.

Description

Technical Field

[0001] The present application relates to the technical field of signal processing, and in particular to a digital delay phase shift circuit and a phased array system. Background Art

[0002] Phased array antennas adjust beam pointing by controlling the phase shift of the radiating elements in the array antenna. There are beam pointing offsets and inaccurate scanning for broadband signals. The reason is the beam "dispersion effect" caused by the aperture transit time, which will limit the instantaneous working bandwidth of the phased array system. Replacing the phase shifter used to adjust the beam pointing with a delay line can reduce or eliminate the aperture transit time and increase the instantaneous working bandwidth of the phased array system. Common delay lines include: coaxial cable delay line, ultrasonic delay line, optical fiber / waveguide delay line, etc. Among them, the coaxial cable delay line has the disadvantages of large size and heavy weight. When the delay time is long, it will bring unbearable high insertion loss. Therefore, the coaxial cable transmission line is only suitable for use as a phase shifter or delay line in the microwave range; the ultrasonic delay line has the disadvantages of difficulty in making a transducer with a relatively flat broadband response, unsatisfactory false signal suppression effect, complex double-ended transducer structure, difficulty in integration with system devices, and low operating frequency. It is suitable for certain occasions that require extra-long delay and high stability; the optical fiber delay line is mainly suitable for pulse encoding, decoding, filtering, related convolution operations and A / D conversion of high-frequency digital signals, but the structure of the optical fiber delay line is quite complex and not easy to integrate, and the cost is relatively high. Summary of the invention

[0003] In order to solve the existing technical problems, the present application provides a digital delay phase shift circuit and a phased array system which are universal and have high delay accuracy and can increase the instantaneous working bandwidth of the phased array system.

[0004] In a first aspect, an embodiment of the present application provides a digital delay phase shift circuit, comprising:

[0005] An analog-to-digital converter receives a target frequency band signal and converts it into a digital signal;

[0006] Digital local oscillator, generating the local oscillator signal required for orthogonal down-conversion;

[0007] A fractional delay filter branch, down-converting the digital signal into a baseband signal based on the local oscillator signal, delaying the baseband signal by a fractional part of a sampling interval based on a fractional delay configuration parameter, and obtaining a baseband delay signal;

[0008] A local oscillator delay inversion branch performs delay compensation and inversion on the local oscillator signal to obtain a compensated local oscillator signal;

[0009] The amplitude and phase adjustment branch up-converts the baseband delay signal into an intermediate frequency signal based on the compensated local oscillator signal, and performs phase compensation on the intermediate frequency signal according to the configured phase value and the compensated phase value according to the digital angular frequency of the down-conversion processing and the compensated phase value determined by the fractional delay configuration parameter.

[0010] In a second aspect, a phased array system is provided, including a phased array antenna, a delay unit and a beamforming network arranged corresponding to each channel in the phased array antenna;

[0011] Each of the time delay units is a digital delay phase shift circuit as described in any embodiment of the present application;

[0012] The beamforming network is an analog beamforming network or a digital beamforming network.

[0013] The digital delay phase shift circuit provided in the above embodiment quantizes and converts the target frequency band signal into a digital signal through an analog-to-digital converter, and completes subsequent signal delay phase shift processing at the baseband after downconverting the digital signal to the baseband. In this way, by completing the delay phase shift processing of the input target frequency band signal in the digital domain, the decimal delay and phase shift of the signal in the entire signal processing link can be accurately determined by calculation. The time delay compensation is performed by setting the local oscillator delay inversion branch, and the phase compensation is performed by setting the amplitude and phase adjustment branch using the configuration phase value and the compensation phase value. By utilizing the flexibility of digital signal processing, the digital delay phase shift circuit can be applied to any phased array system to expand the instantaneous working bandwidth, and has strong versatility and high delay accuracy.

[0014] The phased array system provided by the above embodiment has the same concept as the corresponding digital delay phase shift circuit embodiment, and thus has the same technical effect as the corresponding digital delay phase shift circuit embodiment, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 Schematic diagram of the system architecture of a known phased array system.

[0016] Figure 2 FIG. 4 is a system architecture diagram of another known phased array system.

[0017] Figure 3 FIG. 4 is a schematic diagram of the structure of a digital delay phase shift circuit in an embodiment.

[0018] Figure 4 FIG. 4 is a circuit diagram of a digital delay phase shift circuit in an embodiment.

[0019] Figure 5 As an optional example, the digital delay phase shift circuit uses signal processing simulation results of two different local oscillator initial phases.

[0020] Figure 6 As an optional example, the signal processing simulation result corresponding to the digital delay phase shift circuit when the signal is in the first Nyquist zone.

[0021] Figure 7 As an optional example, the signal processing simulation result corresponding to the digital delay phase shift circuit when the signal is in the second Nyquist zone.

[0022] Figure 8 As an optional example, a digital delay phase shift circuit uses a signal processing simulation result corresponding to a linear frequency modulation signal.

[0023] Fig. 9 A schematic diagram of the structure of a phased array system provided by an embodiment. DETAILED DESCRIPTION

[0024] The technical solution of the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0025] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings. The described embodiments should not be regarded as limiting the present application. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of this application.

[0026] In the following description, the expression "some embodiments" is involved, which describes a subset of all possible embodiments. It should be noted that "some embodiments" may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict.

[0027] In the following description, the terms "first, second, third" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first, second, third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0028] In studying how to solve the problems that arise when known delay lines are applied to phased array systems, the inventors of the present application have conducted the following analysis on the working characteristics of known phased array systems.

[0029] For a phased array antenna controlled by a phase shifter, when the signal is incident perpendicular to the array, each array element receives a frequency-independent in-phase signal; when the signal is incident from other angles, the phase difference between each array element and the reference array element is a function of frequency, which limits the operating bandwidth of the phased array antenna system. Overcoming the frequency correlation of the phase difference between the array element and the reference array element is the key to expanding the operating bandwidth of the phased array antenna system. The ideal solution is to replace the phase shifter with a delay unit, which can be used for array elements or subarrays. The use of a delay unit instead of a phase shifter to expand the bandwidth of a phased array antenna is applicable to both the transmit and receive links, and will not be explained separately below.

[0030] Figure 1 and Figure 2 is a system architecture diagram of a known phased array system, such as Figure 1 As shown, the antenna array element 11 receives the electromagnetic wave signal in the space, the channel 12 converts the RF input signal to the intermediate frequency, and sends it to the beam synthesis network 14 after time delay processing through the delay line 13; Figure 2 As shown, the antenna subarray 15 receives the electromagnetic wave signal in space, and the channel 12 converts the radio frequency signal to an intermediate frequency, and sends it to the beam synthesis network 14 after time delay processing through the delay line 13. The digital delay phase shift circuit provided in the embodiment of the present application quantizes the target frequency band signal into a digital signal through an analog-to-digital converter, converts the digital signal down to the baseband, and completes the subsequent signal delay phase shift processing at the baseband. By completing the delay phase shift processing of the input target frequency band signal in the digital domain, the flexibility of digital signal processing is utilized, so that the decimal delay and phase shift of the signal in the entire signal processing link can be accurately determined by calculation. The compensation phase value is determined, and the phase compensation is performed by setting the amplitude and phase adjustment branch. In this way, the digital delay phase shift circuit can be universally applicable to the delay processing units in various phased array systems, such as for Figure 1 and Figure 2 The delay line in is optimized and replaced.

[0031] The subsequent beamforming network can be analog or digital. For an analog beamforming network, the digital delay phase shifting circuit can convert the phase-compensated digital signal through a digital-to-analog converter and output an analog signal; for a digital beamforming network, the real digital signal after delay phase shifting can be directly output. The specific implementation of the digital delay phase shifting circuit is further described as follows.

[0032] Please refer to Figure 3 and Figure 4, a digital delayed phase shift circuit provided in an embodiment of the present application, includes: an analog-to-digital converter 21, which receives a target frequency band signal and converts it into a digital signal; a digital local oscillator 23, which generates a local oscillator signal required for orthogonal down-conversion 251; a fractional delay filtering branch 25, which down-converts the digital signal into a baseband signal based on the local oscillator signal, and delays the baseband signal by the fractional part of the sampling interval based on the fractional delay configuration parameter to obtain a baseband delayed signal; a local oscillator delay inversion branch 26, which performs delay compensation and inversion on the local oscillator signal to obtain a compensated local oscillator signal; an amplitude and phase adjustment branch 27, which up-converts the baseband delayed signal into an intermediate frequency signal based on the compensated local oscillator signal, and performs phase compensation on the intermediate frequency signal according to the configured phase value and the compensated phase value according to the digital angular frequency of the down-conversion processing and the compensated phase value determined by the fractional delay configuration parameter.

[0033] In this embodiment, the target frequency band signal refers to the input analog intermediate frequency signal. The analog-to-digital converter 21 samples and quantizes the input analog intermediate frequency signal at a set sampling frequency, and converts the analog intermediate frequency signal into a digital signal as an input for subsequent digital signal processing.

[0034] The digital local oscillator 23 (NCO, numerically controlled oscillator) generates address information through a phase accumulator, and the address information is used to find the corresponding value in the sine wave memory, thereby generating the required sine wave or cosine wave. Specifically, the output frequency of the NCO can be adjusted by changing the frequency control word (FCW), thereby realizing the digital control function of the frequency.

[0035] The fractional delay configuration parameter refers to the fractional delay value that can be set through external input. The fractional delay filter branch 25 down-converts the digital signal of the target frequency band signal to the baseband after quantization, and then performs subsequent digital signal processing in the baseband, including delaying the fractional part of the sampling interval of the signal based on the fractional delay configuration parameter, which is beneficial to improving the anti-interference ability and improving the signal delay accuracy. The local oscillator delay inversion branch 26 can be used to compensate for the group delay of the signal processing in the fractional delay filter branch 25. The amplitude and phase adjustment branch 27 performs phase compensation on the intermediate frequency signal according to the configured phase value and the compensation phase value. The introduction of the configured phase value can be used to achieve the phase shift required by the user. The configured phase value and the calculated compensation phase value jointly realize the compensation of the phase difference of the signal processing in the fractional delay filter branch 25.

[0036] The digital delayed phase shift circuit provided in the above embodiment quantizes and converts the target frequency band signal into a digital signal through the analog-to-digital converter 21, and completes the subsequent signal delayed phase shift processing at the baseband after downconverting the digital signal to the baseband. In this way, by completing the delayed phase shift processing of the input target frequency band signal in the digital domain, the decimal delay and phase shift of the signal in the entire signal processing link can be accurately determined by calculation. The time delay compensation is performed by setting the local oscillator delayed inverting branch 26, and the phase compensation is performed by setting the amplitude and phase adjustment branch 27 using the configured phase value and the compensated phase value. By utilizing the flexibility of digital signal processing, the digital delayed phase shift circuit can be applied to any phased array system to expand the instantaneous working bandwidth, and has strong versatility and high delay accuracy.

[0037] In some embodiments, the fractional delay filter branch 25 includes an orthogonal down-conversion 251, a low-pass filter 252 and a fractional delay filter 253. The orthogonal down-conversion 251 down-converts the digital signal into a baseband signal; the low-pass filter 252 separates the image frequency from the real frequency band in the baseband signal by filtering; the fractional delay filter 253 determines a corresponding set of filter coefficients based on the fractional delay configuration parameters. Orthogonal down-conversion 251 (ODC) is a technology in signal processing. It reduces the frequency of the signal by mixing the received signal with the local oscillator signal. The main purpose is to convert the high-frequency signal into a low-frequency signal for further processing. In a specific example, the orthogonal down-conversion 251 mainly includes two parts: a digital mixer and a digital oscillator (NCO), and an anti-aliasing filter. The digital mixer is used to multiply the high-frequency signal with the local oscillator signal to generate an intermediate frequency signal, and the digital oscillator generates the local oscillator signal; the anti-aliasing filter is used to filter out unnecessary frequency components to obtain a low-frequency signal.

[0038] The mirror image frequency and the real frequency band usually have the same power, which will seriously affect the signal processing result of the real frequency band. Through the setting of the low-pass filter 252, filtering is used to suppress the mirror image frequency of the real frequency band, thereby reducing the influence of the mirror image frequency on the real frequency band.

[0039] The fractional delay filter 253 refers to a linear filter for processing signals, and is mainly used to process non-integer delays. In a specific example, the fractional delay filter 253 can be implemented using FIR. In this embodiment, the specific design of the fractional delay filter branch 25 can realize a partial delay that is less than the sampling interval. The fractional delay filter 253 can be implemented using FIR. The coefficients of FIR can be pre-stored in the internal memory. A fractional delay corresponds to a set of FIR filter coefficients. The delay accuracy is completely determined by the memory resources. For example, the delay accuracy is 1 / 128 of the sampling interval. The fractional delay value can be configured through the interface, and the filter coefficient corresponding to the fractional delay value is read and loaded into the filter to realize the required fractional delay part.

[0040] In some embodiments, the digital delay phase shift circuit further includes an integer delayer 22 connected between the analog-to-digital converter 21 and the orthogonal down-conversion 251; the integer delayer 22 implements an integer part delay of the sampling interval for the digital signal based on the integer delay configuration parameter. The integer delayer 22 can be implemented using a dual-port memory, which has two sets of independent data lines and address lines, allowing simultaneous read and write operations, and can set the depth of the memory according to the maximum integer delay value, making it suitable for scenarios requiring high-speed reading and writing.

[0041] In some embodiments, the local oscillator delay inversion branch 26 includes a delay compensation circuit 261 and an inverter 262; the orthogonal local oscillator signals are cos(-Ω c n) and sin(-Ω c n), the compensation value of the delay compensation circuit 261 is N0; the compensation local oscillator signal is cos(Ω c (n-N0)) and sin(Ω c (n-N0)). The local oscillator signal of the orthogonal down-conversion 251 is delayed and reversed to obtain the local oscillator of the orthogonal up-conversion 271, that is, the compensated local oscillator signal here. The local oscillator used for the orthogonal up-conversion 271 can be regarded as a copy of the local oscillator of the orthogonal down-conversion 251. Among them, the delay compensation circuit 261 is used to compensate for the group delay (N0) of the low-pass filter 252 and the fractional delay filter 253 in the signal processing path formed by the fractional delay filter branch 25. The down-conversion local oscillator needs to be inverted to be converted into the up-conversion local oscillator.

[0042] Optionally, according to the sampling frequency area corresponding to the configured signal frequency band, if the sampling frequency area corresponds to the first Nyquist zone, the digital local oscillator 23 determines that the current digital angular frequency is π / 2; if the sampling frequency area corresponds to the second Nyquist zone, the digital local oscillator 23 selects the current digital angular frequency as 3π / 2. In this embodiment, the digital local oscillator 23 supports switching the digital angular frequency according to the signal frequency band in the first Nyquist zone or the second Nyquist zone. In addition to the transient response of the filter, after the signal in the first Nyquist zone or the second Nyquist zone is processed by the digital delay phase shift circuit, the delay and phase shift results are within the filter fluctuation range as well as the theoretical delay and phase shift results.

[0043] In some embodiments, the amplitude and phase adjustment branch 27 includes an orthogonal up-conversion 271 and an amplitude and phase adjuster 272; the orthogonal up-conversion 271 up-converts the baseband delayed signal into an intermediate frequency signal; the amplitude and phase adjuster 272 performs phase compensation on the intermediate frequency signal by determining the phase adjustment parameters according to the configured phase value and the compensation phase value. The orthogonal up-conversion 271 realizes the up-conversion of the signal output by the fractional delay filter to the intermediate frequency as the input of the subsequent analog-to-digital converter 21. The amplitude and phase adjuster 272 is used to compensate for the loss of the signal processing link formed by the fractional delay filter branch 25. According to theory, the processing link loss formed by the fractional delay filter branch 25 can be calculated, and the amplitude adjustment amount here is the link processing loss multiplied by 2; the phase compensation includes two parts: the phase value that needs to be adjusted for the processing link formed by the fractional delay filter branch 25, and the phase difference of the up-down conversion local oscillator caused by the fractional delay.

[0044] Optionally, the phase adjustment parameter is in, To configure the phase value, In this embodiment, the compensation phase value mainly refers to the phase difference of the up-down conversion local oscillator caused by the fractional delay. In order to accurately calculate the compensation phase value, it is assumed that the input signal s(n) is a complex band-limited signal and the digital angular frequency of the digital down-conversion is Ω c , the initial phase of the digital local oscillator 23 is The fractional delay is Δn, then:

[0045] The digital down-converted signal ddc (n) can be expressed as follows:

[0046]

[0047] The signal after the fractional delay s Δn The expression of (n) can be shown as the following formula 2:

[0048]

[0049] The digital up-converted signal sduc The expression of (n) can be shown as the following formula 3:

[0050]

[0051] From the above formulas 1 to 3, it can be seen that the output after down-conversion, fractional delay, and up-conversion is the fractional delay of the input signal plus the phase shift. In order to obtain the fractional delay of the input signal, this phase needs to be compensated. The phase value to be compensated is -Ω c Δn, so the compensation phase value can be determined As shown in Formula 4 below:

[0052] φ c =Ω c Δn (Formula 4)

[0053] Configuring Phase Value It supports configuration through an interface, and uses the configured phase value and the compensation phase value to determine the phase adjustment parameters of the amplitude-phase adjuster 272 to complete the phase compensation of the intermediate frequency signal after the orthogonal up-conversion 271.

[0054] In some embodiments, the digital delay phase shift circuit also includes a configuration circuit 24 and a clock circuit 26; the configuration circuit 24 receives control information and implements the configuration of target parameters according to external control signals; wherein the target parameters at least include fractional delay configuration parameters; the clock circuit 26 generates the clock signal required in the fractional delay processing according to the input clock. It should be noted that the specific implementation of the configuration circuit 24 can be implemented through a known serial port circuit according to the parameter value required for dynamic configuration in the digital delay phase shift circuit under the technical teaching of this application. In a specific example, the configuration circuit 24 receives an external control signal, completes the parsing of the control information and the reading back of the control information, and implements the configuration of the integer delay value of the integer delay 22, the control of the digital local oscillator 23, the loading of the filter coefficient of the fractional delay filter 253 corresponding to the fractional delay value, the signal movement control, and the calculation of the up and down frequency conversion compensation phase caused by the fractional delay. The clock circuit 26 generates a clock signal according to the input clock, so that the fractional delay can work normally and the fixed part delay can be reduced.

[0055] In some embodiments, the digital delay phase shift circuit further includes a digital-to-analog converter 28, which is connected to the amplitude-phase adjustment branch 27 to convert the intermediate frequency signal after phase compensation into an analog signal for output. The digital delay phase shift circuit can perform digital-to-analog conversion on the intermediate frequency signal obtained after delay phase shift processing in the digital domain through the digital-to-analog converter 28, and can be externally connected to an analog beamforming network. Optionally, the digital delay phase shift circuit can also be directly externally connected to a digital beamforming network, in which case the real digital signal of the intermediate frequency signal after phase compensation can be directly output through the amplitude-phase adjustment branch 27.

[0056] In order to have a more comprehensive understanding of the working principle of the digital delay phase shift circuit provided in the embodiment of the present application, Figure 4 The digital delay phase shift circuit shown is used as an example for explanation.

[0057] The digital delay phase shift circuit quantizes the input analog intermediate frequency signal with an ADC, and outputs it with a DAC after digital signal processing. All signal processing is implemented in the digital domain, giving full play to the flexibility of digital signal processing. The digital delay phase shift circuit includes an analog-to-digital converter 21 (ADC), an integer delay device 22, an orthogonal down-conversion 251, a low-pass filter 252, a fractional delay filter 253, an orthogonal up-conversion 271, an amplitude and phase adjustment, and a digital-to-analog converter 28 (DAC) according to the signal flow direction, and includes a clock circuit 26 and a configuration circuit 24.

[0058] Among them, the analog-to-digital converter 21 (ADC) quantizes the input analog intermediate frequency signal into a digital signal to provide input for subsequent signal processing.

[0059] Integer Delay (Z -D ) 22: Delay the integer part of the sampling interval. The integer delay 22 can be implemented by a simple dual-port memory, and the depth of the memory is set according to the maximum delay.

[0060] Digital local oscillator 23 (NCO): Generates the digital local oscillator 23 required by the orthogonal down-conversion 251. In a simple application scenario, the digital angular frequency is π / 2 when the signal frequency band is in the first Nyquist zone, and the digital angular frequency is 3π / 2 when the signal frequency band is in the second Nyquist zone; the digital angular frequency of the digital local oscillator 23 can be determined according to the first Nyquist zone or the second Nyquist zone to which the currently selected signal frequency band belongs, to adapt to various application scenarios.

[0061] Orthogonal down-conversion 251: down-converts the target frequency band signal (i.e., the input analog intermediate frequency signal) to the baseband, and subsequent digital signal processing is completed at the baseband.

[0062] Low-pass filter 252: The image frequency has the same power as the real frequency band, which will seriously affect the signal processing result of the real frequency band. Here, the low-pass filter 252 is used to suppress the image frequency of the real frequency band through filtering, thereby reducing the influence of the image frequency on the real frequency band.

[0063] Fractional delay filter 253: realizes the partial delay less than the sampling interval, and adopts FIR (Finite Impulse Response, finite impulse response digital filter) to realize, and the coefficient of FIR is stored in the internal memory, and a fractional delay value corresponds to a set of FIR filter coefficients, and the delay accuracy can be completely determined by the memory resources. When the configuration circuit 24 is used to configure the fractional delay value through the interface, the filter coefficient corresponding to the fractional delay value is read and loaded into the filter to realize the required fractional delay part.

[0064] Local oscillator delay and inversion: The local oscillator of the quadrature up-conversion 271 is obtained from the local oscillator of the quadrature down-conversion 251. The local oscillator used for the quadrature up-conversion 271 is a copy of the local oscillator of the quadrature down-conversion 251. It is necessary to delay and reverse the local oscillator of the quadrature up-conversion 271. The local oscillator delay is used to compensate for the group delay (N0) of the low-pass filter 252 and the fractional delay filter 253 in the signal processing path formed by the fractional delay filter branch 25. The local oscillator is inverted. The local oscillator needs to be inverted when it is converted from down-conversion to up-conversion.

[0065] Orthogonal up-conversion 271: realizes up-conversion of the target frequency band signal (the input analog intermediate frequency signal is down-converted to the baseband, and the signal is delayed and inverted in the baseband) to the intermediate frequency for the input of the digital-to-analog converter 28.

[0066] Amplitude and phase adjustment: Amplitude adjustment is used to compensate for link processing loss (processing link loss formed by fractional delay filter branch 25). According to theory, the link processing loss can be calculated to be 6dB, and the amplitude adjustment amount here is multiplied by 2 (6dB); Phase compensation includes two parts: the phase value that needs to be adjusted in the link, and the compensation for the phase difference between the up and down conversion local oscillators caused by the fractional delay.

[0067] Digital-to-analog converter 28 (DAC): converts the processed signal (the input analog intermediate frequency signal is down-converted to the baseband, and the signal is processed by delay and inversion in the baseband) from the digital domain to the analog domain.

[0068] Clock circuit 26: Generates the clock signal required by the delay device according to the input clock. The signal processing part of the digital delay phase shift circuit in the baseband can reduce the fixed part delay of the delay device.

[0069] Configuration circuit 24: receives external control information, completes the analysis of control information and reads back control information, and can be selected as a serial port circuit. Configuration circuit 24 mainly implements: integer delay value configuration of integer delayer 22, digital local oscillator 23 control, fractional delay value configuration of fractional delay filter 253 (corresponding to FIR filter coefficient loading), signal phase shift control, and calculation of up and down frequency conversion compensation phase caused by fractional delay.

[0070] The calculation of the up-down conversion compensation phase caused by the fractional delay can be as shown in the above formulas 1 to 4, which will not be repeated here.

[0071] The digital delay phase shift circuit provided in the above embodiment has at least the following characteristics:

[0072] First, a fully digital method is used to implement the architecture of the delay line to replace the analog intermediate frequency signal. The digital delay phase shift circuit can be made into an integrated circuit, in which integer delay values, fractional delay values, and configured phase values ​​can all be configured. The phase difference caused by the delay can be accurately calculated and compensated, and the phase shift function required by the user can be realized. It has the advantages of high delay accuracy, precise adjustment of delay time, easy integration, and low cost.

[0073] The digital delay phase shift circuit converts the input analog intermediate frequency signal down to the baseband for signal processing and then up to the intermediate frequency. The initial phase of the local oscillator signal required for up and down frequency conversion will not affect the accuracy of the signal processing result. Figure 5 By setting the simulation conditions: the sampling rate is 200MHz, the signal frequency is 20MHz, the integer part delay value is 11*5ns, the fractional part delay value is 18 / 128*5ns, the signal phase shift is π / 10, the digital angular frequency of the digital local oscillator 23 is π / 2, and the initial phases of the digital local oscillator 23 are π / 10 and 7π / 10 respectively; the signal processing flow of the digital delay phase shift circuit is simulated, and the signal output and difference of the two delays are obtained as shown in the figure. Figure 5 As shown in , the difference between the two initial phases is only a calculation error, and the local oscillator initial phase does not affect the signal processing result.

[0074] Second, the digital delay phase shift circuit can be applied to the delay of analog intermediate frequency signals in the first and second Nyquist zones, especially the second Nyquist zone of the analog-to-digital / digital-to-analog converter 28 is the frequency range used in phased array radar systems and electronic countermeasures, and is thus suitable for large phased array radar systems and large DBF (Digital BeamForming) reconnaissance systems.

[0075] The digital delay phase shift circuit can be applied to the signal frequency bands in the first Nyquist zone or the second Nyquist zone. Figure 6 , set the simulation conditions: sampling rate is 200MHz, signal frequency is 20MHz, integer part delay value is 11*5ns, fractional part delay value is 18 / 128*5ns, signal phase shift is π / 10, digital angular frequency of digital local oscillator 23 is π / 2, initial phase of digital local oscillator 23 is π / 10; simulate the signal processing flow of the digital delay phase shift circuit, and the simulated signal processing results are basically consistent with the theoretical results.

[0076] See also Figure 7 , set the simulation conditions: sampling rate is 200MHz, signal frequency is 130MHz, integer part delay is 13*5ns, fractional part delay is 69 / 128*5ns, signal phase shift is 3π / 10; simulate the signal processing flow of the digital delay phase shift circuit, and the signal processing results obtained by simulation are basically consistent with the theoretical results.

[0077] In this way, after simulation verification, except for the transient response of the filter, the analog intermediate frequency signals located in the first and second Nyquist zones are processed by the signal processing flow of the digital delay phase shifter circuit provided in the embodiment of the present application, and the results are within the fluctuation range of the filter (0.02dB) as well as the theoretical delay and phase shift results.

[0078] Thirdly, the digital delay phase shift circuit has digital delay and digital phase shift functions, and can replace the traditional circuit design of two components of delay and phase shift.

[0079] The digital delay phase shift circuit can effectively solve the delay problem of broadband signals in the phased array system, has good adaptability to broadband signals, and can expand the instantaneous working bandwidth of the phased array system. Figure 8 , set the simulation conditions: sampling rate is 200MHz, linear frequency modulation center frequency is 150MHz, bandwidth is 50MHz (125MHz~175MHz), frequency modulation slope is 50MHz / μs, integer part delay value is 7*5ns, fractional part delay value is 89 / 128*5ns, signal phase shift is π / 10, digital angular frequency of digital local oscillator 23 is 3π / 2, and initial phase of digital local oscillator 23 is π / 10; Figure 7 As shown in , the signal processing flow of the digital delay phase shift circuit is simulated, and the signal processing results obtained by simulation are basically consistent with the theoretical results. In this way, the simulation verifies that, except for the transient response of the filter, the linear frequency modulation delay and phase shift results are within the filter fluctuation range and the theoretical delay and phase shift results, which can be used to expand the work of the phased array system.

[0080] On the other hand, please see Fig. 9 , a phased array system is also provided, including a phased array antenna 31, a time delay unit 32 corresponding to each channel in the phased array antenna 31, and a beamforming network 14. Each time delay unit 32 is a digital delay phase shift circuit of any embodiment of the present application. The beamforming network 14 is an analog beamforming network or a digital beamforming network.

[0081] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0082] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A digital delay phase shift circuit, characterized in that: include: An analog-to-digital converter receives a target frequency band signal and converts it into a digital signal; Digital local oscillator, generating the local oscillator signal required for orthogonal down-conversion; A fractional delay filter branch, down-converting the digital signal into a baseband signal based on the local oscillator signal, delaying the baseband signal by a fractional part of a sampling interval based on a fractional delay configuration parameter, and obtaining a baseband delay signal; A local oscillator delay inversion branch performs delay compensation and inversion on the local oscillator signal to obtain a compensated local oscillator signal; The amplitude and phase adjustment branch up-converts the baseband delay signal into an intermediate frequency signal based on the compensated local oscillator signal, and performs phase compensation on the intermediate frequency signal according to the configured phase value and the compensated phase value according to the digital angular frequency of the down-conversion processing and the compensated phase value determined by the fractional delay configuration parameter.

2. The digital delay phase shift circuit according to claim 1, characterized in that: The fractional delay filter branch includes an orthogonal down-conversion, a low-pass filter and a fractional delay filter; The orthogonal down-conversion down-converts the digital signal into a baseband signal; The low-pass filter separates the image frequency from the real frequency band in the baseband signal by filtering; The fractional delay filter determines a corresponding set of filter coefficients based on the fractional delay configuration parameters.

3. The digital delay phase shift circuit according to claim 2, characterized in that: Also included is an integer delay connected between the analog-to-digital converter and the orthogonal down-conversion; The integer delayer implements an integer part delay of a sampling interval for the digital signal based on an integer delay configuration parameter.

4. The digital delay phase shift circuit according to claim 1, characterized in that: The local oscillator delay inversion branch includes a delay compensation circuit and an inverter; The orthogonal local oscillator signals are cos(-Ω c n) and sin(-Ω c n), the compensation value of the delay compensation circuit is N0; the compensation local oscillator signal is cos(Ω c (n-N0)) and sin(Ω c (n-N0)).

5. The digital delay phase shift circuit according to claim 4, characterized in that: According to the sampling frequency region corresponding to the configured signal frequency band, if the sampling frequency region corresponds to the first Nyquist zone, the digital local oscillator determines that the current digital angular frequency is π / 2; if the sampling frequency region corresponds to the second Nyquist zone, the digital local oscillator selects the current digital angular frequency as 3π / 2.

6. The digital delay phase shift circuit according to claim 1, characterized in that: The amplitude and phase adjustment branch includes an orthogonal up-conversion and an amplitude and phase adjuster; The orthogonal up-conversion up-converts the baseband delayed signal into an intermediate frequency signal; The amplitude-phase adjuster performs phase compensation on the intermediate frequency signal by determining a phase adjustment parameter according to the configured phase value and the compensation phase value.

7. The digital delay phase shift circuit according to claim 6, characterized in that: The phase adjustment parameter is refers to the configuration phase value, Refers to the compensation phase value.

8. The digital delay phase shift circuit according to any one of claims 1 to 7, characterized in that: The digital delay phase shift circuit also includes a configuration circuit and a clock circuit; The configuration circuit receives control information and implements configuration of target parameters according to external control signals; wherein the target parameters at least include fractional delay configuration parameters; The clock circuit generates a clock signal required for fractional part delay processing according to an input clock.

9. The digital delay phase shift circuit according to any one of claims 1 to 7, characterized in that: The digital delay phase shift circuit further includes a digital-to-analog converter, which is connected to the amplitude-to-phase adjustment branch and converts the intermediate frequency signal after phase compensation into an analog signal for output; Alternatively, the digital delay phase shift circuit outputs the real digital signal of the intermediate frequency signal after phase compensation through the amplitude and phase adjustment branch.

10. A phased array system, characterized in that: It includes a phased array antenna, a time delay unit and a beamforming network arranged corresponding to each channel in the phased array antenna; Each of the time delay units is a digital delay phase shift circuit as claimed in any one of claims 1 to 9; The beamforming network is an analog beamforming network or a digital beamforming network.

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