Method for realizing error correction of optical transport network based on parallel coding and decoding technology

Abstract

The invention relates to the technical field of telecommunication, in particular to a method for realizing error correction of an optical transport network based on a parallel coding and decoding technology, which remarkably improves the processing efficiency of data coding and decoding by adopting a combined parallel working mode of eight single-path encoders and a combined parallel working mode of eight single-path decoders. The data is protected by using RS coding, the anti-interference capability and reliability of the data are further enhanced through an interleaving technology, the integrity of the data in the transmission process is ensured, and the performance of the whole OTN system is improved through a parallel coding and interleaving technology. The method can better adapt to the requirement of high-speed data transmission, and solves the problem that the RS code cannot be corrected due to the fact that some code words contain too many errors when burst errors periodically occur.

Description

Technical Field

[0001] The present invention relates to the field of electrical communication technology, and in particular to a method for realizing error correction of an optical transmission network based on parallel coding technology. Background Art

[0002] In the Optical Transport Network (OTN), the Forward Error Correction (FEC) overhead technology is divided into two categories: in-band FEC and out-band FEC according to the position of the supervision bit in the data frame. The working principle of FEC is that the transmitter adds supervision symbols after the information codewords to be sent according to certain specific rules. The information codewords and supervision symbols constitute the transmission sequence. The receiving end uses the supervision symbols in the receiving sequence and specific rules to detect and correct the error codewords that occur during the transmission process to restore the original information codewords.

[0003] OTN ITU-T G.975 and G.709 protocols use out-of-band FEC technology, that is, the FEC check bytes are not loaded in the overhead bytes of the data frame, but are placed separately after the data frame. The advantage of this technology is that it is not limited by the frame byte length, enhances the coding flexibility, and greatly improves the error correction capability. Reed-Solomon code (RS code) has a simple structure but strong error correction capability, so FEC technology generally uses RS code for error control. RS code is a multi-base binary cyclic redundancy check (Binary Bose-Chaudhuri-Hocquenghem, BCH) code and algebraic geometry code with strong error correction capability. ITU-T G.709 protocol applies RS (255,239) linear block code to OTN, and its information code consists of 239 symbol information bits and 16 symbol check bits.

[0004] However, in OTN high-speed burst channels, the bit error problem still exists, especially when burst error symbols tend to occur within an RS codeword, which may cause the RS code to be unable to correct when burst errors occur periodically because some codewords contain too many errors. Summary of the invention

[0005] The purpose of the present invention is to provide a method for implementing error correction in an optical transport network based on parallel coding technology, aiming to solve the problem that RS code cannot be corrected when burst errors occur periodically because some code words contain too many errors.

[0006] To achieve the above object, the present invention provides a method for implementing error correction in an optical transport network based on parallel encoding and decoding technology, comprising the following steps:

[0007] Preprocess the OTN information structure to synchronously map the OTU frame to the OTU-FEC frame;

[0008] Encoding the information bits of the OTU-FEC frame through a RS encoding module to generate a check bit;

[0009] The encoded OTU-FEC frame is rearranged and error corrected.

[0010] Among them, in "preprocessing the OTN information structure to synchronously map the OTU frame to the OTU-FEC frame", the following steps are included:

[0011] Map service data to the OPU frame payload area, and add OPU, ODU, and OTU overhead layer by layer;

[0012] Add FEC overhead and checksum to the OTU frame, and synchronously map the OTU frame to the OTU-FEC frame.

[0013] Among them, in “encoding the information bits of the OTU-FEC frame through the RS encoding module to generate check bits”, the information bits consist of 239 symbols, and the check bits consist of 16 symbols.

[0014] Among them, in “encoding the information bits of the OTU-FEC frame through the RS encoding module to generate check bits”, the maximum interleaving depth of the RS encoding module is 8.

[0015] Among them, in “rearrange the encoded OTU-FEC frame and perform error correction”, the rearrangement is used to disperse possible burst errors into random errors.

[0016] The present invention provides a method for realizing optical transport network error correction based on parallel encoding and decoding technology, comprising the following steps: pre-processing the OTN information structure to synchronously map the OTU frame to the OTU-FEC frame; encoding the information bit of the OTU-FEC frame through the RS encoding module to generate the check bit; rearranging the encoded OTU-FEC frame and performing error correction. The present invention significantly improves the processing efficiency of data encoding and decoding by adopting the combined parallel working mode of 8-way single-channel encoders and the combined parallel working mode of 8-way single-channel decoders, protects the data by RS encoding, and further enhances the anti-interference ability and reliability of the data by interleaving technology, ensures the integrity of the data during transmission, and improves the performance of the entire OTN system by parallel encoding and interleaving technology, so that it can better adapt to the needs of high-speed data transmission, and solves the problem that the RS code cannot be corrected when burst errors occur periodically due to too many errors in some code words. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 The present invention provides a flowchart of a method for realizing optical transport network error correction based on parallel encoding and decoding technology.

[0019] Figure 2 This is a flowchart of preprocessing the OTN information structure to synchronously map the OTU frame to the OTU-FEC frame.

[0020] Figure 3 This is the OTN interface information including the relationship diagram.

[0021] Figure 4 It is the OTN physical layer interface frame structure.

[0022] Figure 5 It is the OTU-FEC frame structure.

[0023] Figure 6 It is an OTU-FEC frame structure using RS (255,239) encoding.

[0024] Figure 7 It is a schematic diagram of 16-sub-row RS coding, (a) is the implementation process of RS coding interleaving, and (b) is the OTU-FEC frame byte transmission order after filling RS interleaving coding.

[0025] Figure 8 This is the design schematic diagram of RS parallel encoding and interleaving module.

[0026] Fig. 9 This is the design schematic diagram of the RS parallel decoding module.

[0027] Fig.10 This is the block diagram of the RS parallel encoding module.

[0028] Fig.11 This is the block diagram of the RS parallel decoding module. DETAILED DESCRIPTION

[0029] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0030] See also Figures 1 to 11 The present invention provides a method for implementing error correction in an optical transport network based on parallel coding technology, comprising the following steps:

[0031] S1 pre-processes the OTN information structure and synchronously maps the OTU frame to the OTU-FEC frame;

[0032] S11 maps service data to the OPU frame payload area and adds OPU, ODU, and OTU overhead layer by layer;

[0033] Specifically, the optical transport network (OTN) interface has a two-layer structure of electrical layer and optical layer. The electrical layer includes OPU, ODU, and OTU sublayers, while the optical layer corresponds to optical signals. The OTN interface information includes the following: Figure 3 :(1) Map the Ethernet MAC service to the OPU frame payload area, add the OPU overhead, and complete the OPU frame encapsulation;(2) Add the ODU overhead to the OPU frame to implement the ODU layer overhead monitoring function and complete the ODU frame encapsulation;(3) Add the OTU overhead to the ODU frame to implement the OTU layer overhead monitoring function and complete the OTU frame encapsulation.

[0034] The OTN physical layer interface overhead includes FEC overhead, OTU overhead, ODU overhead and OPU overhead. The OTU-FEC frame is used to encapsulate FEC coding. The present invention designs an FEC frame structure based on RS (255, 239) coding, which mainly consists of three parts: FEC overhead, payload and FEC check. Figure 5 The OTU frame is a fixed-length frame structure, including OTU overhead and service payload. The ODU frame is encapsulated in the OTU frame, including ODU overhead and OPU frame. The OPU frame includes OPU overhead and service payload.

[0035] In the present invention, all frame structures and overheads are sent in a little endian (LE) manner, that is, the leftmost bit of the byte is the most significant bit (MSB), and the rightmost bit is the least significant bit (LSB). The sending order is from left to right, and the most significant bit is sent first.

[0036] S12 adds FEC overhead and checksum to the OTU frame and synchronously maps the OTU frame to the OTU-FEC frame.

[0037] Specifically, (4) FEC overhead (OH) and checksum are added to the OTU frame, and the OTU frame is synchronously mapped to the OTU-FEC frame.

[0038] S2 encodes the information bits of the OTU-FEC frame through the RS encoding module to generate check bits;

[0039] The information bits consist of 239 symbols, and the check bits consist of 16 symbols.

[0040] The maximum interleaving depth of the RS encoding module is 8.

[0041] Specifically, the forward error correction technology of the OTU-FEC frame adopts RS (255, 239) coding, the coded information bits are placed in the payload, and the check bits are placed in the FEC check, such as Figure 6 The parameters of RS (255, 239) linear block code (hereinafter referred to as RS code) are as follows:

[0042] The codeword is encoded as a systematic code (n, k), that is, 255 symbols for information bits and 239 symbols for check bits (n=255, k=239).

[0043] The number of information bits represented by one RS code symbol is J = 8 bits;

[0044] The maximum error correction capability of one codeword of RS code is E = (nk) / 2 = (255-239) / 2 = 8 symbols;

[0045] The length of one codeword of RS code is n=2 8 -1=255 symbols, the information bit (payload) length is k=n-2E=239 symbols, and the check bit (FEC check) length is 2E=16 symbols;

[0046] RS code belongs to GF(2 8 ) field (i.e. Galois Field (GF)), whose primitive polynomial is

[0047] F(x)=x 8 +x 4 +x 3 +x 2 +1(1)

[0048] Its generating polynomial is:

[0049]

[0050] S3 rearranges the encoded OTU-FEC frame and performs error correction;

[0051] The rearrangement is used to disperse possible burst errors into random errors.

[0052] Specifically, because long-distance transmission may cause sudden and random errors in information, the interleaver is used to discretize multiple sudden errors into random errors, and then error correction is performed to improve the error correction performance of the system. Error correction coding At the transmitting end, the interleaver rearranges the symbol sequence according to a certain rule, and at the receiving end, the symbol sequence stream is deinterleaved according to the rule to restore the original symbol stream.

[0053] Since the OTN frame length is 3824 bytes, and the RS codeword information bit length is 239 symbols, the maximum interleaving depth when parallel RS coding is used is I max =3824 / 239=16. The symbol width of the RS code is 8 bits. When the interleaving depth is 8, the RS encoder inputs 8 bits*8=64 bits of data each time. When the RS encoding module data bus uses a 64-bit width, data management is convenient.

[0054] The RS encoder uses the XILINX RS encoding IP core (Reed-Solomon Encoder IP core), assuming that the working clock ω encoder MHz, coding delay τ encoder clock cycles, one RS codeword encoding takes 255+τ encoder clock cycles, the encoding capacity of a single combined encoder is v encoder Gbps:

[0055] 8bits*8*(239 / (255+τ emcpder ))*w encolder MHz=υ encoder Gbps (3)

[0056] RS code belongs to GF(2 8 ) domain, its primitive polynomial (1) corresponds to fieldpolynomial=285 (0b100011101 in binary). Its generator polynomial (2) corresponds to scalingfactor=1, generatorstart=0. Therefore, the main parameter configuration of the RS encoding IP core is shown in Table 1.

[0057] Table 1 Main configuration parameters of RS encoding IP core

[0058] Parameter name Configuration codespecification G.709 symbolwidth 8 fieldpolynomial 285 scalingfactor 1 generatorstart 0 symbolperblock 255 datasymbols 239 numberofchannels 1

[0059] The RS parallel encoding module uses 8-channel single-channel encoders to work in parallel:

[0060] (1) Reset the RS parallel encoding module (set enc_reset to "1", hold for 1 clock cycle, then set enc_reset to "0");

[0061] (2) Input data start signal (enc_in_sop is set to "1"), data valid signal (enc_in_valid is set to "1"), and send data to RS parallel encoding module through input data (enc_in_data). After completion, notify RS parallel encoding module (enc_in_eop is set to "1");

[0062] (3) The RS parallel encoding module starts parallel encoding and interleaves the encoded data;

[0063] (4) After completing the coding interleaving, the RS parallel coding module outputs the data start signal (enc_out_sop is set to "1"), the data valid signal (enc_out_valid is set to "1"), and successively outputs the RS code information bit and the check bit (enc_out_data). After completion, it indicates the last byte of the output data (enc_out_eop is set to "1"). The block diagram of the RS parallel coding module is shown in the figure. Fig.10 , the RS parallel encoding module interface signals are shown in Table 2.

[0064] Table 2 RS parallel encoding module signal interface

[0065]

[0066] The RS parallel decoding module adopts 8-way single-way decoders combined in parallel. The block diagram of the RS parallel decoding module is as follows: Fig.11 .

[0067] (1) Reset the RS parallel decoding module (set dec_reset to "1", hold for 1 clock cycle, then set dec_reset to "0");

[0068] (2) Input data start signal (dec_in_sop is set to "1"), data valid signal (dec_in_valid is set to "1"), and send data to RS parallel decoding module through input data (dec_in_data). After completion, notify RS parallel decoding module (dec_in_eop is set to "1");

[0069] (3) The RS parallel decoding module deinterleaves the decoded data and starts decoding;

[0070] (4) After decoding is completed, the RS parallel decoding module outputs the data start signal (dec_out_sop is set to "1") and the data valid signal (dec_out_valid is set to "1"). The data is output successively (dec_out_data), and after completion, it indicates the last byte of the output data (dec_out_eop is set to "1");

[0071] (5) When the number of error symbols exceeds the error correction capability (≥8 bytes), it indicates that the error cannot be corrected (dec_out_fail is set to "1"); conversely, when the number of error symbols is within the error correction range (≤8 bytes), it indicates that an error is found (dec_out_error is set to "1"), and the number of corrected error symbols is counted (dec_out_error_stat). The signal interface of the RS parallel decoding module is shown in Table 3.

[0072] Table 3 RS parallel decoding module signal interface

[0073]

[0074] The parallel RS encoding and interleaving method designed by the present invention is as follows Figure 8 , data enters each encoder through switch #1 from the input port, performs RS encoding, and the encoded data symbols control data output through switch #2. Among them, the output data of the combined encoder #1 and the combined encoder #2 are interleaved to form RS encoding and sent to the line side.

[0075] What is disclosed above is only a preferred embodiment of the method for realizing optical transport network error correction based on parallel coding technology of the present invention. Of course, it cannot be used to limit the scope of rights of the present invention. Ordinary technicians in this field can understand that all or part of the processes of the above embodiments are implemented, and equivalent changes made according to the claims of the present invention still fall within the scope of the invention.

Claims

1. A method for implementing error correction in an optical transport network based on parallel coding technology, characterized in that: The following steps are involved: Preprocess the OTN information structure to synchronously map the OTU frame to the OTU-FEC frame; Encoding the information bits of the OTU-FEC frame through a RS encoding module to generate a check bit; The encoded OTU-FEC frame is rearranged and error corrected.

2. The method for implementing optical transport network error correction based on parallel coding technology according to claim 1, characterized in that: In "Preprocessing the OTN information structure to synchronously map the OTU frame to the OTU-FEC frame", the following steps are included: Map service data to the OPU frame payload area, and add OPU, ODU, and OTU overhead layer by layer; Add FEC overhead and checksum to the OTU frame, and synchronously map the OTU frame to the OTU-FEC frame.

3. The method for implementing optical transport network error correction based on parallel coding technology as claimed in claim 1, characterized in that: In "encoding the information bits of the OTU-FEC frame through the RS encoding module to generate check bits", the information bits consist of 239 symbols, and the check bits consist of 16 symbols.

4. The method for implementing error correction in an optical transport network based on parallel coding technology as claimed in claim 1, characterized in that: In “encoding the information bits of the OTU-FEC frame through the RS encoding module to generate check bits”, the maximum interleaving depth of the RS encoding module is 8.

5. The method for implementing optical transport network error correction based on parallel coding technology as claimed in claim 1, characterized in that: In “rearranging the encoded OTU-FEC frame and performing error correction”, the rearrangement is used to disperse possible burst errors into random errors.

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