Data transmission processing system, method, computer device and storage medium

Abstract

The present application relates to a data transmission processing system, method, device, computer equipment, storage medium and computer program product. The method comprises: transmitting the storage data received from the host to the back end through the storage data forwarding module in the FPGA chip; controlling the initialization of the storage data forwarding module through the SOC chip when an abnormality is detected in the transmission of the storage data; controlling the register module to obtain the queue pointer information of the host; storing the obtained queue pointer information in the initialized storage data forwarding module; sending a retransmission instruction to the initialized storage data forwarding module; and further performing a data retransmission operation of the storage data according to the received retransmission instruction through the initialized storage data forwarding module to transmit the storage data to the back end without loss. The use of this method can realize lossless data transmission and improve the stability and robustness of the system.

Description

Technical Field

[0001] The present application relates to the field of big data technology, and in particular to a data transmission processing system, method, apparatus, computer equipment, storage medium and computer program product. Background Art

[0002] With the development of social technology, the demand for big data processing scenarios has increased, such as cloud application scenarios. More and more users are using cloud application-related products, such as cloud computers and cloud computing, which are cost-saving, convenient, easy to manage, and safer to use. As this demand grows rapidly, the performance requirements for underlying transmission equipment are getting higher and higher. For example, the transmission of network and storage data needs to have high bandwidth, low latency, high reliability and other characteristics.

[0003] This strong demand has promoted the development of basic hardware equipment, such as the birth of smart network cards, which play an important role in accelerating the transmission and processing of big data with the help of the data transmission acceleration characteristics of smart network cards. If an exception occurs when the smart network card is transmitting data, such as network congestion or hardware failure of the smart network card, data will be lost or damaged, resulting in the failure of data to be successfully transmitted to the destination. Summary of the invention

[0004] Based on this, it is necessary to provide a data transmission processing system, method, device, computer equipment, computer-readable storage medium and computer program product that can solve the problem of data transmission errors in smart network cards in response to the above technical problems.

[0005] In a first aspect, the present application provides a data transmission processing system. The system includes: a host, a network card connected to the host, and a backend connected to the network card; the network card includes an FPGA chip and a SOC chip; the FPGA chip includes a storage data forwarding module and a register module;

[0006] The storage data forwarding module is used to transmit the storage data received from the host to the back end;

[0007] The SOC chip is used to control the initialization of the storage data forwarding module if an abnormality is detected in the transmission of the storage data; control the register module to obtain the queue pointer information of the host; store the obtained queue pointer information in the initialized storage data forwarding module; and send a retransmission instruction to the initialized storage data forwarding module;

[0008] The initialized storage data forwarding module is further used to perform a data retransmission operation of the storage data according to the received retransmission instruction, so as to transmit the storage data losslessly to the back end.

[0009] In one of the embodiments, the register module further includes a read-write register; the storage data forwarding module further includes a memory module;

[0010] The SOC chip is further used to control the read / write register to perform a memory read operation on the host to obtain queue pointer information of the host;

[0011] The FPGA chip is also used to actively write the queue pointer information into the memory module to update the pointer information in the memory module.

[0012] In one embodiment, the read / write register further includes a DMA read bus module, a low address register, a high address register, an enable register, and a data register;

[0013] The SOC chip is further used to write the memory address information of the host into the low address register and the high address register;

[0014] The low address register and the high address register are further used to transmit the received memory address information to the DMA read bus module;

[0015] The DMA read bus module is further used to perform a memory read operation on the host according to the received memory address information, store the read queue pointer information in the data register, and set the corresponding value in the enable register as the target value;

[0016] The SOC chip is further configured to obtain the queue pointer information in the data register if it is detected that the corresponding value in the enable register is set to the target value;

[0017] The FPGA chip is also used to clear the corresponding value in the enable register to zero after the SOC chip detects that the corresponding value in the enable register is set to the target value.

[0018] In one of the embodiments, the register module further includes a valid pointer register and a used pointer register;

[0019] The SOC chip is further used to store the valid pointer information in the queue pointer information into the valid pointer register, and to store the used pointer information in the queue pointer information into the used pointer register;

[0020] The FPGA chip is also used to write the valid pointer information in the valid pointer register and the used pointer information in the used pointer register into the memory module if it is detected that there are values ​​in the valid pointer register and the used pointer register.

[0021] In one of the embodiments, the register module further includes a retransmission register; the memory module further includes a first valid pointer memory, a second valid pointer memory, a used pointer memory, a comparator and a retransmission start module;

[0022] The SOC chip is further used to update the value in the retransmission register to a retransmission value after storing the acquired queue pointer information in the initialized storage data forwarding module;

[0023] The register module is further used to generate the retransmission instruction according to the received retransmission value and send it to the memory module;

[0024] The memory module is also used to store the used pointer information in the used pointer memory into the second valid pointer memory in response to the received retransmission instruction, and compare whether the information in the first valid pointer memory and the second valid pointer memory are the same through the comparator; if the comparison shows that the information in the first valid pointer memory and the second valid pointer memory are different, control the retransmission start module to perform a data retransmission operation on the stored data based on the used pointer information.

[0025] In one of the embodiments, the register module further includes a reset register;

[0026] The SOC chip is further used to control the reset register to send a reset instruction to the storage data forwarding module if it is detected that the transmission of the storage data is abnormal due to the storage data forwarding module and / or the back end;

[0027] The stored data forwarding module is further used to clear the currently running data and restore to an initial state according to the received reset instruction.

[0028] In a second aspect, the present application provides a data transmission processing method. The method comprises:

[0029] Transmitting the received storage data from the host connected to the network card to the back end, and if an abnormality is detected in the transmission of the storage data, initializing the storage data forwarding module in the network card;

[0030] Obtaining queue pointer information of the host;

[0031] According to the queue pointer information, updating the pointer information in the initialized storage data forwarding module;

[0032] The initialized storage data forwarding module performs a storage data retransmission operation to transmit the storage data of the network card to the back end without loss.

[0033] In a third aspect, the present application also provides a data transmission processing device. The device comprises:

[0034] An abnormality monitoring unit, used for transmitting the storage data received from the host connected to the network card to the back end, and initializing the storage data forwarding module in the network card if an abnormality is detected in the transmission of the storage data;

[0035] A pointer acquisition unit, used to acquire queue pointer information of the host;

[0036] A pointer updating unit, used to update the pointer information in the initialized storage data forwarding module according to the queue pointer information;

[0037] The data retransmission unit is used to perform a storage data retransmission operation through the initialized storage data forwarding module to transmit the storage data of the network card to the back end without loss.

[0038] In a fourth aspect, the present application further provides a computer device. The computer device includes a memory and a processor, the memory stores a computer program, and the processor implements the following steps when executing the computer program:

[0039] Transmitting the received storage data from the host connected to the network card to the back end, and if an abnormality is detected in the transmission of the storage data, initializing the storage data forwarding module in the network card;

[0040] Obtaining queue pointer information of the host;

[0041] According to the queue pointer information, updating the pointer information in the initialized storage data forwarding module;

[0042] The initialized storage data forwarding module performs a storage data retransmission operation to transmit the storage data of the network card to the back end without loss.

[0043] In a fifth aspect, the present application further provides a computer-readable storage medium. The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the following steps are implemented:

[0044] Transmitting the received storage data from the host connected to the network card to the back end, and if an abnormality is detected in the transmission of the storage data, initializing the storage data forwarding module in the network card;

[0045] Obtaining queue pointer information of the host;

[0046] According to the queue pointer information, updating the pointer information in the initialized storage data forwarding module;

[0047] The initialized storage data forwarding module performs a storage data retransmission operation to transmit the storage data of the network card to the back end without loss.

[0048] In a sixth aspect, the present application further provides a computer program product. The computer program product includes a computer program, and when the computer program is executed by a processor, the following steps are implemented:

[0049] Transmitting the received storage data from the host connected to the network card to the back end, and if an abnormality is detected in the transmission of the storage data, initializing the storage data forwarding module in the network card;

[0050] Obtaining queue pointer information of the host;

[0051] According to the queue pointer information, updating the pointer information in the initialized storage data forwarding module;

[0052] The initialized storage data forwarding module performs a storage data retransmission operation to transmit the storage data of the network card to the back end without loss.

[0053] The above-mentioned data transmission processing system, method, device, computer equipment, storage medium and computer program product transmit the storage data received from the host to the back end through the storage data forwarding module in the FPGA chip; through the SOC chip, when the storage data transmission is detected to be abnormal, the storage data forwarding module is controlled to be initialized; the register module is controlled to obtain the queue pointer information of the host; the obtained queue pointer information is stored in the initialized storage data forwarding module; a retransmission instruction is sent to the initialized storage data forwarding module; and further, through the initialized storage data forwarding module, according to the received retransmission instruction, a data retransmission operation of the storage data is performed to transmit the storage data to the back end without loss. The use of this system can realize the rapid recovery of the network channel and perform the retransmission operation of the storage data when an abnormality occurs in the storage data transmission, so as to achieve the effect of lossless data transmission, thereby improving the stability and robustness of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 An application environment diagram of a data transmission processing system in one embodiment;

[0055] Figure 2 The figure is a flow chart of a SOC chip accessing a host memory in one embodiment;

[0056] Figure 3 is a schematic diagram of the composition of a memory module in one embodiment;

[0057] Figure 4A schematic diagram of a flow chart of a data transmission processing method in an embodiment;

[0058] Figure 5 A schematic diagram of a flow chart of a data transmission processing method in another embodiment;

[0059] Figure 6 is a structural block diagram of a data transmission processing device in one embodiment;

[0060] Figure 7 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0061] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0062] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.

[0063] The data transmission processing method provided in the embodiment of the present application can be applied to Figure 1 In the application environment shown in the figure. The network card is connected to the external Host through the PCIE (Peripheral Component Interconnect Express, peripheral device high-speed connection standard) bus. Among them, PCIE is an end-to-end interconnection protocol that provides a high-speed transmission bandwidth solution. At present, PCIe has developed to the fourth generation PCIe4.0. The most obvious feature of each generation of development is that the rate doubles. The smart network card also uses the SFP module (the SFP module is a miniaturized, hot-swappable optical transceiver module, mainly used for optical communication applications in telecommunications and data communications) to connect to the remote device using the optical module fiber. The smart network card DPU is a bridge between the host and the remote device.

[0064] In one embodiment, a data transmission processing system is provided, the system comprising: Figure 1The host and the network card connected to the host also include a back end connected to the network card; the network card includes an FPGA chip and a SOC chip; the FPGA chip includes a storage data forwarding module and a register module; specifically includes the following steps: the storage data forwarding module is used to transmit the storage data received from the host to the back end; the SOC chip is used to control the initialization of the storage data forwarding module if an abnormality is detected in the transmission of the storage data; the register module is controlled to obtain the queue pointer information of the host; the obtained queue pointer information is stored in the initialized storage data forwarding module; a retransmission instruction is sent to the initialized storage data forwarding module; the initialized storage data forwarding module is also used to perform a data retransmission operation of the storage data according to the received retransmission instruction, so as to transmit the storage data to the back end without loss.

[0065] Among them, the network card may refer to an intelligent network card based on an FPGA chip. Compared with a conventional network card, an intelligent network card can offload some CPU work to the DPU of the intelligent network card to save CPU core overhead, thereby improving data processing efficiency, and the intelligent network card DPU can support virtualized device data transmission. Through virtualization processing on the intelligent network card DPU, a physical machine can support hundreds or thousands of users at the same time, greatly improving the utilization rate of the device. The intelligent network card DPU also has the characteristics of data transmission acceleration. It uses a PCIE interface to connect to the CPU and uses an optical port device to connect to external devices. It has the characteristics of high bandwidth and low latency, and plays an important role in accelerating the transmission and processing of big data.

[0066] Among them, FPGA (Field Programmable Gate Array) chip is a chip that can reconfigure circuits and is a hardware reconfigurable architecture.

[0067] Among them, SOC (System on Chip) is called system-level chip, also known as system on chip, which means it is a product, an integrated circuit with a dedicated purpose, which contains all the contents of the complete system and embedded software.

[0068] Among them, CPU (Central Processing Unit) is the computing and control core of the computer system and the final execution unit for information processing and program running.

[0069] Among them, DPU (Data Processing Unit) is a dedicated processor in data center scenarios, providing a computing engine for high-bandwidth, low-latency, and data-intensive computing scenarios.

[0070] Specifically, the storage data forwarding module may be Figure 1 In virtio_blk, the storage data forwarding module is the main transmission channel for storage data. Its main function is to parse the host-side instructions and storage data through the storage data forwarding module and transmit them to the backend. It also receives feedback information from the backend and transmits it to the host. If the SOC chip detects that an abnormality has occurred in the data transmission process of the storage data, the function of the storage data forwarding module can be restored first, and then the storage data forwarding module can be retransmitted: the storage data forwarding module can be controlled to start the reset operation, initialized, and then the register module can be controlled through the set script command to obtain the queue pointer information of the host, and then the obtained queue pointer information is stored in the initialized storage data forwarding module, and a retransmission instruction is sent to the initialized storage data forwarding module. Then, the initialized storage data forwarding module performs the data retransmission operation of the storage data according to the received retransmission instruction to achieve lossless transmission of the storage data to the backend.

[0071] Among them, the register module can be Figure 1 The csr in the register module is used to store some control, statistics and status registers. Its main function is to connect the host side and the SOC chip side driver, and can realize the initialization process control of the storage data forwarding module. The register module is also an important conversion channel for the SOC chip to control the FPGA chip. The SOC chip can indirectly control the work of the FPGA and obtain related information by reading and writing some registers set by the register module.

[0072] In the above data transmission processing system, the storage data received from the host is transmitted to the back end through the storage data forwarding module in the FPGA chip; through the SOC chip, when an abnormality is detected in the transmission of the storage data, the storage data forwarding module is controlled to be initialized; the register module is controlled to obtain the queue pointer information of the host; the obtained queue pointer information is stored in the initialized storage data forwarding module; a retransmission instruction is sent to the initialized storage data forwarding module; and further, the initialized storage data forwarding module is used to perform a data retransmission operation of the storage data according to the received retransmission instruction, so as to transmit the storage data to the back end without loss. The use of this system can realize the rapid recovery of the network channel and perform the retransmission operation of the storage data when an abnormality occurs in the storage data transmission, so as to achieve the effect of lossless data transmission, thereby improving the stability and robustness of the system.

[0073] In one embodiment, the register module further includes a read-write register; the storage data forwarding module further includes a memory module. The SOC chip is further used to control the read-write register to perform a memory read operation on the host to obtain the queue pointer information of the host; the FPGA chip is further used to actively write the queue pointer information into the memory module to update the pointer information in the memory module.

[0074] Specifically, the SOC chip controls the read / write registers to make the FPGA chip generate a memory read operation on the host, which is equivalent to the SOC chip indirectly reading the queue pointer information in the host memory. Then the SOC chip writes the read queue pointer information to the memory module in the storage data forwarding module again to update the valid pointer information (such as avail_index) and used pointer information (such as used_index) in the memory module. The memory module can be Figure 1 in index_ram.

[0075] In this embodiment, the SOC chip controls the read-write register to perform a memory read operation on the host to obtain the queue pointer information of the host, and then uses the queue pointer information to update the pointer information in the memory module, thereby realizing the alignment of the pointer information inside the FPGA chip with the queue pointer information driven by the host side, laying the foundation for subsequent data retransmission operations.

[0076] In one embodiment, the read-write register also includes a DMA read bus module, a low address register, a high address register, an enable register and a data register. The SOC chip is also used to write the host's memory address information into the low address register and the high address register; the low address register and the high address register are also used to transmit the received memory address information to the DMA read bus module; the DMA read bus module is also used to perform a memory read operation on the host according to the received memory address information, store the read queue pointer information into the data register, and set the corresponding value in the enable register to the target value; the SOC chip is also used to obtain the queue pointer information in the data register if it detects that the corresponding value in the enable register is set to the target value; the FPGA chip is also used to clear the corresponding value in the enable register to zero after the SOC chip detects that the corresponding value in the enable register is set to the target value.

[0077] Among them, the DMA (Direct Memory Access) read bus module refers to a high-speed transmission operation that allows direct reading and writing of data between external devices and memories, and between memories. The transmission process neither passes through the CPU nor requires CPU intervention. The entire data transmission operation is carried out under the control of a "DMA controller".

[0078] Specifically, Figure 2This is a flow chart of the SOC chip accessing the host Host memory. In the csr module, there are 4 groups of registers, namely low address, high address, enable, and data, which are all 32-bit wide registers. The low address and high address together form a 64-bit wide address, which represents the address to be accessed from the host Host memory. These two address registers are assigned and written by the SOC chip. The enable register indicates whether the data register is valid. When the enable register value is 1, it means that the data read back from the host Host has been stored in the data register. When the SOC chip reads the enable register and finds that its value is 1, it immediately reads the value in the data register. This data is the value read back from the host Host memory.

[0079] like Figure 2 As shown, in the register module csr, there is a DMA read bus module, whose main function is to convert the operation timing of 4 groups of registers into the DMA read interface timing, so that it can connect to the pcie_tlp interface and access the host Host memory.

[0080] according to Figure 2 As shown, the operation process of the SOC chip accessing the host host memory is as follows:

[0081] (1) First, the SOC chip will prepare to read the host host memory address information, such as the address of the queue pointer information, and write it to the low address register and high address register of the register module csr;

[0082] (2) After the register module csr receives the high address and low address information, it will pass it to the DMA read bus module and convert it into a DMA read operation to read the host host memory operation. When the DMA read returns, the read value is placed in the data register. And the corresponding value of the enable register is set to 1;

[0083] (3) On the SOC chip side, after writing the low-address register and high-address register of the register module csr, it will intermittently check once every short period of time whether the value corresponding to the enable register is 1. Generally, it will be checked 10 times in a cycle. When its value is 1, it means that the FPGA has read the value of the host host memory. At this time, the SOC chip will actively read the value in the data register again as the final valid return value.

[0084] (4) When the FPGA chip detects that the SOC chip reads the enable register as 1, it will actively clear the enable register to prevent the SOC chip from misreading it next time.

[0085] In this embodiment, the register module csr inside the FPGA chip is controlled by the SOC chip. By reading and writing the registers with four consecutive addresses, the FPGA chip actively reads the host memory pointer information and returns it to the SOC chip, thereby realizing the effective reading of the queue pointer data in the host side memory and the synchronization of the pointer information inside the smart network card, providing a reliable processing basis for the subsequent initiation of retransmission operations.

[0086] In one embodiment, the register module further includes a valid pointer register and a used pointer register. The SOC chip is further used to store the valid pointer information in the queue pointer information into the valid pointer register, and to store the used pointer information in the queue pointer information into the used pointer register; the FPGA chip is further used to write the valid pointer information in the valid pointer register and the used pointer information in the used pointer register into the memory module if it is detected that there are values ​​in the valid pointer register and the used pointer register.

[0087] Specifically, Figure 1 As shown in the figure, the queue pointer information on the host side obtained by the SOC chip mainly includes the valid pointer information avail_index and the used pointer information used_index, and writes these queue pointer information to two registers in the csr module, namely the valid pointer register avail_index_reg and the used pointer register used_index_reg. When the FPGA detects that both registers have values, it will actively write these two values ​​to the memory module index_ram through the wr_index bus, and the data is stored in the ram unit corresponding to the memory module index_ram.

[0088] In this embodiment, the SOC chip will obtain the queue pointer information, and write the queue pointer information to the memory module index_ram through the register module csr, so as to align the pointer information inside the FPGA chip with the pointer information in the host side memory, laying the foundation for subsequent retransmission operations.

[0089] In one embodiment, the register module also includes a retransmission register; the memory module also includes a first valid pointer memory, a second valid pointer memory, a used pointer memory, a comparator and a retransmission start module. The SOC chip is also used to update the value in the retransmission register to the retransmission value after storing the acquired queue pointer information in the initialized storage data forwarding module; the register module is also used to generate a retransmission instruction according to the received retransmission value and send it to the memory module; the memory module is also used to store the used pointer information in the used pointer memory in the second valid pointer memory in response to the received retransmission instruction, and compare the information in the first valid pointer memory and the second valid pointer memory through the comparator to see if they are the same; if the comparison shows that the information in the first valid pointer memory and the second valid pointer memory are different, the retransmission start module is controlled to perform a data retransmission operation on the stored data based on the used pointer information.

[0090] Specifically, the retransmission operation is mainly performed in the memory module index_ram. The memory module index_ram composition diagram is as follows: Figure 3 The memory module index_ram is mainly composed of 3 RAMs, 1 comparator and 1 retransmission start module, among which:

[0091] (1) The first valid pointer memory avail_index_ram_1 is the RAM memory inside the FPGA chip, which is used to store the valid pointer avail_index value written by the SOC chip. The avail_index_1 to avail_index_n units correspond to the valid pointer data of each queue, that is, there are n queues in total.

[0092] (2) The second valid pointer memory avail_index_ram_2: It is the same as the avail_index_ram_1 module, but is used to temporarily cache the count. Moreover, when the memory module index_ram receives the retransmission instruction from the soc, it will actively copy the used pointer used_index in the used_index_ram to the avail_index_ram_2 module in the order of the queue number.

[0093] (3) Used pointer memory used_index_ram: It is the RAM memory inside the FPGA chip, which is used to store the used pointer used_index value written by the SOC chip. The used_index_1 to used_index_n units correspond to the used pointer data of each queue, that is, there are n queues in total.

[0094] (4) Comparator: compares the values ​​in the first valid pointer memory avail_index_ram_1 and the second valid pointer memory avail_index_ram_2 in sequence according to the queue number alignment method, and outputs the pointer data of unequal queues to the retransmission start module.

[0095] (5) Retransmission start module: receives the result from the comparator and initiates the retransmission operation of the corresponding queue.

[0096] The process of data retransmission operation includes:

[0097] (1) After the SOC chip writes the queue pointer information obtained from the host Host to index_ram, the SOC chip will then write a value of 1 to the retransmission register of the register module csr, indicating the initiation of a retransmission instruction. At this time, the register module csr will generate a retransmission signal and transmit it to virtio_blk. After virtio_blk receives the retransmission signal, the index_ram module in it will actively assign the used pointer information used_index in used_index_ram to avail_index_ram_2.

[0098] (2) Then the pointer values ​​in the first valid pointer memory avail_index_ram_1 and the second valid pointer memory avail_index_ram_2 are output to the comparator in sequence according to the queue numbers from 1 to n, and the two values ​​are compared to see if they are the same. If they are not equal, the used pointer information used_index of this queue is transmitted to the retransmission start module.

[0099] (3) In the retransmission startup module, the current used pointer is used as the starting point, triggering the storage data forwarding module virtio_blk to obtain the storage data of the corresponding pointer from the host Host starting from the starting point. Every time a complete storage data is obtained, the starting point is accumulated by 1, and this starting point value is updated back to avail_index_ram_2 in time.

[0100] (4) After the comparison retransmission from queue 0 to queue n is completed, the value of the valid pointer information avail_index in the second valid pointer memory avail_index_ram_2 is updated again. At this time, the process (2) will be executed again. Until it is finally detected that the stored values ​​of the same queue in the first valid pointer memory avail_index_ram_1 and the second valid pointer memory avail_index_ram_2 are equal, that is, the comparator has no output, then the retransmission is completed.

[0101] At this point, the entire system has returned to normal, and the storage data forwarding module virtio_blk can continue to transmit new storage data.

[0102] In this embodiment, when an abnormality occurs in the transmission system, the stored data is retransmitted, thereby achieving the effect of lossless data transmission, thereby improving the stability and robustness of the system.

[0103] In one embodiment, the register module further includes a reset register. The SOC chip is further used to control the reset register to send a reset instruction to the storage data forwarding module if it is detected that the storage data forwarding module and / or the back end causes an abnormality in the transmission of the storage data; the storage data forwarding module is further used to clear the currently running data and restore to the initial state according to the received reset instruction.

[0104] It should be noted that there are usually two situations where there are abnormalities in the transmission of stored data:

[0105] First, the storage data forwarding module virtio_blk inside the FPGA is abnormally blocked, resulting in the failure of normal transmission of storage data. This may be caused by a potential design problem of the storage data forwarding module or a problem caused by the front-end and back-end interaction.

[0106] The second is that the transmission anomaly on the back end causes storage data loss or errors, causing the host side to be unable to receive the completion status returned by the back end, and also unable to detect the update of the queue pointer, resulting in host-side driver anomalies.

[0107] When these situations occur, reset instructions can be used to perform active error correction, thereby achieving lossless transmission of stored data. Specifically, the SOC chip can control the register module csr in the FPGA chip through the PCIE bus. The register module csr mainly stores various configuration and statistical registers, and classifies the registers by address arrangement. Among them, the reset register of the storage data forwarding module virtio_blk is among them. The reset register is named blk_reset_reg and is 32 bits wide. When the SOC chip writes 1 to the reset register blk_reset_reg, the reset register blk_reset_reg will output a high-level signal to the outside, which lasts for 400 nanoseconds. After 400 nanoseconds, the level signal will be pulled low. This level signal is named blk_reset (such as Figure 1 As shown), the level signal blk_reset is directly connected to the storage data forwarding module virtio_blk, and the level signal blk_reset is used as a reset instruction of the storage data forwarding module.

[0108] When the storage data forwarding module virtio_blk receives the level signal blk_reset and pulls it high, it means that the reset instruction starts to execute, and then the storage data forwarding module virtio_blk actively clears all the registers, buffers, and state machines inside its module, and other initialization operations. At this time, even if there are running data flows or control operations, they will be forcibly interrupted and cleared. The advantage of this is that whether it is a normal state or an error state, it can be restored to the initial state to achieve the effect of clearing the error. Of course, there are also disadvantages, that is, the normal storage data flow and control commands are also forcibly cleared, resulting in data loss. However, this problem can be solved in the next few steps to retransmit the lost storage data.

[0109] When the storage data forwarding module virtio_blk receives the level signal blk_reset and pulls it low, it means that the reset is over. At this time, the internal part of the storage data forwarding module virtio_blk is in the initial state. However, one point to emphasize here is that after the reset is over, the input and output of the storage data forwarding module virtio_blk will be specially processed.

[0110] For example, the input interface of the storage data forwarding module virtio_blk will discard data. For example, when data is received from Figure 1 If the data is input from the pcie_tlp module in the virtio_net_blk module or the data is input from the virtio_blk module, it will be discarded at the input interface of the storage data forwarding module virtio_blk, and it cannot be transmitted to the module. It will keep the initial state until the subsequent retransmission operation starts and it will run normally. Among them, the pcie_tlp module: the main function is to connect the pcie driver on the host side and the virtio on the FPGA side, etc., to convert and transmit the data format, and also includes interrupt mapping, etc. The virtio_net_blk module is equivalent to a transit interface module. The main function is to send the data of virtio_blk to the SOC chip, and then forward the TCP message parsed by the SOC chip to the optical port. At the same time, the TCP message from the optical port is received, sent to the SOC chip for parsing, and then the parsed information is forwarded to virtio_blk.

[0111] The output interface of the storage data forwarding module virtio_blk will perform data integrity detection and protection. For example, there is a cache space where the virtio_blk module outputs data to the pcie_tlp module. This space will perform data integrity detection. If the data transmission is generally truncated due to the impact of reset, and the data packet output from virtio_blk is incomplete, the cache space will be detected and discarded again, and the residual packet will not be transmitted to the pcie_tlp module, protecting it from being affected.

[0112] In this embodiment, by monitoring whether the transmission of stored data generates an abnormality, when an abnormality is detected, a reset instruction can be sent to the stored data forwarding module by controlling the reset register to restore the stored data forwarding module to an initialized state, thereby laying the foundation for subsequent data retransmission operations.

[0113] In one embodiment, Figure 4 As shown, a data transmission processing method is provided. In this embodiment, the method is applied to Figure 1 In this embodiment, the method includes the following steps:

[0114] Step S401, the storage data received from the host connected to the network card is transmitted to the back end, and if it is detected that the transmission of the storage data is abnormal, the storage data forwarding module in the network card is initialized.

[0115] Step S402, obtaining the host's queue pointer information.

[0116] Step S403: updating the pointer information in the initialized storage data forwarding module according to the queue pointer information.

[0117] Step S404: performing a storage data retransmission operation through the initialized storage data forwarding module to transmit the storage data of the network card to the back end without loss.

[0118] The specific processing process is shown in the above embodiment and will not be described in detail here.

[0119] In the above data transmission processing method, if an abnormality is detected in the storage data forwarding module in the FPGA chip of the network card, the storage data forwarding module is initialized; the queue pointer information of the host connected to the network card is obtained; and the storage data forwarding module is used to perform a storage data retransmission operation to transfer the storage data of the network card to the host without loss. By adopting this method, when an abnormality occurs in the storage data transmission, the network channel can be quickly restored, and the storage data retransmission operation can be performed to achieve the effect of lossless data transmission, thereby improving the stability and robustness of the system.

[0120] In order to more clearly illustrate the data transmission processing method provided by the embodiment of the present disclosure, the data transmission processing method is specifically described below with a specific embodiment. Figure 5 As shown, another data transmission processing method is provided, which can be applied to Figure 1 The network card in the system includes the following:

[0121] (1) The operation and maintenance department monitors virtio_blk for abnormalities. If an abnormality occurs, such as one of the two error conditions described above, human intervention is required to start the error correction function.

[0122] (2) Manually execute commands to control the soc to start the reset operation on virtio_blk, initialize it, and implement error correction.

[0123] (3) After executing step (2), the system will automatically execute the set script command to control the soc to read the host side queue pointer information and write this information to the index_ram module.

[0124] (4) After executing step (3), the system will automatically execute the set script command to control the soc to initiate a retransmission instruction to virtio_blk.

[0125] (5) After the FPGA receives the retransmission instruction, vrtio_blk will actively initiate the retransmission operation of the stored data to achieve lossless transmission of the stored data.

[0126] The above data transmission processing method can achieve the following beneficial effects: using basic hardware such as smart network cards, for the scenario of storage data transmission, it is proposed to actively reset the FPGA storage data interaction module, realign the host and FPGA pointer information, and finally start the retransmission of the storage data. It solves the recovery problem when the storage-related module in the FPGA is abnormal, retransmits the lost or erroneous storage data, and achieves the effect of lossless transmission.

[0127] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0128] Based on the same inventive concept, the embodiment of the present application also provides a data transmission processing device for implementing the data transmission processing method involved above. The implementation solution provided by the device to solve the problem is similar to the implementation solution recorded in the above method, so the specific limitations in the one or more data transmission processing device embodiments provided below can refer to the limitations of the data transmission processing method above, and will not be repeated here.

[0129] In one embodiment, Figure 6 As shown, a data transmission processing device 600 is provided, comprising: an abnormality monitoring unit 601, a pointer acquisition unit 602, a pointer update unit 603 and a data retransmission unit 604, wherein:

[0130] The abnormality monitoring unit 601 is used to transmit the storage data received from the host connected to the network card to the back end, and initialize the storage data forwarding module in the network card if an abnormality is detected in the transmission of the storage data.

[0131] The pointer acquisition unit 602 is used to acquire the queue pointer information of the host.

[0132] The pointer updating unit 603 is used to update the pointer information in the initialized storage data forwarding module according to the queue pointer information.

[0133] The data retransmission unit 604 is used to perform a storage data retransmission operation through the initialized storage data forwarding module to transmit the storage data of the network card to the back end without loss.

[0134] Each module in the above-mentioned data transmission processing device can be implemented in whole or in part by software, hardware or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute operations corresponding to each module above.

[0135] In one embodiment, a computer device is provided. The computer device may be a smart network card, and its internal structure diagram may be as follows: Figure 7As shown. The computer device includes a processor, a memory, an input / output interface (Input / Output, referred to as I / O) and a communication interface. The processor, the memory and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store data. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a data transmission processing method is implemented.

[0136] Those skilled in the art will understand that Figure 7 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0137] In one embodiment, a computer device is further provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the steps in the above method embodiments when executing the computer program.

[0138] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments are implemented.

[0139] In one embodiment, a computer program product is provided, including a computer program, which implements the steps in the above method embodiments when executed by a processor.

[0140] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited to this.

[0141] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0142] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A data transmission processing system, characterized in that: The system comprises: a host, a network card connected to the host, and a backend connected to the network card for communication; the network card comprises an FPGA chip and a SOC chip; the FPGA chip comprises a storage data forwarding module and a register module; The storage data forwarding module is used to transmit the storage data received from the host to the back end; The SOC chip is used to control the initialization of the storage data forwarding module if an abnormality is detected in the transmission of the storage data; control the register module to obtain the queue pointer information of the host; store the obtained queue pointer information in the initialized storage data forwarding module; and send a retransmission instruction to the initialized storage data forwarding module; The initialized storage data forwarding module is further used to perform a data retransmission operation of the storage data according to the received retransmission instruction, so as to transmit the storage data losslessly to the back end.

2. The system according to claim 1, characterized in that The register module also includes a read-write register; the storage data forwarding module also includes a memory module; The SOC chip is further used to control the read / write register to perform a memory read operation on the host to obtain queue pointer information of the host; The FPGA chip is also used to actively write the queue pointer information into the memory module to update the pointer information in the memory module.

3. The system according to claim 2, characterized in that The read-write register also includes a DMA read bus module, a low address register, a high address register, an enable register and a data register; The SOC chip is further used to write the memory address information of the host into the low address register and the high address register; The low address register and the high address register are further used to transmit the received memory address information to the DMA read bus module; The DMA read bus module is further used to perform a memory read operation on the host according to the received memory address information, store the read queue pointer information in the data register, and set the corresponding value in the enable register as the target value; The SOC chip is further configured to obtain the queue pointer information in the data register if it is detected that the corresponding value in the enable register is set to the target value; The FPGA chip is also used to clear the corresponding value in the enable register to zero after the SOC chip detects that the corresponding value in the enable register is set to the target value.

4. The system according to claim 2, characterized in that The register module also includes a valid pointer register and a used pointer register; The SOC chip is further used to store the valid pointer information in the queue pointer information into the valid pointer register, and to store the used pointer information in the queue pointer information into the used pointer register; The FPGA chip is also used to write the valid pointer information in the valid pointer register and the used pointer information in the used pointer register into the memory module if it is detected that there are values ​​in the valid pointer register and the used pointer register.

5. The system according to claim 4, characterized in that The register module also includes a retransmission register; the memory module also includes a first valid pointer memory, a second valid pointer memory, a used pointer memory, a comparator and a retransmission start module; The SOC chip is further used to update the value in the retransmission register to a retransmission value after storing the acquired queue pointer information in the initialized storage data forwarding module; The register module is further used to generate the retransmission instruction according to the received retransmission value and send it to the memory module; The memory module is also used to store the used pointer information in the used pointer memory into the second valid pointer memory in response to the received retransmission instruction, and compare whether the information in the first valid pointer memory and the second valid pointer memory are the same through the comparator; if the comparison shows that the information in the first valid pointer memory and the second valid pointer memory are different, control the retransmission start module to perform a data retransmission operation on the stored data based on the used pointer information.

6. The system according to claim 1, characterized in that The register module also includes a reset register; The SOC chip is further used to control the reset register to send a reset instruction to the storage data forwarding module if it is detected that the transmission of the storage data is abnormal due to the storage data forwarding module and / or the back end; The stored data forwarding module is further used to clear the currently running data and restore to an initial state according to the received reset instruction.

7. A data transmission processing method, characterized in that: The method comprises: Transmitting the received storage data from the host connected to the network card to the back end, and if an abnormality is detected in the transmission of the storage data, initializing the storage data forwarding module in the network card; Obtaining queue pointer information of the host; According to the queue pointer information, updating the pointer information in the initialized storage data forwarding module; The initialized storage data forwarding module performs a storage data retransmission operation to transmit the storage data of the network card to the back end without loss.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to claim 7 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to claim 7 are implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to claim 7 are implemented.

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