PSE system supporting dual-feature load detection and multi-pulse power grading

Abstract

The invention discloses a PSE system supporting double-feature load detection and multi-pulse power grading, and belongs to the technical field of power supply equipment. The PSE system includes: a power source; the double-feature active detection module is used for detecting whether a load is accessed or not and whether the accessed load is a single-feature load or a double-feature load to obtain a load detection result; the double-path grading module is used for carrying out single-characteristic load power grading or double-characteristic load power grading according to the load detection result, judging the grade of the current load and obtaining a grading result; the double-circuit power supply module is used for supplying power to the load according to the load detection result and the grading result and monitoring the power supply of the load; and the main control module is used for controlling the normal work of each module of the system. According to the invention, a double-path scheme and an eight-line connection scheme of an Ethernet port are provided, the single-feature and double-feature load requirements of an IEEE 802.3 bt specification can be adapted, and meanwhile, multi-level grading is realized, so that accurate power distribution of PSE is facilitated.

Description

Technical Field

[0001] The present invention belongs to the technical field of power supply equipment, and in particular relates to a PSE system supporting dual-signature load detection and multi-pulse power classification. Background Art

[0002] PoE technology (Power over Ethernet) refers to the PSE (Power Sourcing Equipment) identifying and grading PD devices (Powered Devices) to provide power to PD devices that support PoE power supply. Currently, there are standard PSE chip controllers and some MCU-based PSE solutions on the market. These solutions usually use discrete analog devices to build PoE voltage-dividing detection circuits, drive circuits, and power supply circuits. They can all be applied to PSE source devices to achieve identification and power supply of terminal PD devices. However, the existing standard PSE chip controllers and some MCU-based PSE solutions have many shortcomings, mainly: 1) The existing PoE power supply system composed of standard PSE chip controller is expensive; 2) MCU solution PSE equipment uses passive single voltage division detection, which has low detection accuracy and cannot identify capacitive loads. It is easy to misjudge, thus causing power supply abnormalities; 3) Existing MCU solution PSE equipment only supports 4-wire power supply or forced 8-wire power supply, and cannot detect and identify single-signature or dual-signature PDs defined in the IEEE 802.3bt specification; 4) Existing MCU solution PSE equipment does not have a classification function. PoE technology requires PSE and PD to be classified to achieve a better power allocation plan. Summary of the invention

[0003] The present invention aims to solve one of the technical problems in the above-mentioned related art at least to a certain extent.

[0004] To this end, the purpose of the present invention is to provide a PSE system that supports dual-signature load detection and multi-pulse power classification, and proposes an analog PSE design scheme and working process of dual-path active detection, dual-path classification, and dual-path power supply, as well as an 8-wire connection scheme of the PSE design on the Ethernet port, which can adapt to the single-signature and dual-signature load requirements of the IEEE 802.3bt specification.

[0005] In order to solve the above-mentioned technical problems, the present invention is achieved as follows: An embodiment of the present invention provides a PSE system supporting dual-signature load detection and multi-pulse power classification, the PSE system comprising: power supply; The dual-signature active detection module is used to detect whether there is a load connected and whether the connected load is a single-signature load or a dual-signature load, and obtain the load detection result; The dual-path classification module is used to perform single-feature load power classification or dual-feature load power classification according to the load detection result, determine the level of the current load, and obtain the classification result; A dual-channel power supply module is used to supply power to the load and monitor the load power supply according to the load detection results and classification results; The main control module is used to control the normal operation of each module of the system.

[0006] In addition, the PSE system supporting dual-signature load detection and multi-pulse power classification according to the present invention may also have the following additional technical features: In some embodiments, the dual-signature active detection module includes a group A of active detection circuits and a group B of active detection circuits, which are used to detect whether the type of the load belongs to a single-signature or a dual-signature; The first end of the active detection circuit of group A is connected to the main control module, and is used to receive the high and low levels configured by the main control module to perform corresponding work; the second end is connected to the main control module, and is used for the main control module to implement ADC sampling and determine whether the load belongs to a single feature or a dual feature; The first end of the active detection circuit of group B is connected to the main control module, and is used to receive the high and low levels configured by the main control module to perform corresponding work; the second end is connected to the main control module, and is used for the main control module to implement ADC sampling and determine whether the load has a single feature or a dual feature.

[0007] In some embodiments, when the first ends of the active detection circuit group A and the active detection circuit group B are a high level and a low level: if only one of the second ends of the active detection circuits of the two groups A and B detects a voltage signal, the load is judged to be a single feature; if the second ends of the two groups A and B active detection circuits both detect voltage signals, the load is judged to be a dual feature.

[0008] In some of the embodiments, the ADC sampling of the active detection circuits of group A and group B is achieved by using transistors to control on and off and by connecting a current sampling resistor and a voltage regulator in series.

[0009] In some of the embodiments, the characteristic resistance of the load is obtained as follows: The first end of the active detection circuit of group A is configured with a high level, and the first end of the active detection circuit of group B is configured with a low level; the value of the second end of the active detection circuit of group A is recorded as VR1_1, and the value of the second end of the active detection circuit of group B is recorded as VR2_1; The first end of the active detection circuit of group A is configured with a low level, and the first end of the active detection circuit of group B is configured with a high level; the value of the second end of the active detection circuit of group A is recorded as VR1_2, and the value of the second end of the active detection circuit of group B is recorded as VR2_2; The first ends of the active detection circuits of group A and group B are both configured with a low level; the value of the second end of the active detection circuit of group A is recorded as VR1_3, and the value of the second end of the active detection circuit of group B is recorded as VR2_3; The first ends of the active detection circuits of group A and group B are both configured with a high level; the value of the second end of the active detection circuit of group A is recorded as VR1_4, and the value of the second end of the active detection circuit of group B is recorded as VR2_4; If VR2_1=0 and VR1_2=0, the load type is determined to be a single-characteristic load, otherwise it is a dual-characteristic load; The characteristic resistance of the single characteristic load is: R=VZD2 / (((VR1_4+VR2_4)-(VR1_3+VR2_3)) / RS1); The characteristic resistance of the dual-characteristic load is: The characteristic resistance of group A is R A =VZD2 / ((VR1_4-VR1_3) / RS1); The characteristic resistance of group B is R B =VZD2 / ((VR2_4-VR2_3) / RS1); Wherein, VZD2 is the regulated voltage of the voltage regulator tube, and RS1 is the resistance value of the detection current sampling resistor.

[0010] In some of the embodiments, the characteristic capacitance of the load is obtained as follows: The first ends of the active detection circuits of group A and group B are configured as high and low levels, and the voltage stabilization time t0 of the second ends of the active detection circuits of group A and group B is recorded; the characteristic capacitance of the load is calculated as: When the load is single characteristic, the characteristic capacitance is: C=(((VR1_4+VR2_4)-(VR1_3+VR2_3)) / RS1)*t0 / VZD2 When the load is dual-characteristic, the characteristic capacitance is: The characteristic capacitance of group A is C A =((VR1_4-VR1_3) / RS1)*t0 / VZD2; The characteristic capacitance of group B is C B =((VR2_4-VR2_3) / RS1)*t0 / VZD2; Wherein, VZD2 is the regulated voltage of the voltage regulator tube, and RS1 is the resistance value of the detection current sampling resistor.

[0011] In some of the embodiments, the two-way classification module includes a group A classification circuit and a group B classification circuit; The first end of the A group classification circuit is connected to the main control module, and is used to receive the high and low levels configured by the main control module to perform corresponding work; the second end is connected to the main control module, and is used for the main control module to implement ADC sampling and determine the level of the current load; The first end of the B group grading circuit is connected to the main control module, and is used to receive the high and low levels configured by the main control module to perform corresponding work; the second end is connected to the main control module, and is used for the main control module to implement ADC sampling and determine the current load level.

[0012] In some implementation modes, determining the current load level includes: The main control module makes a judgment based on the result of ADC sampling; When the pulse current sampled by the ADC is greater than the first threshold, it is determined as classification failure; When the pulse current sampled by the ADC is not greater than the first threshold, the load is divided into 9 levels.

[0013] In some of the embodiments, the dual power supply module includes a group A power supply circuit and a group B power supply circuit; The first ends of the group A power supply circuit and the group B power supply circuit are respectively connected to the dual-path classification module, and are used to receive the classification result of the dual-path classification module and provide power according to the classification result; The second ends of the group A power supply circuit and the group B power supply circuit are respectively connected to the main control module, and are used to receive the high and low levels configured by the main control module to perform corresponding work; The third ends of the group A power supply circuit and the group B power supply circuit are respectively connected to the main control module, so as to enable the main control module to implement ADC sampling and determine the power of the current load for monitoring.

[0014] In some of the embodiments, the PSE system includes an external 8-wire connector.

[0015] Compared with the prior art, the present invention has at least the following beneficial effects: In the embodiment of the present invention, the PSE system supporting dual-signature load detection and multi-pulse power classification is provided, which improves the support for the latest PoE protocol: each module circuit adopts a dual-path design, which can effectively support the detection, classification, and power supply of the dual-signature load of IEEE 802.3bt, and is compatible with single-path load designs such as IEEE 802.3at and IEEE 802.3af; the dual-path detection module can distinguish and identify single-signature and dual-signature loads; the dual-path classification module realizes the PoE classification function, and can respectively realize 9-level power classification of class0-class8 for PDs with different characteristics, so that the PSE can accurately allocate power; the dual-path power supply module can realize dual-path power supply, especially for dual-signature loads, it can realize independent power supply and power supply monitoring; In the embodiment of the present invention, a PSE system supporting dual-signature load detection and multi-pulse power classification is provided, which improves the detection accuracy of PD signature resistance: the detection module circuit adopts active dual voltage detection, and the theoretical result of the detected characteristic resistance is completely decoupled from the PSE power supply voltage, with higher accuracy; In the embodiment of the present invention, the PSE system supporting dual-signature load detection and multi-pulse power classification is provided, and a PD signature capacitance detection function is added: the detection module circuit adopts active dual voltage detection, which can realize capacitive load detection, can distinguish capacitive loads, and further avoid incorrect power supply; In an embodiment of the present invention, a PSE system supporting dual-signature load detection and multi-pulse power classification is provided, and a new handshake mechanism - PoE classification is added: the signature resistance and capacitance detection of the PD load is the first handshake in the PoE negotiation process, and the classification module circuit realizes the PoE classification function. PoE classification is the second handshake in the PoE negotiation process. If the classification is successful, PoE is allowed to supply power, thereby further avoiding incorrect power supply.

[0016] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A block diagram of an 8-wire analog PSE structure disclosed in one embodiment of the present invention; Figure 2 This is a power supply connection diagram of an 8-wire analog PSE port disclosed in an embodiment of the present invention; Figure 3 A schematic diagram of a dual-signature active detection module circuit disclosed in an embodiment of the present invention; Figure 4 A schematic diagram of a dual-path classification module circuit disclosed in one embodiment of the present invention; Figure 5 The present invention is a schematic diagram of a dual-circuit power supply module circuit disclosed in an embodiment of the present invention. DETAILED DESCRIPTION

[0018] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0019] The embodiments of the present invention are described in detail below through specific embodiments and application scenarios in conjunction with the accompanying drawings.

[0020] The dual-channel design of the present invention is adapted to the high-power single-signature load and dual-signature load requirements of the IEEE 802.3bt specification. The detection, classification, and power supply circuits can also be designed as a single channel to adapt to ordinary low-power single-signature loads (IEEE802.3at and IEEE 802.3af loads). A new active detection circuit design is proposed. By controlling the levels of OUT_0 and OUT_1, the conduction and shutdown of Q1 and Q2 tubes are controlled, so that the detection circuit can provide two sets of detection voltages with different high and low levels to the outside, thereby improving the detection accuracy. A new detection calculation method for the PD signature resistance of the dual-voltage active detection circuit is proposed. The theoretical results are only related to RS and VZD2, and are decoupled from the power supply voltage and other devices. A PD signature capacitance detection method for the dual-voltage active detection circuit is proposed. The theoretical results are only related to RS and VZD2, and are decoupled from the power supply voltage and other devices. A classification circuit is proposed in the analog PSE circuit to realize the second handshake of the PoE negotiation process. A new classification circuit design and the implementation of a multi-pulse classification scheme are proposed. The single-chip microcomputer controls the high and low levels of OUT_10 and OUT_11. A classification result lookup table of each classification current under different classification pulses in the classification process is given. A classification current limiting protection design in the classification circuit is proposed to avoid overcurrent damage to the circuit by illegal PD devices in the classification process. A port power lookup table of different detection and classification results is given.

[0021] See also Figure 1 As shown, in some embodiments of the present invention, a PSE system supporting dual-signature load detection and multi-pulse power classification is provided. The PSE circuit includes a power module, a dual-signature active detection module, a dual-path classification module, a dual-path power supply module and a single-chip microcomputer module. The system composition block diagram of the PSE and the PD device (also called load) is shown in FIG. Figure 1 As shown, the dual-signature active detection module, the dual-path classification module, and the dual-path power supply module are all divided into two groups, A and B, namely the solid line part and the dotted line part in the figure.

[0022] In this embodiment, the working principle and working process of the PSE circuit are as follows: 1) After the power is turned on, set the dual-signature active detection module to access detection mode; 2) The dual-signature active detection module detects whether a PD load is connected through the access detection mode. After identifying that a PD load is connected, the dual-signature active detection module is set to the load detection mode; 3) The dual-signature active detection module performs load detection on the PD load through the load detection mode and returns the PD load detection result. According to the load detection result, the operation continues; When the detection result is a single-signature PD load, the dual-channel classification module is set to a single-signature load power classification mode; When the detection result is a dual-signature PD load, the dual-channel classification module is set to a dual-signature load power classification mode; When the detection result is non-PD load, return to 2); 4) The dual-path classification module executes the single-feature or dual-feature classification process respectively, and after completion, returns the classification result, and continues to perform operations based on the classification result and load detection result; 5) Set the dual power supply module to power-on mode; 6) After the power-on mode ends, set the power supply module to the power supply monitoring mode.

[0023] In some embodiments of the present invention, the external output interfaces of the PSE include S1, S2, and S3. The external 8-wire power supply connection diagram of S1, S2, and S3 is shown in FIG. Figure 2 As shown. Among them, S1 is the positive power supply of PSE; S2 is the common point of group A of active detection module, power classification module and power supply module; S3 is the common point of group B of active detection module, power classification module and power supply module. S1 is connected to the center taps of line pairs 3, 6 and 4, 5 of the network port transformer, which is the positive power supply of load; S2 is connected to the center taps of line pairs 1, 2 of the network port transformer, which is the negative power supply of load group A; S3 is connected to the center taps of line pairs 7, 8 of the network port transformer, which is the negative power supply of load group B.

[0024] See also Figure 3 As shown, in some embodiments of the present invention, in the dual-signature active detection module circuit design, the detection circuit designs of groups A and B are completely consistent, which are used to detect whether the PD device is connected. At the same time, the circuits of groups A and B are designed to detect whether the type of PD belongs to single-signature or dual-signature. OUT_0, OUT_1, IN_0, and IN_1 of the circuit are connected to the single-chip microcomputer, S2 is connected to the collector of transistor Q1 through a voltage regulator, S3 is connected to the collector of transistor Q2 through a voltage regulator, and S1 is connected to the positive pole of the PSE power supply. The IO function of the single-chip microcomputer connected to OUT_0 and OUT_1 is required to be able to output high and low levels; the IO function of the single-chip microcomputer connected to IN_0 and IN_1 is required to be used as input IO and can support ADC sampling.

[0025] In the circuit, the types of devices are as follows: D1 and D2 are voltage regulator tubes, and the voltage regulator voltage is VZD1; D3 and D4 are voltage regulator tubes, and the voltage regulator voltage is VZD2; The resistors R1 and R2 are current sampling resistors with an accuracy of 1% or above, and the resistor is RS1; Q1 and Q2 are NPN transistors; Resistors R3 and R4 are protection resistors.

[0026] In the detection circuit of group A, the base of transistor Q1 is connected in series with the protection resistor R3 and connected to the single-chip microcomputer, and the port is recorded as OUT_0; the emitter of transistor Q1 is divided into two paths, one is connected in series with the detection current sampling resistor R1 and then grounded, and the other is connected in series with the voltage regulator D3 and the voltage regulator D1 as the S2 signal terminal, and at the same time, the collector of transistor Q1 is connected to the middle connection point (also called the center tap) between the voltage regulator D3 and the voltage regulator D1. The detection circuit of group B has a similar structure to the detection circuit of group A. The base of transistor Q2 is connected in series with the protection resistor R4 and connected to the single-chip microcomputer, and the port is recorded as OUT_1; the emitter of transistor Q2 is divided into two paths, one is connected in series with the detection current sampling resistor R2 and then grounded, and the other is connected in series with the voltage regulator D4 and the voltage regulator D2 as the S3 signal terminal, and at the same time, the collector of transistor Q2 is connected to the middle connection point (also called the center tap) between the voltage regulator D4 and the voltage regulator D2. The emitter of transistor Q1 is connected to the single chip microcomputer as signal IN_0; the emitter of transistor Q2 is connected to the single chip microcomputer as signal IN_1 to perform detection current sampling of groups A and B.

[0027] The working principle and workflow of the dual-feature active detection module are as follows: 1. Control OUT_0 to output high level and OUT_1 to output low level. Record the voltage signal ADC values ​​of R1 and R2 as VR1_1 and VR2_1. At this time, the D3 tube of group A is bypassed, the voltage regulation value of group A is VZD1, and the voltage regulation value of group B is VZD1+VZD2. Group B is higher impedance than group A. If the PD is a single-characteristic load, the detection current goes through group A, the R1 resistor can detect the voltage signal, while group B has no current and the R2 resistor cannot detect the voltage signal; if the PD is a dual-characteristic load, groups A and B will have their own detection currents, and the R1 and R2 resistors will have voltage signals.

[0028] 2. Control OUT_0 to output low level and OUT_1 to output high level. Record the voltage signal ADC values ​​of R1 and R2 as VR1_2 and VR2_2. At this time, the D4 tube of group B is bypassed, the voltage regulation value of group A is VZD1+VZD2, and the voltage regulation value of group B is VZD1. Group A is higher impedance than group B. If the PD is a single-characteristic load, the detection current goes through group B, the R2 resistor can detect the voltage signal, while there is no current in group A, and the R1 resistor cannot detect the voltage signal; if the PD is a dual-characteristic load, groups A and B will have their own detection currents, and the R1 and R2 resistors will have voltage signals.

[0029] 3. Control the outputs of OUT_0 and OUT_1 to be low level at the same time; record the ADC values ​​of the voltage signals of R1 and R2 as VR1_3 and VR2_3.

[0030] 4. Control the outputs of OUT_0 and OUT_1 to be high level at the same time; record the ADC values ​​of the voltage signals of R1 and R2 as VR1_4 and VR2_4 at this time; If VR2_1=0 and VR1_2=0, it is a single-signature load. Its characteristic resistance is R=VZD2 / (((VR1_4+VR2_4)-(VR1_3+VR2_3)) / RS1); Others are dual-signature loads, The characteristic resistance of group A is R A =VZD2 / ((VR1_4-VR1_3) / RS1); The characteristic resistance of group B is R B =VZD2 / ((VR2_4-VR2_3) / RS1).

[0031] 5. Control the output of OUT_0 and OUT_1 to high and low levels, and record the voltage stabilization time of R1 and R2 as t0, and the characteristic capacitance of PD can be obtained; When the load is a single characteristic, The characteristic capacitance is C=(((VR1_4+VR2_4)-(VR1_3+VR2_3)) / RS1)*t0 / VZD2 When the load is dual-signature, The characteristic capacitance of group A is C A =((VR1_4-VR1_3) / RS1)*t0 / VZD2; The characteristic capacitance of group B is C B =((VR2_4-VR2_3) / RS1)*t0 / VZD2.

[0032] If the characteristic resistance and capacitance values ​​meet the PoE power supply protocol specifications, it is a valid PD signature.

[0033] In some embodiments of the present invention, see Figure 4 As shown in the figure, in the dual-channel classification module circuit design, the classification circuit designs of Group A and Group B are exactly the same. OUT_10, OUT_11, IN_10, and IN_11 of the circuit are connected to the microcontroller, S2 is connected to the collector of transistor Q11 through a voltage regulator, S3 is connected to the collector of transistor Q12 through a voltage regulator, and S1 is connected to the positive electrode of the PSE power supply. The IO function of the microcontroller connected to OUT_10 and OUT_11 is required to be able to output high and low levels; the IO function of the microcontroller connected to IN_10 and IN_11 is required to be used as input IO and support ADC sampling.

[0034] In the circuit, the types of devices are as follows: D11 and D12 are voltage regulator tubes, and the voltage regulator voltage is VZD3; The resistors R11 and R12 are graded current sampling resistors with an accuracy of 1% or above, and the resistor is RS2; Q11, Q12, Q13, and Q14 are NPN transistors; Resistors R13, R14, R15, and R16 are protection resistors.

[0035] In the grading circuit of group A, the base of transistor Q11 is connected to the microcontroller through a series protection resistor R15, which is recorded as OUT_10; the emitter of transistor Q11 is divided into two paths, one is connected in series with the grading current sampling resistor R11 and then grounded, and the other is connected in series with the protection resistor R13 and then connected to the base of transistor Q13; the emitter of transistor Q13 is grounded, and the collector is connected to the base of transistor Q11; the collector of transistor Q11 is connected in series with the voltage regulator D11 as the S2 signal terminal. The structure of the grading circuit of group B is similar to that of group A. The base of transistor Q12 is connected to the microcontroller through a series protection resistor R16, which is recorded as OUT_11. The emitter of transistor Q12 is divided into two paths, one of which is connected to the ground after being connected to the grading current sampling resistor R12, and the other is connected to the base of transistor Q14 after being connected to the protection resistor R14. The emitter of transistor Q14 is grounded, and the collector is connected to the base of transistor Q12. The collector of transistor Q12 is connected to the voltage regulator D12 in series as the S3 signal terminal. The emitter of transistor Q11 is connected to the microcontroller as signal IN_10, and the emitter of transistor Q12 is connected to the microcontroller as signal IN_11, so as to perform grading current sampling of groups A and B.

[0036] When the PD is a single-signature load, it only needs to control either the A group or the B group of classification circuits to achieve classification work. When the PD is a dual-signature load, the A and B groups of classification circuits need to complete the classification work separately.

[0037] The working principle and working process of the grading module are as follows: when group A is graded, OUT_10 is controlled to realize at most 5 groups of graded pulses.

[0038] The first group of grading pulses: control OUT_10 to a high level, Q11 to conduct, R11 to flow grading current, and record R11 voltage as VR11_1; then control OUT_10 to a low level, Q11 to be cut off; realize the first group of grading pulses. If the grading current Iclass=VR11_1 / RS2 is greater than 45mA, the grading result is grading failure, and no subsequent actions will be performed; if the grading current Iclass is less than 6mA, the grading result is class0, and no subsequent actions will be performed; if the grading current Iclass is greater than 6mA and less than 15mA, the grading result is class1, and no subsequent actions will be performed; if the grading current Iclass is greater than 15mA and less than 23mA, the grading result is class2, and no subsequent actions will be performed; if the grading current Iclass is greater than 23mA and less than 33mA, the grading result is class3, and no subsequent actions will be performed; if the grading current Iclass is greater than 33mA and less than 45mA, the grading result is unknown, and the subsequent actions will continue to be performed, giving a new grading pulse.

[0039] The second set of grading pulses: control OUT_10 to a high level, Q11 to conduct, grading current flows through R11, and the voltage of R11 is recorded as VR11_2; then control OUT_10 to a low level, Q11 to be cut off; the second set of grading pulses is realized. If the grading current Iclass = VR11_2 / RS2 is greater than 45mA or less than 33mA, the grading result is grading failure, and no subsequent actions are performed; if the grading current Iclass is greater than 33mA and less than 45mA, the grading result is unknown, and the subsequent actions are continued to give a new grading pulse.

[0040] The third group of grading pulses: control OUT_10 to a high level, Q11 to conduct, grading current flows through R11, and the voltage of R11 is recorded as VR11_3; then control OUT_10 to a low level, Q11 to be cut off; the third group of grading pulses is realized. If the grading current Iclass = VR11_3 / RS2 is greater than 45mA, the grading result is grading failure, and no subsequent actions are performed; if the grading current Iclass is greater than 33mA and less than 45mA, the grading result is class4, and no subsequent actions are performed; if the grading current Iclass is less than 33mA, the grading result is unknown, and the subsequent actions continue to be performed, giving a new grading pulse.

[0041] The fourth group of grading pulses: control OUT_10 to a high level, Q11 to conduct, grading current flows through R11, and the voltage of R11 is recorded as VR11_4; then control OUT_10 to a low level, and Q11 to be cut off; the fourth group of grading pulses is realized. If the grading current Iclass = VR11_4 / RS2 is greater than 33mA, the grading result is grading failure, and no subsequent actions are performed; if the grading current Iclass is less than 6mA, the grading result is class5, and no subsequent actions are performed; if the grading current Iclass is greater than 6mA and less than 15mA, the grading result is class6, and no subsequent actions are performed; if the grading current Iclass is greater than 15mA and less than 33mA, the grading result is unknown, and subsequent actions continue to be performed, giving a new grading pulse.

[0042] The fifth group of grading pulses: control OUT_10 to a high level, Q11 to be turned on, grading current flows through R11, and the voltage of R11 is recorded as VR11_5; then control OUT_10 to a low level, and Q11 to be turned off; the fifth group of grading pulses is realized. If the grading current Iclass = VR11_5 / RS2 is greater than 33mA or less than 15mA, the grading result is grading failure, and no subsequent actions are performed; if the grading current Iclass is greater than 15mA and less than 23mA, the grading result is class7, and no subsequent actions are performed; if the grading current Iclass is greater than 23mA and less than 33mA, the grading result is class8, and no subsequent actions are performed.

[0043] Under the premise of meeting the requirements of IEEE 802.3bt, the classification current and classification results of each classification pulse are shown in Table 1.

[0044]

[0045] When group B is graded, it is the same as group A, and OUT_11 is controlled to realize 5 groups of pulses of group B graded.

[0046] In the design, the power classification stage requires current limiting protection, which is achieved through negative feedback of classification resistors in the classification circuit, making the design more reliable. The implementation principle is as follows: When Q11 or Q12 is turned on, if overcurrent occurs, the voltage of R11 or R12 will increase, which will cause Q13 and Q14 to be turned on, thereby lowering the base voltage of Q11 and Q12, realizing the current limiting function in the classification stage.

[0047] In some embodiments of the present invention, see Figure 5As shown in the figure, in the dual-power supply module circuit design, the power supply circuit designs of groups A and B are exactly the same. OUT_20, OUT_21, IN_20, and IN_21 of the circuit are connected to the microcontroller, S2 is connected to the drain of group A Q21, S3 is connected to the drain of group B Q22, and S1 is connected to the positive pole of the PSE power supply. The IO function of the microcontroller connected to OUT_20 and OUT_21 is required to be able to output high and low levels; the IO function of the microcontroller connected to IN_20 and IN_21 is required to be used as input IO and support ADC sampling.

[0048] In the circuit, the types of devices are as follows: Q21 and Q22 are N-channel enhancement MOSFETs; R21 and R22 are power sampling resistors; R23 and R24 are protection resistors.

[0049] In the power supply circuit of group A, the gate of MOSFET tube Q21 is connected to the single-chip microcomputer through a series protection resistor R23, the source of MOSFET tube Q21 is connected to the ground after being connected to the power sampling resistor R21, the drain of MOSFET tube Q21 is used as the S2 signal terminal, the source of MOSFET tube Q21 is connected to the single-chip microcomputer as the signal terminal IN_20, and sampling is used to monitor the load status. The power supply circuit of group B is similar to the power supply circuit of group A. The gate of MOSFET tube Q22 is connected to the single-chip microcomputer through a series protection resistor R24, the source of MOSFET tube Q22 is connected to the ground after being connected to the power sampling resistor R22, the drain of MOSFET tube Q22 is used as the S3 signal terminal, the source of MOSFET tube Q22 is connected to the single-chip microcomputer as the signal terminal IN_21, and sampling is used to monitor the load status.

[0050] The working principle and process of the dual-power supply module are as follows: The microcontroller controls OUT_20 or OUT_21 to be high level to control the conduction of Q21 and Q22, thereby realizing the power supply of the A and B group line pairs respectively.

[0051] The MCU samples the voltage analog signals of IN_20 and IN_21, converts them into power information, and monitors the real-time power supply of the PD load for power management.

[0052] Power management is shown in Table 2. You can refer to Table 2 to find the port power.

[0053]

[0054] The corresponding power level is the maximum power information that the design outputs. For single-signature loads, the output power distribution is subject to the output power constraints of both group A and group B and the total power (i.e. the sum of the power of group A and group B). For single-signature loads, the output power distribution is only subject to the output power constraints of group A and group B. If the output power exceeds the power constraint, the load behaves abnormally and the design should cut off the corresponding power supply.

[0055] In the single-chip microcomputer circuit, it is necessary to provide 6 groups of GPIO outputs and 6 groups of ADC inputs for the dual-signature active detection module, the dual-channel classification module, and the dual-channel power supply module respectively.

[0056] The parts not described in detail in the present invention are well-known technologies for those skilled in the art or can be implemented with reference to the existing technologies in the field, and the present invention will not elaborate on them in detail.

[0057] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation modes, which are merely illustrative rather than restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. A PSE system supporting dual-signature load detection and multi-pulse power classification, characterized in that: The PSE system comprises: power supply; The dual-signature active detection module is used to detect whether there is a load connected and whether the connected load is a single-signature load or a dual-signature load, and obtain the load detection result; The dual-path classification module is used to perform single-feature load power classification or dual-feature load power classification according to the load detection result, determine the level of the current load, and obtain the classification result; A dual-channel power supply module is used to supply power to the load and monitor the load power supply according to the load detection results and classification results; The main control module is used to control the normal operation of each module of the system.

2. The PSE system supporting dual-signature load detection and multi-pulse power classification according to claim 1, characterized in that: The dual-signature active detection module includes a group A active detection circuit and a group B active detection circuit, which are used to detect whether the type of the load is single-signature or dual-signature; The first end of the active detection circuit of group A is connected to the main control module, and is used to receive the high and low levels configured by the main control module to perform corresponding work; the second end is connected to the main control module, and is used for the main control module to implement ADC sampling and determine whether the load belongs to a single feature or a dual feature; The first end of the active detection circuit of group B is connected to the main control module, and is used to receive the high and low levels configured by the main control module to perform corresponding work; the second end is connected to the main control module, and is used for the main control module to implement ADC sampling and determine whether the load has a single feature or a dual feature.

3. The PSE system supporting dual-signature load detection and multi-pulse power classification according to claim 2, characterized in that: When the first ends of the active detection circuit group A and the active detection circuit group B are a high level and a low level: if only one of the second ends of the active detection circuits of groups A and B detects a voltage signal, the load is judged to be single-featured; if the second ends of the active detection circuits of groups A and B both detect voltage signals, the load is judged to be dual-featured.

4. The PSE system supporting dual-signature load detection and multi-pulse power classification according to claim 2, characterized in that: The ADC sampling of the active detection circuit of group A and the active detection circuit of group B is achieved by using a transistor to control on and off and by connecting a detection current sampling resistor and a voltage regulator in series.

5. The PSE system supporting dual-signature load detection and multi-pulse power classification according to claim 4, characterized in that: The characteristic resistance of the load is obtained as follows: The first end of the active detection circuit of group A is configured with a high level, and the first end of the active detection circuit of group B is configured with a low level; the value of the second end of the active detection circuit of group A is recorded as VR1_1, and the value of the second end of the active detection circuit of group B is recorded as VR2_1; The first end of the active detection circuit of group A is configured with a low level, and the first end of the active detection circuit of group B is configured with a high level; the value of the second end of the active detection circuit of group A is recorded as VR1_2, and the value of the second end of the active detection circuit of group B is recorded as VR2_2; The first ends of the active detection circuits of group A and group B are both configured with a low level; the value of the second end of the active detection circuit of group A is recorded as VR1_3, and the value of the second end of the active detection circuit of group B is recorded as VR2_3; The first ends of the active detection circuits of group A and group B are both configured with a high level; the value of the second end of the active detection circuit of group A is recorded as VR1_4, and the value of the second end of the active detection circuit of group B is recorded as VR2_4; If VR2_1=0 and VR1_2=0, the load type is determined to be a single-characteristic load, otherwise it is a dual-characteristic load; The characteristic resistance of the single characteristic load is: R=VZD2 / (((VR1_4+VR2_4)-(VR1_3+VR2_3)) / RS1); The characteristic resistance of the dual-characteristic load is: The characteristic resistance of group A is R A =VZD2 / ((VR1_4-VR1_3) / RS1); The characteristic resistance of group B is R B =VZD2 / ((VR2_4-VR2_3) / RS1); Wherein, VZD2 is the regulated voltage of the voltage regulator tube, and RS1 is the resistance value of the detection current sampling resistor.

6. The PSE system supporting dual-signature load detection and multi-pulse power classification according to claim 5, characterized in that: The characteristic capacitance of the load is obtained as: The first ends of the active detection circuits of group A and group B are configured as high and low levels, and the voltage stabilization time t0 of the second ends of the active detection circuits of group A and group B is recorded; the characteristic capacitance of the load is calculated as: When the load is single characteristic, the characteristic capacitance is: C=(((VR1_4+VR2_4)-(VR1_3+VR2_3)) / RS1)*t0 / VZD2 When the load is dual-characteristic, the characteristic capacitance is: The characteristic capacitance of group A is C A =((VR1_4-VR1_3) / RS1)*t0 / VZD2; The characteristic capacitance of group B is C B =((VR2_4-VR2_3) / RS1)*t0 / VZD2; Wherein, VZD2 is the regulated voltage of the voltage regulator tube, and RS1 is the resistance value of the detection current sampling resistor.

7. The PSE system supporting dual-signature load detection and multi-pulse power classification according to claim 1, characterized in that: The dual-path classification module includes a group A classification circuit and a group B classification circuit; The first end of the A group classification circuit is connected to the main control module, and is used to receive the high and low levels configured by the main control module to perform corresponding work; the second end is connected to the main control module, and is used for the main control module to implement ADC sampling and determine the level of the current load; The first end of the B group grading circuit is connected to the main control module, and is used to receive the high and low levels configured by the main control module to perform corresponding work; the second end is connected to the main control module, and is used for the main control module to implement ADC sampling and determine the current load level.

8. The PSE system supporting dual-signature load detection and multi-pulse power classification according to claim 7, characterized in that: The content of judging the current load level includes: The main control module makes a judgment based on the result of ADC sampling; When the pulse current sampled by the ADC is greater than the first threshold, it is determined as classification failure; When the pulse current sampled by the ADC is not greater than the first threshold, the load is divided into 9 levels.

9. The PSE system supporting dual-signature load detection and multi-pulse power classification according to claim 1, characterized in that: The dual-circuit power supply module includes a group A power supply circuit and a group B power supply circuit; The first ends of the group A power supply circuit and the group B power supply circuit are respectively connected to the dual-path classification module, and are used to receive the classification result of the dual-path classification module and provide power according to the classification result; The second ends of the group A power supply circuit and the group B power supply circuit are respectively connected to the main control module, and are used to receive the high and low levels configured by the main control module to perform corresponding work; The third ends of the group A power supply circuit and the group B power supply circuit are respectively connected to the main control module, so as to enable the main control module to implement ADC sampling and determine the power of the current load for monitoring.

10. The PSE system supporting dual-signature load detection and multi-pulse power classification according to claim 1, characterized in that: The PSE system has an external 8-wire connector.

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