Semiconductor device and preparation method thereof

Abstract

The invention provides a semiconductor device and a preparation method thereof. According to the method, an ion implantation process is performed on a part of a first interlayer dielectric layer covering a protruding structure so as to enhance the flowability of the part of the first interlayer dielectric layer, and after a first backflow process is performed, the part of the first interlayer dielectric layer subjected to ion implantation forms a smooth surface so as to enhance the flowability of the part of the first interlayer dielectric layer. The step difference between a part of the first interlayer dielectric layer located on the protruding structure and the substrate is effectively reduced. Compared with a method of superposing a layer of dielectric structure with a smooth surface on the first interlayer dielectric layer, the method of the invention directly performs smooth treatment on part of the first interlayer dielectric layer, and can obtain a better surface smoothing effect on the basis of a smaller step difference. Moreover, the second interlayer dielectric layer formed on the first interlayer dielectric layer also has a smooth surface after the second backflow process, thereby facilitating the prevention of metal residues in the subsequent metal plug forming process, relieving the short circuit problem of the device, and improving the performance and yield of the device.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor device and a preparation method thereof. Background Art

[0002] Insulated Gate Bipolar Transistor (IGBT) is a composite fully controlled voltage-driven power semiconductor device composed of a bipolar junction transistor (BJT) and a metal-oxide-semiconductor field-effect transistor (MOSFET). IGBT combines the advantages of MOS and BJT. It has the advantages of MOS, such as high input impedance, low control power, simple drive circuit, fast switching speed, and low switching loss, and it also has the advantages of BJT, such as high current density, low saturation voltage drop, and strong current handling capability.

[0003] See also Figure 1 and Figure 2 , the IGBT includes a cell region C and a terminal region T. The key structure of the IGBT is formed in the cell region C, involving the gate 101 and the emitter, etc. A field plate 102 is formed in the terminal region T to achieve the voltage division of the planar electric field and improve the device performance. However, since the field plate 102 is formed on the oxide layer 103 and its edge is a right-angle structure, the interlayer dielectric layer 104 covering the field plate 102 and the oxide layer 103 has a corner A or a concave morphology. As a result, when the metal material layer 105 used to form the tungsten through hole 106 is subsequently etched, metal etching residues 105a are likely to exist at the corner A. And the metal etching residues 105a are easily directly connected to the metal layer of the field plate 102 and / or the emitter, etc., resulting in a short circuit problem, which seriously affects the yield of the device.

[0004] Therefore, a new preparation method is urgently needed to solve the above technical problems. Summary of the invention

[0005] The object of the present invention is to provide a semiconductor device and a method for manufacturing the same, so as to solve at least one of the problems of how to alleviate metal residues on an interlayer dielectric layer of an IGBT and how to avoid a short circuit of the device.

[0006] In order to solve the above technical problems, the present invention provides a method for preparing a semiconductor device, comprising:

[0007] A substrate is provided; the substrate comprises a cell region and a terminal region, a trench gate is formed in the cell region, and a protrusion structure is formed on the terminal region;

[0008] forming a first interlayer dielectric layer on the surfaces of the substrate and the protruding structure;

[0009] forming a patterned first photoresist layer on the first interlayer dielectric layer to expose at least a portion of the first interlayer dielectric layer covering the protruding structure;

[0010] Using the patterned first photoresist layer as a barrier, performing an ion implantation process on the exposed portion of the first interlayer dielectric layer;

[0011] Removing the patterned first photoresist layer and performing a first reflow process so that a portion of the first interlayer dielectric layer covering the protruding structure has a smooth surface;

[0012] forming a second interlayer dielectric layer on the first interlayer dielectric layer;

[0013] A second reflow process is performed to make at least a portion of the second interlayer dielectric layer located on the protruding structure have a smooth surface.

[0014] Optionally, in the method for preparing the semiconductor device, the doping ions used in the ion implantation process include boron ions.

[0015] Optionally, in the method for preparing the semiconductor device, in the first interlayer dielectric layer, a thickness of a region doped by the ion implantation process is less than 2 / 3 of a total thickness of the first interlayer dielectric layer.

[0016] Optionally, in the method for preparing a semiconductor device, after performing the first reflow process, the method for preparing a semiconductor device further includes:

[0017] forming a second interlayer dielectric layer on the first interlayer dielectric layer;

[0018] A second reflow process is performed to make at least a portion of the second interlayer dielectric layer located on the protruding structure have a smooth surface.

[0019] Optionally, in the method for preparing the semiconductor device, the material of the first interlayer dielectric layer includes USG; the material of the second interlayer dielectric layer includes BPSG or BSG.

[0020] Optionally, in the method for preparing a semiconductor device, after performing the second reflow process, the method for preparing a semiconductor device further includes:

[0021] A metal plug is formed at least on the side of the trench gate, and the metal plug penetrates the first interlayer dielectric layer and the second interlayer dielectric layer.

[0022] Optionally, in the method for preparing the semiconductor device, the process of forming a patterned first photoresist layer on the first interlayer dielectric layer to expose at least a portion of the first interlayer dielectric layer covering the protruding structure includes:

[0023] coating a first photoresist layer on the first interlayer dielectric layer;

[0024] The first photoresist layer is exposed by using a first photomask, and the patterned first photoresist layer is formed to expose at least a portion of the first interlayer dielectric layer covering the top surface and the sidewall of the protruding structure.

[0025] Optionally, in the method for preparing the semiconductor device, the process of forming the protruding structure on the terminal region includes:

[0026] forming a polysilicon layer on the substrate;

[0027] coating a second photoresist layer on the polysilicon layer;

[0028] Using the first photomask to expose the second photoresist layer and form a patterned second photoresist layer to cover a portion of the polysilicon layer located on the terminal region and expose the remaining portion of the polysilicon layer;

[0029] The patterned second photoresist layer is used as a barrier to etch and remove the exposed portion of the polysilicon layer; and the remaining portion of the polysilicon layer is the protruding structure.

[0030] Optionally, in the method for preparing the semiconductor device, the first photoresist layer is a positive photoresist, the second photoresist layer is a negative photoresist, and the opening width of the first photomask toward the protruding structure is equal to the width of the top surface of the protruding structure; or, the first photoresist layer is a negative photoresist, the second photoresist layer is a positive photoresist, and the shielding width of the first photomask toward the protruding structure is equal to the width of the top surface of the protruding structure; and,

[0031] The photosensitivity of the first photoresist layer is different from the photosensitivity of the second photoresist layer, so that the width of the portion of the polysilicon layer covered by the patterned second photoresist layer is equal to the width of the top surface of the protruding structure; and the width of the portion of the first interlayer dielectric layer exposed by the patterned first photoresist layer is a first width, and the first width D satisfies the following formula:

[0032] D≥d1+2d2;

[0033] Wherein, d1 is the width of the top surface of the protruding structure, and d2 is the width of the first interlayer dielectric layer covering a side wall of the protruding structure.

[0034] Optionally, in the method for preparing the semiconductor device, the protrusion structure includes a field plate and / or a temperature sensor.

[0035] Optionally, in the method for preparing the semiconductor device, the process of forming a patterned first photoresist layer on the first interlayer dielectric layer to expose at least a portion of the first interlayer dielectric layer covering the protruding structure includes:

[0036] coating a first photoresist layer on the first interlayer dielectric layer;

[0037] Using a second photomask to expose the first photoresist layer and form the patterned first photoresist layer to at least expose a portion of the first interlayer dielectric layer covering the top surface and the sidewall of the protruding structure;

[0038] The first photoresist layer is a positive photoresist, and the opening width of the second photomask toward the protruding structure is a first width D; or, the first photoresist layer is a negative photoresist, and the shielding width of the second photomask toward the protruding structure is a first width D; and the first width D satisfies the following formula:

[0039] D≥d1+2d2;

[0040] Wherein, d1 is the width of the top surface of the protruding structure, and d2 is the width of the first interlayer dielectric layer covering a side wall of the protruding structure.

[0041] Based on the same inventive concept, the present invention also provides a semiconductor device, comprising:

[0042] A substrate; the substrate comprises a cell region and a terminal region, a trench gate is formed in the cell region, and a protrusion structure is formed on the terminal region;

[0043] a first interlayer dielectric layer; the first interlayer dielectric layer covers the surfaces of the substrate and the protruding structure; and after a first reflow process, the first interlayer dielectric layer has a first rounded portion, and the first rounded portion at least covers the sidewall of the protruding structure;

[0044] The second interlayer dielectric layer covers the first interlayer dielectric layer; and after a second reflow process, the second interlayer dielectric layer has a second rounded portion, and the second rounded portion at least covers the first rounded portion.

[0045] Optionally, in the semiconductor device, the first rounded portion also covers a portion of the top surface of the protruding structure connected to the side wall of the protruding structure and a portion of the substrate.

[0046] Optionally, in the semiconductor device, at least a portion of the first interlayer dielectric layer covering the top surface and sidewalls of the protruding structure is doped with boron ions.

[0047] Optionally, in the semiconductor device, in the first interlayer dielectric layer, a thickness of a partial region doped with boron ions is less than 2 / 3 of a total thickness of the first interlayer dielectric layer.

[0048] Optionally, in the semiconductor device, the material of the first interlayer dielectric layer includes USG; the material of the second interlayer dielectric layer includes BPSG or BSG.

[0049] Optionally, in the semiconductor device, the protrusion structure includes a field plate and / or a temperature sensor.

[0050] Optionally, in the semiconductor device, the semiconductor device further includes a plurality of metal plugs; and at least some of the metal plugs are located on sides of the trench gate, and the metal plugs penetrate the first interlayer dielectric layer and the second interlayer dielectric layer.

[0051] In summary, the present invention provides a semiconductor device and a method for preparing the same. Compared with the prior art, the method for preparing the semiconductor device performs an ion implantation process on a portion of the first interlayer dielectric layer covering the surface of the protruding structure to enhance the fluidity of the portion of the first interlayer dielectric layer. After the first reflow process is performed, the portion of the first interlayer dielectric layer implanted with ions forms a smooth surface, which effectively reduces the step difference between the portion of the first interlayer dielectric layer located on the protruding structure and the substrate. Compared with superimposing a dielectric structure with a smooth surface on the first interlayer dielectric layer, the present invention directly performs a smoothing process on a portion of the first interlayer dielectric layer, which can obtain a better surface smoothing effect on the basis of a smaller step difference. In addition, the second interlayer dielectric layer formed on the first interlayer dielectric layer also has a smooth surface after the second reflow process, which is beneficial to the subsequent process of forming a metal plug, ensuring that the metal is etched cleanly and avoiding metal residue, thereby effectively alleviating the short circuit problem of the device and improving the performance and yield of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Those skilled in the art will appreciate that the drawings are provided for a better understanding of the present invention, but do not constitute any limitation on the scope of the present invention.

[0053] Figure 1 It is a schematic diagram of the structure in which the surface of the interlayer dielectric layer is uneven in the prior art.

[0054] Figure 2 It is a schematic diagram of a structure in which metal etching residues exist at corners in the prior art.

[0055] Figure 3 It is a flow chart of a method for preparing a semiconductor device in an embodiment of the present invention.

[0056] Figure 4 Flow chart of the method for preparing the protruding structure in an embodiment of the present invention.

[0057] Figure 5 It is a schematic diagram of using a first photomask to expose a second photoresist layer in an embodiment of the present invention.

[0058] Figure 6 Schematic diagram of the structure of the patterned second photoresist layer in an embodiment of the present invention.

[0059] Figure 7 Schematic diagram of etching a polysilicon layer using a patterned second photoresist layer in an embodiment of the present invention.

[0060] Figure 8 It is a schematic diagram of a polysilicon layer synchronously covering the trench gate trench and the substrate surface in an embodiment of the present invention.

[0061] Fig. 9 Schematic diagram of forming a first interlayer dielectric layer in an embodiment of the present invention.

[0062] Fig.10 Schematic diagram of using a first mask to expose a first photoresist layer in an embodiment of the present invention.

[0063] Fig.11 Schematic diagram of a patterned first photoresist layer in an embodiment of the present invention.

[0064] Fig.12 Schematic diagram of using a second mask to expose a first photoresist layer in an embodiment of the present invention.

[0065] Fig.13 is a schematic diagram of performing ion implantation in an embodiment of the present invention.

[0066] Fig.14 Schematic diagram of the structure of the first interlayer dielectric layer with a smooth surface in an embodiment of the present invention.

[0067] Fig.15 Schematic diagram of the structure of the second interlayer dielectric layer with a smooth surface in an embodiment of the present invention.

[0068] Fig.16 Schematic diagram of forming a contact hole in an embodiment of the present invention.

[0069] Fig.17 Schematic diagram of forming a metal material layer in an embodiment of the present invention.

[0070] Fig.18 Schematic diagram of forming a metal plug in an embodiment of the present invention.

[0071] And, in the attached drawings:

[0072] 101 - gate; 102 - field plate; 103 - oxide layer; 104 - interlayer dielectric layer; 105 - metal material layer; 105a - metal etching residue; 106 - tungsten through hole;

[0073] 200-first drift region; 201-polysilicon gate; 202-gate oxide layer; 203-second drift region; 204-oxide layer; 205-polysilicon layer; 206-second photoresist layer; 207-patterned second photoresist layer; 208-protruding structure; 209-first interlayer dielectric layer; 209a-first rounded portion; 210-first photoresist layer; 211-patterned first photoresist layer; 212-second interlayer dielectric layer; 212a-second rounded portion; 213-contact hole; 214-metal material layer; 215-metal plug;

[0074] C-cell region; T-terminal region; A-corner; D-first width; d1-width of the top surface of the protruding structure; d2-width of the first interlayer dielectric layer covering one side wall of the protruding structure. DETAILED DESCRIPTION

[0075] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different proportions are used. It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are only used to distinguish between the various components, elements, steps, etc. in the specification, and are not used to represent the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0076] See also Figure 3 This embodiment provides a method for preparing a semiconductor device, comprising:

[0077] Step 1 S10: providing a substrate; the substrate comprises a cell region and a terminal region, wherein a trench gate is formed in the cell region, and a protrusion structure is formed on the terminal region;

[0078] Step 2 S20: forming a first interlayer dielectric layer on the surfaces of the substrate and the protruding structure;

[0079] Step three S30: forming a patterned first photoresist layer on the first interlayer dielectric layer to expose at least a portion of the first interlayer dielectric layer covering the protruding structure;

[0080] Step 4 S40: using the patterned first photoresist layer as a barrier, performing an ion implantation process on the exposed portion of the first interlayer dielectric layer;

[0081] Step 5 S50: removing the patterned first photoresist layer, and performing a first reflow process, so that the portion of the first interlayer dielectric layer covering the protruding structure has a smooth surface;

[0082] Step six S60: forming a second interlayer dielectric layer on the first interlayer dielectric layer;

[0083] Step seven S70: performing a second reflow process to at least make a portion of the second interlayer dielectric layer located on the protruding structure have a smooth surface.

[0084] Based on this, the preparation method provided in this embodiment performs an ion implantation process and a first reflow process on the portion of the first interlayer dielectric layer covering the surface of the protruding structure, so that the portion of the first interlayer dielectric layer located at the protruding structure has a smooth surface; and the second interlayer dielectric layer formed on the first interlayer dielectric layer also has a smooth surface after the second reflow process, which is beneficial to avoid the occurrence of metal etching residues in subsequent processes, thereby effectively alleviating the short circuit problem of the device and improving the performance and yield of the device.

[0085] The following is combined with Figures 3 to 18 , specifically describe the method for preparing the semiconductor device provided in this embodiment.

[0086] Step 1 S10: Please refer to Figures 4 to 8 , providing a substrate; the substrate includes a cell region C and a terminal region T, and a trench gate is formed in the cell region C, and a protrusion structure 208 is formed on the terminal region T.

[0087] It should be noted that the structure of the IGBT is mainly divided into a cell region C and a terminal region T, and the terminal region T surrounds the cell region C. The cell region C is a key device region, in which a gate, an emitter and various well regions are arranged; a field plate, a temperature sensor and a floating field ring are arranged in the terminal region T to improve the performance of the IGBT. The collector of the IGBT is generally arranged on the other side of the substrate. Based on this, the cell region C includes a first drift region 200, and a plurality of trench gates, a P well region and an N well region are arranged in the first drift region 200. The trench gate includes a polysilicon gate 201 and a gate oxide layer 202 formed on the periphery of the polysilicon gate 201. In other embodiments, the gate of the IGBT can also be a planar gate. And the terminal region T includes a second drift region 203, and a doping structure such as a floating field ring is arranged in the second drift region 203, and a field plate and / or a temperature sensor and other structures are arranged on the surface of the second drift region 203. Since structures such as field plates and temperature sensors have morphological features protruding from the surface of the substrate, they are collectively referred to as protruding structures 208 in this embodiment. It should be noted that each of the protruding structures 208 located on the terminal region T may be a field plate, or may be partially a field plate and partially a temperature sensor, which is not specifically limited in this embodiment, and this embodiment is only described by taking the simultaneous formation of a field plate and a temperature sensor as an example.

[0088] For details, please refer to Figure 4 The process of forming a field plate and / or a temperature sensor on the surface of the second drift region 203 comprises the following steps:

[0089] Sub-step 1 S101: Please refer to Figure 5 , a polysilicon layer 205 is formed on the substrate.

[0090] After forming trench gates, various well regions and various field rings in the first drift region 200 and the second drift region 203, respectively, an oxide layer 204 is formed on the surface of the substrate to protect the substrate structure and prevent doping ions from diffusing. Subsequently, a polysilicon layer 205 is formed on the substrate for subsequent preparation of a protruding structure of a field plate and / or a temperature sensor.

[0091] Sub-step 2 S102: Please refer to Figure 5 , a second photoresist layer 206 is coated on the polysilicon layer 205 .

[0092] This embodiment does not limit whether the second photoresist layer 206 is a positive photoresist or a negative photoresist. If the second photoresist layer 206 is a positive photoresist, a cross-linking reaction will occur after exposure, so that the exposed part is dissolved and the unexposed part is insoluble. If the second photoresist layer 206 is a negative photoresist, the exposed part becomes insoluble after exposure, while the unexposed part is dissolved.

[0093] Sub-step 3 S103: Please refer to Figure 5 and Figure 6 The first mask M1 is used to expose the second photoresist layer 206 and form a patterned second photoresist layer 207 to cover a portion of the polysilicon layer 205 located on the terminal region T and expose the remaining portion of the polysilicon layer 205 .

[0094] Exemplarily, the second photoresist layer 206 is a negative photoresist, so the opening of the first mask M1 faces the terminal region T, and during the exposure process, the light beam is irradiated through the opening onto a portion of the photoresist layer 206 in the terminal region T, so that the portion of the photoresist layer 206 is retained, while the remaining photoresist layer 206 not irradiated by the light beam is dissolved, and a portion of the polysilicon layer 205 is exposed. Figure 7 A patterned second photoresist layer 207 is shown.

[0095] Sub-step 4 S104: Please refer to Figure 6 and Figure 7 , using the patterned second photoresist layer 207 as a barrier, etching and removing the exposed portion of the polysilicon layer 205 ; and the remaining portion of the polysilicon layer 205 is the protruding structure 208 .

[0096] Because the patterned second photoresist layer 207 exposes the polysilicon layer 205 located in the cell area C and also exposes part of the polysilicon layer 205 located in the terminal area T, the polysilicon layer 205 is etched with the patterned second photoresist layer 207 as a barrier, and the exposed part of the polysilicon layer 205 is removed, while the part of the polysilicon layer 205 covered by the patterned second photoresist layer 207 is retained. The polysilicon layer 205 retained at last can be used as a field plate in subsequent processes, and / or formed into a protruding structure 208 such as a temperature sensor with a PN junction through ion doping. In addition, after the protruding structure 208 is formed, the patterned second photoresist layer 207 is removed. It should be noted that the above-mentioned process for preparing the protruding structure 208 provided in this embodiment is only an example. And in other examples, the trench gate and the protruding structure 208 can be formed simultaneously. As Figure 8As shown, the formed polysilicon layer 205 not only covers the surface of the substrate in the cell region C and the terminal region T, but also fills and covers the trench for forming the trench gate in the cell region C. Then, under the blocking of the patterned second photoresist layer 207, the polysilicon layer 205 is etched until the oxide layer 204 on the substrate is exposed, and the polysilicon material filling of the trench gate and the formation of the protruding structure 208 are completed simultaneously. Therefore, this embodiment does not limit the specific process of forming the protruding structure 208.

[0097] Step 2 S20: Please refer to Fig. 9 , forming a first interlayer dielectric layer 209 on the surfaces of the substrate and the protruding structure 208 .

[0098] After the trench gate and various well regions are formed in the first drift region 200, a metal interconnection structure needs to be formed on the surface thereof to realize the electrical extraction of the gate and the emitter. Therefore, it is necessary to first form a first interlayer dielectric layer 209 on the surface of the substrate and the protruding structure 208 to achieve electrical isolation. Preferably, the first interlayer dielectric layer 209 is formed by a chemical vapor deposition process. And the material of the first interlayer dielectric layer 209 includes undoped silicate glass material (Usable Size Grown, USG). And based on the characteristic of the material without ion doping, it can further protect the substrate structure and avoid the diffusion of doped ions in the substrate.

[0099] It should be noted that, in view of the structural characteristics and process cost of the IGBT, the thickness of the interlayer dielectric layer in the metal interconnect structure is lower than the thickness of the protruding structure 208, so the part of the first interlayer dielectric layer 209 covering the protruding structure 208 will protrude from the part of the first interlayer dielectric layer 209 covering the surface of the substrate. And because the protruding structure 208 has a vertical sidewall, the first interlayer dielectric layer 209 is easy to form a concave corner A, and it is very easy to cause a metal etching residue problem when a metal plug or a metal line is formed later, thereby causing a short circuit of the device. Therefore, in order to avoid the first interlayer dielectric layer 209 having a concave corner A on the surface, this embodiment improves the fluidity of the first interlayer dielectric layer 209 through an ion doping process, and combines the reflow process to make the concave corner A on the surface of the first interlayer dielectric layer 209 smooth and gentle, thereby avoiding the subsequent metal etching residue problem. Among them, please refer to the following steps S30 to S50 for the specific process.

[0100] Step 3 S30: Please refer to Figures 10 to 12 , a patterned first photoresist layer 211 is formed on the first interlayer dielectric layer 209 to expose at least a portion of the first interlayer dielectric layer 209 covering the protruding structure 208 .

[0101] Since the portion of the first interlayer dielectric layer 209 covering the protruding structure 208 has a vertical sidewall morphology similar to that of the protruding structure 208, in order to achieve sidewall smoothing of the first interlayer dielectric layer 209, the patterned first photoresist layer 211 should expose the portion of the first interlayer dielectric layer 209 covering the protruding structure 208 and its surrounding adjacent substrate, so as to ensure that the range of subsequent ion implantation includes the portion of the first interlayer dielectric layer 209 covering the top surface and sidewall of the protruding structure 208, so as to form a smooth surface in the subsequent reflow process.

[0102] Therefore, if Fig.11 As shown, the width of the portion of the first interlayer dielectric layer 209 exposed by the patterned first photoresist layer 211 is a first width D, and the first width D satisfies the following formula:

[0103] D≥d1+2d2;

[0104] Wherein, d1 is the width of the top surface of the protruding structure, d2 is the width of the first interlayer dielectric layer covering a side wall of the protruding structure, and the width referred to in this embodiment is the distance in the direction parallel to the substrate surface in the figure.

[0105] In one example, the step 3 S30 specifically includes: Fig.10 and Fig.11 , firstly, a first photoresist layer 210 is coated on the first interlayer dielectric layer 209. Then, the first photomask M1 is used to expose the first photoresist layer 210 to form a patterned first photoresist layer 211. The patterned first photoresist layer 211 exposes the first interlayer dielectric layer 209 covering the top surface, the sidewall of the protruding structure 208, and a portion of the substrate adjacent to the sidewall, and shields the remaining portion of the first interlayer dielectric layer 209.

[0106] Further, such as Figure 5 , Fig.10 and Fig.11 As shown, the exposed and covered areas of the patterned first photoresist layer 211 and the patterned second photoresist layer 207 are opposite. Therefore, if the same first photomask M1 is used to reduce costs, the polarities of the first photoresist layer 210 and the second photoresist layer 206 are opposite. That is, if the first photoresist layer 210 is a positive photoresist, the second photoresist layer 206 is a negative photoresist; or, if the first photoresist layer 210 is a negative photoresist, the second photoresist layer 206 is a positive photoresist.

[0107] And, if Fig.11 As shown, the width D of the first interlayer dielectric layer 209 exposed by the patterned first photoresist layer 211 is greater than the width d1 of the top surface of the protruding structure 208, and the width of the polysilicon layer 205 blocked by the patterned second photoresist layer 207 is equal to the width d1 of the protruding structure 208. Therefore, if the same first photomask M1 is used to obtain different exposure widths, the light sensitivity of the first photoresist layer 210 should be different from the light sensitivity of the second photoresist layer 206. For example, Figure 5 , Figure 6 , Fig.10 and Fig.11 As shown, the first photoresist layer 210 is a positive photoresist, the second photoresist layer 206 is a negative photoresist, and the opening width of the first mask M1 toward the protruding structure 208 is equal to the width d1 of the top surface of the protruding structure 208, and the light sensitivity of the first photoresist layer 210 should be greater than the light sensitivity of the second photoresist layer 206. Under the same exposure adjustment, the width of the portion of the polysilicon layer 205 covered by the patterned second photoresist layer 207 is equal to the width d1 of the top surface of the protruding structure 208. The width of the portion of the first interlayer dielectric layer 209 exposed by the patterned first photoresist layer 211 is the first width D; that is, D≥d1+2d2. Alternatively, the first photoresist layer 206 is a negative photoresist, the second photoresist layer 210 is a positive photoresist, and the shielding width of the first mask M1 toward the protruding structure 208 is equal to the width d1 of the top surface of the protruding structure 208. The light sensitivity of the first photoresist layer 210 should be smaller than the light sensitivity of the second photoresist layer 206. Similarly, different exposure widths of the above-mentioned patterned first photoresist layer 211 and the patterned second photoresist layer 207 can be obtained.

[0108] In another example, if Fig.12 As shown, a second photomask M2 may be used to expose the first photoresist layer 210 and form a patterned first photoresist layer 211 to expose a portion of the first interlayer dielectric layer 209 covering the protruding structure 208 and the adjacent substrate. The light sensitivity of the first photoresist layer 210 may be equal to the light sensitivity of the second photoresist layer 206. Based on this, when the first photoresist layer 210 is a positive photoresist, the opening width of the second photomask M2 toward the protruding structure 208 is the first width D; or, when the first photoresist layer 210 is a negative photoresist, the blocking width of the second photomask M2 toward the protruding structure 208 is the first width D. Therefore, it is also possible to form Fig.11The patterned first photoresist layer 211 not only exposes a portion of the first interlayer dielectric layer 209 on the top surface of the protruding structure 208 , but also exposes a portion of the first interlayer dielectric layer 209 on the sidewall of the protruding structure 208 and a peripheral portion of the substrate.

[0109] Step 4 S40: Please refer to Fig.13 , using the patterned first photoresist layer 211 as a barrier, an ion implantation process is performed on the exposed portion of the first interlayer dielectric layer 209 .

[0110] Preferably, the doping ions used in the ion implantation process include boron ions. The doping of boron ions helps to improve the fluidity of the first interlayer dielectric layer 209, which can not only reduce the thickness of the first interlayer dielectric layer 209 on the protruding structure 208, but also help to make the sidewall of the first interlayer dielectric layer 209 have a smooth profile in the subsequent reflow process, avoiding the formation of a concave corner A, and thus effectively alleviating the subsequent metal etching residue problem.

[0111] Furthermore, since the material of the first interlayer dielectric layer 209 includes USG, ion diffusion can be blocked. Therefore, in order to take into account the blocking effect and the reflow effect of the first interlayer dielectric layer 209 on ion diffusion, in the first interlayer dielectric layer 209, the thickness of the area doped by the ion implantation process is less than 2 / 3 of the total thickness of the first interlayer dielectric layer 209. That is, after executing the step four S40, some areas close to the top surface of the first interlayer dielectric layer 209 are doped with ions to ensure the subsequent reflow effect; while some areas close to the bottom surface of the interlayer dielectric layer 209 are not doped with ions, which can effectively block the doped ions and avoid affecting other film layers. Compared with the multi-film layer structure in the prior art, this embodiment only uses one layer of the first interlayer dielectric layer 209 to simultaneously achieve the blocking of ion diffusion and ensure the reflow effect, which is beneficial to reduce the film thickness of the overall dielectric layer on the protruding structure 208 and reduce the preparation cost.

[0112] Step 5 S50: Please refer to Fig.13 and Fig.14 , removing the patterned first photoresist layer 211, and performing a first reflow process, so that a portion of the first interlayer dielectric layer 209 covering the protruding structure 208 has a smooth surface.

[0113] Because part of the first interlayer dielectric layer 209 located on the protruding structure 208 is doped with boron ions, the doped part of the first interlayer dielectric layer 209 has better fluidity during the first reflow process performed at high temperature. After the first reflow process, the part of the first interlayer dielectric layer 209 that has been ion-implanted has a smooth surface. In this embodiment, the smooth sidewall of the first interlayer dielectric layer 209 located on the protruding structure 208 is defined as a first smooth portion 209a. The first smooth portion 209a covers the sidewall of the protruding structure 208, and covers part of the top surface of the protruding structure 208 connected to the sidewall of the protruding structure 208 and part of the substrate. It can be understood that the first smooth portion 209a effectively reduces the step difference between the part of the first interlayer dielectric layer 209 located on the protruding structure 209 and the substrate. Obviously, compared with superimposing a dielectric structure with a smooth surface on the first interlayer dielectric layer 209, the semiconductor device formed by the method provided in this embodiment has a lower overall film thickness and a better rounding effect, and it directly performs rounding treatment on part of the first interlayer dielectric layer 209, so that a better surface smoothing effect can be obtained on the basis of a smaller step difference. In other words, the method provided in this embodiment forms the first rounded portion 209a on the premise of the step difference between the first interlayer dielectric layer 209 of the thickness not doped with ions and the substrate, so that the first rounded portion 209a obtained has a smaller slope relative to the surface of the substrate and a lower degree of surface undulation, which is beneficial to avoid the device short circuit problem caused by metal etching residues in the subsequent preparation of metal plugs.

[0114] Step 6 S60: Please refer to Fig.15 , a second interlayer dielectric layer 212 is formed on the first interlayer dielectric layer 209 .

[0115] Step 7 S70: Please refer to Fig.15 , performing a second reflow process to make at least a portion of the second interlayer dielectric layer 212 located on the protruding structure 208 have a smooth surface.

[0116] In order to optimize the electrical performance of the IGBT and enhance its durability and radial uniformity, after the first interlayer dielectric layer 209 is subjected to the first reflow process, a second interlayer dielectric layer 212 needs to be formed on the first interlayer dielectric layer 209. Since the first interlayer dielectric layer 209 has a smooth surface, the second interlayer dielectric layer 212 deposited on the first interlayer dielectric layer 209 also has a similar morphology. However, in order to further smooth the morphology of the second interlayer dielectric layer 212, preferably, the material of the second interlayer dielectric layer 212 includes borophospho-silicate glass (BPSG) or boron-silicate glass (BSG). Both BPSG and BSG are doped with boron ions, so that the second interlayer dielectric layer 212 has good reflowability. Therefore, after the second interlayer dielectric layer 212 is subjected to the second reflow process, the top surface of the second interlayer dielectric layer 212 is smoother and has a second rounded portion 212a.

[0117] It can be understood that the material of the first smooth portion 209a formed after ion implantation is the same as the material of the second smooth portion 212a, then the second smooth portion 212a covers the first smooth portion 209a and can be stably connected to the first smooth portion 209a, thereby further reducing the slope of the dielectric layer located on the protruding structure 208, so that the undulation of the top surface of the second interlayer dielectric layer 212 is lower, which is beneficial to avoid metal etching residues in subsequent processes, thereby avoiding device short circuit problems and improving device performance and yield.

[0118] For further information, see Figures 16 to 18 After performing a second reflow process on the second interlayer dielectric layer 212, the method for preparing the semiconductor device further includes: forming a metal plug 215 at least on the side of the trench gate, and the metal plug 215 penetrates the first interlayer dielectric layer 209 and the second interlayer dielectric layer 212.

[0119] Specifically, Fig.16As shown, a plurality of contact holes 213 are formed by an etching process. It should be noted that the above-mentioned reflow process is performed before forming the contact holes 213 to avoid affecting the morphology of the contact holes 213 and causing the contact holes 213 to be tilted. Specifically, in the cell region C, in order to lead out the emitter, the contact hole 213 can be formed on the side of the trench gate, and the contact hole 213 extends into the first drift region 200 and penetrates the first interlayer dielectric layer 209 and the second interlayer dielectric layer 212. Also, in the terminal region T, the contact hole 213 can also be formed on the protruding structure 208 used as a temperature sensor, and the contact hole 213 extends into the protruding structure 208 and penetrates the first interlayer dielectric layer 209 and the second interlayer dielectric layer 212. Subsequently, as Fig.17 As shown, a metal material layer 214 is formed on the surface of the second interlayer dielectric layer 212 having a smooth morphology, and the metal material layer 214 fills and covers each of the contact holes 213. Finally, as shown Fig.18 As shown, an etching process is used to remove part of the metal material layer 214 on the surface of the second interlayer dielectric layer 212, and the metal material layer 214 in the contact hole 213 is retained to form each metal plug 215. Optionally, the metal material layer 214 is made of metal tungsten.

[0120] Furthermore, the etching process used in the method for preparing the semiconductor device may be a dry etching process or a wet etching process. Also, the deposition method used includes but is not limited to physical vapor deposition or chemical vapor deposition.

[0121] Based on the same concept, this embodiment also provides a semiconductor device. Fig.18 The semiconductor device includes: a substrate, a first interlayer dielectric layer 209 , a second interlayer dielectric layer 212 and a plurality of metal plugs 215 .

[0122] Specifically, the substrate includes a cell region C and a terminal region T; the cell region C is a main device region, and a trench gate is formed in the cell region C; the terminal region T surrounds the cell region C, and a protruding structure 208 is formed on the terminal region T. Preferably, a plurality of the protruding structures 208 are formed on the terminal region T, and each of the protruding structures 208 is a field plate and / or a temperature sensor. Furthermore, an oxide layer 204 is formed on the surface of the substrate to protect the substrate; and the protruding structure 208 can be located on the oxide layer 204.

[0123] The first interlayer dielectric layer 209 covers the surface of the substrate and the protruding structure 208. Since an oxide layer 204 is formed on the surface of the substrate, the first interlayer dielectric layer 209 can be directly connected to the oxide layer 204. Preferably, the material of the first interlayer dielectric layer 209 includes USG to have a good electrical isolation effect. Furthermore, a partial area of ​​the first interlayer dielectric layer 209 located on the protruding structure 208 is doped with boron ions, and the thickness of the doped area is less than 2 / 3 of the total thickness of the first interlayer dielectric layer 209. It can be understood that boron ions can enhance the fluidity of the material, so after the first reflow process, the surface of the first interlayer dielectric layer 209 is relatively smooth and has a first smooth portion 209a. The first rounded portion 209a covers the sidewall of the protruding structure 208, and covers the top surface of the part of the protruding structure 208 connected to the sidewall and the part of the substrate, effectively reducing the undulation of the top surface of the first interlayer dielectric layer 209, so that the slope of the part of the first interlayer dielectric layer 209 located on the protruding structure 208 is lower, thereby avoiding the formation of corners and other morphologies, which is conducive to the subsequent metal etching process. Clean metal etching avoids etching residues and improves device performance and yield. At the same time, the thickness of the doped area is less than 2 / 3 of the total thickness of the first interlayer dielectric layer 209, and a part of the area close to the bottom surface of the first interlayer dielectric layer 209 can be reserved to block ion diffusion and avoid affecting the substrate or other structures.

[0124] The second interlayer dielectric layer 212 covers the first interlayer dielectric layer 209. Preferably, the material of the second interlayer dielectric layer includes BPSG or BSG. Based on this, after the second reflow process, the second interlayer dielectric layer 212 has a second rounded portion 212a. Fig.18 As shown, the second rounded portion 212a covers a portion of the first interlayer dielectric layer 209 located on the first rounded portion 210a and its periphery, so that the top surface of the semiconductor structure has a smoother surface, further alleviating the problem of metal etching residue in subsequent processes.

[0125] A plurality of metal plugs 215 are used to realize electrical lead-out. Fig.18 As shown, the metal plug 215 located in the cell region C is located at the side of the trench gate, and sequentially penetrates the second interlayer dielectric layer 212 and the first interlayer dielectric layer 209, and extends into the substrate. When part of the protruding structure 208 in the terminal region T is a temperature sensor, part of the metal plug 215 sequentially penetrates the second interlayer dielectric layer 212 and the first interlayer dielectric layer 209, and extends into the protruding structure 208.

[0126] Preferably, the semiconductor device is prepared by the above-mentioned method for preparing a semiconductor device, and the semiconductor device is an insulated gate bipolar transistor.

[0127] In summary, the semiconductor device and the preparation method thereof provided in this embodiment perform an ion implantation process on a portion of the first interlayer dielectric layer 209 covering the surface of the protruding structure 208 to enhance the fluidity of a portion of the first interlayer dielectric layer 209. After the first reflow process is performed, the portion of the first interlayer dielectric layer 209 implanted with ions forms a smooth surface, which effectively reduces the step difference between the portion of the first interlayer dielectric layer 209 located on the protruding structure 208 and the substrate. Compared with superimposing a dielectric structure with a smooth surface on the first interlayer dielectric layer 209, the semiconductor device formed by the method provided in this embodiment has a lower overall film thickness and a better rounding effect, because the portion of the first interlayer dielectric layer 209 is directly rounded, and a better surface smoothing effect can be obtained on the basis of a smaller step difference. Furthermore, the second interlayer dielectric layer formed on the first interlayer dielectric layer also has a smooth surface after the second reflow process, which is beneficial in the process of forming the metal plug 215, ensuring that the metal material can be etched cleanly and is difficult to remain on the surface of the second interlayer dielectric layer 212, thereby effectively avoiding the problem of device short circuit caused by metal residue, and is beneficial to improving the performance and yield of the device.

[0128] In addition, it should be recognized that although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still belongs to the scope of protection of the technical solution of the present invention.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: A substrate is provided; the substrate comprises a cell region and a terminal region, a trench gate is formed in the cell region, and a protrusion structure is formed on the terminal region; forming a first interlayer dielectric layer on the surfaces of the substrate and the protruding structure; forming a patterned first photoresist layer on the first interlayer dielectric layer to expose at least a portion of the first interlayer dielectric layer covering the protruding structure; Using the patterned first photoresist layer as a barrier, performing an ion implantation process on the exposed portion of the first interlayer dielectric layer; Removing the patterned first photoresist layer and performing a first reflow process so that a portion of the first interlayer dielectric layer covering the protruding structure has a smooth surface; forming a second interlayer dielectric layer on the first interlayer dielectric layer; A second reflow process is performed to make at least a portion of the second interlayer dielectric layer located on the protruding structure have a smooth surface.

2. The method for preparing a semiconductor device according to claim 1, wherein: The doping ions used in the ion implantation process include boron ions.

3. The method for preparing a semiconductor device according to claim 1 or 2, characterized in that: In the first interlayer dielectric layer, a thickness of a region doped by the ion implantation process is less than 2 / 3 of a total thickness of the first interlayer dielectric layer.

4. The method for preparing a semiconductor device according to claim 1, wherein: The material of the first interlayer dielectric layer includes USG; the material of the second interlayer dielectric layer includes BPSG or BSG.

5. The method for preparing a semiconductor device according to claim 1, characterized in that: After performing the second reflow process, the method for preparing the semiconductor device further includes: A metal plug is formed at least on the side of the trench gate, and the metal plug penetrates the first interlayer dielectric layer and the second interlayer dielectric layer.

6. The method for preparing a semiconductor device according to claim 1, wherein: The process of forming a patterned first photoresist layer on the first interlayer dielectric layer to expose at least a portion of the first interlayer dielectric layer covering the protruding structure includes: coating a first photoresist layer on the first interlayer dielectric layer; The first photoresist layer is exposed by using a first photomask, and the patterned first photoresist layer is formed to expose at least a portion of the first interlayer dielectric layer covering the top surface and the sidewall of the protruding structure.

7. The method for preparing a semiconductor device according to claim 6, characterized in that: The process of forming the protruding structure on the terminal region includes: forming a polysilicon layer on the substrate; coating a second photoresist layer on the polysilicon layer; Using the first photomask to expose the second photoresist layer and form a patterned second photoresist layer to cover a portion of the polysilicon layer located on the terminal region and expose the remaining portion of the polysilicon layer; The patterned second photoresist layer is used as a barrier to etch and remove the exposed portion of the polysilicon layer; and the remaining portion of the polysilicon layer is the protruding structure.

8. The method for preparing a semiconductor device according to claim 7, characterized in that: The first photoresist layer is a positive photoresist, the second photoresist layer is a negative photoresist, and the opening width of the first photomask toward the protruding structure is equal to the width of the top surface of the protruding structure; Alternatively, the first photoresist layer is a negative photoresist, the second photoresist layer is a positive photoresist, and the shielding width of the first photomask toward the protruding structure is equal to the width of the top surface of the protruding structure; as well as, The photosensitivity of the first photoresist layer is different from the photosensitivity of the second photoresist layer, so that the width of the portion of the polysilicon layer covered by the patterned second photoresist layer is equal to the width of the top surface of the protruding structure; and the width of the portion of the first interlayer dielectric layer exposed by the patterned first photoresist layer is a first width, and the first width D satisfies the following formula: D≥d1+2d2; Wherein, d1 is the width of the top surface of the protruding structure, and d2 is the width of the first interlayer dielectric layer covering a side wall of the protruding structure.

9. The method for preparing a semiconductor device according to claim 1 or 7, characterized in that: The raised structure includes a field plate and / or a temperature sensor.

10. The method for preparing a semiconductor device according to claim 1, characterized in that: The process of forming a patterned first photoresist layer on the first interlayer dielectric layer to expose at least a portion of the first interlayer dielectric layer covering the protruding structure includes: coating a first photoresist layer on the first interlayer dielectric layer; Using a second photomask to expose the first photoresist layer and form the patterned first photoresist layer to at least expose a portion of the first interlayer dielectric layer covering the top surface and the sidewall of the protruding structure; The first photoresist layer is a positive photoresist, and the opening width of the second photomask toward the protruding structure is a first width D; or, the first photoresist layer is a negative photoresist, and the shielding width of the second photomask toward the protruding structure is a first width D; and the first width D satisfies the following formula: D≥d1+2d2; Wherein, d1 is the width of the top surface of the protruding structure, and d2 is the width of the first interlayer dielectric layer covering a side wall of the protruding structure.

11. A semiconductor device, characterized in that: include: A substrate; the substrate comprises a cell region and a terminal region, a trench gate is formed in the cell region, and a protrusion structure is formed on the terminal region; a first interlayer dielectric layer; The first interlayer dielectric layer covers the surfaces of the substrate and the protruding structure; and after a first reflow process, the first interlayer dielectric layer has a first rounded portion, and the first rounded portion at least covers the sidewall of the protruding structure; a second interlayer dielectric layer; The second interlayer dielectric layer covers the first interlayer dielectric layer; After the second reflow process, the second interlayer dielectric layer has a second rounded portion, and the second rounded portion at least covers the first rounded portion.

12. The semiconductor device according to claim 11, characterized in that The first rounded portion also covers a portion of the top surface of the protruding structure connected to the side wall of the protruding structure and a portion of the substrate.

13. The semiconductor device according to claim 11, characterized in that At least a portion of the first interlayer dielectric layer covering the top surface and the sidewall of the protruding structure is doped with boron ions.

14. The semiconductor device according to claim 13, characterized in that In the first interlayer dielectric layer, a thickness of a partial region doped with boron ions is less than 2 / 3 of a total thickness of the first interlayer dielectric layer.

15. The semiconductor device according to claim 11, wherein: The material of the first interlayer dielectric layer includes USG; the material of the second interlayer dielectric layer includes BPSG or BSG.

16. The semiconductor device according to claim 11, characterized in that The raised structure includes a field plate and / or a temperature sensor.

17. The semiconductor device according to claim 11, characterized in that The semiconductor device further includes a plurality of metal plugs; at least a portion of the metal plugs are located on the sides of the trench gate, and the metal plugs penetrate the first interlayer dielectric layer and the second interlayer dielectric layer.

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