IGBT device and preparation method thereof
By forming a multi-layer inter-dielectric layer in the IGBT device and performing a reflow process, the short circuit problem caused by metal residue on the inter-dielectric layer is solved, and the performance and yield of the device are improved.
Patent Information
- Application Number
- CN202411517903.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-28
- Publication Date
- 2025-02-07
AI Technical Summary
There is metal residue on the interlayer dielectric layer of IGBT devices, which leads to short-circuit problems and seriously affects the yield of the device.
By sequentially forming inter-layer dielectric layers on the substrate and convex structure surfaces of the IGBT device, and the surface is smooth through the reflow process to ensure that the metal material is clean and free of residues during etching.
It effectively avoids the problem of device short circuit caused by metal residues, and improves the performance and yield of the device.
Smart Images
Figure CN119403145A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to an IGBT device and a preparation method thereof. Background Art
[0002] Insulated Gate Bipolar Transistor (IGBT) is a composite fully controlled voltage-driven power semiconductor device composed of a bipolar junction transistor (BJT) and a metal-oxide-semiconductor field-effect transistor (MOSFET). IGBT combines the advantages of MOS and BJT. It has the advantages of MOS, such as high input impedance, low control power, simple drive circuit, fast switching speed, and low switching loss, and it also has the advantages of BJT, such as high current density, low saturation voltage drop, and strong current handling capability.
[0003] See also Figure 1 and Figure 2 , the IGBT includes a cell region C and a terminal region T. The key structure of the IGBT is formed in the cell region C, involving the gate 101 and the emitter, etc. A field plate 102 is formed in the terminal region T to achieve the voltage division of the planar electric field and improve the device performance. However, since the field plate 102 is formed on the oxide layer 103 and its edge is a right-angle structure, the interlayer dielectric layer 104 covering the field plate 102 and the oxide layer 103 has a corner A or other recessed structure. As a result, when the metal material layer 105 used to form the tungsten through hole 106 is subsequently etched, metal etching residues 105a are likely to exist at the corner A. And the metal etching residues 105a are easily directly connected to the metal layer of the field plate 102 and / or the emitter, etc., resulting in a short circuit problem, which seriously affects the yield of the device.
[0004] Therefore, a new preparation method is urgently needed to solve the above technical problems. Summary of the invention
[0005] The object of the present invention is to provide an IGBT device and a method for manufacturing the same, so as to solve at least one of the problems of how to alleviate metal residue on the interlayer dielectric layer of the IGBT and how to avoid device short circuit.
[0006] In order to solve the above technical problems, the present invention provides a method for preparing an IGBT device, comprising:
[0007] A substrate is provided; the substrate comprises a cell region and a terminal region, a trench gate is formed in the cell region, and a protrusion structure is formed on the terminal region;
[0008] Sequentially forming a first interlayer dielectric layer and a second interlayer dielectric layer on the surfaces of the substrate and the protruding structure;
[0009] removing a portion of the second interlayer dielectric layer and retaining at least a portion of the second interlayer dielectric layer located on the protruding structure;
[0010] Performing a first reflow process so that a remaining portion of the second interlayer dielectric layer has a smooth surface;
[0011] Sequentially forming a third interlayer dielectric layer and a fourth interlayer dielectric layer on the surface of the first interlayer dielectric layer and a retained portion of the second interlayer dielectric layer;
[0012] A second reflow process is performed to make a portion of the fourth interlayer dielectric layer have a smooth surface.
[0013] Optionally, in the method for preparing the IGBT device, the material of the second interlayer dielectric layer and the fourth interlayer dielectric layer contains boron ions.
[0014] Optionally, in the method for preparing the IGBT device, the content of boron ions in the fourth interlayer dielectric layer is greater than the content of boron ions in the second interlayer dielectric layer.
[0015] Optionally, in the method for preparing the IGBT device, the materials of the first interlayer dielectric layer and the third interlayer dielectric layer both include USG; and the materials of the second interlayer dielectric layer and the fourth interlayer dielectric layer both include BPSG or BSG.
[0016] Optionally, in the method for preparing the IGBT device, the process of removing a portion of the second interlayer dielectric layer and retaining at least a portion of the second interlayer dielectric layer located on the protruding structure includes:
[0017] coating a first photoresist layer on the second interlayer dielectric layer;
[0018] Using a first photomask to expose the first photoresist layer and form a patterned first photoresist layer to at least cover a portion of the second interlayer dielectric layer located on the top surface and the sidewall of the protruding structure and expose the remaining portion of the second interlayer dielectric layer;
[0019] The patterned first photoresist layer is used as a barrier to etch away the exposed portion of the second interlayer dielectric layer, and retain the remaining portion of the second interlayer dielectric layer.
[0020] Optionally, in the method for preparing the IGBT device, the process of forming the protruding structure on the terminal region includes:
[0021] forming a polysilicon layer on the substrate;
[0022] coating a second photoresist layer on the polysilicon layer;
[0023] Using the first photomask to expose the second photoresist layer and form a patterned second photoresist layer to cover a portion of the polysilicon layer located on the terminal region and expose the remaining portion of the polysilicon layer;
[0024] The patterned second photoresist layer is used as a barrier to etch and remove the exposed portion of the polysilicon layer; and the remaining portion of the polysilicon layer is the protruding structure.
[0025] Optionally, in the method for preparing the IGBT device, the first photoresist layer and the second photoresist layer are both negative photoresists, and the opening width of the first photomask toward the protruding structure is equal to the width of the top surface of the protruding structure; or, the first photoresist layer and the second photoresist layer are both positive photoresists, and the shielding width of the first photomask toward the protruding structure is equal to the width of the top surface of the protruding structure; and,
[0026] The photosensitivity of the first photoresist layer is different from the photosensitivity of the second photoresist layer, so that the width of the portion of the polysilicon layer covered by the patterned second photoresist layer is equal to the width of the top surface of the protruding structure; and the width of the portion of the second interlayer dielectric layer covered by the patterned first photoresist layer is a first width, and the first width D satisfies the following formula:
[0027] D≥d1+2d2;
[0028] Wherein, d1 is the width of the top surface of the protruding structure, and d2 is the sum of the widths of the first interlayer dielectric layer and the second interlayer dielectric layer covering a side wall of the protruding structure.
[0029] Optionally, in the method for preparing the IGBT device, the protrusion structure includes a field plate and / or a temperature sensor.
[0030] Optionally, in the method for preparing the IGBT device, the process of removing a portion of the second interlayer dielectric layer and retaining at least a portion of the second interlayer dielectric layer located on the protruding structure includes:
[0031] coating a third photoresist layer on the second interlayer dielectric layer;
[0032] Using a second photomask to expose the third photoresist layer and form a patterned third photoresist layer to at least cover a portion of the second interlayer dielectric layer located on the top surface and the sidewall of the protruding structure and expose the remaining portion of the second interlayer dielectric layer;
[0033] Using the patterned third photoresist layer as a barrier, etching and removing the exposed portion of the second interlayer dielectric layer, and retaining the remaining portion of the second interlayer dielectric layer;
[0034] The third photoresist layer is a negative photoresist, and the opening width of the second photomask toward the protruding structure is a first width D; or the third photoresist layer is a positive photoresist, and the shielding width of the second photomask toward the protruding structure is a first width D; and the first width D satisfies the following formula:
[0035] D≥d1+2d2;
[0036] Wherein, d1 is the width of the top surface of the protruding structure, and d2 is the sum of the widths of the first interlayer dielectric layer and the second interlayer dielectric layer covering a side wall of the protruding structure.
[0037] Optionally, in the method for preparing the IGBT device, after performing the second reflow process, the method for preparing the IGBT device further includes:
[0038] A metal plug is formed at least on the side of the trench gate, and the metal plug penetrates the first interlayer dielectric layer, the third interlayer dielectric layer and the fourth interlayer dielectric layer.
[0039] Optionally, in the method for preparing the IGBT device, in the process of forming the metal plug on the side of the trench gate, the method for preparing the IGBT device further includes:
[0040] The metal plug is formed on the protruding structure, and the metal plug penetrates the first interlayer dielectric layer, the second interlayer dielectric layer, the third interlayer dielectric layer and the fourth interlayer dielectric layer.
[0041] Based on the same inventive concept, the present invention also provides an IGBT device, comprising:
[0042] A substrate; the substrate comprises a cell region and a terminal region, a trench gate is formed in the cell region, and a protrusion structure is formed on the terminal region;
[0043] A first interlayer dielectric layer; the first interlayer dielectric layer covers the surfaces of the substrate and the protruding structure;
[0044] a second interlayer dielectric layer; the second interlayer dielectric layer covers a portion of the first interlayer dielectric layer located on the protruding structure; and after a first reflow process, the second interlayer dielectric layer has a first rounded portion, and the first rounded portion at least covers a portion of the first interlayer dielectric layer located on the side wall of the protruding structure;
[0045] a third interlayer dielectric layer; the third interlayer dielectric layer covers the exposed portions of the first interlayer dielectric layer and the second interlayer dielectric layer;
[0046] A fourth interlayer dielectric layer; the fourth interlayer dielectric layer covers the third interlayer dielectric layer; and after a second reflow process, the fourth interlayer dielectric layer has a second rounded portion, the second rounded portion at least covers a portion of the third interlayer dielectric layer located on the first rounded portion.
[0047] Optionally, in the IGBT device, the first rounded portion also covers a portion of the top surface of the protruding structure connected to the side wall of the protruding structure and a portion of the first interlayer dielectric layer on the substrate.
[0048] Optionally, in the IGBT device, the material of the second interlayer dielectric layer and the fourth interlayer dielectric layer includes boron ions.
[0049] Optionally, in the IGBT device, a content of boron ions in the fourth interlayer dielectric layer is greater than a content of boron ions in the second interlayer dielectric layer.
[0050] Optionally, in the IGBT device, the materials of the first interlayer dielectric layer and the third interlayer dielectric layer both include USG; and the materials of the second interlayer dielectric layer and the fourth interlayer dielectric layer both include BPSG or BSG.
[0051] Optionally, in the IGBT device, the protrusion structure includes a field plate and / or a temperature sensor.
[0052] Optionally, in the IGBT device, the IGBT device further includes: a plurality of metal plugs; at least some of the metal plugs are located on the sides of the trench gate and penetrate the first interlayer dielectric layer, the third interlayer dielectric layer and the fourth interlayer dielectric layer.
[0053] Optionally, in the IGBT device, some of the metal plugs are located on the protruding structure, and the metal plugs penetrate the first interlayer dielectric layer, the second interlayer dielectric layer, the third interlayer dielectric layer and the fourth interlayer dielectric layer.
[0054] In summary, the present invention provides an IGBT device and a method for preparing the same. Compared with the prior art, the preparation method retains part of the second interlayer dielectric layer located on the protruding structure, and combines the first reflow process to make the second interlayer dielectric layer have a smooth surface, taking into account the thickness control and morphology optimization of the interlayer dielectric layer. The first interlayer dielectric layer and the third interlayer dielectric layer are respectively formed on the upper and lower surfaces of the second interlayer dielectric layer to avoid affecting the device performance due to ion diffusion. In addition, a fourth interlayer dielectric layer is also formed on the surface of the third interlayer dielectric layer, and the second reflow process is used to make the fourth interlayer dielectric layer have a smoother surface on the basis of the second interlayer dielectric layer, so that when the metal plug is formed, it can ensure that the metal material is etched cleanly, thereby effectively avoiding the problem of device short circuit caused by metal residue, which is beneficial to improving the performance and yield of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0055] Those skilled in the art will appreciate that the drawings are provided for a better understanding of the present invention, but do not constitute any limitation on the scope of the present invention.
[0056] Figure 1 It is a schematic diagram of the uneven surface of the interlayer dielectric layer in the prior art.
[0057] Figure 2 It is a schematic diagram of metal etching residues existing at the corners in the prior art.
[0058] Figure 3 It is a flow chart of a method for preparing an IGBT device in an embodiment of the present invention.
[0059] Figure 4 Flow chart of the method for preparing the protruding structure in an embodiment of the present invention.
[0060] Figure 5 It is a schematic diagram of using a first mask to expose a second photoresist layer in an embodiment of the present invention.
[0061] Figure 6 Schematic diagram of the structure of the patterned second photoresist layer in an embodiment of the present invention.
[0062] Figure 7 Schematic diagram of etching a polysilicon layer using a patterned second photoresist layer in an embodiment of the present invention.
[0063] Figure 8 It is a schematic diagram of a polysilicon layer synchronously covering the trench gate trench and the substrate surface in an embodiment of the present invention.
[0064] Fig. 9 Schematic diagram of the structure of the first interlayer dielectric layer and the second interlayer dielectric layer in an embodiment of the present invention.
[0065] Fig.10 It is a flow chart of using a first photomask to remove part of the second interlayer dielectric layer in an embodiment of the present invention.
[0066] Fig.11 It is a schematic diagram of using a first mask to expose a first photoresist layer in an embodiment of the present invention.
[0067] Fig.12 is a schematic diagram of a patterned first photoresist layer in an embodiment of the present invention.
[0068] Fig.13 Schematic diagram of a portion of the second interlayer dielectric layer retained in an embodiment of the present invention.
[0069] Fig.14 It is a schematic diagram of using a second mask to expose a third photoresist layer in an embodiment of the present invention.
[0070] Fig.15 is a schematic diagram of a patterned first photoresist layer in an embodiment of the present invention.
[0071] Fig.16 Schematic diagram of a second interlayer dielectric layer having a smooth surface in an embodiment of the present invention.
[0072] Fig.17 Schematic diagram of the third interlayer dielectric layer in an embodiment of the present invention.
[0073] Fig.18 Schematic diagram of a fourth interlayer dielectric layer in an embodiment of the present invention.
[0074] Fig.19 Schematic diagram of forming a contact hole in an embodiment of the present invention.
[0075] Fig. 20 Schematic diagram of forming a metal material layer in an embodiment of the present invention.
[0076] Fig.21 Schematic diagram of forming a metal plug in an embodiment of the present invention.
[0077] And, in the attached drawings:
[0078] 101 - gate; 102 - field plate; 103 - oxide layer; 104 - interlayer dielectric layer; 105 - metal material layer; 105a - metal etching residue; 106 - tungsten through hole;
[0079] 200-first drift region; 201-polysilicon gate; 202-gate oxide layer; 203-second drift region; 204-oxide layer; 205-polysilicon layer; 206-second photoresist layer; 207-patterned second photoresist layer; 208-protruding structure; 209-first interlayer dielectric layer; 210-second interlayer dielectric layer; 210a-first rounded portion; 211-first photoresist layer; 212-patterned first photoresist layer; 213-third photoresist layer; 214-patterned third photoresist layer; 215-third interlayer dielectric layer; 216-fourth interlayer dielectric layer; 216a-second rounded portion; 217-contact hole; 218-metal material layer; 219-metal plug;
[0080] C-cell region; T-terminal region; A-corner; D-first width; d1-width of the top surface of the protruding structure; d2-the sum of the widths of the first interlayer dielectric layer and the second interlayer dielectric layer covering one side wall of the protruding structure. DETAILED DESCRIPTION
[0081] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different proportions are used. It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are only used to distinguish between the various components, elements, steps, etc. in the specification, and are not used to represent the logical relationship or sequential relationship between the various components, elements, steps, etc.
[0082] See also Figure 3 This embodiment provides a method for preparing an IGBT device, comprising:
[0083] Step 1 S10: providing a substrate; the substrate comprises a cell region and a terminal region, wherein a trench gate is formed in the cell region, and a protrusion structure is formed on the terminal region;
[0084] Step 2 S20: forming a first interlayer dielectric layer and a second interlayer dielectric layer on the surfaces of the substrate and the protruding structure in sequence;
[0085] Step three S30: removing a portion of the second interlayer dielectric layer, and retaining at least a portion of the second interlayer dielectric layer located on the protruding structure;
[0086] Step 4 S40: performing a first reflow process to make the remaining portion of the second interlayer dielectric layer have a smooth surface;
[0087] Step five S50: forming a third interlayer dielectric layer and a fourth interlayer dielectric layer in sequence on the surface of the first interlayer dielectric layer and the retained portion of the second interlayer dielectric layer;
[0088] Step six S60: performing a second reflow process to make the fourth interlayer dielectric layer have a smooth surface.
[0089] Based on this, the preparation method provided in this embodiment retains part of the second interlayer dielectric layer located on the protruding structure, and combines the first reflow process to make the second interlayer dielectric layer have a smooth surface, thereby achieving a balance between thickness control and morphology optimization of the interlayer dielectric layer. In addition, the fourth interlayer dielectric layer and the second reflow process are used to further smooth the surface of the film layer, which is conducive to etching the metal material cleanly when forming the metal plug, avoiding the problem of device short circuit caused by metal residue.
[0090] The following is combined with Figures 3 to 21 , specifically describe the method for preparing the IGBT device provided in this embodiment.
[0091] Step 1 S10: Please refer to Figures 4 to 8 , providing a substrate; the substrate includes a cell region C and a terminal region T, and a trench gate is formed in the cell region C, and a protrusion structure 208 is formed on the terminal region T.
[0092] It should be noted that the structure of the IGBT is mainly divided into a cell region C and a terminal region T, and the terminal region T surrounds the cell region C. The cell region C is a key device region, in which a gate, an emitter and various well regions are arranged; a field plate, a temperature sensor and a floating field ring are arranged in the terminal region T to improve the performance of the IGBT. The collector of the IGBT is generally arranged on the other side of the substrate. Based on this, the cell region C includes a first drift region 200, and a plurality of trench gates, a P well region and an N well region are arranged in the first drift region 200. The trench gate includes a polysilicon gate 201 and a gate oxide layer 202 formed on the periphery of the polysilicon gate 201. In other embodiments, the gate of the IGBT can also be a planar gate. And the terminal region T includes a second drift region 203, and a doping structure such as a floating field ring is arranged in the second drift region 203, and a field plate and / or a temperature sensor and other structures are arranged on the surface of the second drift region 203. Since structures such as field plates and temperature sensors have morphological features protruding from the surface of the substrate, they are collectively referred to as protruding structures 208 in this embodiment. It should be noted that each of the protruding structures 208 located on the terminal region T may be a field plate, or may be partially a field plate and partially a temperature sensor, which is not specifically limited in this embodiment, and this embodiment is only described by taking the simultaneous formation of a field plate and a temperature sensor as an example.
[0093] For details, please refer to Figure 4 The process of forming a field plate and / or a temperature sensor on the surface of the second drift region 203 comprises the following steps:
[0094] Sub-step 1 S101: Please refer to Figure 5 , a polysilicon layer 205 is formed on the substrate.
[0095] After forming trench gates, various well regions and various field rings in the first drift region 200 and the second drift region 203, respectively, an oxide layer 204 is formed on the surface of the substrate to protect the substrate structure and prevent doping ions from diffusing. Subsequently, a polysilicon layer 205 is formed on the substrate for subsequent preparation of a protruding structure of a field plate and / or a temperature sensor.
[0096] Sub-step 2 S102: Please refer to Figure 5 , coating a second photoresist layer 206 on the polysilicon layer 205 .
[0097] This embodiment does not limit whether the second photoresist layer 206 is a positive photoresist or a negative photoresist. If the second photoresist layer 206 is a positive photoresist, a cross-linking reaction will occur after exposure, so that the exposed part is dissolved and the unexposed part is insoluble. If the second photoresist layer 206 is a negative photoresist, the exposed part becomes insoluble after exposure, while the unexposed part is dissolved.
[0098] Sub-step 3 S103: Please refer to Figure 5 and Figure 6 The first mask M1 is used to expose the second photoresist layer 206 and form a patterned second photoresist layer 207 to cover a portion of the polysilicon layer 205 located on the terminal region T and expose the remaining portion of the polysilicon layer 205 .
[0099] Exemplarily, the second photoresist layer 206 is a negative photoresist, so the opening of the first mask M1 faces the terminal region T, and during the exposure process, the light beam is irradiated through the opening onto a portion of the photoresist layer 206 in the terminal region T, so that the portion of the photoresist layer 206 is retained, while the remaining photoresist layer 206 not irradiated by the light beam is dissolved, and a portion of the polysilicon layer 205 is exposed. Figure 7 A patterned second photoresist layer 207 is shown.
[0100] Sub-step 4 S104: Please refer to Figure 6 and Figure 7 , using the patterned second photoresist layer 207 as a barrier, etching and removing the exposed portion of the polysilicon layer 205 ; and the remaining portion of the polysilicon layer 205 is the protruding structure 208 .
[0101] Because the patterned second photoresist layer 207 exposes the polysilicon layer 205 located in the cell area C and also exposes part of the polysilicon layer 205 located in the terminal area T, the polysilicon layer 205 is etched with the patterned second photoresist layer 207 as a barrier, and the exposed part of the polysilicon layer 205 is removed, while the part of the polysilicon layer 205 covered by the patterned second photoresist layer 207 is retained. The polysilicon layer 205 retained at last can be used as a field plate in subsequent processes, and / or formed into a protruding structure 208 such as a temperature sensor with a PN junction through ion doping. In addition, after the protruding structure 208 is formed, the patterned second photoresist layer 207 is removed. It should be noted that the above-mentioned process for preparing the protruding structure 208 provided in this embodiment is only an example. And in other examples, the trench gate and the protruding structure 208 can be formed simultaneously. As Figure 8As shown, the formed polysilicon layer 205 not only covers the surface of the substrate in the cell region C and the terminal region T, but also fills and covers the trench for forming the trench gate in the cell region C. Then, under the blocking of the patterned second photoresist layer 207, the polysilicon layer 205 is etched until the oxide layer 204 on the substrate is exposed, and the polysilicon material filling of the trench gate and the formation of the protruding structure 208 are simultaneously completed. Therefore, this embodiment does not limit the specific process of forming the protruding structure 208.
[0102] Step 2 S20: Please refer to Fig. 9 A first interlayer dielectric layer 209 and a second interlayer dielectric layer 210 are sequentially formed on the surfaces of the substrate and the protruding structure 208 .
[0103] After the trench gate and various well regions are formed in the first drift region 200, a metal interconnection structure needs to be formed on the surface thereof to realize the electrical extraction of the gate and the emitter. Therefore, it is necessary to first form a first interlayer dielectric layer 209 on the surface of the substrate and the protruding structure 208. Preferably, the material of the first interlayer dielectric layer 209 includes undoped silicate glass material (Usable Size Grown, USG). And based on the characteristic of the material without ion doping, it can further protect the substrate structure and avoid the diffusion of doped ions in the substrate.
[0104] However, in view of the structural characteristics and process cost of the IGBT, the thickness of the interlayer dielectric layer in the metal interconnect structure is lower than the thickness of the protruding structure 208, so the part of the first interlayer dielectric layer 209 covering the protruding structure 208 will protrude from other surfaces. And because the protruding structure 208 has a vertical sidewall, the first interlayer dielectric layer 209 deposited thereon is likely to form a concave corner A, and metal etching residue problems are likely to occur when a metal plug or metal line is subsequently formed, thereby causing a short circuit of the device. Therefore, in order to alleviate the morphology problem of the concave corner A on the first interlayer dielectric layer 209, the second interlayer dielectric layer 210 is further formed on the surface of the first interlayer dielectric layer 209 in this embodiment. Among them, the material of the second interlayer dielectric layer 210 contains boron ions. And preferably, the material of the second interlayer dielectric layer 210 includes borophospho-silicate glass (BPSG) or boron-silicate glass (BSG). Both BPSG and BSG are doped with boron ions, which can enhance the fluidity of the material through the reflow process, making the surface of the film layer smooth, thereby avoiding pits or other concave structures, and effectively alleviating the problem of metal etching residues. It should be noted that the first interlayer dielectric layer 209 located below the second interlayer dielectric layer 210 can also prevent the ions in the second interlayer dielectric layer 210 from diffusing into the substrate, which is beneficial to improving the stability of the device.
[0105] Step 3 S30: Please refer to Figures 9 to 15 , removing a portion of the second interlayer dielectric layer 210 , and retaining at least a portion of the second interlayer dielectric layer 210 located on the protruding structure 208 .
[0106] As can be seen from the above, the purpose of depositing the second interlayer dielectric layer 210 in the preparation method provided in this embodiment is to optimize the morphology of the corner A of the first interlayer dielectric layer 209 on the protruding structure 208. In view of the structural characteristics and process costs of the IGBT, the interlayer dielectric layer in the IGBT device has strict film thickness requirements. Therefore, only the second interlayer dielectric layer 210 located at the protruding structure 208 and its surrounding adjacent portions needs to be retained, and the second interlayer dielectric layer 210 in other portions needs to be etched and removed to ensure that the film thickness requirements are met.
[0107] Specifically, in one example, Fig.10 As shown, the process of removing part of the second interlayer dielectric layer 210 includes:
[0108] Sub-step 1 S301: Please refer to Fig.11 , coating a first photoresist layer 211 on the second interlayer dielectric layer 210 .
[0109] Sub-step 2 S302: Please refer to Fig.11 and Fig.12 , using a first mask M1, exposing the first photoresist layer 211, and forming a patterned first photoresist layer 212 to at least cover a portion of the second interlayer dielectric layer 210 located on the top surface and sidewall of the protruding structure 208, and exposing the remaining portion of the second interlayer dielectric layer 210.
[0110] according to Figure 5 , Figure 6 , Fig.11 and Fig.12 It can be seen that the exposed and covered areas of the patterned first photoresist layer 212 and the patterned second photoresist layer 207 are the same. Therefore, in order to reduce the cost, the same first photomask M1 can be used, and the polarity of the first photoresist layer 211 and the second photoresist layer 206 are the same. That is, the first photoresist layer 211 and the second photoresist layer 206 are both positive photoresists, or both are negative photoresists.
[0111] Furthermore, in order to optimize the sidewall morphology of the first interlayer dielectric layer 209 and avoid forming pits or concave structures, the area shielded by the patterned first photoresist layer 212 includes not only the portion of the second interlayer dielectric layer 210 located on the top surface of the protruding structure 208, but also the portion of the second interlayer dielectric layer 210 located on the sidewall of the protruding structure 208 and its surroundings. Therefore, if the same first photomask M1 is used to obtain different exposure widths, the light sensitivity of the first photoresist layer 211 should be different from the light sensitivity of the second photoresist layer 206. For example, Figure 5 , Figure 6 , Fig.11 and Fig.12 As shown, the first photoresist layer 211 and the second photoresist layer 206 are both negative photoresists, and the opening width of the first mask M1 toward the protruding structure 208 is equal to the width d1 of the top surface of the protruding structure 208. Then, under the same exposure adjustment, the width of the portion of the polysilicon layer 205 covered by the patterned second photoresist layer 207 is equal to the width d1 of the top surface of the protruding structure 208. The light sensitivity of the first photoresist layer 211 is greater than the light sensitivity of the second photoresist layer 206, so that the width of the portion of the second interlayer dielectric layer 210 covered by the patterned first photoresist layer 212 is greater than the width d1 of the top surface of the protruding structure 208. Preferably, the width of the portion of the second interlayer dielectric layer 210 covered by the patterned first photoresist layer 212 is a first width D, and the first width D satisfies the following formula:
[0112] D≥d1+2d2;
[0113] Wherein, d1 is the width of the top surface of the protruding structure 208 , and d2 is the sum of the widths of the first interlayer dielectric layer 209 and the second interlayer dielectric layer 210 covering a side wall of the protruding structure 208 .
[0114] Alternatively, when both the first photoresist layer 211 and the second photoresist layer 206 are positive photoresists, and the shielding width of the first photomask M1 toward the protruding structure 208 is equal to the width d1 of the top surface of the protruding structure 208, the light sensitivity of the first photoresist layer 211 should be less than the light sensitivity of the second photoresist layer 206, and different exposure widths of the patterned first photoresist layer 212 and the patterned second photoresist layer 207 can also be obtained. The width referred to in this embodiment is the distance in the direction parallel to the substrate surface in the figure.
[0115] Sub-step 3 S303: Please refer to Fig.12 and Fig.13 , using the patterned first photoresist layer 212 as a barrier, etching away the exposed portion of the second interlayer dielectric layer 210, and retaining the remaining portion of the second interlayer dielectric layer 210. It can be understood that removing the exposed portion of the second interlayer dielectric layer 210 can effectively control the total thickness of the overall dielectric layer structure on the substrate to meet the device requirements. And, after the second interlayer dielectric layer 210 is etched, the patterned first photoresist layer 212 is cleaned and removed.
[0116] In another example, see Fig.14 and Fig.15In order to ensure that the portion of the second interlayer dielectric layer 210 located on the top surface and the sidewall of the protruding structure 208 can be shielded by the photoresist, a third photoresist layer 213 can be coated on the surface of the second interlayer dielectric layer 210, and the third photoresist layer 213 can be a positive photoresist or a negative photoresist. Then, a second photomask M2 is used to expose the third photoresist layer 213 and form a patterned third photoresist layer 214 to cover the portion of the second interlayer dielectric layer 210 located on the protruding structure 208 and the adjacent substrate, and expose the remaining portion of the second interlayer dielectric layer 210. Optionally, the photosensitivity of the third photoresist layer 213 can be consistent with the photosensitivity of the second photoresist layer 206. Based on this, when the third photoresist layer 213 is a negative photoresist, and the opening width of the second photomask M2 toward the protruding structure 208 is the first width D; or, the third photoresist layer 213 is a positive photoresist, and the blocking width of the second photomask M2 toward the protruding structure 208 is the first width D. Therefore, the morphology of the patterned third photoresist layer 214 is consistent with the morphology of the patterned first photoresist layer 212, and the patterned third photoresist layer 214 not only covers the second interlayer dielectric layer 210 located on the top surface of the protruding structure 208, but also covers part of the second interlayer dielectric layer 210 located on the sidewall of the protruding structure 208 and the surrounding substrate. Then, using the patterned third photoresist layer 214 as a barrier, etching away the exposed part of the second interlayer dielectric layer 210, and a similar structure to that of FIG. Fig.13 The second interlayer dielectric layer 210 has the same morphological features as shown, that is, only the second interlayer dielectric layer 210 located on the top surface, sidewall and adjacent substrate of the protruding structure 208 is retained. And, after the second interlayer dielectric layer 210 is etched, the patterned third photoresist layer 214 is cleaned and removed.
[0117] Step 4 S40: Please refer to Fig.16 , performing a first reflow process so that the remaining portion of the second interlayer dielectric layer 210 has a smooth surface.
[0118] Since the material of the second interlayer dielectric layer 210 includes boron ions, the second interlayer dielectric layer 210 has better fluidity during the first reflow process performed at high temperature, so that the second interlayer dielectric layer 210 coated on the first interlayer dielectric layer 209 has a smooth surface. In particular, the second interlayer dielectric layer 210 located on the sidewall of the protruding structure 208 forms a smooth sidewall after being processed by the first reflow process, which is defined as a first smooth portion 210a in this embodiment. The first smooth portion 210a coats the first interlayer dielectric layer 209 located on the sidewall of the protruding structure 208, covers the first interlayer dielectric layer 209 located on the portion of the top surface of the protruding structure 208 connected to the sidewall of the protruding structure 208, and covers the first interlayer dielectric layer 209 located on the portion of the substrate connected to the sidewall of the protruding structure 208. Therefore, under the coverage of the first smooth portion 210a, the slope of the dielectric layer located on the protruding structure 208 is effectively reduced, so that the dielectric layer corresponding to the corner of the protruding structure 208 becomes smooth and gentle, which is beneficial to avoid metal etching residues in subsequent processes, thereby avoiding device short circuit problems and improving device performance and yield.
[0119] Step 5 S50: Please refer to Fig.17 and Fig.18 A third interlayer dielectric layer 215 and a fourth interlayer dielectric layer 216 are sequentially formed on the surfaces of the first interlayer dielectric layer 209 and a remaining portion of the second interlayer dielectric layer 210 .
[0120] Step 6 S60: Please refer to Fig.18 , performing a second reflow process to make the fourth interlayer dielectric layer 216 have a smooth surface.
[0121] Specifically, after forming the second interlayer dielectric layer 210 with a smooth surface, in order to avoid ion diffusion in the second interlayer dielectric layer 210, a third interlayer dielectric layer 215 is formed on the exposed surfaces of the first interlayer dielectric layer 209 and the second interlayer dielectric layer 210, so that the retained second interlayer dielectric layer 210 is covered by the first interlayer dielectric layer 209 and the third interlayer dielectric layer 215. Preferably, the material of the third interlayer dielectric layer 215 is consistent with that of the first interlayer dielectric layer 209, both including USG, that is, undoped dielectric material, which can effectively block ions in the second interlayer dielectric layer 210 and avoid affecting device performance. In addition, since the second interlayer dielectric layer 210 has a smooth surface, the third interlayer dielectric layer 215 deposited thereon also has a similar morphology.
[0122] However, in order to further optimize the morphology of the dielectric layer and enhance the device performance, after forming the third interlayer dielectric layer 215, the preparation method provided in this embodiment further forms a fourth interlayer dielectric layer 216 on the surface of the third interlayer dielectric layer 215. And preferably, the material of the fourth interlayer dielectric layer 216 contains boron ions, and its material may include: BPSG or BSG. It should be noted that the formed fourth interlayer dielectric layer 216 can optimize the performance of the IGBT device and enhance its withstand voltage capability on the one hand; on the other hand, because the material of the fourth interlayer dielectric layer 216 contains boron ions, it is beneficial to enhance the fluidity of the material. Therefore, performing a second reflow process on the fourth interlayer dielectric layer 216 can not only further optimize the morphology of the top surface of the semiconductor structure and form a smoother surface, but also improve the radial uniformity of the film layer.
[0123] Preferably, the content of boron ions in the fourth interlayer dielectric layer 216 is greater than the content of boron ions in the second interlayer dielectric layer 210, so that in the subsequent second reflow process, the slope of the protruding portion of the fourth interlayer dielectric layer 216 relative to the flat portion is lower, and the rounding effect is better. Based on this, after the second reflow process is performed, the fourth interlayer dielectric layer 216 has a second rounded portion 216a. And the second rounded portion 216a covers the portion of the third interlayer dielectric layer 215 located on the first rounded portion 210a. That is, the second rounded portion 216a makes the sidewall and corner of the protruding structure 208 cause the protruding morphology of the dielectric layer to be further smoothed, which is beneficial to avoid metal etching residues in subsequent processes, thereby avoiding device short circuit problems and improving device performance and yield.
[0124] Furthermore, after performing the second reflow process, the method for preparing the IGBT device also includes: forming a metal plug 219 at least on the side of the trench gate, and the metal plug 219 penetrates the first interlayer dielectric layer 209, the third interlayer dielectric layer 215 and the fourth interlayer dielectric layer 216.
[0125] Specifically, Fig.19As shown, a plurality of contact holes 217 are formed by etching process. It should be noted that the above reflow process is performed before forming the contact holes 217 to avoid affecting the morphology of the contact holes 217 and causing the contact holes 217 to be tilted. Specifically, in the cell region C, in order to lead out the emitter, the contact holes 217 can be formed on the side of the trench gate, and the contact holes 217 extend into the first drift region 200 and penetrate the first interlayer dielectric layer 209, the third interlayer dielectric layer 215 and the fourth interlayer dielectric layer 216. And, in the terminal region T, the contact holes 217 can also be formed on the protruding structure 208 used as a temperature sensor, and the contact holes 217 extend into the protruding structure 208 and penetrate the first interlayer dielectric layer 209, the second interlayer dielectric layer 210, the third interlayer dielectric layer 215 and the fourth interlayer dielectric layer 216.
[0126] Secondly, if Fig. 20 As shown in FIG. 2 , a metal material layer 218 is formed on the surface of the fourth interlayer dielectric layer 216 having a smooth morphology, and the metal material layer 218 fills and covers each of the contact holes 217. Finally, as shown in FIG. Fig.21 As shown, an etching process is used to remove part of the metal material layer 218 on the surface of the fourth interlayer dielectric layer 216, and the metal material layer 218 in the contact hole 217 is retained to form each of the metal plugs 219. The metal plug 219 located in the cell region C extends into the first drift region 200 and penetrates the first interlayer dielectric layer 209, the third interlayer dielectric layer 215 and the fourth interlayer dielectric layer 216. The metal plug 219 located in the terminal region T can extend into the protruding structure 208 and penetrate the first interlayer dielectric layer 209, the second interlayer dielectric layer 210, the third interlayer dielectric layer 215 and the fourth interlayer dielectric layer 216. Optionally, the material of the metal material layer 218 is metal tungsten.
[0127] Furthermore, the etching process used in the above-mentioned method for preparing the IGBT device may be a dry etching process or a wet etching process. Also, the deposition method used includes but is not limited to physical vapor deposition or chemical vapor deposition.
[0128] Based on the same concept, this embodiment also provides an IGBT device. Fig.21 The IGBT device includes: a substrate, a first interlayer dielectric layer 209 , a second interlayer dielectric layer 210 , a third interlayer dielectric layer 215 , a fourth interlayer dielectric layer 216 and a plurality of metal plugs 219 .
[0129] Specifically, the substrate includes a cell region C and a terminal region T; the cell region C is a main device region, and a trench gate is formed in the cell region C; the terminal region T surrounds the cell region C, and a protruding structure 208 is formed on the terminal region T. Preferably, a plurality of protruding structures 208 are formed on the terminal region T, and each of the protruding structures 208 is a field plate and / or a temperature sensor. Furthermore, an oxide layer 204 is formed on the surface of the substrate to protect the substrate; and the protruding structure 208 can be located on the oxide layer 204.
[0130] The first interlayer dielectric layer 209 covers the surface of the substrate and the protruding structure 208. Since an oxide layer 204 is formed on the surface of the substrate, the first interlayer dielectric layer 209 can be directly connected to the oxide layer 204. Preferably, the material of the first interlayer dielectric layer 209 includes USG to have a good electrical isolation effect. However, since the protruding structure 208 protrudes from the substrate and has a vertical sidewall, the first interlayer dielectric layer 209 covering the protruding structure 208 also protrudes from the protruding structure 208 and also has a vertical sidewall. This morphology is prone to forming etching residues in the subsequent metal etching process, affecting device performance. Therefore, the IGBT device provided in this embodiment is also provided with a second interlayer dielectric layer 210.
[0131] The second interlayer dielectric layer 210 covers a portion of the first interlayer dielectric layer 209 located on the protruding structure 208. Preferably, the second interlayer dielectric layer 210 not only covers the first interlayer dielectric layer 209 located on the top surface of the protruding structure 208, but also covers the first interlayer dielectric layer 209 located on the sidewall of the protruding structure 208, and covers the first interlayer dielectric layer 209 located on a portion of the substrate connected to the sidewall of the protruding structure 208, thereby achieving full coverage of the protruding portion of the first interlayer dielectric layer 209 and its adjacent areas. Furthermore, the material of the second interlayer dielectric layer 210 includes boron ions, such as BPSG or BSG, and has good reflow performance. Therefore, after the first reflow process, the second interlayer dielectric layer 210 has a smooth surface and a first smooth portion 210a. Fig.21As shown, the first rounded portion 210a covers the first interlayer dielectric layer 209 located on the sidewall of the protruding structure 208, and covers the top surface of the portion of the protruding structure 208 connected to the sidewall of the protruding structure 208 and the first interlayer dielectric layer 209 on the substrate. In other words, the first rounded portion 210a completely covers the vertical sidewall of the first interlayer dielectric layer 209 formed with the protruding structure 208 and its adjacent area, effectively reducing the slope of the sidewall, so that the dielectric layer located on the protruding structure 208 has a smooth and gentle surface, avoiding the occurrence of pits and other structures to cause metal residues.
[0132] The third interlayer dielectric layer 215 covers the exposed portions of the first interlayer dielectric layer 209 and the second interlayer dielectric layer 210. Preferably, the material of the third interlayer dielectric layer 215 is consistent with that of the first interlayer dielectric layer 209, both of which include USG, which can effectively block ions in the second interlayer dielectric layer 210 and avoid affecting device performance.
[0133] The fourth interlayer dielectric layer 216 covers the third interlayer dielectric layer 215. Preferably, the material of the fourth interlayer dielectric layer 216 contains boron ions. Exemplarily, the material of the fourth interlayer dielectric layer 216 is BPSG or BSG, which has good reflow performance. Based on this, after the second reflow process, the fourth interlayer dielectric layer 216 has a smooth surface and a second smooth portion 216a. Fig.21 As shown, the second rounded portion 216a covers the third interlayer dielectric layer 215 located on the first rounded portion 210a and its periphery, so that the top surface of the semiconductor structure has a smoother surface. Further, the content of boron ions in the fourth interlayer dielectric layer 216 is greater than the content of boron ions in the second interlayer dielectric layer 210, so that the slope of the second rounded portion 216a is lower than that of the first rounded portion 210a, the rounded effect is better, and the problem of metal etching residue in subsequent processes is further alleviated.
[0134] A plurality of metal plugs 219 are used to realize electrical lead-out. Fig.21 As shown, the metal plug 219 located in the cell region C is located at the side of the trench gate, and sequentially penetrates the fourth interlayer dielectric layer 216, the third interlayer dielectric layer 215 and the first interlayer dielectric layer 209, and extends into the substrate. When part of the protruding structure 208 in the terminal region T is a temperature sensor, part of the metal plug 219 sequentially penetrates the fourth interlayer dielectric layer 216, the third interlayer dielectric layer 215, the second interlayer dielectric layer 210 and the first interlayer dielectric layer 209, and extends into the protruding structure 208.
[0135] Preferably, the IGBT device is prepared by adopting the above-mentioned method for preparing the IGBT device.
[0136] In summary, in the IGBT device and its preparation method provided in this embodiment, in order to take into account the thickness control and morphology optimization of the interlayer dielectric layer, only the part of the second interlayer dielectric layer 210 located on the protruding structure 208 is retained, and the first reflow process is used to make the second interlayer dielectric layer 210 have a smooth surface. The first interlayer dielectric layer 209 and the third interlayer dielectric layer 215 are used to cover the second interlayer dielectric layer 210 to prevent its ion diffusion from affecting the device performance. In addition, the fourth interlayer dielectric layer 216 is formed on the surface of the third interlayer dielectric layer 215, and the second reflow process is used to further optimize the morphology of the top surface of the semiconductor structure, so that the protruding surface is smoother and pits or other concave structures are avoided, so that when the metal plug 219 is formed, it can ensure that the metal material is etched cleanly, thereby effectively avoiding the problem of device short circuit caused by metal residue, which is conducive to improving the performance and yield of the device.
[0137] In addition, it should be recognized that although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still belongs to the scope of protection of the technical solution of the present invention.
Claims
1. A method for preparing an IGBT device, characterized in that: include: A substrate is provided; the substrate comprises a cell region and a terminal region, a trench gate is formed in the cell region, and a protrusion structure is formed on the terminal region; Sequentially forming a first interlayer dielectric layer and a second interlayer dielectric layer on the surfaces of the substrate and the protruding structure; removing a portion of the second interlayer dielectric layer and retaining at least a portion of the second interlayer dielectric layer located on the protruding structure; Performing a first reflow process so that a remaining portion of the second interlayer dielectric layer has a smooth surface; Sequentially forming a third interlayer dielectric layer and a fourth interlayer dielectric layer on the surface of the first interlayer dielectric layer and a retained portion of the second interlayer dielectric layer; A second reflow process is performed to make a portion of the fourth interlayer dielectric layer have a smooth surface.
2. The method for preparing an IGBT device according to claim 1, characterized in that: The materials of the second interlayer dielectric layer and the fourth interlayer dielectric layer contain boron ions.
3. The method for preparing an IGBT device according to claim 2, characterized in that: The content of boron ions in the fourth interlayer dielectric layer is greater than the content of boron ions in the second interlayer dielectric layer.
4. The method for preparing an IGBT device according to claim 1 or 2, characterized in that: The materials of the first interlayer dielectric layer and the third interlayer dielectric layer both include USG; the materials of the second interlayer dielectric layer and the fourth interlayer dielectric layer both include BPSG or BSG.
5. The method for preparing an IGBT device according to claim 1, characterized in that: The process of removing a portion of the second interlayer dielectric layer and retaining at least a portion of the second interlayer dielectric layer located on the protruding structure includes: coating a first photoresist layer on the second interlayer dielectric layer; Using a first photomask to expose the first photoresist layer and form a patterned first photoresist layer to at least cover a portion of the second interlayer dielectric layer located on the top surface and the sidewall of the protruding structure and expose the remaining portion of the second interlayer dielectric layer; The patterned first photoresist layer is used as a barrier to etch away the exposed portion of the second interlayer dielectric layer, and retain the remaining portion of the second interlayer dielectric layer.
6. The method for preparing an IGBT device according to claim 5, characterized in that: The process of forming the protruding structure on the terminal region includes: forming a polysilicon layer on the substrate; coating a second photoresist layer on the polysilicon layer; Using the first photomask to expose the second photoresist layer and form a patterned second photoresist layer to cover a portion of the polysilicon layer located on the terminal region and expose the remaining portion of the polysilicon layer; The patterned second photoresist layer is used as a barrier to etch and remove the exposed portion of the polysilicon layer; and the remaining portion of the polysilicon layer is the protruding structure.
7. The method for preparing an IGBT device according to claim 6, characterized in that: The first photoresist layer and the second photoresist layer are both negative photoresists, and the opening width of the first photomask toward the protruding structure is equal to the width of the top surface of the protruding structure; Alternatively, both the first photoresist layer and the second photoresist layer are positive photoresists, and the shielding width of the first photomask toward the protruding structure is equal to the width of the top surface of the protruding structure; as well as, The photosensitivity of the first photoresist layer is different from the photosensitivity of the second photoresist layer, so that the width of the portion of the polysilicon layer covered by the patterned second photoresist layer is equal to the width of the top surface of the protruding structure; and the width of the portion of the second interlayer dielectric layer covered by the patterned first photoresist layer is a first width, and the first width D satisfies the following formula: D≥d1+2d2; Wherein, d1 is the width of the top surface of the protruding structure, and d2 is the sum of the widths of the first interlayer dielectric layer and the second interlayer dielectric layer covering a side wall of the protruding structure.
8. The method for preparing an IGBT device according to claim 1 or 6, characterized in that: The raised structure includes a field plate and / or a temperature sensor.
9. The method for preparing an IGBT device according to claim 1, characterized in that: The process of removing a portion of the second interlayer dielectric layer and retaining at least a portion of the second interlayer dielectric layer located on the protruding structure includes: coating a third photoresist layer on the second interlayer dielectric layer; Using a second photomask to expose the third photoresist layer and form a patterned third photoresist layer to at least cover a portion of the second interlayer dielectric layer located on the top surface and the sidewall of the protruding structure and expose the remaining portion of the second interlayer dielectric layer; Using the patterned third photoresist layer as a barrier, etching and removing the exposed portion of the second interlayer dielectric layer, and retaining the remaining portion of the second interlayer dielectric layer; The third photoresist layer is a negative photoresist, and the opening width of the second photomask toward the protruding structure is a first width D; or the third photoresist layer is a positive photoresist, and the shielding width of the second photomask toward the protruding structure is a first width D; and the first width D satisfies the following formula: D≥d1+2d2; Wherein, d1 is the width of the top surface of the protruding structure, and d2 is the sum of the widths of the first interlayer dielectric layer and the second interlayer dielectric layer covering a side wall of the protruding structure.
10. The method for preparing an IGBT device according to claim 1, characterized in that: After performing the second reflow process, the method for preparing the IGBT device further includes: A metal plug is formed at least on the side of the trench gate, and the metal plug penetrates the first interlayer dielectric layer, the third interlayer dielectric layer and the fourth interlayer dielectric layer.
11. The method for preparing an IGBT device according to claim 10, characterized in that: In the process of forming the metal plug on the side of the trench gate, the method for preparing the IGBT device further includes: The metal plug is formed on the protruding structure, and the metal plug penetrates the first interlayer dielectric layer, the second interlayer dielectric layer, the third interlayer dielectric layer and the fourth interlayer dielectric layer.
12. An IGBT device, characterized in that: include: A substrate; the substrate comprises a cell region and a terminal region, a trench gate is formed in the cell region, and a protrusion structure is formed on the terminal region; a first interlayer dielectric layer; The first interlayer dielectric layer covers the surfaces of the substrate and the protruding structure; a second interlayer dielectric layer; The second interlayer dielectric layer covers a portion of the first interlayer dielectric layer located on the protruding structure; After the first reflow process, the second interlayer dielectric layer has a first rounded portion, and the first rounded portion at least covers a portion of the first interlayer dielectric layer located on the side wall of the protruding structure; a third interlayer dielectric layer; The third interlayer dielectric layer covers the exposed portions of the first interlayer dielectric layer and the second interlayer dielectric layer; a fourth interlayer dielectric layer; The fourth interlayer dielectric layer covers the third interlayer dielectric layer; After the second reflow process, the fourth interlayer dielectric layer has a second rounded portion, and the second rounded portion at least covers a portion of the third interlayer dielectric layer located on the first rounded portion.
13. The IGBT device according to claim 10, characterized in that: The first rounded portion also covers a portion of the top surface of the protruding structure connected to the side wall of the protruding structure and a portion of the first interlayer dielectric layer on the substrate.
14. The IGBT device according to claim 10, characterized in that: include: The materials of the second interlayer dielectric layer and the fourth interlayer dielectric layer contain boron ions.
15. The IGBT device according to claim 10, characterized in that: The content of boron ions in the fourth interlayer dielectric layer is greater than the content of boron ions in the second interlayer dielectric layer.
16. The IGBT device according to claim 10 or 12, characterized in that: The materials of the first interlayer dielectric layer and the third interlayer dielectric layer both include USG; the materials of the second interlayer dielectric layer and the fourth interlayer dielectric layer both include BPSG or BSG.
17. The IGBT device according to claim 10, characterized in that: The raised structure includes a field plate and / or a temperature sensor.
18. The IGBT device according to claim 10, characterized in that: The IGBT device further includes: a plurality of metal plugs; at least some of the metal plugs are located on the sides of the trench gate and penetrate the first interlayer dielectric layer, the third interlayer dielectric layer and the fourth interlayer dielectric layer.
19. The IGBT device according to claim 18, characterized in that: Some of the metal plugs are located on the protruding structure, and the metal plugs penetrate the first interlayer dielectric layer, the second interlayer dielectric layer, the third interlayer dielectric layer, and the fourth interlayer dielectric layer.