Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. A gate structure on the substrate; the channel column is located on the substrate and penetrates through the gate structure in the longitudinal direction; the side wall extends along the longitudinal direction and is positioned between the side wall of the channel column and the gate structure; and the compensation layer is filled at the bottom position of the side wall and in a gap between the channel column and the gate structure. The working performance of the semiconductor structure can be improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Semiconductor devices are integrated on packages to realize integrated circuit (IC) chips to meet the use conditions of various electronic products. In recent years, the demand for integrated systems for dedicated processing applications has continued to increase in complex scenarios such as the Internet of Things and edge computing. Functionally integrated systems require the integration of underlying materials. However, traditional semiconductor memory devices can be two-dimensional or planar semiconductor memory devices, and their integration level is an important factor in determining product prices.

[0003] In addition, the integration level mainly depends on the area occupied by the unit memory cell and is therefore greatly affected by the level of fine pattern formation technology. However, the integration level of two-dimensional semiconductor memory devices is improving, but it is still limited because the miniaturization of patterns requires ultra-expensive equipment. Therefore, it is necessary to increase the integration level of semiconductor memory devices to meet the superior performance and low cost required by consumers. Summary of the invention

[0004] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which are beneficial to improving the working performance of the semiconductor structure.

[0005] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate; a gate structure located on the substrate; a channel column located on the substrate and penetrating the gate structure along the longitudinal direction; a side wall extending along the longitudinal direction and located between the side wall of the channel column and the gate structure; and a compensation layer filled in the gap between the channel column and the gate structure at the bottom of the side wall.

[0006] Optionally, the semiconductor structure further includes: a spacer layer located between the sidewall and the sidewall of the channel column; and a compensation layer is also filled in the gap between the channel column and the gate structure at the bottom of the spacer layer.

[0007] Optionally, the spacer layer is a protective layer, and the protective layer covers the side walls of the side wall; or, the spacer layer is an air gap.

[0008] Optionally, the spacer layer is a protective layer, and the material of the protective layer includes amorphous silicon, polycrystalline silicon, a combination of polycrystalline silicon, silicon oxide and tungsten, or a combination of polycrystalline silicon, silicon oxide and titanium nitride.

[0009] Optionally, the compensation layer is also filled in the gap enclosed by the top of the side wall and the spacer layer.

[0010] Optionally, the sidewall includes a first sidewall covering the sidewall of the gate structure, and a second sidewall covering the sidewall of the first sidewall; at the bottom of the sidewall, the gap filled by the compensation layer is surrounded by the bottom of the second sidewall, the bottom of the spacer layer, the first sidewall, and the sidewall of the channel column; at the top of the sidewall, the gap filled by the compensation layer is surrounded by the top of the second sidewall, the sidewall of the spacer layer, and the sidewall of the first sidewall.

[0011] Optionally, the material of the first sidewall spacer includes silicon nitride; and the material of the second sidewall spacer includes silicon oxide.

[0012] Optionally, the material of the compensation layer includes silicon nitride.

[0013] Optionally, the semiconductor structure also includes: a top dielectric layer covering the top surface of the gate structure; a bottom dielectric layer located between the gate structure and the substrate; the channel column also extends through the top dielectric layer and the bottom dielectric layer; the side wall also extends between the side wall of the channel column and the top dielectric layer; and the compensation layer also fills the gap between the channel column and the bottom dielectric layer.

[0014] Optionally, the semiconductor structure further includes: a source-drain doped layer, which is located in the substrate, and the source-drain doped layer is exposed on the top surface of the substrate; and a channel column is located on the source-drain doped layer and in contact with the source-drain doped layer.

[0015] Optionally, a groove located in the channel column at a partial height is formed on one side of the top of the channel column, and the semiconductor structure further includes: an insulating layer filled in the groove.

[0016] Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate, on which a gate structure is formed; forming an opening that penetrates the gate structure; forming a side wall covering the side wall of the opening; performing gap compensation processing at the bottom corner of the opening to form a compensation layer that fills the gap at the bottom of the side wall; and forming a channel column in the opening that is located on the substrate and penetrates the gate structure.

[0017] Optionally, before performing the gap compensation treatment at the bottom corner of the opening, it also includes: forming a protective layer covering the side wall; in the step of performing the gap compensation treatment at the bottom corner of the opening, the compensation layer is also filled in the gap at the bottom of the protective layer at the bottom corner of the opening; in the step of forming a channel column located on the substrate and passing through the gate structure in the opening, the channel column is in contact with the protective layer.

[0018] Optionally, after forming a channel column in the opening which is located on the substrate and penetrates the gate structure, the method further includes: removing the protective layer to form an air gap between the sidewall and the sidewall of the channel column.

[0019] Optionally, in the step of performing gap compensation processing at the bottom corner of the opening, the compensation layer is also filled in the gap surrounded by the top of the side wall and the protective layer.

[0020] Optionally, the step of forming a sidewall covering the sidewall of the opening includes: forming a sidewall material layer covering the sidewall and bottom of the opening, and the top of the gate structure; removing the sidewall material layer at the bottom of the opening and the top of the gate structure, and retaining the sidewall material layer covering the sidewall of the opening as the sidewall.

[0021] Optionally, in the step of providing a substrate, a top dielectric layer is also formed on the top of the gate structure, and a bottom dielectric layer is also formed between the gate structure and the substrate; in the step of forming an opening that penetrates the gate structure, the opening also penetrates the top dielectric layer, and the opening also extends into a portion of the thickness of the bottom dielectric layer; in the step of removing the sidewall material layer at the bottom of the opening and the top of the gate structure, it also includes: removing the remaining thickness of the bottom dielectric layer to expose the top surface of the substrate; in the step of performing gap compensation processing at the bottom corner of the opening, the compensation layer also fills the gap enclosed by the bottom dielectric layer and the substrate at the bottom corner of the opening.

[0022] Optionally, the step of forming a sidewall material layer covering the sidewalls and bottom of the opening and the top of the gate structure includes: forming a first sidewall material layer covering the sidewalls and bottom of the opening and the top of the gate structure; forming a second sidewall material layer covering the first sidewall material layer; in the step of removing the sidewall material layer at the bottom of the opening and the top of the gate structure, the first sidewall material layer and the second sidewall material layer at the bottom of the opening and the top of the gate structure are removed, and the first sidewall material layer covering the sidewall of the opening is retained as the first sidewall, and the second sidewall material layer covering the sidewall of the opening is retained as the second sidewall; in the step of performing gap compensation processing at the corner of the bottom of the opening, the compensation layer is filled in the gap surrounded by the bottom of the second sidewall, the bottom of the protective layer, and the first sidewall, and the compensation layer is also filled in the gap surrounded by the top of the second sidewall, the sidewall of the protective layer, and the sidewall of the first sidewall.

[0023] Optionally, before removing the sidewall material layer at the bottom of the opening and the top of the gate structure, the step also includes: forming a protective material layer covering the sidewall material layer; the step of removing the sidewall material layer at the bottom of the opening and the top of the gate structure also includes: removing the protective material layer at the bottom of the opening and the top of the gate structure, and retaining the protective material layer covering the sidewall sidewall as a protective layer.

[0024] Optionally, a dry etching process is used to remove the sidewall material layer at the bottom of the opening and the top of the gate structure; after removing the sidewall material layer at the bottom of the opening and the top of the gate structure, before performing gap compensation processing at the bottom corner of the opening, it also includes: cleaning the sidewall.

[0025] Optionally, a gap compensation process is performed at the bottom corner of the opening to form a compensation layer filling the gap at the bottom of the sidewall, including the steps of: forming a compensation material layer covering the bottom of the opening, the sidewall sidewalls of the opening, the top of the gate structure, and the gap filling the bottom of the sidewall; removing the compensation material layer covering the bottom of the opening, the sidewall sidewalls of the opening, and the top of the gate structure, and retaining the compensation material layer filling the gap at the bottom of the sidewall as the compensation layer.

[0026] Optionally, an atomic layer deposition process or a low pressure chemical vapor deposition process is used to form a compensation material layer covering the bottom of the opening, the sidewalls of the opening, the top of the gate structure, and the gap filling the bottom of the sidewalls.

[0027] Optionally, a wet etching process is used to remove the compensation material layer covering the bottom of the opening, the sidewalls of the opening, and the top of the gate structure.

[0028] Optionally, the etching solution of the wet etching process includes a phosphoric acid solution; the mass percentage of phosphoric acid in the phosphoric acid solution is 40wt% to 86wt%; and the process temperature of the wet etching process is 100°C to 160°C.

[0029] Optionally, in the step of providing a substrate, a source-drain doped layer is also formed in the substrate, and the source-drain doped layer is exposed on the top surface of the substrate; in the step of forming an opening that passes through the gate structure, an opening is formed above the source-drain doped layer; in the step of forming a channel column located on the substrate and passing through the gate structure in the opening, the channel column is formed on the source-drain doped layer and in contact with the source-drain doped layer.

[0030] Optionally, in the step of forming a channel column in the opening that is located on the substrate and passes through the gate structure, the channel column fills the opening; or, in the step of forming a channel column in the opening that is located on the substrate and passes through the gate structure, a groove in the channel column at a partial height is formed on one side of the top of the channel column; and an insulating layer filling the groove is formed.

[0031] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0032] In the semiconductor structure provided by the embodiment of the present invention, the channel column is located on the substrate and penetrates the gate structure in the longitudinal direction, the side wall extends in the longitudinal direction and is located between the side wall of the channel column and the gate structure, and the compensation layer is filled in the gap between the channel column and the gate structure at the bottom of the side wall; in the embodiment of the present invention, at the bottom of the side wall, the gap between the channel column and the gate structure is filled with the compensation layer, and the compensation layer can be used to compensate for the isolation performance of the bottom of the side wall to the gate structure and the channel column, which is beneficial to ensure the insulation effect between the gate structure and the channel column, thereby helping to reduce the probability of leakage current between the gate structure and the channel column, helping to ensure that the semiconductor structure meets the threshold voltage required by the process, helping to reduce the probability of the drain induced potential barrier of the semiconductor structure being reduced, and thus helping to ensure the working performance of the semiconductor structure.

[0033] In the formation method provided in the embodiment of the present invention, an opening is formed to penetrate the gate structure, a side wall is formed to cover the side wall of the opening, a gap compensation process is performed at the bottom corner of the opening, a compensation layer is formed to fill the gap at the bottom of the side wall, and a channel column is formed in the opening and is located on the substrate and penetrates the gate structure; in the embodiment of the present invention, the gap compensation process is performed at the bottom corner of the opening, and the compensation layer can be used to compensate for the isolation performance of the bottom of the side wall to the gate structure and the channel column, which is beneficial to ensure the insulation effect between the gate structure and the channel column, thereby helping to reduce the probability of leakage current between the gate structure and the channel column, helping to ensure that the threshold voltage of the semiconductor structure meets the process requirements, helping to reduce the probability of the drain induced potential barrier of the semiconductor structure being reduced, and further helping to ensure the working performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a structural schematic diagram corresponding to a semiconductor structure;

[0035] Figure 2 is a structural schematic diagram corresponding to an embodiment of a semiconductor structure of the present invention;

[0036] Figure 3 is a structural schematic diagram corresponding to another embodiment of the semiconductor structure of the present invention;

[0037] Figure 4 is a structural schematic diagram corresponding to another embodiment of the semiconductor structure of the present invention;

[0038] Figures 5 to 12 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention;

[0039] Figures 13 to 15 is a schematic structural diagram corresponding to each step in another embodiment of the method for forming a semiconductor structure of the present invention;

[0040] Fig.16It is a schematic structural diagram corresponding to each step in another embodiment of the method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0041] As can be seen from the background technology, it is difficult to guarantee the working performance of semiconductor structures at present. Now, the reasons why the working performance of semiconductor structures still needs to be improved are analyzed in combination with a semiconductor structure.

[0042] Figure 1 A structural schematic diagram corresponding to a semiconductor structure is shown.

[0043] refer to Figure 1 The semiconductor structure includes: a substrate 10, in which a source-drain doped layer 11 is formed; a gate structure 20, located on the substrate 10; a channel column 61, located on the source-drain doped layer 11 in the substrate 10 and penetrating the gate structure 20 in the longitudinal direction; and a sidewall 46, extending in the longitudinal direction and located between the sidewall of the channel column 61 and the gate structure 20.

[0044] In the semiconductor manufacturing process, the process of forming the sidewall 46 is likely to cause damage to the bottom of the sidewall 46, resulting in the loss of the sidewall 46 at the bottom of the channel pillar 61 (eg Figure 1 As shown by the dotted circle in the middle, at the bottom of the sidewall 46, the isolation performance between the channel pillar 61 and the gate structure 20 is poor, which easily leads to leakage current (Off-state Leakage Current, I off ), which affects the threshold voltage (V t ), resulting in a decrease in the drain induced barrier low (DIBL) of the semiconductor structure, thereby affecting the working performance of the semiconductor structure.

[0045] In order to solve the technical problem, an embodiment of the present invention provides a semiconductor structure, including: a substrate; a gate structure located on the substrate; a channel column located on the substrate and penetrating the gate structure along the longitudinal direction; a side wall extending along the longitudinal direction and located between the side wall of the channel column and the gate structure; a compensation layer filled in the gap between the channel column and the gate structure at the bottom of the side wall.

[0046] In an embodiment of the present invention, a compensation layer is filled in the gap between the channel column and the gate structure at the bottom of the side wall. The compensation layer can be used to compensate for the isolation performance of the bottom of the side wall to the gate structure and the channel column, which is beneficial to ensuring the insulation effect between the gate structure and the channel column, thereby helping to reduce the probability of leakage current between the gate structure and the channel column, helping to ensure that the threshold voltage of the semiconductor structure meets the process requirements, helping to reduce the probability of the drain induced potential barrier of the semiconductor structure being reduced, and further helping to ensure the working performance of the semiconductor structure.

[0047] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0048] Figure 2 It is a structural schematic diagram corresponding to an embodiment of a semiconductor structure of the present invention.

[0049] refer to Figure 2 The semiconductor structure includes: a substrate 100; a gate structure 200, located on the substrate 100; a channel column 610, located on the substrate 100 and penetrating the gate structure 200 in the longitudinal direction; a sidewall 460, extending in the longitudinal direction and located between the sidewall of the channel column 610 and the gate structure 200; and a compensation layer 510, filling the gap between the channel column 610 and the gate structure 200 at the bottom of the sidewall 460.

[0050] The substrate 100 provides a process operation basis for the formation process of the semiconductor structure.

[0051] In this embodiment, the substrate 100 is a dielectric material, specifically, the material of the substrate 100 includes silicon oxide or silicon nitride. As an example, in this embodiment, the material of the substrate 100 is silicon oxide.

[0052] The gate structure 200 is used to control the opening and closing of the channel of the transistor.

[0053] In this embodiment, the gate structure 200 is a metal gate structure. Specifically, the material of the gate structure 200 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC. As an example, in this embodiment, the material of the gate structure 200 is W.

[0054] The channel pillar 610 is used to serve as a channel of a transistor.

[0055] Specifically, in this embodiment, the channel pillar 610 extends longitudinally through the gate structure 200 to form a vertical channel transistor (VCT). Through the vertical channel design, the integration of the transistor is improved, so that more transistors can be integrated on the same wafer area, thereby improving the performance and efficiency of the chip.

[0056] In this embodiment, the material of the channel pillar 610 includes silicon, germanium, silicon germanium or III-V semiconductor material. As an example, in this embodiment, the material of the channel pillar 610 is silicon. In other embodiments, the material of the channel pillar is determined according to the type and performance of the transistor.

[0057] The spacer 460 is used to isolate the gate structure 200 from the channel pillar 610 .

[0058] In this embodiment, the spacer 460 includes a first spacer 440 covering the sidewall of the gate structure 200 , and a second spacer 450 covering the sidewall of the first spacer 440 .

[0059] The first side wall 440 and the second side wall 450 are used to form the side wall 460 , which is beneficial to ensuring the isolation function of the side wall 460 . The dielectric constant of the side wall 460 can also be adjusted through the first side wall 440 and the second side wall 450 .

[0060] Specifically, in this embodiment, the material of the first spacer 440 includes silicon nitride, and the material of the second spacer 450 includes silicon oxide.

[0061] In this embodiment, the thickness of the first sidewall 440 is 1 nm to 8 nm, which is beneficial for making the first sidewall 440 have sufficient thickness to ensure the isolation performance of the sidewall 460, and the first sidewall 440 does not occupy too much space to meet the integration of the semiconductor structure.

[0062] In this embodiment, the thickness of the second sidewall 450 is 1 nm to 8 nm, which is beneficial for making the second sidewall 450 have sufficient thickness to ensure the isolation performance of the sidewall 460, and the second sidewall 450 does not occupy too much space to meet the integration of the semiconductor structure.

[0063] The compensation layer 510 is filled in the bottom of the sidewall 460 and in the gap between the channel pillar 610 and the gate structure 200 (eg Figure 2 The dotted circle in the middle is used to compensate for the isolation effect between the bottom gate structure 200 of the spacer 460 and the channel pillar 610 .

[0064] In the present embodiment, at the bottom of the side wall 460, the gap between the channel column 610 and the gate structure 200 is filled with a compensation layer 510. The compensation layer 510 can be used to compensate for the isolation performance of the bottom of the side wall 460 to the gate structure 200 and the channel column 610, which is beneficial to ensure the insulation effect between the gate structure 200 and the channel column 610, thereby helping to reduce the probability of leakage current between the gate structure 200 and the channel column 610, helping to ensure that the threshold voltage of the semiconductor structure meets the process requirements, helping to reduce the probability of the drain induced potential barrier of the semiconductor structure being reduced, and thus helping to ensure the working performance of the semiconductor structure.

[0065] It should be noted that in the semiconductor manufacturing process, the bottom of the sidewall 460 is easily damaged to form a gap. Therefore, the compensation layer 510 is filled in the gap between the channel pillar 610 and the gate structure 200 at the bottom of the sidewall 460 .

[0066] In this embodiment, the material of the compensation layer 510 includes silicon nitride.

[0067] Using silicon nitride to form the compensation layer 510 can achieve a better isolation effect. Silicon nitride has a greater hardness and is less damaged during the semiconductor manufacturing process, thus ensuring the isolation effect of the compensation layer 510 .

[0068] In this embodiment, the semiconductor structure further includes: a spacer layer 480 located between the sidewall 460 and the sidewall of the channel pillar 610 .

[0069] The spacer layer 480 is located between the sidewall 460 and the sidewall of the channel pillar 610 . The area of ​​the spacer layer 480 is used to protect the sidewall 460 during the process of forming the channel pillar 610 .

[0070] In this embodiment, the compensation layer 510 is also filled in the gap between the channel pillar 610 and the gate structure 200 at the bottom of the spacer layer 480 .

[0071] Specifically, in the semiconductor manufacturing process, the area of ​​the spacer layer 480 covers the side wall of the side wall 460. During the formation process of the side wall 460, the side wall 460 will be damaged through the bottom of the area of ​​the spacer layer 480. Accordingly, the compensation layer 510 is also filled in the gap between the channel column 610 and the gate structure 200 at the bottom of the spacer layer 480.

[0072] In this embodiment, the thickness of the spacer layer 480 is 3 nm to 12 nm.

[0073] The thickness of the spacer layer 480 is 3 nm to 12 nm, which is conducive to reducing the difficulty of forming the spacer layer 480 and also conducive to providing sufficient protection for the sidewall 460 .

[0074] In this embodiment, the compensation layer 510 is also filled in the gap formed by the top of the sidewall 460 and the spacer layer 480 .

[0075] It should be noted that in the semiconductor process, the top of the sidewall 460 is also exposed by the spacer layer 480, and the top of the sidewall 460 is also easily damaged by the process to form a gap. Therefore, the compensation layer 510 is also filled in the gap surrounded by the top of the sidewall 460 and the spacer layer 480.

[0076] Specifically, in this embodiment, at the bottom of the side wall 460, the gap filled by the compensation layer 510 is surrounded by the bottom of the second side wall 450, the bottom of the spacer layer 480, the first side wall 440, and the side wall of the channel column 610; at the top of the side wall 460, the gap filled by the compensation layer 510 is surrounded by the top of the second side wall 450, the side wall of the spacer layer 480, and the side wall of the first side wall 440.

[0077] It should be noted that, in the semiconductor process, a side wall 460 covering the side wall of the gate structure 200 is first formed, and then a channel column 610 is formed between the side walls 460. In the process of the side wall 460, the second side wall 450 is closer to the process operation area than the first side wall 440, so that the second side wall 450 is more easily damaged. In addition, the material of the first side wall 440 includes silicon nitride, and the material of the second side wall 450 includes silicon oxide. Silicon oxide is more easily damaged than silicon nitride, that is, the top and bottom of the second side wall 450 are easily damaged and removed by the process. Therefore, at the bottom of the side wall 460, the gap filled by the compensation layer 510 is surrounded by the bottom of the second side wall 450, the bottom of the spacer layer 480, the first side wall 440, and the side wall of the channel column 610; at the top of the side wall 460, the gap filled by the compensation layer 510 is surrounded by the top of the second side wall 450, the side wall of the spacer layer 480, and the side wall of the first side wall 440.

[0078] In this embodiment, the spacer layer 480 is a protection layer 470 , and the protection layer 470 covers the sidewalls of the sidewall 460 .

[0079] The protection layer 470 is used to protect the sidewall 460 during the manufacturing process of the sidewall 460 to reduce damage to the sidewall 460 .

[0080] In this embodiment, the material of the protection layer 470 includes amorphous silicon, polycrystalline silicon, a combination of polycrystalline silicon, silicon oxide and tungsten, or a combination of polycrystalline silicon, silicon oxide and titanium nitride.

[0081] The protective layer 470 is formed by using amorphous silicon, polycrystalline silicon, a combination of polycrystalline silicon, silicon oxide and tungsten, or a combination of polycrystalline silicon, silicon oxide and titanium nitride. This can provide better protection, and retaining the protective layer 470 on both sides of the channel column 610 will not introduce other elements that are easily contaminated, which is beneficial to ensuring the basic working performance of the transistor.

[0082] In this embodiment, the semiconductor structure further includes: a top dielectric layer 320 covering the top surface of the gate structure 200 .

[0083] The top dielectric layer 320 is used to isolate the gate structure 200 from other device structures above it.

[0084] In this embodiment, the material of the top dielectric layer 320 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.

[0085] Correspondingly, in this embodiment, the sidewall spacer 460 also extends between the sidewall of the channel pillar 610 and the top dielectric layer 320 .

[0086] In this embodiment, the semiconductor structure further includes: a bottom dielectric layer 310 located between the gate structure 200 and the substrate 100 .

[0087] The bottom dielectric layer 310 is used to isolate the gate structure 200 from other device structures thereunder.

[0088] In this embodiment, the material of the bottom dielectric layer 310 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.

[0089] Correspondingly, in this embodiment, the channel pillar 610 also extends through the top dielectric layer 320 and the bottom dielectric layer 310 .

[0090] In this embodiment, the compensation layer 510 is also filled in the gap between the channel pillar 610 and the bottom dielectric layer 310 .

[0091] In the semiconductor manufacturing process, a protective layer 470 is first formed to cover the side wall 460, and then a region for forming a channel column 610 is formed to penetrate the bottom dielectric layer 310. During the process operation, the side wall of the bottom dielectric layer 310 is also exposed to the outside, so that the bottom dielectric layer 310 is also partially damaged by the process operation. Therefore, in the process of forming the compensation layer 510, the compensation layer 510 is also filled in the gap between the channel column 610 and the bottom dielectric layer 310.

[0092] In this embodiment, the semiconductor structure further includes: a source-drain doped layer 110 located in the substrate 100 , and the source-drain doped layer 110 is exposed on the top surface of the substrate 100 .

[0093] The source-drain doped layer 110 is used as a source region or a drain region of a transistor. Specifically, the doping type of the source-drain doped layer 110 is the same as the channel conductivity type of the corresponding transistor.

[0094] In this embodiment, the source-drain doping layer 110 is exposed on the top surface of the substrate 100 , so that the channel pillar 610 located on the substrate 100 is in contact with the source-drain doping layer 110 .

[0095] Accordingly, in this embodiment, the channel pillar 610 is located on the source-drain doping layer 110 and is in contact with the source-drain doping layer 110 .

[0096] Figure 3 It is a structural schematic diagram corresponding to another embodiment of the semiconductor structure of the present invention.

[0097] The similarities between this embodiment and the above embodiment are not described in detail here. The difference between this embodiment and the above embodiment is that the structure of the channel pillar is different.

[0098] refer to Figure 3 A groove 620 located in a partial height of the channel column 611 is formed on one side of the top of the channel column 611 . The semiconductor structure further includes: an insulating layer 640 filled in the groove 620 .

[0099] The channel pillar 611 does not completely fill the area between the sidewalls 461 , and the insulating layer 640 is filled in the groove 620 , which is beneficial for obtaining a top surface of the channel pillar 611 with better surface flatness.

[0100] In the present embodiment, the material of the insulating layer 640 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.

[0101] Figure 4 It is a structural schematic diagram corresponding to another embodiment of the semiconductor structure of the present invention.

[0102] The similarities between this embodiment and the above embodiment are not described in detail here. The difference between this embodiment and the above embodiment is that the structure of the spacer layer is different.

[0103] refer to Figure 4 , the spacer layer 482 is an air gap 650.

[0104] The air gap 650 is used to isolate the gate structure 202 from the channel pillar 612 together with the spacer 462 .

[0105] Specifically, in this embodiment, a protection layer is formed in advance to occupy a position, and after the channel pillar 612 is formed, the protection layer is removed to form the air gap 650 .

[0106] In this embodiment, the air gap 650 and the side wall 462 together isolate the gate structure 202 and the channel column 612. The dielectric constant of air is relatively low, so the air gap 650 and the side wall 462 are used together to isolate the gate structure 202 and the channel column 612, which is beneficial to reduce the overall isolation dielectric constant between the gate structure 202 and the channel column 612, thereby helping to reduce parasitic capacitance and improve the working performance of the semiconductor structure.

[0107] Figures 5 to 12 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0108] refer to Figure 5 , a substrate 100 is provided, and a gate structure 200 is formed on the substrate 100 .

[0109] The substrate 100 provides a process operation basis for the formation process of the semiconductor structure.

[0110] In this embodiment, the substrate 100 is a dielectric material, specifically, the material of the substrate 100 includes silicon oxide or silicon nitride. As an example, in this embodiment, the material of the substrate 100 is silicon oxide.

[0111] The gate structure 200 is used to control the opening and closing of the channel of the transistor.

[0112] In this embodiment, the gate structure 200 is a metal gate structure. Specifically, the material of the gate structure 200 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC. As an example, in this embodiment, the material of the gate structure 200 is W.

[0113] In this embodiment, in the step of providing the substrate 100 , a top dielectric layer 320 is further formed on the top of the gate structure 200 , and a bottom dielectric layer 310 is further formed between the gate structure 200 and the substrate 100 .

[0114] The top dielectric layer 320 is used to isolate the gate structure 200 from other device structures above it.

[0115] In this embodiment, the material of the top dielectric layer 320 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.

[0116] The bottom dielectric layer 310 is used to isolate the gate structure 200 from other device structures thereunder.

[0117] In this embodiment, the material of the bottom dielectric layer 310 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.

[0118] In this embodiment, in the step of providing the substrate 100 , a source-drain doped layer 110 is further formed in the substrate 100 , and the source-drain doped layer 110 is exposed on the top surface of the substrate 100 .

[0119] The source-drain doped layer 110 is used as a source region or a drain region of a transistor. Specifically, the doping type of the source-drain doped layer 110 is the same as the channel conductivity type of the corresponding transistor.

[0120] In this embodiment, the source-drain doping layer 110 is exposed on the top surface of the substrate 100 , so that the channel pillars subsequently formed on the substrate 100 are in contact with the source-drain doping layer 110 .

[0121] Continue to refer Figure 5 , forming an opening 210 penetrating the gate structure 200 .

[0122] The opening 210 is used to provide a space for the subsequent formation of a sidewall spacer and a channel pillar.

[0123] Accordingly, in this embodiment, in the step of forming the opening 210 penetrating the gate structure 200 , the opening 210 also penetrates the top dielectric layer 320 , and the opening 210 also extends into a partial thickness of the bottom dielectric layer 310 .

[0124] The opening 210 extends into a portion of the bottom dielectric layer 310 , and the remaining portion of the bottom dielectric layer 310 is retained to cover the top surface of the source / drain doped layer 110 , so as to protect the source / drain doped layer 110 in the subsequent step of forming the sidewalls.

[0125] In this embodiment, in the step of forming the opening 210 penetrating the gate structure 200 , the opening 210 is formed above the source-drain doped layer 110 .

[0126] An opening 210 is formed above the source-drain doped layer 110 so that a channel pillar to be formed subsequently can contact the source-drain doped layer 110 .

[0127] Combined with reference Figure 6 and Figure 7 , forming a sidewall 460 covering the sidewall of the opening 210 .

[0128] The spacer 460 is used to isolate the gate structure 200 from the subsequently formed channel pillar.

[0129] refer to Figure 6 The step of forming a spacer 460 covering the sidewall of the opening 210 includes: forming a spacer material layer 400 covering the sidewall and bottom of the opening 210 and the top of the gate structure 200 .

[0130] The spacer material layer 400 is used to form a spacer 460 .

[0131] Specifically, in this embodiment, the step of forming a spacer material layer 400 covering the sidewalls and bottom of the opening 210 and the top of the gate structure 200 includes: forming a first spacer material layer 410 covering the sidewalls and bottom of the opening 210 and the top of the gate structure 200 .

[0132] The first spacer material layer 410 is used to form a first spacer.

[0133] In this embodiment, the material of the first spacer material layer 410 includes silicon nitride.

[0134] In the present embodiment, in the step of forming a first sidewall material layer 410 covering the sidewalls and bottom of the opening 210 and the top of the gate structure 200, the thickness of the first sidewall material layer 410 is 1 nm to 8 nm, which is beneficial for the subsequently formed first sidewall to have sufficient thickness to ensure the isolation performance of the sidewall 460, and the first sidewall will not occupy too much space to meet the integration of the semiconductor structure.

[0135] In this embodiment, a second spacer material layer 420 is formed to cover the first spacer material layer 410 .

[0136] Specifically, the second spacer material layer 420 conformally covers the first spacer material layer 410 , and the second spacer material layer 420 is used to form a second spacer.

[0137] In this embodiment, the material of the second spacer material layer 420 includes silicon oxide.

[0138] In the present embodiment, in the step of forming the second sidewall material layer 420 covering the first sidewall material layer 410, the thickness of the second sidewall material layer 420 is 1 nm to 8 nm, which is beneficial for the subsequently formed second sidewall to have sufficient thickness to ensure the isolation performance of the sidewall 460, and the second sidewall will not occupy too much space to meet the integration of the semiconductor structure.

[0139] refer to Figure 7 , remove the spacer material layer 400 at the bottom of the opening 210 and the top of the gate structure 200 , and retain the spacer material layer 400 covering the sidewall of the opening as the spacer 460 .

[0140] In this embodiment, a dry etching process is used to remove the spacer material layer 400 at the bottom of the opening 210 and the top of the gate structure 200 .

[0141] The dry etching process has the characteristic of anisotropic etching. Therefore, by selecting the dry etching process, it is beneficial to reduce the damage to the bottom substrate 100 of the opening 210. At the same time, dry etching is more directional, which is beneficial to improve the morphology quality and dimensional accuracy of the sidewall 460.

[0142] Specifically, in the present embodiment, in the step of removing the spacer material layer 400 at the bottom of the opening 210 and the top of the gate structure 200, the first spacer material layer 410 and the second spacer material layer 420 at the bottom of the opening 210 and the top of the gate structure 200 are removed, and the first spacer material layer 410 covering the side wall of the opening 210 is retained as the first spacer 440, and the second spacer material layer 420 covering the side wall of the opening 210 is retained as the second spacer 450.

[0143] The first side wall 440 and the second side wall 450 are used to form the side wall 460 , which is beneficial to ensuring the isolation function of the side wall 460 . The dielectric constant of the side wall 460 can also be adjusted through the first side wall 440 and the second side wall 450 .

[0144] Specifically, in this embodiment, the material of the first spacer 440 includes silicon nitride, and the material of the second spacer 450 includes silicon oxide.

[0145] In this embodiment, before performing gap compensation processing at the bottom corner of the opening 210 , the process further includes: forming a protection layer 470 covering the sidewalls of the sidewall 460 .

[0146] The protection layer 470 is used to protect the sidewall 460 during the manufacturing process of the sidewall 460 to reduce damage to the sidewall 460 .

[0147] In this embodiment, in the step of forming the protection layer 470 covering the sidewalls of the spacer 460 , the material of the protection layer 470 includes amorphous silicon, polycrystalline silicon, a combination of polycrystalline silicon, silicon oxide and tungsten, or a combination of polycrystalline silicon, silicon oxide and titanium nitride.

[0148] The protective layer 470 is formed by using amorphous silicon, polycrystalline silicon, a combination of polycrystalline silicon, silicon oxide and tungsten, or a combination of polycrystalline silicon, silicon oxide and titanium nitride. This can provide better protection. After the channel pillar is subsequently formed, the protective layer 470 is retained on both sides of the channel pillar without introducing other elements that are easily contaminated, which is beneficial to ensuring the basic working performance of the transistor.

[0149] Specifically, refer to Figure 6 Before removing the spacer material layer 400 at the bottom of the opening 210 and the top of the gate structure 200 , the method further includes: forming a protection material layer 430 covering the spacer material layer 400 .

[0150] Specifically, the protection material layer 430 conformally covers the spacer material layer 400 , and the protection material layer 430 is used to form a protection layer 470 .

[0151] refer to Figure 7 The step of removing the spacer material layer 400 at the bottom of the opening 210 and the top of the gate structure 200 also includes: removing the protective material layer 430 at the bottom of the opening 210 and the top of the gate structure 200, and retaining the protective material layer 430 covering the sidewall of the spacer 460 as a protective layer 470.

[0152] Specifically, in this embodiment, a dry etching process is used to remove the protective material layer 430 at the bottom of the opening 210 and the top of the gate structure 200 .

[0153] In this embodiment, the step of removing the spacer material layer 400 at the bottom of the opening 210 and the top of the gate structure 200 further includes: removing the remaining thickness of the bottom dielectric layer 310 to expose the top surface of the substrate 100 .

[0154] Specifically, in this embodiment, the remaining thickness of the bottom dielectric layer 310 is removed to expose the top surface of the source-drain doped layer 110 of the substrate 100 , in preparation for the subsequent formation of a channel pillar in contact with the source-drain doped layer 110 .

[0155] refer to Figure 8 After removing the spacer material layer 400 at the bottom of the opening 210 and the top of the gate structure 200 , before performing gap compensation processing at the bottom corner of the opening 210 , the process further includes: cleaning the spacer 460 .

[0156] The process for forming the side wall 460 is likely to cause residues to remain, especially at the bottom of the opening 210. Especially in this embodiment, a dry etching process is used to form the side wall 460 and the protective layer 470, which is likely to have dry etching residues in the opening 210. Therefore, the side wall 460 is cleaned to remove the residues in the opening 210, thereby reducing contamination to subsequent processes and providing a better process platform for subsequent process steps.

[0157] It should be noted that when the side wall 460 is cleaned, the top and bottom of the side wall 460 exposed by the protective layer 470 will be damaged. Specifically, the material of the first side wall 440 is silicon nitride, and the material of the second side wall 450 is silicon oxide. Silicon oxide is more easily damaged. Therefore, the cleaning process will remove part of the second side wall 450 at the top position of the side wall 460 and part of the second side wall 450 at the bottom position of the side wall 460. At the same time, the opening 210 also penetrates the bottom dielectric layer 310, that is, the opening 210 also exposes the bottom dielectric layer 310. Therefore, the cleaning process will also remove part of the bottom dielectric layer 310 at the bottom corner of the opening 210.

[0158] In this embodiment, the cleaning solution used in the cleaning process is a diluted hydrofluoric acid (DHF) solution.

[0159] The etching rate of the diluted hydrofluoric acid solution is slower and more stable, which is conducive to better cleaning and less damage to the film layer. It should be noted that the fluorine-containing cleaning solution is prone to cause etching damage to silicon oxide.

[0160] Specifically, in this embodiment, in the diluted hydrofluoric acid solution, the volume ratio of water to hydrofluoric acid is 100:1 to 2000:1.

[0161] In other embodiments, the cleaning solution for the cleaning process may also be a diluted sulfuric acid and hydrogen peroxide (DSP) mixed solution or a SST-A47 organic solution.

[0162] Combined with reference Fig. 9 and Fig.10 , gap compensation processing is performed at the bottom corner of the opening 210 to form a bottom of the filling sidewall 460 (such as Fig.10 A compensation layer 510 is formed in the gap (shown by the dotted circle in the figure).

[0163] The compensation layer 510 fills the bottom of the side wall 460 at the bottom corner of the opening 210, and a channel column will be formed in the opening 210 later, that is, the compensation layer 510 compensates in the gap between the channel column formed later and the gate structure 200, and is used to compensate for the isolation effect between the gate structure 200 at the bottom of the side wall 460 and the channel column.

[0164] In the present embodiment, gap compensation processing is performed at the bottom corner of the opening 210, so that the compensation layer 510 can be used to compensate for the isolation performance of the bottom of the side wall 460 to the gate structure 200 and the channel column 610, which is beneficial to ensure the insulation effect between the gate structure 200 and the channel column 610, thereby helping to reduce the probability of leakage current between the gate structure 200 and the channel column 610, helping to ensure that the threshold voltage of the semiconductor structure meets the process requirements, helping to reduce the probability of the drain induced potential barrier of the semiconductor structure being reduced, and thus helping to ensure the working performance of the semiconductor structure.

[0165] In this embodiment, when the side wall 460 is cleaned, the bottom of the side wall 460 exposed by the protective layer 470 causes damage to the side wall 460. Therefore, in the step of performing gap compensation at the bottom corner of the opening 210, the compensation layer 510 is also filled in the gap at the bottom of the protective layer 470 at the bottom corner of the opening 210.

[0166] In this embodiment, when the side wall 460 is cleaned, the top of the side wall 460 exposed by the protective layer 470 is also damaged. Therefore, in the step of performing gap compensation at the bottom corner of the opening 210, the compensation layer is also filled in the gap enclosed by the top of the side wall 460 and the protective layer 470.

[0167] Specifically, in this embodiment, the material of the second side wall 450 is silicon oxide, and the material of the first side wall 440 is silicon nitride. Silicon oxide is easily damaged, and a gap is formed by removing the top and bottom parts of the second side wall 450. Therefore, in the step of performing gap compensation processing at the bottom corner of the opening 210, the compensation layer 510 is filled in the gap surrounded by the bottom of the second side wall 450, the bottom of the protective layer 470, and the first side wall 440. The compensation layer 510 is also filled in the gap surrounded by the top of the second side wall 450, the side wall of the protective layer 470, and the side wall of the first side wall 440.

[0168] In this embodiment, when the side wall 460 is cleaned, the cleaning process will also remove part of the bottom dielectric layer 310 at the bottom corner of the opening 210. Therefore, in the step of performing gap compensation treatment at the bottom corner of the opening 210, the compensation layer 510 is also filled in the gap enclosed by the bottom dielectric layer 310 and the substrate 100 at the bottom corner of the opening 210.

[0169] In this embodiment, in the step of forming the compensation layer 510 to fill the gap at the bottom of the spacer 460 , the material of the compensation layer 510 includes silicon nitride.

[0170] Using silicon nitride to form the compensation layer 510 can achieve a better isolation effect. Silicon nitride has a greater hardness and is less damaged during the semiconductor manufacturing process, thus ensuring the isolation effect of the compensation layer 510 .

[0171] Specifically, refer to Fig. 9 , performing gap compensation processing at the bottom corner of the opening 210, and forming a compensation layer 510 filling the gap at the bottom of the sidewall 460 includes: forming a compensation material layer 500 covering the bottom of the opening 210, the sidewall of the sidewall 460 of the opening 210, the top of the gate structure 200, and filling the gap at the bottom of the sidewall 460.

[0172] The compensation material layer 500 is used to form a compensation layer 510 .

[0173] Specifically, in this embodiment, the compensation material layer 500 also fills the gap at the top of the sidewall 460 and the gap in the bottom dielectric layer 310 at the bottom corner of the opening 210 .

[0174] In this embodiment, in the step of forming a compensation material layer 500 covering the bottom of the opening 210, the sidewalls of the sidewall spacer 460 of the opening 210, the top of the gate structure 200, and filling the gap at the bottom of the sidewall spacer 460, the thickness of the compensation material layer 500 is 1nm to 10nm.

[0175] The thickness of the compensation material layer 500 is 1 nm to 10 nm, so that the compensation material layer 500 can sufficiently fill the gap without causing unnecessary material waste.

[0176] In this embodiment, an atomic layer deposition (ALD) process is used to form a compensation material layer 500 covering the bottom of the opening 210 , the sidewalls of the sidewall spacer 460 of the opening 210 , the top of the gate structure 200 , and filling the gap at the bottom of the sidewall spacer 460 .

[0177] The compensation material layer 500 formed by the atomic layer deposition process has good thickness uniformity and good step coverage capability, so that the compensation material layer 500 can conformally cover the bottom of the opening 210, the sidewalls of the sidewalls 460 of the opening 210, the top of the gate structure 200, and fill the gap at the bottom of the sidewalls 460.

[0178] In other embodiments, a low pressure chemical vapor deposition (LPCVD) process may be used to form a compensation material layer covering the bottom of the opening, the sidewalls of the opening, the top of the gate structure, and filling the gap at the bottom of the sidewalls.

[0179] refer to Fig.10, remove the compensation material layer 500 covering the bottom of the opening 210 , the sidewalls of the sidewall spacer 460 of the opening 210 , and the top of the gate structure 200 , and retain the compensation material layer filling the gap at the bottom of the sidewall spacer 460 as the compensation layer 510 .

[0180] Specifically, in this embodiment, the compensation material layer 500 filling the gap at the top of the spacer 460 and the gap in the bottom dielectric layer 310 at the bottom corner of the opening 210 is retained as the compensation layer 510 .

[0181] In this embodiment, a wet etching process is used to remove the compensation material layer 500 covering the bottom of the opening 210 , the sidewalls of the spacer 460 of the opening 210 , and the top of the gate structure 200 .

[0182] The cost of the wet etching process is relatively low, the operation steps are simple, and a larger etching selectivity ratio can be achieved, which is beneficial for reducing damage to other film layers during the process of removing the sidewalls 460 covering the bottom of the opening 210, the sidewalls of the opening 210, and the compensation material layer 500 on the top of the gate structure 200.

[0183] In this embodiment, the etching solution of the wet etching process includes a phosphoric acid solution.

[0184] Phosphoric acid has a high viscosity, usually 37.10 mPa.s, that is, the viscosity of the phosphoric acid solution is high, and the phosphoric acid solution is not easy to enter the gap, that is, the phosphoric acid solution is not easy to react with the compensation material layer 500 in the gap, so that the wet etching process can easily retain the compensation material layer 500 in the gap when removing the compensation material layer 500 covering the bottom of the opening 210, the sidewalls of the sidewalls 460 of the opening 210, and the top of the gate structure 200, which is conducive to the formation of the compensation layer 510.

[0185] In this embodiment, the mass percentage of phosphoric acid in the phosphoric acid solution is 40 wt % to 86 wt %.

[0186] The mass percentage of phosphoric acid in the phosphoric acid solution is 40wt% to 86wt%, which is conducive to cleanly removing the compensation material layer 500 covering the bottom of the opening 210, the sidewalls of the sidewalls 460 of the opening 210, and the top of the gate structure 200, and it is easy to maintain a high viscosity, so that the compensation material layer 500 in the gap is easy to retain.

[0187] Specifically, in this embodiment, the mass percentage of phosphoric acid in the phosphoric acid solution is 40 wt % to 60 wt %.

[0188] The mass percentage of phosphoric acid in the phosphoric acid solution is 40wt% to 60wt%, which is beneficial to reducing the etching rate and making the wet etching easier to control.

[0189] In this embodiment, the process temperature of the wet etching process is 100° C. to 160° C.

[0190] The process temperature of the wet etching process is 100° C. to 160° C., so that high etching efficiency and good etching quality are maintained.

[0191] Specifically, in this embodiment, the process temperature of the wet etching process is 100° C. to 130° C.

[0192] The process temperature of the wet etching process is 100° C. to 130° C., which is beneficial to reducing the etching rate and making the wet etching easier to control.

[0193] Combined with reference Fig.11 and Fig.12 , a channel pillar 610 is formed in the opening 210 and is located on the substrate 100 and penetrates the gate structure 200 .

[0194] The channel pillar 610 is used to serve as a channel of a transistor.

[0195] Specifically, in this embodiment, the channel pillar 610 extends longitudinally through the gate structure 200 to form a vertical channel transistor (VCT). Through the vertical channel design, the integration of the transistor is improved, so that more transistors can be integrated on the same wafer area, thereby improving the performance and efficiency of the chip.

[0196] In this embodiment, the material of the channel pillar 610 includes silicon, germanium, silicon germanium or III-V semiconductor material. As an example, in this embodiment, the material of the channel pillar 610 is silicon. In other embodiments, the material of the channel pillar is determined according to the type and performance of the transistor.

[0197] Accordingly, in the present embodiment, in the step of forming a channel pillar 610 located on the substrate 100 and penetrating the gate structure 200 in the opening 210 , the channel pillar 610 is in contact with the protection layer 470 .

[0198] In this embodiment, the opening 210 exposes the top surface of the source-drain doped layer 110 . Accordingly, in the step of forming a channel column 610 located on the substrate 100 and penetrating the gate structure 200 in the opening 210 , the channel column 610 is formed on the source-drain doped layer 110 and in contact with the source-drain doped layer 110 .

[0199] In this embodiment, in the step of forming a channel pillar 610 located on the substrate 100 and penetrating the gate structure 200 in the opening 210 , the channel pillar 610 fills the opening 210 .

[0200] Specifically, refer to Fig.11The step of forming a channel pillar 610 in the opening 210 , which is located on the substrate 100 and penetrates the gate structure 200 , includes: forming a channel material layer 600 filling the opening 210 and covering the top of the top dielectric layer 320 .

[0201] The channel material layer 600 is used to form a channel pillar 610 .

[0202] refer to Fig.12 , planarizing the channel material layer 600 , removing the channel material layer 600 above the top dielectric layer 320 , and retaining the channel material layer 600 filling the opening 210 as a channel pillar 610 .

[0203] Fig.13 swine Fig.15 It is a schematic structural diagram corresponding to each step in another embodiment of the method for forming a semiconductor structure of the present invention.

[0204] The similarities between this embodiment and the above embodiment are not described in detail here. The difference between this embodiment and the above embodiment is that the structure of the channel pillar is different.

[0205] Combined with reference Figures 13 to 15 In the step of forming a channel column 611 located on the substrate 101 and penetrating the gate structure 201 in the opening 211 , a groove 620 located in the channel column 611 at a partial height is formed on one side of the top of the channel column 611 .

[0206] If the channel pillars 611 do not completely fill the areas between the openings 211 , it is beneficial to reduce the probability of a concave morphology appearing on the top surface of the formed channel pillars 611 .

[0207] In this embodiment, an insulating layer 640 is formed to fill the groove 620 .

[0208] Filling the groove 620 with an insulating layer 640 is beneficial to obtaining a top surface of the channel pillar 611 with better surface flatness.

[0209] In the present embodiment, in the step of forming the insulating layer 640 filling the groove 620 , the material of the insulating layer 640 is an insulating material including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.

[0210] Specifically, refer to Fig.13 , forming a channel material layer 601 covering the sidewall and bottom of the opening 211 and the top of the top dielectric layer 321 , and forming a groove 620 in the channel material layer 601 in the opening 211 .

[0211] The channel material layer 601 is used to form a channel pillar 611 .

[0212] refer to Fig.14, forming an insulating material layer 630 filling the groove 620 and covering the channel material layer 601.

[0213] The insulating material layer 630 is used to form the insulating layer 640 .

[0214] refer to Fig.15 , planarize the insulating material layer 630 and the channel material layer 601, remove the insulating material layer 630 and the channel material layer 601 above the top dielectric layer 321, retain the channel material layer 601 in the opening 211 as the channel pillar 611, and retain the insulating material layer 630 in the opening 211 as the insulating layer 640.

[0215] Fig.16 It is a schematic structural diagram corresponding to each step in another embodiment of the method for forming a semiconductor structure of the present invention.

[0216] The similarities between this embodiment and the above embodiment are not described in detail here. The difference between this embodiment and the above embodiment is that the protective layer is removed.

[0217] refer to Fig.16 After forming a channel column 612 in the opening 212 that is located on the substrate 102 and penetrates the gate structure 202 , the method further includes: removing the protection layer to form an air gap 650 between the sidewall 462 and the sidewall of the channel column 612 .

[0218] The air gap 650 is used to isolate the gate structure 202 from the channel pillar 612 together with the spacer 462 .

[0219] In this embodiment, the air gap 650 and the side wall 462 together isolate the gate structure 202 and the channel column 612. The dielectric constant of air is relatively low, so the air gap 650 and the side wall 462 are used together to isolate the gate structure 202 and the channel column 612, which is beneficial to reduce the overall isolation dielectric constant between the gate structure 202 and the channel column 612, thereby helping to reduce parasitic capacitance and improve the working performance of the semiconductor structure.

[0220] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A gate structure, located on the substrate; A channel column, located on the substrate and penetrating the gate structure in a longitudinal direction; A sidewall extending along the longitudinal direction and located between the sidewall of the channel column and the gate structure; The compensation layer is filled in the gap between the channel column and the gate structure at the bottom of the sidewall.

2. The semiconductor structure according to claim 1, wherein: The semiconductor structure further comprises: a spacer layer located between the sidewall and the sidewall of the channel pillar; The compensation layer is also filled in the gap between the channel pillar and the gate structure at the bottom of the spacer layer.

3. The semiconductor structure according to claim 2, wherein: The spacer layer is a protective layer, and the protective layer covers the side wall of the side wall; or, The spacer layer is an air gap.

4. The semiconductor structure according to claim 3, characterized in that The spacer layer is a protective layer, and the material of the protective layer includes amorphous silicon, polycrystalline silicon, a combination of polycrystalline silicon, silicon oxide and tungsten, or a combination of polycrystalline silicon, silicon oxide and titanium nitride.

5. The semiconductor structure according to claim 2, wherein: The compensation layer is also filled in the gap surrounded by the top of the side wall and the spacing layer.

6. The semiconductor structure according to claim 5, characterized in that The sidewall spacer comprises a first sidewall spacer covering the sidewall of the gate structure, and a second sidewall spacer covering the sidewall of the first sidewall spacer; At the bottom of the sidewall, the gap filled by the compensation layer is surrounded by the bottom of the second sidewall, the bottom of the spacer layer, the first sidewall, and the sidewall of the channel column; At the top of the sidewall, the gap filled by the compensation layer is surrounded by the top of the second sidewall, the sidewall of the spacer layer, and the sidewall of the first sidewall.

7. The semiconductor structure according to claim 6, wherein: The material of the first sidewall spacer includes silicon nitride; the material of the second sidewall spacer includes silicon oxide.

8. The semiconductor structure according to claim 1, wherein: The material of the compensation layer includes silicon nitride.

9. The semiconductor structure according to claim 1, wherein: The semiconductor structure further comprises: a top dielectric layer covering the top surface of the gate structure; A bottom dielectric layer, located between the gate structure and the substrate; The channel pillar also extends through the top dielectric layer and the bottom dielectric layer; The sidewall also extends between the sidewall of the channel pillar and the top dielectric layer; The compensation layer is also filled in the gap between the channel pillar and the bottom dielectric layer.

10. The semiconductor structure according to claim 1, wherein: The semiconductor structure further comprises: a source-drain doping layer, which is located in the substrate, and the source-drain doping layer is exposed on the top surface of the substrate; The channel pillar is located on the source-drain doping layer and contacts the source-drain doping layer.

11. The semiconductor structure according to claim 1, wherein: A groove located in a part of the height of the channel column is formed on one side of the top of the channel column, and the semiconductor structure further includes: an insulating layer filled in the groove.

12. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, on which a gate structure is formed; forming an opening penetrating the gate structure; forming a side wall covering the side wall of the opening; Performing gap compensation processing at the bottom corner of the opening to form a compensation layer filling the gap at the bottom of the side wall; A channel column is formed in the opening and is located on the substrate and penetrates the gate structure.

13. The method for forming a semiconductor structure according to claim 12, wherein: Before performing gap compensation processing at the bottom corner of the opening, the method further includes: forming a protective layer covering the sidewall of the sidewall; In the step of performing gap compensation processing at the bottom corner of the opening, the compensation layer is also filled in the gap at the bottom of the protective layer at the bottom corner of the opening; In the step of forming a channel column located on the substrate and penetrating the gate structure in the opening, the channel column is in contact with the protection layer.

14. The method for forming a semiconductor structure according to claim 13, wherein: After forming a channel column in the opening which is located on the substrate and penetrates the gate structure, the method further includes: removing the protection layer to form an air gap between the sidewall and the sidewall of the channel column.

15. The method for forming a semiconductor structure according to claim 13, wherein: In the step of performing gap compensation processing at the bottom corner of the opening, the compensation layer is also filled in the gap surrounded by the top of the side wall and the protection layer.

16. The method for forming a semiconductor structure according to claim 15, wherein: The step of forming a sidewall covering the sidewall of the opening includes: forming a sidewall material layer covering the sidewall and bottom of the opening and the top of the gate structure; The spacer material layer at the bottom of the opening and the top of the gate structure is removed, and the spacer material layer covering the sidewall of the opening is retained as the spacer.

17. The method for forming a semiconductor structure according to claim 16, wherein: In the step of providing the substrate, a top dielectric layer is formed on the top of the gate structure, and a bottom dielectric layer is formed between the gate structure and the substrate; In the step of forming an opening penetrating the gate structure, the opening also penetrates the top dielectric layer, and the opening also extends into a portion of the thickness of the bottom dielectric layer; The step of removing the spacer material layer at the bottom of the opening and the top of the gate structure further includes: removing the remaining thickness of the bottom dielectric layer to expose the top surface of the substrate; In the step of performing gap compensation processing at the bottom corner of the opening, the compensation layer is also filled in the gap surrounded by the bottom dielectric layer and the substrate at the bottom corner of the opening.

18. The method for forming a semiconductor structure according to claim 16, wherein: The step of forming a spacer material layer covering the sidewalls and bottom of the opening and the top of the gate structure includes: forming a first spacer material layer covering the sidewalls and bottom of the opening and the top of the gate structure; forming a second spacer material layer covering the first spacer material layer; In the step of removing the spacer material layer at the bottom of the opening and the top of the gate structure, the first spacer material layer and the second spacer material layer at the bottom of the opening and the top of the gate structure are removed, and the first spacer material layer covering the side wall of the opening is retained as the first spacer, and the second spacer material layer covering the side wall of the opening is retained as the second spacer; In the step of performing gap compensation processing at the bottom corner of the opening, the compensation layer is filled in the gap surrounded by the bottom of the second side wall, the bottom of the protective layer, and the first side wall, and the compensation layer is also filled in the gap surrounded by the top of the second side wall, the side wall of the protective layer, and the side wall of the first side wall.

19. The method for forming a semiconductor structure according to claim 16, wherein: Before removing the spacer material layer at the bottom of the opening and the top of the gate structure, the method further includes: forming a protective material layer covering the spacer material layer; The step of removing the sidewall material layer at the bottom of the opening and the top of the gate structure also includes: removing the protective material layer at the bottom of the opening and the top of the gate structure, and retaining the protective material layer covering the sidewall of the sidewall as the protective layer.

20. The method for forming a semiconductor structure according to claim 19, wherein: Using a dry etching process to remove the sidewall material layer at the bottom of the opening and the top of the gate structure; After removing the sidewall material layer at the bottom of the opening and the top of the gate structure, and before performing gap compensation processing at the corner of the bottom of the opening, the method further includes: cleaning the sidewall.

21. The method for forming a semiconductor structure according to claim 12, wherein: The step of performing gap compensation processing at the bottom corner of the opening to form a compensation layer filling the gap at the bottom of the sidewall comprises: forming a compensation material layer covering the bottom of the opening, the sidewall of the sidewall of the opening, the top of the gate structure, and filling the gap at the bottom of the sidewall; The compensation material layer covering the bottom of the opening, the sidewalls of the opening, and the top of the gate structure is removed, and the compensation material layer filling the gap at the bottom of the sidewall is retained as the compensation layer.

22. The method for forming a semiconductor structure according to claim 21, wherein: An atomic layer deposition process or a low pressure chemical vapor deposition process is adopted to form a compensation material layer covering the bottom of the opening, the sidewalls of the sidewalls of the opening, the top of the gate structure, and the gap filling the bottom of the sidewalls.

23. The method for forming a semiconductor structure according to claim 21, wherein: A wet etching process is used to remove the compensation material layer covering the bottom of the opening, the sidewalls of the sidewalls of the opening, and the top of the gate structure.

24. The method for forming a semiconductor structure according to claim 23, wherein: The etching solution of the wet etching process includes a phosphoric acid solution; The mass percentage of phosphoric acid in the phosphoric acid solution is 40wt% to 86wt%; The process temperature of the wet etching process is 100° C. to 160° C.

25. The method for forming a semiconductor structure according to claim 12, wherein: In the step of providing the substrate, a source-drain doped layer is further formed in the substrate, and the source-drain doped layer is exposed on the top surface of the substrate; In the step of forming an opening penetrating the gate structure, the opening is formed above the source-drain doped layer; In the step of forming a channel column in the opening which is located on the substrate and penetrates the gate structure, the channel column is formed on the source-drain doping layer and contacts the source-drain doping layer.

26. The method for forming a semiconductor structure according to claim 12, wherein: In the step of forming a channel pillar located on the substrate and penetrating the gate structure in the opening, the channel pillar fills the opening; Alternatively, in the step of forming a channel column located on the substrate and penetrating the gate structure in the opening, a groove located in the channel column at a partial height is formed on one side of the top of the channel column; An insulating layer filling the groove is formed.

Images