Chip stacking multi-layer heat dissipation packaging structure and packaging method thereof

Abstract

The invention relates to a chip stacking multi-layer heat dissipation packaging structure and a packaging method. The packaging structure sequentially comprises an upper-layer single-side copper-clad plate, a first chip, a middle-layer copper-layer circuit board, a second chip, a lower-layer single-side copper-clad plate and a first plastic package body from top to bottom, the inner side electrodes of the first chip and the second chip are communicated to the outer pin through a conducting circuit on the middle-layer copper layer circuit board, and the outer side electrode of the first chip is communicated to the outer pin through the inner side copper layer of the upper-layer single-side copper-clad plate, the boss and the conducting circuit on the middle-layer copper layer circuit board; and the outer side electrode of the second chip is communicated with the outer pin through the inner side copper layer of the lower-layer single-sided copper-clad plate, the boss and the conductive circuit on the middle-layer copper layer circuit board. The thickness of the whole packaging structure is greatly reduced, the size of the packaging structure is smaller, the heat dissipation path is shorter, the heat dissipation efficiency is higher, the power density of the module can be greatly improved, the use of packaging materials is less, and the cost is lower; a chip circuit path is shortened, parasitic inductance and circuit power consumption are reduced, and signal response is faster.

Description

Technical Field

[0001] The present application relates to the field of semiconductor packaging technology, and in particular to a chip stacking multi-layer heat dissipation packaging structure and a packaging method thereof. Background Art

[0002] IGBT / MOSFET power modules are widely used in various energy fields, especially new energy vehicles. When the power module is running at high power and high current, the chip inside the power module will generate a lot of heat, which must be dissipated in time. Otherwise, the chip temperature will rise too high, resulting in unstable chip performance and even direct damage and failure of the chip.

[0003] The Chinese patent application with application number 202410948243.1 discloses a chip stacked double-sided heat dissipation power module packaging structure, including an upper double-sided copper clad laminate, a middle double-sided copper clad laminate, a lower double-sided copper clad laminate, a first chip, a second chip and a plastic package. The chip stacked double-sided heat dissipation packaging structure is used to achieve vertical symmetry and rapid heat dissipation. It has the advantages of more stable performance, higher power density, better heat dissipation, lower power consumption, higher reliability, and longer service life. The module is smaller in size, uses less materials, and has lower costs. However, the upper, middle, and lower layers of this technical solution all use double-sided copper clad laminates, and the thickness is still relatively large, so the size of the entire packaging structure still has room for improvement. Summary of the invention

[0004] In response to the above pain points, the present application provides a chip stacking multi-layer heat dissipation packaging structure and its packaging method, which has the advantages of smaller module thickness, higher power density, better heat dissipation, and higher reliability.

[0005] The technical solution disclosed in the present application is: a chip stacking multi-layer heat dissipation packaging structure, which includes, from top to bottom, an upper single-sided copper clad laminate, a first chip, a middle copper layer circuit board, a second chip and a lower single-sided copper clad laminate, and also includes a first plastic package for wrapping the upper single-sided copper clad laminate, the middle copper layer circuit board, the lower single-sided copper clad laminate, the first chip and the second chip; the upper single-sided copper clad laminate and the lower single-sided copper clad laminate both include an insulating heat-conductive substrate and an inner copper layer, and a boss is also provided on the inner copper layer; the middle copper layer circuit board is provided with a plurality of external pins and a plurality of conductive circuits, the inner electrodes of the first chip and the second chip are connected to the external pins through the conductive circuits on the middle copper layer circuit board, the outer electrodes of the first chip are connected to the external pins through the inner copper layer of the upper single-sided copper clad laminate, the boss and the conductive circuits on the middle copper layer circuit board, and the outer electrodes of the second chip are connected to the external pins through the inner copper layer of the lower single-sided copper clad laminate, the boss and the conductive circuits on the middle copper layer circuit board.

[0006] The first chip and the second chip are identical chips and are soldered on the front and back sides of the middle copper layer circuit board in a mirror-symmetrical manner.

[0007] The number of the first chips and the second chips is multiple groups, and the groups are arranged horizontally in parallel.

[0008] The insulating thermally conductive substrate is an insulating thermally conductive ceramic substrate, and the insulating thermally conductive ceramic substrate and the inner copper layer are sintered into one by a low-temperature sintering material, and the low-temperature sintering material is sintered silver, sintered copper, solder paste, prefabricated tin sheet or non-conductive heat dissipation glue.

[0009] Wherein, the side surfaces of the insulating thermally conductive ceramic substrate and the inner copper layer are also wrapped with a second plastic packaging body.

[0010] Among them, the first chip and the second chip are power chips, including a first pole and a second pole located on the front side, and a third pole located on the back side; the first chip is flipped, and the second chip is mounted upright; the middle copper layer circuit board is provided with a first external pin, a second external pin, a third external pin, a first conductive circuit, a second conductive circuit and a third conductive circuit; the first pole of the first chip is connected to the first external pin through the first conductive circuit on the middle copper layer circuit board, the second pole of the first chip is connected to the second external pin through the second conductive circuit on the middle copper layer circuit board, and the third pole of the first chip is connected to the third external pin through the inner copper layer of the upper single-sided copper clad board, the boss, and the third conductive circuit on the middle copper layer circuit board; the first pole of the second chip is connected to the first external pin through the first conductive circuit on the middle copper layer circuit board, the second pole of the second chip is connected to the second external pin through the second conductive circuit on the middle copper layer circuit board, and the third pole of the second chip is connected to the third external pin through the inner copper layer of the lower single-sided copper clad board, the boss, and the third conductive circuit on the middle copper layer circuit board.

[0011] Among them, the first chip and the second chip are field effect transistors, the first pole is the D pole, the second pole is the G pole, and the third pole is the S pole; or the first chip and the second chip are IGBTs, the first pole is the E pole, the second pole is the G pole, and the third pole is the C pole.

[0012] Wherein, the middle copper layer circuit board is also provided with a fourth external pin, and a temperature sensing element is connected between the fourth external pin and the first conductive circuit.

[0013] Among them, the second external pin includes a first sub-pin and a second sub-pin that are independent of each other, the second conductive circuit includes a first sub-circuit and a second sub-circuit, the first sub-pin is conductive with the first sub-circuit, the second sub-pin is conductive with the second sub-circuit, and a unidirectional diode is provided between the first sub-circuit and the second sub-circuit.

[0014] The present application also discloses another technical solution: a packaging method of the chip stacking multi-layer heat dissipation packaging structure described above, comprising the following steps:

[0015] S1, mounting the second chip on the upper surface of the lower single-sided copper-clad board, and then performing a first sintering or reflow soldering, preferably sintering soldering;

[0016] S2, mounting the middle copper layer circuit board on the second chip and the boss of the lower single-sided copper clad board, and then performing a second sintering or reflow soldering, preferably sintering soldering;

[0017] S3, mounting the first chip on the upper surface of the middle copper layer circuit board, and then performing a third sintering or reflow soldering, preferably sintering soldering;

[0018] S4, mounting the upper single-sided copper clad laminate on the first chip and the middle copper layer circuit board, and then performing a fourth sintering or reflow soldering, preferably sintering soldering;

[0019] S5, performing plastic sealing to obtain a first plastic sealing body;

[0020] S6, grinding the upper and lower surfaces of the first plastic package body to expose the outer surfaces of the insulating heat-conductive substrates of the upper single-sided copper clad laminate and the lower single-sided copper clad laminate.

[0021] This application also provides another more concise packaging method, including the following steps:

[0022] S1, mounting the first chip on the copper layer of the lower surface of the upper single-sided copper clad laminate, mounting the second chip on the copper layer of the upper surface of the lower single-sided copper clad laminate, and then performing the first sintering or reflow soldering, preferably sintering soldering;

[0023] S2, mounting the middle copper layer circuit board on the second chip and the boss of the lower single-sided copper clad board, and then performing a second sintering or reflow soldering, preferably sintering soldering;

[0024] S3, mounting the components welded by the first chip and the upper single-sided copper-clad board in step S1 on the other side of the middle copper-layer circuit board in step S2, and then performing a third sintering or reflow soldering, preferably sintering soldering;

[0025] S4, performing plastic sealing to obtain a first plastic sealing body;

[0026] S5, grinding the upper and lower surfaces of the first plastic package body to expose the outer surfaces of the insulating heat-conductive substrates of the upper single-sided copper clad laminate and the lower single-sided copper clad laminate.

[0027] The present application includes at least one of the following beneficial technical effects: The present application adopts an upper single-sided copper clad laminate, a middle copper layer circuit board and a lower single-sided copper clad laminate. Compared with the three double-sided copper clad laminates in the current technology, the thickness is thinner, while the overall structure of the chip stacking has not changed, so that the thickness of the entire packaging structure is greatly thinner, the packaging structure is smaller, the heat dissipation path is shorter, the heat dissipation efficiency is higher, and the power density of the module can be greatly improved. The packaging material is used less, and the cost of the single-sided copper clad laminate is lower. The direct welding type electrical connection is adopted, the chip circuit path in the module is shortened, the parasitic inductance is reduced, the power consumption loss of the circuit path during operation is reduced, and the signal response is faster. The structure is simplified, the size is reduced, and more chips and components can be integrated and transplanted into the module, providing conditions for realizing higher integration of the module without increasing or even reducing the size, and improving the space utilization of the module. Three-dimensional heat dissipation on multiple levels of top layer heat dissipation, middle layer heat dissipation and bottom layer heat dissipation is realized, so the heat dissipation is better, the power consumption is lower, the performance is more stable, and the reliability is higher. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a three-dimensional diagram of the first embodiment of the packaging structure of the present invention;

[0029] Figure 2 is a top view of the first embodiment of the packaging structure of the present invention;

[0030] Figure 3 yes Figure 2 Sectional view along the AA direction;

[0031] Figure 4 is a schematic structural diagram of a middle copper layer circuit board in Embodiment 1;

[0032] Figure 5 It is a schematic diagram of the structure of the upper single-sided copper clad laminate in Example 1;

[0033] Figure 6 It is a schematic diagram of the action of printing the welding material onto the upper surface of the lower single-sided copper clad laminate;

[0034] Figure 7 It is a schematic diagram of the action of mounting the second chip on the upper surface of the lower single-sided copper-clad board;

[0035] Figure 8 It is a schematic diagram of the action of printing the soldering material onto the second chip and the bosses on the lower single-sided copper-clad board;

[0036] Fig. 9 It is a schematic diagram of the action of attaching the middle copper layer circuit board to the second chip and the boss on the lower single-sided copper clad board;

[0037] Fig.10 It is a schematic diagram of the action of printing the soldering material onto the upper surface of the middle copper layer circuit board;

[0038] Fig.11 It is a schematic diagram of the action of mounting the first chip on the upper surface of the middle copper layer circuit board;

[0039] Fig.12 It is a schematic diagram of the action of printing the soldering material onto the first chip and the upper surface of the middle copper layer circuit board;

[0040] Fig.13 It is a schematic diagram of the action of attaching the upper single-sided copper-clad board to the upper surface of the first chip and the middle copper layer circuit board;

[0041] Fig.14 It is a schematic diagram of the structure obtained after the upper single-sided copper clad board, the first chip, the middle copper layer circuit board, the second chip and the lower single-sided copper clad board are welded;

[0042] Fig.15 It is a schematic diagram of the structure of the semi-finished product obtained after plastic packaging;

[0043] Fig.16 is a top view of the second embodiment of the packaging structure of the present invention;

[0044] Fig.17 It is a structural schematic diagram of a middle copper layer circuit board in Embodiment 2 of the packaging structure of the present invention;

[0045] Fig.18 It is a schematic diagram of the matching structure of the first chip and the middle copper layer circuit board in the second embodiment of the packaging structure of the present invention;

[0046] Fig.19 It is a schematic diagram of the action of attaching a glue film to the outer surface of the inner copper layer in the method for manufacturing the upper single-sided copper clad laminate of the present invention;

[0047] Fig. 20 It is a schematic diagram of printing a low-temperature sintering material on the inner copper layer in the method for manufacturing the upper single-sided copper-clad laminate of the present invention;

[0048] Fig.21 It is a schematic diagram of placing an insulating heat-conducting substrate on a low-temperature sintering material in the method for manufacturing an upper single-sided copper-clad laminate of the present invention;

[0049] Fig. 22 It is a schematic diagram of plastic sealing the semi-finished product obtained after sintering in the method for manufacturing the upper single-sided copper-clad laminate of the present invention;

[0050] Fig.23 It is a schematic diagram of removing the plastic encapsulation material on the outer surface of the insulating heat-conducting substrate in the method for manufacturing the upper single-sided copper-clad laminate of the present invention;

[0051] Fig.24 It is a schematic diagram of the manufacturing method of the entire upper single-sided copper clad laminate;

[0052] Fig.25 is a schematic diagram of the structure of the first chip of the present application;

[0053] Fig.26 It is a cross-sectional view of another embodiment of the packaging method of the packaging structure of the present invention.

[0054] Among them, 1. upper single-sided copper clad laminate; 11. insulating thermal conductive substrate; 12. inner copper layer; 13. boss; 14. low-temperature sintering material; 15. second plastic package; 2. first chip; 21. first pole; 22. second pole; 23. third pole; 3. middle copper layer circuit board; 31. first external pin; 32. second external pin; 321. first sub-pin; 322. second sub-pin; 33. third external pin; 34. first conductive circuit; 35. second conductive circuit; 351. first sub-circuit; 352. second sub-circuit; 36. third conductive circuit; 37. fourth external pin; 4. second chip; 5. lower single-sided copper clad laminate; 6. first plastic package; 7. temperature sensor element; 8. unidirectional diode; 9. adhesive film. DETAILED DESCRIPTION

[0055] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0056] As the first embodiment of the chip stacking multi-layer heat dissipation packaging structure of the present invention, Figures 1 to 15 As shown, it includes, from top to bottom, an upper single-sided copper clad laminate 1, a first chip 2, a middle copper layer circuit board 3, a second chip 4 and a lower single-sided copper clad laminate 5, and also includes a first plastic package 6 for wrapping the upper single-sided copper clad laminate 1, the middle copper layer circuit board 3, the lower single-sided copper clad laminate 5, the first chip 2 and the second chip 4; the upper single-sided copper clad laminate 1 includes an insulating heat-conductive substrate 11 and an inner copper layer 12, and a boss 13 is also provided on the inner copper layer 12; the lower single-sided copper clad laminate 5 has the same structure as the upper single-sided copper clad laminate 1; The middle copper layer circuit board 3 is provided with a plurality of external pins and a plurality of conductive circuits. The inner electrodes of the first chip 2 and the second chip 4 are connected to the external pins through the conductive circuits on the middle copper layer circuit board 3. The outer electrodes of the first chip 2 are connected to the external pins through the inner copper layer 12 of the upper single-sided copper clad board 1, the boss 13 and the conductive circuits on the middle copper layer circuit board 3. The outer electrodes of the second chip 4 are connected to the external pins through the inner copper layer, the boss and the conductive circuits on the middle copper layer circuit board 3 of the lower single-sided copper clad board 5. The size of the external pins is designed to match the current to be carried.

[0057] In this embodiment, the first chip 2 and the second chip 4 are the same chip, and preferably a GaN chip or a SiC chip. GaN chips or SiC chips are both power chips with high heat dissipation requirements, and the electrical performance and heat dissipation advantages of the packaging structure described in the present invention are more obvious. The first chip 2 and the second chip 4 are mirror-symmetrically welded on the front and back sides of the middle copper layer circuit board 3 to form a symmetrical stacking structure, achieving vertical symmetry and rapid heat dissipation, enhancing the balance of product heat dissipation, and having more stable performance and greater power density.

[0058] In this embodiment, the first chip 2 and the second chip 4 are power chips, including a first pole 21 and a second pole 22 located on the front side, and a third pole 23 located on the back side; the first chip 2 is flipped, and the second chip 4 is mounted upright; the middle copper layer circuit board 3 is provided with a first external pin 31, a second external pin 32, a third external pin 33, a first conductive circuit 34, a second conductive circuit 35 and a third conductive circuit 36; the first pole 21 of the first chip 2 is connected to the first external pin 31 through the first conductive circuit 34 on the middle copper layer circuit board 3, and the second pole 22 of the first chip 2 is connected to the second conductive circuit 35 on the middle copper layer circuit board 3 The second external pin 32, the third pole 23 of the first chip 2 is connected to the third external pin 33 through the inner copper layer 12 of the upper single-sided copper clad laminate 1, the boss 13, and the third conductive circuit 36 ​​on the middle copper layer circuit board 3; the first pole 21 of the second chip 4 is connected to the first external pin 31 through the first conductive circuit 34 on the middle copper layer circuit board 3, the second pole 22 of the second chip 4 is connected to the second external pin 32 through the second conductive circuit 35 on the middle copper layer circuit board 3, and the third pole 23 of the second chip 4 is connected to the third external pin 33 through the inner copper layer of the lower single-sided copper clad laminate 5, the boss, and the third conductive circuit 36 ​​on the middle copper layer circuit board 3.

[0059] In this embodiment, the first chip 2 and the second chip 4 are IGBTs, the first pole 21 is the E pole, the second pole 22 is the G pole, and the third pole 23 is the C pole. Of course, the first chip 2 and the second chip 4 can also be field effect transistors, the first pole is the D pole, the second pole is the G pole, and the third pole is the S pole.

[0060] In this embodiment, the number of the first chip 2 and the second chip 4 is multiple groups, and the groups are arranged horizontally in parallel. Specifically, there are two groups, including a total of four chips. Multiple chips can basically be understood as a parallel relationship, so they can be expanded to more chips to improve the current capacity, or they can be reduced to a minimum of two chips.

[0061] The packaging method of the chip stacking multi-layer heat dissipation packaging structure described in this embodiment includes the following steps:

[0062] S1. Attach the second chip 4 to the upper surface of the lower single-sided copper clad laminate 5, and then perform the first sintering or reflow soldering, preferably sintering soldering;

[0063] S2. Attach the middle copper layer circuit board 3 to the bosses of the second chip 4 and the lower single-sided copper clad laminate 5, and then perform the second sintering or reflow soldering, preferably sintering soldering;

[0064] S3. Attach the first chip 2 to the upper surface of the middle copper layer circuit board 3, and then perform the third sintering or reflow soldering, preferably sintering soldering;

[0065] S4. Attach the upper single-sided copper clad laminate to the first chip 2 and the middle copper layer circuit board 3, and then perform the fourth sintering or reflow soldering, preferably sintering soldering;

[0066] S5. Perform plastic encapsulation to obtain the first plastic encapsulated body 6;

[0067] S6. Grind the upper and lower surfaces of the first plastic encapsulated body 6 to expose the outer surfaces of the insulating and heat-conducting substrates of the upper single-sided copper clad laminate 1 and the lower single-sided copper clad laminate 5, so as to better dissipate heat or fit with external heat dissipation devices.

[0068] After S6, step S7 can be added. Deposit a layer of high heat dissipation metal on the outer surfaces of the insulating and heat-conducting substrates of the upper single-sided copper clad laminate 1 and the lower single-sided copper clad laminate 5 to enhance the heat dissipation effect. Specifically, sputtering or electroless plating can be used. The high heat dissipation metal material is preferably copper, and the coating thickness is preferably 10μm - 30μm.

[0069] To ensure good electrical connection between the bosses and the middle copper layer circuit board 3, the height H of the bosses should meet the following requirements: (chip thickness + 0.8 × chip solder layer thickness) < H < (chip thickness + 1.5 × chip solder layer thickness).

[0070] As an equivalent replacement scheme for the above-mentioned encapsulation method, or a more optimal and simpler scheme, the steps are deformed as follows:

[0071] S1. Attach the first chip to the inner copper layer of the upper single-sided copper clad laminate; attach the second chip to the inner copper layer of the lower single-sided copper clad laminate, and then perform the first sintering or reflow soldering, preferably sintering soldering;

[0072] S2. Attach the middle copper layer circuit board to the bosses of the second chip and the lower single-sided copper clad laminate, and then perform the second sintering or reflow soldering, preferably sintering soldering;

[0073] S3. Attach the assembly of the first chip and the upper single-sided copper clad laminate after soldering to the upper surface of the middle copper layer circuit board completed in step S2, and then perform the third sintering or reflow soldering, preferably sintering soldering;

[0074] S4, performing plastic sealing to obtain a first plastic sealing body;

[0075] S5, grinding the upper and lower surfaces of the first plastic package body to expose the outer surfaces of the insulating heat-conductive substrates of the upper single-sided copper clad laminate and the lower single-sided copper clad laminate.

[0076] The packaging method of this embodiment reduces one sintering or reflow soldering, is simpler in steps, and has higher packaging efficiency.

[0077] The present application adopts an upper single-sided copper clad laminate 1, a middle copper layer circuit board 3 and a lower single-sided copper clad laminate 5. Compared with the three double-sided copper clad laminates in the current technology, the thickness is thinner, while the overall structure of the chip stack is not changed, so that the thickness of the entire packaging structure is greatly thinner, the packaging structure is smaller, the heat dissipation path is shorter, the heat dissipation efficiency is higher, and the power density of the module can be greatly improved. Less packaging material is used, and the cost of the single-sided copper clad laminate is lower.

[0078] The outer electrode of the first chip 2 can be connected to the outer pin through the inner copper layer 12 and the boss 13 of the upper single-sided copper clad laminate 1, and the conductive circuit on the middle copper layer circuit board 3. The outer electrode of the second chip 4 can be connected to the outer pin through the inner copper layer and the boss of the lower single-sided copper clad laminate 5, and the conductive circuit on the middle copper layer circuit board 3, to achieve a complete circuit connection, thereby realizing the function of the module, and adopting direct welding electrical connection, compared with the indirect welding of metal gaskets, or welding of metal wires or metal sheets in current technology, it greatly simplifies the welding process and materials, reduces the problem of welding tilt, optimizes the electrical connection structure, shortens the chip circuit path in the module, greatly reduces the parasitic inductance of the module, and has faster signal response. The power consumption loss of the circuit path during operation is reduced, the performance is more stable, the service life is improved, and the power density is higher.

[0079] The present application has a simplified structure and reduced size, and can be integrated and transplanted into more chips and components into the module, providing conditions for higher module integration without increasing or even reducing the size, thereby improving the module space utilization.

[0080] The packaging method of the present application can use sintering or reflow soldering in its entirety, thereby simplifying the chip welding process. The chip is directly welded to the middle copper layer circuit board 3, the upper single-sided copper clad board 1 and the lower single-sided copper clad board 5 to form a circuit. The welding dielectric layer is reduced, and defects such as welding voids and tilt are reduced. The module packaging yield is higher, the packaging process flow is simplified, the packaging cycle is shortened, and the use of packaging equipment and packaging materials is reduced.

[0081] The upper single-sided copper clad board 1 and the lower single-sided copper clad board 5 not only carry the high current output of multiple chips, but also can quickly conduct away the heat generated by the operation of the chips. The middle copper layer circuit board 3 is not only used for circuit connection, but also can quickly transfer the heat generated by the operation of the chips to the external pins, and then transfer it to the circuit board and the surrounding environment through the external pins, so as to achieve three-dimensional heat dissipation on multiple levels of top layer heat dissipation, middle layer heat dissipation and bottom layer heat dissipation, so as to have better heat dissipation, lower power consumption, more stable performance and higher reliability.

[0082] The middle copper layer circuit board 3 is formed in an integrated manner, and external pins and conductive circuits can be manufactured simultaneously. It is easy to manufacture and has low cost. It eliminates the process of separating pins and then welding in previous products, reduces welding quality risks, and improves product reliability.

[0083] By adopting the packaging structure of this embodiment, the module power density is higher and can withstand greater current. According to the applicant's statistics, the module size can be reduced by up to 50%, the module thickness is reduced by 60%, the use of plastic packaging materials is reduced by 60%, the size of the copper clad board is reduced by 50%, the heat dissipation is improved by 40%, and the product cost is reduced by 50%; the packaging process is simplified, all reflow soldering is used, the process is unified, the steps are simplified, the product yield is improved, the production capacity is increased by 20%, the chip circuit path in the module is shortened, parasitic inductance is not easily generated, and the parasitic inductance is very small, less than 2nH; the power loss of the circuit path during operation is reduced by 30%, and the signal response is faster.

[0084] As a second embodiment of the chip stacking multi-layer heat dissipation packaging structure of the present invention, Figures 16 to 18 As shown, the difference from the first embodiment is that the middle copper layer circuit board 3 is further provided with a fourth external pin 37, and a temperature sensing element 7 is connected between the fourth external pin 37 and the first conductive circuit 34. The temperature signal of the temperature sensing element 7 can be transmitted through the fourth external pin 37 and the first external pin 31, thereby realizing the internal temperature detection function of the module.

[0085] In addition, the second external pin 32 includes a first sub-pin 321 and a second sub-pin 322 that are independent of each other, the second conductive circuit 35 includes a first sub-circuit 351 and a second sub-circuit 352, the first sub-pin 321 is connected to the first sub-circuit 351, the second sub-pin 322 is connected to the second sub-circuit 352, and a unidirectional diode 8 is provided between the first sub-circuit 351 and the second sub-circuit 352. When only the first sub-pin 321 is connected to an external control signal, the two groups of first chips 2 and second chips 4 can work normally and are in a full-power working state; when only the second sub-pin 322 is connected to an external control signal, only the left group of chips in the two groups of first chips 2 and second chips 4 can work normally, and the right group of chips does not work and is in a half-power working state, thereby adding a means of adjusting power. Other structures and beneficial effects are consistent with those of the first embodiment, and are not repeated here.

[0086] In the present application, the insulating thermally conductive substrate 11 is an insulating thermally conductive ceramic substrate, and the insulating thermally conductive ceramic substrate and the inner copper layer 12 are sintered into one by a low-temperature sintering material 14. The low-temperature sintering material 14 is sintered silver, sintered copper, solder paste, prefabricated tin sheet or non-conductive heat dissipation glue. The sintering temperature of these materials is below 300°C, and sintered silver and sintered copper are preferred. The insulating thermally conductive substrate 11 material can be specifically selected from AI 2 O 3 , AIN, AISiC, etc. The side surfaces of the insulating thermally conductive ceramic substrate and the inner copper layer 12 are also wrapped with a second plastic package 15 .

[0087] The upper single-sided copper clad laminate 1 and the lower single-sided copper clad laminate 5 described in the present application also adopt a very special manufacturing method. Taking the upper single-sided copper clad laminate 1 as an example, the method specifically includes the following steps:

[0088] S0.1, making the inner copper layer 12, and at the same time making the boss 13, and also making some conductive circuits (if the conductive circuit is not designed separately, then the entire inner copper layer 12 is a conductive circuit);

[0089] S0.2, refer to Fig.19 , a film 9 is pasted on the outer surface of the inner copper layer 12 and compacted to keep one side of the boss 13 flat; the preferred relationship between the thickness H1 of the film 9 and the height T1 of the boss 13 is H1-T1>50μm-100μm;

[0090] S0.3, cleaning the surface of the inner copper layer 12 to remove dirt and impurities on the surface;

[0091] S0.4, refer to Fig. 20 , printing or coating a low-temperature sintering material 14 on the inner copper layer 12;

[0092] S0.5, cleaning the surface of the insulating thermally conductive substrate 11;

[0093] S0.6, refer to Fig.21 , placing the insulating heat-conducting substrate 11 on the low-temperature sintering material 14 for low-temperature sintering;

[0094] S0.7, cleaning the surface of the semi-finished product obtained in S0.6;

[0095] S0.8, refer to Fig. 22 , plastic-sealing the semi-finished product obtained in S0.7 to form a second plastic-sealed body 15, wherein the second plastic-sealed body 15 covers all surfaces except one side of the adhesive film 9;

[0096] S0.9, refer to Fig.23, remove the plastic packaging material on the outer surface of the insulating thermally conductive substrate 11 to expose the outer surface of the insulating thermally conductive substrate 11, specifically, a grinding or punching and milling process can be used; finally, remove the adhesive film 9 attached in step S0.2 to obtain a single-sided copper clad laminate product.

[0097] This method ensures the cleanliness of the surface of the inner copper layer 12 and prevents it from being covered by the plastic packaging material; it fully utilizes the flexibility of the adhesive film 9, solves the avoidance problem of the boss 13, and reduces the risk of deformation of the boss 13.

[0098] The first plastic package body 6 and the second plastic package body 15 have consistent properties and good bonding strength, thereby providing higher reliability and stability for the power module packaging structure.

[0099] In this embodiment, Fig.24 As shown, the overall plastic sealing of the entire page in step S0.8 refers to the integrated plastic sealing of the entire page product, and a single product does not have an independent plastic sealing body. The advantage of this is that as long as the size of the entire page is the same and the packaging thickness is consistent, the plastic sealing mold can be universal, which can save mold opening costs; in addition, since the plastic sealing no longer distinguishes between single products, there is no need to press the connecting ribs between single products, the plastic sealing mold structure is simpler and the plastic sealing yield is higher. When cutting the single-sided copper clad laminate into individual units, just cut off the plastic sealing material and the connecting ribs in the middle.

[0100] The single-sided copper-clad ceramic board of the present application is a brand-new design. It no longer adopts the traditional sandwich-type symmetrical structure of the upper and lower double-layer copper-clad boards to reduce the overall deformation and warping. Instead, it only sets a single-sided copper layer, and the structure is simpler. Low-temperature sintering (less than or equal to 300°C) replaces high-temperature welding (above 800°C) to reduce the overall deformation and warping caused by inconsistent thermal expansion, which greatly reduces the process difficulty and has fewer material bonding interfaces. Compared with the welding voids and welding delamination caused by two high temperatures, the defects are much reduced. At the same time, the number of processes and the processing materials used (solder, photosensitive adhesive, etching solution, cleaning solution) are also much less, the processing technology is simpler, the manufacturing cost is lower, and it is more suitable for large-scale production, with obvious overall advantages.

[0101] The manufacturing process of the inner copper layer 12 of the present application is similar to the processing method of the lead frame. It is directly manufactured through processes such as stamping, rather than etching. Compared with the two etchings of the original process, the number of processes is greatly reduced, the process is simpler, the processing flexibility is stronger, the conductive circuit accuracy is higher, and the manufacturing cost is lower. It completely changes the current situation of using etching process to manufacture conductive circuits in the existing double-sided copper-clad ceramic board. In mass production, the production and processing is carried out according to the inner copper layer 12 of the entire plate, with large batches and high production efficiency. The low-temperature sintered material 14 as the intermediate bonding layer can not only conduct heat and dissipate heat quickly, and improve the reliability of heat dissipation, but also has better toughness when the temperature changes, and plays a buffering role for the internal stress generated by the inconsistent deformation of the insulating thermally conductive substrate 11 and the inner copper layer 12, thereby reducing the risk of fracture and delamination of the intermediate bonding layer. The second plastic packaging body 15 is used to wrap the side surfaces of the insulating thermally conductive substrate 11 and the inner copper layer 12 to improve the overall strength of the single-sided copper clad laminate, while reducing the intrusion of moisture from the side and improving product reliability. The plastic packaging material on the outer surface of the insulating thermally conductive substrate 11 is removed through post-processing, which is not only beneficial to heat dissipation, but also can make the surface of the single-sided copper clad laminate smooth, which is beneficial to subsequent other operations.

[0102] In the present application, the manufacturing method of the insulating heat-conducting substrate 11 includes the step: S0.9, removing the plastic packaging material on the outer surface of the insulating heat-conducting substrate 11 to expose the outer surface of the insulating heat-conducting substrate 11; the packaging method of the chip stacking multi-layer heat dissipation packaging structure includes the step S5: grinding the upper and lower surfaces of the first plastic packaging body 6 to expose the outer surfaces of the insulating heat-conducting substrates of the upper single-sided copper-clad plate 1 and the lower single-sided copper-clad plate 5. Fig.26 As shown, in the manufacturing method of the insulating thermally conductive substrate 11, step S0.9 can be reduced, and the plastic encapsulation material on the outer surface of the insulating thermally conductive substrate 11 does not need to be removed; only the plastic encapsulation material on the outer surface of the insulating thermally conductive substrate 11 needs to be removed in step S5 of the packaging method to expose the outer surface of the insulating thermally conductive substrate 11. In this way, the manufacturing method of the insulating thermally conductive substrate 11 reduces one process step, and the cost is lower; the packaging method of the chip stacking multi-layer heat dissipation packaging structure does not increase the process step, but the grinding process slightly increases the processing time, and the comprehensive process is more concise.

[0103] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A chip stacking multi-layer heat dissipation packaging structure, characterized in that: From top to bottom, it includes an upper single-sided copper clad laminate, a first chip, a middle copper layer circuit board, a second chip and a lower single-sided copper clad laminate, and also includes a first plastic package for wrapping the upper single-sided copper clad laminate, the middle copper layer circuit board, the lower single-sided copper clad laminate, the first chip and the second chip; the upper single-sided copper clad laminate and the lower single-sided copper clad laminate both include an insulating heat-conductive substrate and an inner copper layer, and a boss is also provided on the inner copper layer; the middle copper layer circuit board is provided with a plurality of external pins and a plurality of conductive circuits, the inner electrodes of the first chip and the second chip are connected to the external pins through the conductive circuits on the middle copper layer circuit board, the outer electrodes of the first chip are connected to the external pins through the inner copper layer of the upper single-sided copper clad laminate, the boss and the conductive circuits on the middle copper layer circuit board, and the outer electrodes of the second chip are connected to the external pins through the inner copper layer of the lower single-sided copper clad laminate, the boss and the conductive circuits on the middle copper layer circuit board.

2. The chip stacking multi-layer heat dissipation packaging structure according to claim 1, characterized in that: The first chip and the second chip are identical chips and are soldered on the front and back sides of the middle copper layer circuit board in a mirror-symmetrical manner.

3. The chip stacking multi-layer heat dissipation packaging structure according to claim 2, characterized in that: The number of the first chips and the second chips is multiple groups, and the groups are arranged horizontally in parallel.

4. The chip stacking multi-layer heat dissipation packaging structure according to claim 1, characterized in that: The insulating thermally conductive substrate is an insulating thermally conductive ceramic substrate, and the insulating thermally conductive ceramic substrate and the inner copper layer are sintered into one by a low-temperature sintering material, and the low-temperature sintering material is sintered silver, sintered copper, solder paste, prefabricated tin sheet or non-conductive heat dissipation glue.

5. The chip stacking multi-layer heat dissipation packaging structure according to claim 4, characterized in that: The insulating thermally conductive ceramic substrate and the side surfaces of the inner copper layer are also wrapped with a second plastic packaging body.

6. The chip stacking multi-layer heat dissipation packaging structure according to claim 1, characterized in that: The first chip and the second chip are power chips, including a first pole and a second pole located on the front side, and a third pole located on the back side; the first chip is flipped, and the second chip is mounted upright; the middle copper layer circuit board is provided with a first external pin, a second external pin, a third external pin, a first conductive circuit, a second conductive circuit and a third conductive circuit; the first pole of the first chip is connected to the first external pin through the first conductive circuit on the middle copper layer circuit board, the second pole of the first chip is connected to the second external pin through the second conductive circuit on the middle copper layer circuit board, the third pole of the first chip is connected to the inner copper layer of the upper single-sided copper clad board, the boss, the middle copper layer circuit board The third conductive circuit on the middle copper layer circuit board is connected to the third external pin; the first pole of the second chip is connected to the first external pin through the first conductive circuit on the middle copper layer circuit board, the second pole of the second chip is connected to the second external pin through the second conductive circuit on the middle copper layer circuit board, and the third pole of the second chip is connected to the third external pin through the inner copper layer of the lower single-sided copper clad board, the boss, and the third conductive circuit on the middle copper layer circuit board; the first chip and the second chip are field effect transistors, the first pole is the D pole, the second pole is the G pole, and the third pole is the S pole; or the first chip and the second chip are IGBTs, the first pole is the E pole, the second pole is the G pole, and the third pole is the C pole.

7. The chip stacking multi-layer heat dissipation packaging structure according to claim 6, characterized in that: The middle copper layer circuit board is also provided with a fourth external pin, and a temperature sensing element is connected between the fourth external pin and the first conductive circuit.

8. The chip stacking multi-layer heat dissipation packaging structure according to claim 6, characterized in that: The second external pin includes a first sub-pin and a second sub-pin that are independent of each other, the second conductive circuit includes a first sub-circuit and a second sub-circuit, the first sub-pin is conductively connected to the first sub-circuit, the second sub-pin is conductively connected to the second sub-circuit, and a unidirectional diode is provided between the first sub-circuit and the second sub-circuit.

9. A packaging method for the chip stacking multi-layer heat dissipation packaging structure according to any one of claims 1 to 8, characterized in that: The following steps are involved: S1, mounting the second chip on the upper surface of the lower single-sided copper-clad board, and then performing the first sintering or reflow soldering; S2, mounting the middle copper layer circuit board on the second chip and the boss of the lower single-sided copper clad board, and then performing a second sintering or reflow soldering; S3, mounting the first chip on the upper surface of the middle copper layer circuit board, and then performing a third sintering or reflow soldering; S4, mounting the upper single-sided copper clad laminate on the first chip and the middle copper layer circuit board, and then performing a fourth sintering or reflow soldering; S5, performing plastic sealing to obtain a first plastic-sealed body; S6, grinding the upper and lower surfaces of the first plastic package body to expose the outer surfaces of the insulating heat-conductive substrates of the upper single-sided copper clad laminate and the lower single-sided copper clad laminate.

10. A packaging method for the chip stacking multi-layer heat dissipation packaging structure according to any one of claims 1 to 8, characterized in that: The following steps are involved: S1, mounting the first chip on the inner copper layer of the upper single-sided copper-clad laminate; mounting the second chip on the inner copper layer of the lower single-sided copper-clad laminate, and then performing the first sintering or reflow soldering; S2, mounting the middle copper layer circuit board on the second chip and the boss of the lower single-sided copper clad board, and then performing a second sintering or reflow soldering; S3, mounting the first chip and the upper single-sided copper-clad laminate after welding on the upper surface of the middle copper-layer circuit board after completing step S2, and then performing a third sintering or reflow soldering; S4, performing plastic sealing to obtain a first plastic sealing body; S5, grinding the upper and lower surfaces of the first plastic package body to expose the outer surfaces of the insulating heat-conductive substrates of the upper single-sided copper clad laminate and the lower single-sided copper clad laminate.

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