Display substrate and display device

Abstract

The invention provides a display substrate and a display device. The display substrate comprises a substrate; the plurality of first wires are arranged on the same layer or different layers, and a first gap is formed between orthographic projections of at least part of two adjacent first wires on the substrate; the film layer where the first wires are located is located on the side, close to the substrate, of the film layer where the second wires are located, and a first insulating layer is arranged between the film layer where the first wires are located and the film layer where the second wires are located; the film layer where the segment difference compensation patterns are located is located between the film layer where the first wires are located and the substrate, and orthographic projections of the segment difference compensation patterns on the substrate are located between every two adjacent first wires so as to be at least partially overlapped with the first gaps. According to the display substrate and the display device, the reliability of the display substrate can be improved, and the product quality is improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] With the rapid development of electronic devices, users have higher and higher requirements on the display quality of electronic devices. However, display panels in related technologies are prone to display defects, such as bright lines, dark lines, and bright spots. Summary of the invention

[0003] The embodiments of the present disclosure provide a display substrate and a display device, which can improve the reliability of the display substrate and enhance product quality.

[0004] The technical solutions provided by the embodiments of the present disclosure are as follows:

[0005] In a first aspect, an embodiment of the present disclosure provides a display substrate, comprising:

[0006] substrate substrate;

[0007] A plurality of first routing lines, wherein the plurality of first routing lines are arranged in the same layer or in different layers, and an orthographic projection on the substrate between at least two adjacent first routing lines has a first gap;

[0008] a plurality of second routing lines, wherein the film layer where the first routing lines are located is located on a side of the film layer where the second routing lines are located close to the base substrate, and a first insulating layer is provided between the film layer where the first routing lines are located and the film layer where the second routing lines are located; and

[0009] A plurality of step compensation patterns, wherein the film layer where the plurality of step compensation patterns are located is located between the film layer where the first routing line is located and the base substrate, and the orthographic projection of the step compensation pattern on the base substrate is located between two adjacent first routing lines to at least partially overlap with the first gap.

[0010] Exemplarily, the display substrate includes:

[0011] At least one gate metal layer and at least one source-drain metal layer, the gate metal layer includes a plurality of gate metal lines, and the source-drain metal layer includes a plurality of source-drain metal lines; wherein at least part of the first wiring includes the gate metal line, and at least part of the second wiring includes the source-drain metal line.

[0012] Exemplarily, the display substrate includes:

[0013] There are at least two layers of gate metal layers, a second insulating layer is provided between adjacent gate metal layers, at least part of the first routing includes gate metal wires respectively located on different gate metal layers, wherein at least part of the two gate metal wires of different layers and adjacent to each other have the first gap between their orthographic projections on the substrate, and at least part of the orthographic projection of the step difference compensation pattern on the substrate is located between the two gate metal wires of different layers and adjacent to each other.

[0014] Exemplarily, the step compensation pattern has a first thickness in a direction perpendicular to the base substrate, and the first thickness is 1-2.5 μm; the step compensation pattern has a first width in a line width direction of the first trace, and the first width is 0.5-3.2 μm.

[0015] Exemplarily, the display substrate includes a bottom shading layer, and the bottom shading layer is located between the film layer where the first wiring is located and the base substrate, wherein the step compensation pattern is in the same layer and made of the same material as the pattern of the bottom shading layer.

[0016] Exemplarily, in the line width direction of the first routing line, the step difference compensation pattern and the orthographic projection of the first routing line adjacent thereto on the substrate substrate at least partially overlap to form an overlapping area; the first insulating layer conformally covers the side of the first routing line away from the substrate substrate, and forms a first area at a position corresponding to the step difference compensation pattern, and forms a second area at a position corresponding to the overlapping area, the second area protrudes in a direction away from the substrate substrate relative to the first area, and the step difference between the surface of the first area and the second area on the side facing away from the substrate substrate is within a threshold.

[0017] Exemplarily, in the line width direction of the first routing line, the step compensation pattern and the orthographic projection of the first routing line adjacent thereto on the substrate substrate do not overlap; the first insulating layer conformally covers the side of the first routing line away from the substrate substrate, and the first insulating layer forms a first area at a position corresponding to the step compensation pattern, and forms a third area at a position corresponding to the first routing line; wherein,

[0018] The first area and the third area are located in the same plane on a side surface facing away from the substrate;

[0019] Alternatively, the first region is recessed relative to the third region toward the substrate, and a step difference between a surface of the first region and a surface of the third region facing away from the substrate is within a threshold.

[0020] Exemplarily, the display area of ​​the display substrate includes a first display area and a second display area, and the light transmittance of the first display area is greater than the light transmittance of the second display area;

[0021] Wherein, the area between the second display area and the first display area includes a first transition area and a second transition area which are sequentially arranged along a direction from the first display area to the second display area;

[0022] Among them, at least part of the first routing, the second routing and the step compensation pattern are arranged in the first transition area; and / or at least part of the first routing, the second routing and the step compensation pattern are arranged in the second transition area.

[0023] Exemplarily, the display area of ​​the display substrate has a pixel array;

[0024] The display substrate further comprises:

[0025] a plurality of first signal lines and a plurality of second signal lines arranged in the second display area and extending along a row direction of the pixel array;

[0026] a plurality of third signal lines and a plurality of fourth signal lines arranged in the second display area and extending along a column direction of the pixel array;

[0027] Wherein, arranged in the first transition zone are:

[0028] A first winding line extending around a portion of the circumference of the first display area, the first winding line being connected to the corresponding first signal line;

[0029] a second winding extending around a portion of the circumference of the first display area, the second winding being connected to the corresponding second signal line;

[0030] a third winding extending around a portion of the circumference of the first display area, the third winding being connected to the corresponding third signal line;

[0031] a fourth winding extending around a portion of the circumference of the first display area, the fourth winding being connected to the corresponding fourth signal line;

[0032] Among them, at least part of the first routing includes the first winding and the second winding, at least part of the second routing includes the third winding and the fourth winding, and there is the first gap between the first winding and the second winding; the orthographic projection of the step compensation pattern on the substrate is located between the adjacently arranged first winding and the second winding, and at least partially overlaps with the first gap.

[0033] Exemplarily, the display area of ​​the display substrate has a pixel array;

[0034] Arranged in the second transition zone are:

[0035] a fifth signal line and a sixth signal line extending along a row direction of the pixel array;

[0036] a seventh signal line and an eighth signal line extending along a column direction of the pixel array;

[0037] Among them, at least part of the first routing includes the fifth signal line and the sixth signal line, and at least part of the second routing includes the seventh signal line and the eighth signal line; and there is the first gap between the fifth signal line and the sixth signal line; the orthographic projection of the step difference compensation pattern on the substrate is located between the adjacently arranged fifth signal line and the sixth signal line, and at least partially overlaps with the first gap.

[0038] In a second aspect, an embodiment of the present disclosure further provides a display device, which includes the display substrate as described above.

[0039] The beneficial effects brought by the embodiments of the present disclosure are as follows:

[0040] In the above scheme, a plurality of first routing lines and a plurality of second routing lines are provided on the display substrate, the first routing lines and the second routing lines are provided in different layers, and the film layer where the first routing lines are located is located on the side of the film layer where the second routing lines are located close to the base substrate, the first routing lines and the second routing lines are insulated by a first insulating layer, a plurality of step compensation patterns are provided on the side of the first routing lines close to the base substrate, and the step compensation patterns are located at the position corresponding to the first gap between two adjacent first routing lines, so that the step compensation can be performed on the area corresponding to the first gap in the first insulating layer, so as to avoid the occurrence of a large step difference, such as the formation of a deeper groove, when the first insulating layer is conformally covered on the film layer where the first routing lines are located due to the existence of the first gap, thereby avoiding the problem of residual conductive material in the groove when the pattern of the second routing lines is formed on the side of the first insulating layer away from the base substrate, thereby causing a short circuit between the second routing lines for transmitting different signals, thereby effectively avoiding poor display such as bright lines, dark lines or bright spots caused by short circuit of the second routing lines, improving the reliability of the display substrate, and improving product quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 One of the partial cross-sectional structural schematic diagrams of a display substrate provided in some embodiments of the present disclosure is shown;

[0042] Figure 2 A second schematic diagram showing a partial cross-sectional structure of a display substrate provided in some embodiments of the present disclosure;

[0043] Figure 3 A front view of a display substrate provided in some embodiments of the present disclosure

[0044] Figure 4 A schematic diagram showing a portion of wiring in a first transition area outside a first display area of ​​a display substrate in some embodiments of the present disclosure;

[0045] Figure 5 express Figure 4 A-A' sectional view;

[0046] Figure 6 A schematic diagram showing a portion of wiring in a second transition area outside a first display area of ​​a display substrate in some embodiments of the present disclosure;

[0047] Figure 7 express Figure 6 Sectional view along the BB' axis. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0049] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0050] The features such as "parallel", "perpendicular", and "same" used in the embodiments of the present disclosure include the features such as "parallel", "perpendicular", and "same" in a strict sense, as well as the cases where "approximately parallel", "approximately perpendicular", "approximately the same", etc. include certain tolerances, taking into account the tolerances associated with the measurement of specific quantities (e.g., the limitations of the measurement system), and represent the acceptable deviation range for a specific value determined by ordinary technicians in the field. For example, "approximately" can mean within one or more standard deviations, or within 3% or 5% of the value.

[0051] In addition, in this document, unless otherwise defined, the terms "substantially", "substantially", "approximately" and "about" are used to describe and explain small changes. When used with an event or situation, these terms can cover situations where the event or situation occurs exactly, and can also cover situations where the event or situation occurs approximately. For example, when used with a numerical value, these terms can include a range of variation of less than or equal to 10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, less than or equal to ±0.05%. The term "substantially coplanar" can refer to two surfaces being arranged along the same plane in the micrometer range, for example, arranged along the same plane within 40μm, 30μm, 20μm, 10μm or 1μm.

[0052] It should be understood that in the exemplary embodiments of the present disclosure, when a layer or an element is referred to as being on another layer or substrate, the layer or element may be directly on the other layer or substrate, or there may be an intermediate layer between the layer or element and the other layer or substrate. "A and B are arranged on the same layer" means that after A and B adopt the same film forming process to form a film layer for forming a specific pattern, a layer structure is formed by a single patterning process using the same mask.

[0053] In the embodiments of the present disclosure, before describing in detail the display substrate and the display device provided in the embodiments of the present disclosure, the related technologies are described as follows.

[0054] In the related art, with the rapid development of electronic devices, users have higher and higher requirements on the display quality of electronic devices. However, display defects such as bright lines, dark lines and bright spots are prone to occur in the display panels of the related art.

[0055] The applicant of the present disclosure has found through research that one of the reasons for the above problems is that short circuits occur between adjacent wirings for transmitting different signals, resulting in problems such as bright lines, dark lines or bright spots.

[0056] Specifically, a plurality of metal layers are arranged on the display substrate, such as a gate metal layer and a source-drain metal layer, and signal routing lines are arranged on each metal layer. Taking the gate metal layer and the source-drain metal layer as examples, a plurality of gate metal lines are arranged on the gate metal layer, a plurality of source-drain metal lines are arranged on the source-drain metal layer, an insulating layer is arranged between the gate metal layer and the source-drain metal layer, a certain gap is arranged between two adjacent gate metal lines, and the insulating layer is conformally covered on the gate metal layer. Due to the existence of the gap, a groove is formed on the surface of the insulating layer away from the substrate in the region corresponding to the gap between two adjacent gate metal lines, that is, a large step difference is generated, which results in that when the source-drain metal layer is formed on the surface of the insulating layer away from the substrate, part of the source-drain metal will remain in the groove, thereby causing the source-drain metal lines used to transmit different signals to be connected by the source-drain metal remaining in the groove, resulting in a short circuit, thereby causing problems such as bright lines, dark lines or bright spots.

[0057] In the related art, taking full-screen display as an example, in the related art, a hole area is formed in the display area of ​​the display panel, and the hole area can be a blind hole or a through hole. The hole area has a higher light transmittance, so that photosensitive modules such as a front camera, an earpiece, and an infrared sensor element can be integrated in the area opposite to the hole area in the display panel to increase the screen-to-body ratio. However, there are many wirings near the hole area in the display panel, which is prone to display defects such as bright lines, dark lines, and bright spots.

[0058] In order to improve problems such as bright lines, dark lines or bright spots in a display substrate, the embodiments of the present disclosure provide a display substrate and a display device, which can improve the reliability of the display substrate and enhance product quality.

[0059] like Figure 1 and Figure 2 As shown, the display substrate provided by the embodiment of the present disclosure includes: a base substrate 100, a plurality of first wirings 200 arranged on the base substrate 100, a plurality of second wirings 300 arranged on the base substrate 100, and a plurality of step compensation graphics 400 arranged on the base substrate 100.

[0060] A plurality of first routing lines 200 are arranged in the same layer or in different layers, and a first gap A1 is formed between two adjacent first routing lines 200 that are at least partially in the same layer or in different layers; a plurality of second routing lines 300 are arranged in the same layer or in different layers, and the film layer where the first routing lines 200 are located is located on a side of the film layer where the second routing lines 300 are located close to the base substrate 100, and a first insulating layer 500 is provided between the film layer where the first routing lines 200 are located and the film layer where the second routing lines 300 are located;

[0061] The film layer where the multiple step compensation patterns 400 are located is located between the film layer where the first routing line 200 is located and the base substrate 100. The orthographic projection of the step compensation pattern 400 on the base substrate 100 is located between two adjacent first routing lines 200 so as to at least partially overlap with the first gap A1. The step compensation pattern 400 is used to perform height compensation on the area of ​​the first insulating layer 500 corresponding to the first gap A1 to avoid the step difference caused by the existence of the first gap A1.

[0062] In the above scheme, a plurality of first routing lines 200 and a plurality of second routing lines 300 are provided on the display substrate, the first routing lines 200 and the second routing lines 300 are arranged in different layers, and the film layer where the first routing lines 200 are located is located on the side of the film layer where the second routing lines 300 are located close to the base substrate 100, the first routing lines 200 and the second routing lines 300 are insulated by a first insulating layer 500, and a plurality of step compensation patterns 400 are arranged on the side of the first routing lines 200 close to the base substrate 100, and the step compensation patterns 400 are located at a position corresponding to the first gap A1 between two adjacent first routing lines 200.

[0063] In this way, the step difference compensation can be performed on the area corresponding to the first gap A1 in the first insulating layer 500, so as to avoid the first insulating layer 500 from conformally covering the film layer where the first wiring 200 is located due to the existence of the first gap A1, thereby avoiding the problem of residual conductive material in the groove when the pattern of the second wiring 300 is formed on the side of the first insulating layer 500 away from the base substrate 100, thereby causing a short circuit between the second wirings 300 used to transmit different signals, thereby effectively avoiding poor display of bright lines, dark lines or bright spots caused by short circuit of the second wiring 300, thereby improving the reliability of the display substrate and enhancing product quality.

[0064] It should be noted that, in the display substrate, the routing directions of the first routing line 200 and the second routing line 300 may be substantially parallel or cross each other.

[0065] As some exemplary embodiments, at a first position on the display substrate, at least part of the first routing line 200 and at least part of the second routing line 300 are roughly parallel in routing direction, a first gap A1 is provided between at least part of the two adjacent first routing lines 200, and a second gap A2 is provided between at least part of the two adjacent second routing lines 300, the orthographic projections of the first gap A1 and the second gap A2 on the base substrate 100 at least partially overlap, and the step difference compensation pattern 400 is provided at a position corresponding to the first gap A1 so as to at least partially overlap with the first gap A1.

[0066] In the above scheme, at the first position, the first routing line 200 is roughly parallel to the routing direction of at least part of the line segments of at least part of the second routing line 300. If the step compensation pattern 400 is not provided, a groove will be formed at the first gap A1 between two adjacent first routing lines 200. Since the second gap A2 between two adjacent second routing lines 300 corresponds to the position of the first gap A1, when the conductive material remains in the groove, the two adjacent second routing lines 300 will be turned on, thereby causing a short circuit between the two adjacent second routing lines 300 for transmitting different signals. Therefore, by providing the step compensation pattern 400 at the position corresponding to the first gap A1 between two adjacent first routing lines 200, the formation of the groove can be avoided, and the conductive material can be avoided from remaining in the groove, thereby avoiding a short circuit between the two adjacent second routing lines 300 for transmitting different signals.

[0067] As other exemplary embodiments, at a second position on the display substrate, at least part of the first routing line 200 and at least part of the second routing line 300 have intersecting routing directions of at least part of the line segments, a first gap A1 is provided between at least part of the two adjacent first routing lines 200, and a second gap A2 is provided between at least part of the two adjacent second routing lines 300, the orthographic projections of the first gap A1 and the second gap A2 on the base substrate 100 at least partially overlap, and the step difference compensation pattern 400 is provided at a position corresponding to the first gap A1 so as to at least partially overlap with the first gap A1.

[0068] In the above scheme, at the second position, the first routing line 200 intersects with at least part of the routing direction of at least part of the second routing line 300. If the step compensation pattern 400 is not provided, a groove will be formed at the first gap A1 between two adjacent first routing lines 200. Since the second gap A2 between two adjacent second routing lines 300 corresponds to the position of the first gap A1, when the conductive material remains in the groove, the two adjacent second routing lines 300 will be turned on, thereby causing a short circuit between the two adjacent second routing lines 300 for transmitting different signals. Therefore, by providing the step compensation pattern 400 at the position corresponding to the first gap A1 between two adjacent first routing lines 200, the formation of the groove can be avoided, and the conductive material can be avoided from remaining in the groove, thereby avoiding a short circuit between the two adjacent second routing lines 300 for transmitting different signals.

[0069] It should be noted that the above-mentioned first position can be, according to the product wiring layout, any suitable position on the display substrate where the first wiring 200 and the second wiring 300 are in different layers and are arranged roughly in parallel; the above-mentioned second position can be, according to the product wiring layout, any suitable position on the display substrate where the first wiring 200 and the second wiring 300 are in different layers and are arranged roughly crosswise, and is not limited.

[0070] In addition, as some exemplary embodiments of the present disclosure, the display substrate includes: at least one gate metal layer GATE and at least one source-drain metal layer SD, the gate metal layer GATE includes a plurality of gate metal lines, and the source-drain metal layer SD includes a plurality of source-drain metal lines; wherein at least a portion of the first routing 200 includes the gate metal line, and at least a portion of the second routing 300 includes the source-drain metal line.

[0071] In the above solution, at least part of the first wiring 200 is a gate metal line on the gate metal layer GATE, and at least part of the second wiring 300 is a source-drain metal layer SD on the source-drain metal layer SD. By correspondingly arranging the step difference compensation pattern 400 at the position between two adjacent gate metal lines, a short circuit between the two adjacent source-drain metal lines can be avoided. It can be understood that in practical applications, the first wiring 200 is not limited to the gate metal line, and the second wiring 300 is not limited to the source-drain metal line.

[0072] As an exemplary embodiment, Figure 1 As shown, the display substrate includes: at least two layers of the gate metal layer GATE, a second insulating layer 600 is arranged between adjacent gate metal layers GATE, at least part of the first routing 200 includes gate metal lines respectively located on different gate metal layers GATE, wherein at least part of the two gate metal lines of different layers and adjacent to each other have the first gap A1 between their orthographic projections on the base substrate 100, and at least part of the step difference compensation pattern 400 has its orthographic projection on the base substrate 100 located between the two gate metal lines of different layers and adjacent to each other.

[0073] For example, at least two gate metal layers GATE may include a first gate metal layer Gate1 and a second gate metal layer Gate2, wherein the first gate metal layer Gate1 is located on a side of the second gate metal layer Gate2 close to the substrate 100, the second insulating layer 600 is conformally covered on a side of the first gate metal layer Gate1 away from the substrate 100, the second gate metal layer Gate2 is located on a side of the second insulating layer 600 away from the substrate 100, and when the first gate metal line on the first gate metal layer Gate1 and the second gate metal line on the second gate metal layer Gate2 are arranged adjacent to each other, the surface of the first insulating layer 500 facing away from the substrate 100 is conformally covered on the second insulating layer 600 and the second gate metal layer Gate2.

[0074] Since a first gap A1 is formed between the adjacent first gate metal line and the second gate metal line, the step compensation pattern 400 is set at a position corresponding to the first gap A1, which can avoid the formation of a deeper groove in the first insulating layer 500 corresponding to the first gap A1 between the first gate metal line and the second gate metal line, thereby preventing a short circuit between two adjacent source-drain metal lines located on the source-drain metal layer SD.

[0075] As an exemplary embodiment, at least two gate metal layers GATE may include a first gate metal layer Gate1 and a second gate metal layer Gate2, and the first routing 200 may include a first gate metal line located on the first gate metal layer Gate1 and a second gate metal line located on the second gate metal layer Gate2.

[0076] As another exemplary embodiment, the at least two gate metal layers GATE may also include a first gate metal layer Gate1, a second gate metal layer Gate2 and a third gate metal layer Gate3, and the first routing 200 may include a first gate metal line located on the first gate metal layer Gate1, a second gate metal line located on the second gate metal layer Gate2 and a third gate metal line located on the third gate metal layer Gate3.

[0077] In addition, as an exemplary embodiment, the step compensation pattern 400 has a first thickness in a direction perpendicular to the base substrate 100, and the first thickness is 1 to 2.5 μm; the step compensation pattern 400 has a first width in a line width direction of the first trace 200, and the first width is 0.5 to 3.2 μm.

[0078] By adopting the above scheme, based on the above analysis, it can be known that the step compensation pattern 400 is mainly used to compensate for the step difference at the first gap A1 between two adjacent first wirings 200, so as to avoid the second insulating layer 600 from forming a deeper groove in the area corresponding to the first gap A1. The first thickness of the step compensation pattern 400 in the direction perpendicular to the base substrate 100 can range from 1 to 2.5 μm, and the first width in the line width direction of the first wiring 200 can range from 0.5 to 3.2 μm, so as to ensure that the interlayer dielectric layer ILD at the first gap A1 can form a small protrusion or a smaller groove with a depth of less than 0.5 μm.

[0079] The specific numerical values ​​of the first thickness and the first width of the step compensation pattern 400 may be reasonably selected in combination with parameters such as the thickness of each film layer in an actual product and the width of the first gap A1 between the first traces 200 .

[0080] For example, in the case where the display substrate includes at least two layers of the gate metal layer GATE, as shown in the figure, the first insulating layer 500 is conformally covered on a gate metal layer GATE (for example, the first gate metal layer Gate1) close to the side of the base substrate 100, and the second insulating layer 600 is conformally covered on the uppermost gate metal layer GATE (for example, the second gate metal layer Gate2 farthest from the base substrate 100). If the step difference compensation pattern 400 is not provided at the first gap A1 corresponding to two adjacent gate metal lines in different layers, the second gate metal layer Gate2 and the first insulating layer 500 will have a first step difference between the surface of the side away from the base substrate 100, and therefore, the first thickness of the step difference compensation pattern 400 may be such that the difference with the first step difference is within a threshold.

[0081] The specific value of the threshold value must satisfy the requirement that when the second insulating layer 600 forms a concave-convex structure (such as a small groove or a small protrusion) at the position corresponding to the first gap A1, material will not remain in the concave-convex structure when the second trace 300 is patterned. For example, the threshold value can be 0 in theory.

[0082] It should be understood that the threshold value here can be 0, specifically, including a range of variation of less than or equal to 10% of the value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, less than or equal to ±0.05%.

[0083] In some exemplary embodiments, the display substrate includes a bottom shading layer (BSM), which is located between the film layer where the first wiring 200 is located and the base substrate 100, wherein the step compensation pattern 400 is in the same layer and has the same material as the pattern of the bottom shading layer.

[0084] By adopting the above scheme, the step compensation pattern 400 is formed directly by the same patterning process when the pattern of the bottom light shielding layer is formed, and no additional patterning process is required, and the process steps are not increased. The film thickness of the bottom light shielding layer is generally 1 to 2.5 μm, which can meet the step compensation requirements. Of course, it is understandable that the step compensation pattern 400 can also be a separately set film layer pattern, or it can be set in the same layer as other film layers in the display substrate.

[0085] In addition, theoretically, in the line width direction of the first routing line 200, when the orthographic projection of the step difference compensation pattern 400 on the base substrate 100 is exactly the same as or close to the width of the corresponding first gap A1, it can be ensured that the second insulating layer 600 on the side away from the base substrate 100 is roughly in the same plane as the surface of the area corresponding to the first gap A1 and the area corresponding to the first routing line 200.

[0086] However, considering the actual process accuracy and actual wiring conditions, in practice, the orthographic projection of the step compensation pattern 400 on the base substrate 100 may be the same as or different from the width of the first gap A1.

[0087] Specifically, as an exemplary embodiment, Figure 1 As shown, when the width of the first gap A1 is small, in the line width direction of the first line 200, the level difference compensation pattern 400 and the orthographic projection of the first line 200 adjacent thereto on the base substrate 100 at least partially overlap to form an overlapping area. The first insulating layer 500 conformally covers the side of the first line 200 away from the base substrate 100, and forms a first area 510 at a position corresponding to the level difference compensation pattern 400, and forms a second area 520 at a position corresponding to the overlapping area, the second area 520 protrudes in a direction away from the base substrate 100 relative to the first area 510, and the level difference between the first area 510 and the second area 520 on the side surface away from the base substrate 100 is within a threshold.

[0088] In other words, see Figure 1As shown, the first insulating layer 500 conformally covers the overlapping area and forms a small protrusion at a position corresponding to the overlapping area on the surface of the side away from the substrate 100, and the protrusion height of the small protrusion is less than or equal to a threshold value to avoid residual conductive material in the area between two adjacent small protrusions.

[0089] It should be noted that the specific value of the threshold value must satisfy the requirement that when the second insulating layer 600 forms a small protrusion at the position corresponding to the first gap A1, the material will not remain in the area between two adjacent small protrusions when the second wiring 300 is patterned. For example, the threshold value can be 0 in theory. It should be understood that the value of the threshold value here can be 0, specifically including a range of variation of less than or equal to 10% of the value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, less than or equal to ±0.05%.

[0090] In addition, it should be noted that the orthographic projections of the step compensation pattern 400 and the first routing line 200 adjacent thereto on the base substrate 100 at least partially overlap to form an overlapping area, wherein the orthographic projection of the step compensation pattern 400 on the base substrate 100 does not exceed the two first routing lines 200 adjacent to the step compensation pattern 400 in the line width direction of the first routing line 200. In other words, the width of the step compensation pattern 400 in the line width direction of the first routing line 200 should be less than a threshold value, which is the sum of the line widths of the two first routing lines 200 adjacent to the step compensation pattern 400 and the width of the first gap A1 between the two first routing lines 200.

[0091] As another exemplary embodiment, when the width of the first gap A1 is small, in the line width direction of the first routing line 200, the step compensation pattern 400 and the orthographic projection of the first routing line 200 adjacent thereto on the substrate 100 do not overlap; the first insulating layer 500 conformally covers the side of the first routing line 200 away from the substrate 100, and the first insulating layer 500 forms a first area 510 at a position corresponding to the step compensation pattern 400, and forms a third area 530 at a position corresponding to the first routing line 200; wherein the first area 510 and the third area 530 are in the same plane on the side surface facing away from the substrate 100.

[0092] In other words, a continuous and flat plane is formed on the surface of the second insulating layer 600 on the side away from the base substrate 100 at the position corresponding to the overlapping area and other positions, so as to prevent the conductive material from remaining.

[0093] As another exemplary embodiment, Figure 2 As shown, when the width of the first gap A1 is small, in the line width direction of the first routing line 200, the orthographic projections of the step compensation pattern 400 and the first routing line 200 adjacent thereto on the substrate 100 do not overlap; the first insulating layer 500 conformally covers the side of the first routing line 200 away from the substrate 100, and the first insulating layer 500 forms a first area 510 at a position corresponding to the step compensation pattern 400, and forms a third area 530 at a position corresponding to the first routing line 200; wherein the first area 510 is recessed relative to the third area 530 toward the substrate 100, and the step difference between the surface of the first area 510 and the surface of the third area 530 facing away from the substrate 100 is within a threshold.

[0094] In other words, a small groove is formed on the surface of the first insulating layer 500 away from the base substrate 100 at a position corresponding to the overlapping area, and the depression depth of the small groove is less than or equal to a threshold value to avoid residual conductive material in the small groove.

[0095] It should be noted that the specific value of the threshold value must satisfy the requirement that when the second insulating layer 600 forms a small groove corresponding to the position of the first gap A1, the material will not remain in the small groove when the second wiring 300 is patterned. For example, the threshold value can be 0 in theory. It should be understood that the value of the threshold value here can be 0, specifically including a range of variation of less than or equal to 10% of the value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, less than or equal to ±0.05%.

[0096] In addition, as described above, the first wiring 200 and the second wiring 300 can be arranged at the first position or the second position of the display substrate, and the first wiring 200 and the second wiring 300 can be arranged substantially in parallel or crosswise. The first position and the second position are explained in more detail below with reference to the full-screen display substrate as an example.

[0097] As an exemplary embodiment, Figure 3 As shown, the display area of ​​the display substrate includes a first display area AA1 and a second display area AA2, wherein the second display area AA2 is located at least on one side of the first display area AA1, for example, the second display area AA2 is arranged around the first display area AA1. The light transmittance of the first display area AA1 is greater than the light transmittance of the second display area AA2.

[0098] Herein, it is preferred that the transmittance of the first display area AA1 is greater than or equal to 15%. To ensure that the transmittance of the first display area AA1 is greater than 15%, even greater than 40%, or even higher, the transmittance of each functional film layer of the display substrate in this embodiment is greater than 80%, and even the transmittance of at least some functional film layers is greater than 90%.

[0099] According to the display substrate of the embodiment of the present invention, the transmittance of the first display area AA1 is greater than the transmittance of the second display area AA2, so that the display substrate can integrate a photosensitive component on the back of the first display area AA1, realizing under-screen integration of a photosensitive component of a camera, and at the same time, the first display area AA1 can display images, increase the display area of ​​the display panel, and realize a full-screen design of the display device. For example, the first display area AA1 can be a hole area.

[0100] The area between the second display area AA2 and the first display area AA1 includes a first transition area S11 and a second transition area S12 which are sequentially arranged along a direction from the first display area AA1 to the second display area AA2.

[0101] See also Figure 4 As shown, in order to avoid affecting the transmittance of the first display area AA1, some wiring needs to be designed to be wound around the first display area AA1. That is, the first transition area S11 can be an area where the wiring is arranged around the first display area AA1.

[0102] Among them, at least part of the first wiring 200, the second wiring 300 and the step compensation pattern 400 can be arranged in the first transition area S11. That is, in the first transition area S11 where the winding design is performed around the first display area AA1, the step compensation pattern 400 can be arranged at the position corresponding to the first gap A1 between two adjacent first wirings 200 to improve the display defects such as bright lines, dark lines and bright spots that appear near the hole area of ​​the full screen in the related art.

[0103] Specifically, as an exemplary embodiment, the display area of ​​the display substrate has a pixel array.

[0104] like Figures 3 to 5As shown, the display substrate further includes: a plurality of first signal lines 11 and a plurality of second signal lines 12 arranged in the second display area AA2 and extending in the row direction of the pixel array; a plurality of third signal lines 13 and a plurality of fourth signal lines 14 arranged in the second display area AA2 and extending in the column direction of the pixel array. For example, any one of the first signal lines 11 and the second signal lines 12 may be a driving signal line in the row direction for realizing display driving, such as a ground signal line GN, an EM control line, an S1 control line, an S3 control line, or a second initial voltage signal line Vinit2, etc. Any one of the third signal line 13 and the fourth signal line 14 may be a driving signal line in the column direction for realizing display driving, such as a data line Data, etc.

[0105] Among them, a first winding 21, a second winding 22, a third winding 23 and a fourth winding 24 are arranged in the first transition zone S11, the first winding 21 extends partially around the first display area AA1, and is connected to the corresponding first signal line 11; the second winding 22 extends partially around the first display area AA1, and is connected to the corresponding second signal line 12; the third winding 23 extends partially around the first display area AA1, and is connected to the corresponding third signal line 13; and the fourth winding 24 extends partially around the first display area AA1, and is connected to the corresponding fourth signal line 14.

[0106] In other words, any one of the first winding 21 and the second winding 22 can be a driving signal line in the row direction for transmitting display driving, such as a ground signal line GN, an EM control line, an S1 control line, an S3 control line, or a second initial voltage signal line Vinit2, etc. Any one of the third winding 23 and the fourth winding 24 can be a driving signal line in the column direction for realizing display driving, such as a data line Data, etc.

[0107] In which, at least part of the first routing 200 may include the first winding 21 and the second winding 22, at least part of the second routing 300 includes the third winding 23 and the fourth winding 24, and there is the first gap A1 between the first winding 21 and the second winding 22; the orthographic projection of the step difference compensation pattern 400 on the base substrate 100 is located between the adjacently arranged first winding 21 and the second winding 22, and at least partially overlaps with the first gap A1.

[0108] In the above scheme, since in the first transition zone S11 adjacent to the periphery of the first display area AA1, the routing along the row direction and the column direction of the pixel array are designed to be wound around the periphery of the first display area AA1, the number of routing arrangements in this area is large, and the space is limited, the wiring is relatively dense, and it is easy to produce the above-mentioned bright lines or dark lines or bright spots and other defects. Therefore, the step compensation pattern 400 can be set between the first winding 21 and the second winding 22 that transmit the drive signal in the row direction to avoid a short circuit between the third winding 23 and the fourth winding 24.

[0109] It should be noted that the first winding 21 and the second winding 22 may transmit the same driving signal or different driving signals, and the first winding 21 and the second winding 22 may be arranged in the same layer or in different layers. The third winding 23 and the fourth winding 24 may be arranged in the same layer.

[0110] As an exemplary embodiment, the first winding 21 can be set on the same layer on the first gate metal layer Gate1, and the second winding 22 can be set on the same layer on the second gate metal layer Gate2. The first winding 21 is used to transmit the driving signal on the GN line, the EM control line or the second initial voltage signal line Vinit2; the third winding 23 and the fourth winding 24 can be used to transmit data line Data signals on different pixels. For example, the third winding 23 is used to transmit the data line Data signal of the green pixel, and the fourth winding 24 is used to transmit the data line Data signal of the blue pixel.

[0111] By setting a corresponding step compensation pattern 400 at the first gap A1 between the adjacent first winding 21 and the second winding 22, a short circuit between the data line Data signal for transmitting the green pixel and the data line Data signal for transmitting the blue pixel can be avoided, thereby preventing the occurrence of dark lines along the pixel array row direction (X) around the first display area AA1.

[0112] However, it is understandable that the first winding 21 and the second winding 22 may also be arranged in the same layer, and the signals transmitted by the first winding 21, the second winding 22, the third winding 23, and the fourth winding 24 are not limited thereto.

[0113] Also, see Figures 3 to 5As shown, in some exemplary embodiments, a fifth winding 25 and a sixth winding 26 may be arranged in the first transition area S11, wherein the fifth winding 25 extends around a portion of the circumference of the first display area AA1 and is connected to the corresponding first signal line 11; the sixth winding 26 extends around a portion of the circumference of the first display area AA1 and is connected to the corresponding second signal line 12. That is, the fifth winding 25 and the sixth winding 26 may be used to transmit driving signals in the row direction, such as the ground signal line GN, the EM control line, the S1 control line, the S3 control line, or the second initial voltage signal line Vinit2.

[0114] In some embodiments, the fifth winding 25 and the sixth winding 26 can be arranged in a different layer from any one of the first winding 21 and the second winding 22, and the fifth winding 25 and the sixth winding 26 can be arranged in the same layer or in different layers. The orthographic projections of the fifth winding 25 and the sixth winding 26 on the base substrate 100 are located at the first gap A1 between the first winding 21 and the second winding 22. Taking the fifth winding 25 and the sixth winding 26 as an example of being arranged in different layers, the fifth winding 25 can be arranged on the first gate metal layer Gate1, and the sixth winding 26 can be arranged on the third gate metal layer Gate3.

[0115] In some exemplary embodiments of the present disclosure, the fifth winding 25 can be used to transmit signals on the ground signal line GN, the S1 control line, and the S3 control line; the sixth winding 26 can be used to transmit signals on the S1 control line and the S3 control line. However, this is not limited thereto.

[0116] In some exemplary embodiments of the present disclosure, Figure 3 , Figure 6 and Figure 7 As shown, arranged in the second transition zone S12 are:

[0117] A fifth signal line 15 and a sixth signal line 16 extending along a row direction of the pixel array;

[0118] a seventh signal line 17 and an eighth signal line 18 extending along a column direction of the pixel array;

[0119] Among them, at least part of the first routing line 200 includes the fifth signal line 15 and the sixth signal line 16, and at least part of the second routing line 300 includes the seventh signal line 17 and the eighth signal line 18; and there is the first gap A1 between the fifth signal line 15 and the sixth signal line 16; the orthographic projection of the step difference compensation pattern 400 on the base substrate 100 is located between the adjacently arranged fifth signal line 15 and the sixth signal line 16, and at least partially overlaps with the first gap A1.

[0120] In the above scheme, in the second transition area S12 adjacent to the second display area AA2, there is a boundary of the signal line used to transmit the driving signal in the row direction and the column direction in the second display area AA2. The number of wiring arrangements in this area is large, and the space is limited. The wiring is relatively dense, and it is also easy to produce the above-mentioned bright lines or dark lines or bright spots. Therefore, the step compensation pattern 400 can be set between the fifth signal line 15 that transmits the driving signal in the row direction and the sixth signal line 16 to avoid a short circuit between the seventh signal line 17 and the eighth signal line 18 extending along the column direction.

[0121] The fifth signal line 15 and the sixth signal line 16 may transmit different drive signals, and the fifth signal line 15 and the sixth signal line 16 may be arranged in the same layer or in different layers. The seventh signal line 17 and the eighth signal line 18 may be arranged in the same layer. The seventh signal line 17 and the eighth signal line 18 may also transmit different drive signals.

[0122] As an exemplary embodiment, the fifth signal line 15 and the sixth signal line 16 can be respectively arranged on the second gate metal layer Gate2 and the third gate metal layer Gate3, the fifth signal line 15 can be used to transmit the driving signal on the first initial voltage signal line Vinit1, and the sixth signal line 16 can be used to transmit the driving signal on the second initial voltage signal line Vinit2; the seventh signal line 17 and the eighth signal line 18 can be used to transmit the driving signal in the row direction, for example: the ground signal line GN, the EM control line, the S1 control line, the S3 control line or the second initial voltage signal line Vinit2, etc.

[0123] For example, the seventh signal line 17 may be used to transmit a driving signal on the EM control line, and the eighth signal line 18 may be used to transmit a driving signal on the S1 control line.

[0124] In addition, illustratively, a ninth signal line 9 arranged parallel to the seventh signal line 17 and the eighth signal line 18 may be included, and the ninth signal line 19 may be used to transmit a driving signal on the S3 control line.

[0125] By setting a corresponding step compensation pattern 400 at the first gap A1 between the adjacent fifth signal line 15 and sixth signal line 16, short circuits between signal lines extending along the column direction can be avoided, thereby preventing the occurrence of bright line phenomenon along the pixel array column direction (Y) around the first display area AA1.

[0126] It should be understood that the above is merely an exemplary description of the first routing line 200 and the second routing line 300 in the first transition zone and the second transition zone S12, and is not limited thereto in practical applications.

[0127] In addition, it should be noted that the first gap A1 may refer to a gap formed between any first wirings 200 in the same film layer, such as a gap formed between two adjacent first wirings 200 in the first gate metal layer Gate1; the first gap A1 may also refer to a gap formed between any first wirings 200 in different film layers, such as a gap formed between two adjacent first wirings 200 in the first gate metal layer Gate1, the second gate metal layer Gate2, the third gate metal layer Gate3 or the first source-drain metal layer SD1. Furthermore, there is no limitation on the specific material of the first wiring 200. In other words, the first gap A1 may also be a gap formed between any materials, such as a gap formed between wirings on any two of an inorganic film layer, an organic film layer or a metal film material.

[0128] The step compensation pattern 400 can be any inorganic material such as SiNx (silicon nitride), SiOx (silicon oxide), any one or a mixture of SiNx and SiOx, etc., or the step compensation pattern 400 can also be a metal material, such as Mo (molybdenum), Ti / Al / Ti (titanium metal / aluminum / titanium metal), etc.

[0129] In addition, the step compensation pattern 400 may be in a floating state, ie, not connected to any signal, or may be connected to a signal, such as a power supply voltage signal VDD.

[0130] In addition, the embodiments of the present disclosure further provide a display device, which includes the display substrate provided in the embodiments of the present disclosure. The display device includes but is not limited to devices with display functions such as smart phones, displays, laptops, tablet computers, electronic photo frames, driving recorders, smart wearable devices, etc. Other essential components of the display device (such as driver chips) should be understood by those of ordinary skill in the art, and will not be described in detail here, nor should they be used as limitations on the present disclosure. Since the principle of solving the problem by the display device is similar to the principle of solving the problem by the above-mentioned display substrate, the embodiment of the display device provided in the embodiments of the present disclosure can refer to the embodiment of the above-mentioned display substrate provided in the embodiments of the present disclosure, and will not be described in detail here.

[0131] There are a few points to note:

[0132] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

[0133] (2) For the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness of layers or regions is exaggerated or reduced, that is, these drawings are not drawn according to the actual scale. It is understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element or there may be intermediate elements.

[0134] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0135] The above are only specific implementations of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A display substrate, characterized in that: include: substrate substrate; A plurality of first routing lines, wherein the plurality of first routing lines are arranged in the same layer or in different layers, and an orthographic projection on the substrate between at least two adjacent first routing lines has a first gap; A plurality of second routing lines, wherein the film layer where the first routing lines are located is located on a side of the film layer where the second routing lines are located close to the base substrate, and a first insulating layer is provided between the film layer where the first routing lines are located and the film layer where the second routing lines are located; and A plurality of step compensation patterns, wherein the film layer where the plurality of step compensation patterns are located is located between the film layer where the first routing line is located and the base substrate, and the orthographic projection of the step compensation pattern on the base substrate is located between two adjacent first routing lines to at least partially overlap with the first gap.

2. The display substrate according to claim 1, characterized in that: The display substrate comprises: At least one gate metal layer and at least one source-drain metal layer, the gate metal layer includes a plurality of gate metal lines, and the source-drain metal layer includes a plurality of source-drain metal lines; wherein at least part of the first wiring includes the gate metal line, and at least part of the second wiring includes the source-drain metal line.

3. The display substrate according to claim 2, characterized in that: The display substrate comprises: There are at least two layers of gate metal layers, a second insulating layer is provided between adjacent gate metal layers, at least part of the first routing includes gate metal wires respectively located on different gate metal layers, wherein at least part of the two gate metal wires of different layers and adjacent to each other have the first gap between their orthographic projections on the substrate, and at least part of the orthographic projection of the step difference compensation pattern on the substrate is located between the two gate metal wires of different layers and adjacent to each other.

4. The display substrate according to claim 1, characterized in that: The step compensation pattern has a first thickness in a direction perpendicular to the base substrate, and the first thickness is 1 to 2.5 μm; The step compensation pattern has a first width in a line width direction of the first wiring, and the first width is 0.5-3.2 μm.

5. The display substrate according to claim 1, characterized in that: The display substrate comprises a bottom light shielding layer, and the bottom light shielding layer is located between the film layer where the first wiring is located and the base substrate, wherein the step compensation pattern is in the same layer and made of the same material as the pattern of the bottom light shielding layer.

6. The display substrate according to claim 1, characterized in that: In the line width direction of the first routing line, the step difference compensation pattern and the orthographic projection of the first routing line adjacent thereto on the substrate at least partially overlap to form an overlapping area; The first insulating layer conformally covers a side of the first routing line away from the substrate, and forms a first area at a position corresponding to the step compensation pattern, and forms a second area at a position corresponding to the overlapping area, the second area protrudes in a direction away from the substrate relative to the first area, and the step difference between the first area and the second area on a side surface away from the substrate is within a threshold.

7. The display substrate according to claim 1, characterized in that: In the line width direction of the first routing line, the step compensation pattern and the orthographic projection of the first routing line adjacent thereto on the substrate do not overlap; the first insulating layer conformally covers the side of the first routing line away from the substrate, and the first insulating layer forms a first area at a position corresponding to the step compensation pattern, and forms a third area at a position corresponding to the first routing line; wherein, The first area and the third area are located in the same plane on a side surface facing away from the substrate; Alternatively, the first region is recessed relative to the third region toward the substrate, and a step difference between a surface of the first region and a surface of the third region facing away from the substrate is within a threshold.

8. The display substrate according to claim 1, characterized in that: The display area of ​​the display substrate includes a first display area and a second display area, and the light transmittance of the first display area is greater than the light transmittance of the second display area; Wherein, the area between the second display area and the first display area includes a first transition area and a second transition area which are sequentially arranged along a direction from the first display area to the second display area; Among them, at least part of the first routing, the second routing and the step compensation pattern are arranged in the first transition area; and / or at least part of the first routing, the second routing and the step compensation pattern are arranged in the second transition area.

9. The display substrate according to claim 8, characterized in that: The display area of ​​the display substrate has a pixel array; The display substrate further comprises: a plurality of first signal lines and a plurality of second signal lines arranged in the second display area and extending along a row direction of the pixel array; a plurality of third signal lines and a plurality of fourth signal lines arranged in the second display area and extending along a column direction of the pixel array; Wherein, arranged in the first transition zone are: A first winding line extending around a portion of the circumference of the first display area, the first winding line being connected to the corresponding first signal line; a second winding extending around a portion of the circumference of the first display area, the second winding being connected to the corresponding second signal line; a third winding extending around a portion of the circumference of the first display area, the third winding being connected to the corresponding third signal line; a fourth winding extending around a portion of the circumference of the first display area, the fourth winding being connected to the corresponding fourth signal line; Among them, at least part of the first routing includes the first winding and the second winding, at least part of the second routing includes the third winding and the fourth winding, and there is the first gap between the first winding and the second winding; the orthographic projection of the step compensation pattern on the substrate is located between the adjacently arranged first winding and the second winding, and at least partially overlaps with the first gap.

10. The display substrate according to claim 8, characterized in that: The display area of ​​the display substrate has a pixel array; Arranged in the second transition zone are: a fifth signal line and a sixth signal line extending along a row direction of the pixel array; a seventh signal line and an eighth signal line extending along a column direction of the pixel array; Among them, at least part of the first routing includes the fifth signal line and the sixth signal line, and at least part of the second routing includes the seventh signal line and the eighth signal line; and there is the first gap between the fifth signal line and the sixth signal line; the orthographic projection of the step difference compensation pattern on the substrate is located between the adjacently arranged fifth signal line and the sixth signal line, and at least partially overlaps with the first gap.

11. A display device, characterized in that: The display substrate comprises the display substrate as claimed in any one of claims 1 to 10.

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