Phase-locked loop

Abstract

A phase-locked loop circuit (10) comprises an analog section (15), an integration section (17), and a voltage-controlled oscillator (19) configured to receive a first current signal from the analog section (15) and a second current signal from the integration section (17), and configured to output an output clock (fO). The integration section (17) is configured to receive first and second update signals (UP, DOWN) each having at least one state based on a phase difference between an input clock (fI) and an output clock (fO). The integration section (17) includes three integrator units (31) connected to each other to form a ring oscillator.

Description

[0001] A phase-locked loop (PLL) is a control system in which the output phase of a voltage-controlled oscillator (VCO) can be automatically synchronized ("locked") to the phase of a periodic input signal. The periodic input signal is often referred to as the input reference clock. PLLs can be used in a variety of applications, such as sensor applications, communications, etc. Summary of the invention

[0002] Concepts are being sought by which a PLL with reduced area and high performance can be provided.

[0003] It is an object of the invention to provide an improved phase locked loop. The above objects are achieved by the subject matter claimed in accordance with the independent claims. Further developments are defined in the dependent claims.

[0004] According to an embodiment, a phase-locked loop circuit includes an analog section, an integration section, and a voltage-controlled oscillator, the voltage-controlled oscillator being configured to receive a first current signal from the analog section and a second current signal from the integration section, and being configured to output an output clock. The integration section is configured to receive a first update signal and a second update signal, each of which has at least one state based on a phase difference between an input clock and an output clock, and the integration section includes three integrator units connected to each other to form a ring oscillator.

[0005] The term "analog portion" used in the present disclosure may refer to a portion of a phase-locked loop circuit that includes components that have been used in a classic analog PLL.

[0006] For example, each of the integrator cells may include a first digital input configured to receive a signal according to a phase difference between an input clock and an output clock.

[0007] The phase locked loop may further comprise a current generator electrically connected to at least one of the integrator cells. The current generator may form part of the integrating section.

[0008] The current generator may be configured to receive the first voltage signal from at least one of the integrator cells and to generate a first sub-signal of the second current signal, the first sub-signal being dependent on a phase difference between the input clock and the output clock.

[0009] According to an embodiment, each of the integrator units comprises a digital output connected to a second digital input of another of the integrator units. The digital output signal output by the digital output may indicate whether the first voltage signal output by the integrator unit is below a first predetermined value or above a first predetermined value.

[0010] For example, the phase-locked loop circuit may further include a counter. The digital output of at least one of the integrator units may further be connected to the counter.

[0011] As an example, when the digital output signal indicates that the first voltage signal changes to a value lower than the first predetermined value, the counter value of the counter may change in the first direction. For example, depending on the polarity of the transistors of the current generator used, when the digital output signal indicates that the first voltage signal changes to a value lower than the first predetermined value, the counter value may increase. For example, in the case where the current generator includes a pMOS transistor, the counter value may increase. When the current generator includes an nMOS transistor, the counter value may decrease.

[0012] In addition, when the digital output signal indicates that the first voltage signal changes to a value higher than the first predetermined value, the counter value of the counter may change in a second direction opposite to the first direction. For example, when the current generator includes a pMOS transistor, the counter value may decrease. When the current generator includes an nMOS transistor, the counter value may increase.

[0013] According to another embodiment, the digital output of the first integrator unit in the integrator unit is connected to a counter, and when the digital output signal indicates that the first voltage signal changes to a value higher than the first predetermined value, the counter value of the counter changes in the first direction. In a similar manner to that already discussed above, depending on the polarity of the transistors of the current generator used, when the digital output signal indicates that the first voltage signal changes to a value lower than the first predetermined value, the counter value may increase. For example, in the case where the current generator includes a pMOS transistor, the counter value may increase. When the current generator includes an nMOS transistor, the counter value may decrease.

[0014] The current generator may also be configured to receive the counter signal from the counter and to generate a second sub-signal of the second current signal, the first sub-signal and the second sub-signal being added. Thus, the current generator may function as a digital-to-analog converter (DAC).

[0015] For example, the current generator may be configured to generate a constant current when the phase difference is zero.

[0016] Each of the integrator units may be configured to receive a digital output signal output from another of the integrator units, and to set the level of the output voltage to a second predetermined value when the digital output signal indicates that the output voltage of another of the integrator units changes to a value lower than the first predetermined value.

[0017] For example, each of the integrator units may be operable in a first oscillation mode or a second oscillation mode. In the first oscillation mode, the output voltage of the integrator unit may drop from a second predetermined value to ground, and in the second oscillation mode, the output voltage of the integrator unit may rise from ground to a second predetermined value.

[0018] For example, the oscillation mode can be selected based on the detection result of the phase difference between the input clock and the output clock. As an example, when the output clock lags behind the input clock, the first oscillation mode can be selected, and when the output clock leads the input clock, the second oscillation mode can be selected, or vice versa.

[0019] The integrated circuit may include the phase-locked loop circuit described above.

[0020] The electronic device may include the phase-locked loop circuit described above.

[0021] For example, the electronic device may be selected from sensors, ambient light sensors, time of flight sensors, biomedical applications, or electronic devices for automotive applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings are included to provide a further understanding of embodiments of the present invention and are incorporated into and constitute a part of this specification. The accompanying drawings illustrate embodiments of the present invention and are used together with the specification to illustrate the principles. Other embodiments of the present invention and many expected advantages will be readily understood as they become better understood by reference to the following detailed description. The elements of the accompanying drawings are not necessarily to scale with respect to each other. Like reference numerals designate corresponding like parts.

[0023] Figure 1 is a schematic diagram showing a phase locked loop according to an embodiment.

[0024] Figure 2 The components of the integrating section are shown in more detail.

[0025] Figure 3A Shown are waveforms generated by components of a phase locked loop according to an embodiment.

[0026] Figure 3B The waveform of the current characteristics is shown in more detail.

[0027] Figure 4 Components of a phase locked loop according to another embodiment are shown.

[0028] Figure 5A A schematic diagram of an integrated circuit according to an embodiment is shown.

[0029] Figure 5B A schematic diagram of an electronic device according to an embodiment is shown. DETAILED DESCRIPTION

[0030] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which are shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terms, such as "top", "bottom", "front", "rear", "over", "on", "above", "leading", "trailing", etc., are used with reference to the orientation of the drawings being described. Because components of embodiments of the present invention may be positioned in a number of different orientations, the directional terms are used for illustrative purposes and are in no way limiting. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope defined in the claims.

[0031] The description of the embodiments is not restrictive. In particular, elements of the embodiments described below may be combined with elements of different embodiments.

[0032] As used in this specification, the terms "coupled" and / or "electrically coupled" are not meant to imply that elements must be directly coupled together - intermediate elements may be provided between "coupled" or "electrically coupled" elements. The term "electrically connected" is intended to describe a low-ohmic electrical connection between elements that are electrically connected together.

[0033] As used herein, the terms "having", "containing", "including", "comprising" and the like are open-ended terms that indicate the presence of stated elements or features, but do not exclude additional elements or features. The articles "a", "an" and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

[0034] Figure 1 1 is a schematic diagram showing a general configuration of a PLL 10 according to an embodiment. The PLL 10 includes a phase detector 13, an analog section 15, and an integration section 17. The phase detector 13 receives an input clock f I and the feedback signal f F For example, the feedback signal f F The output clock f outputted by the voltage controlled oscillator (VCO) 19 may correspond to O According to another implementation, as will be described below, the feedback signal f F Can be the output clock f O score.

[0035] The phase detector 13 generates a phase signal according to the input clock f IWith the feedback signal f f The output signal of the phase detector 13 is provided to the analog section 15 and the integral section 17. The analog section 15 may include a loop filter 23 and a charge pump 21. The charge pump 21 may be constructed in a generally known manner. For example, the loop filter 23 may include a first capacitor 25, a second capacitor 27 and a resistor 28.

[0036] VCO 19 receives the first current signal from analog section 15 and the second current signal from integration section 17. Generally, the total gain K of the VCO is VCO is divided into proportional gain K P and the integral gain K provided by the integral unit 17 I The integrator 17 can set the operating point (eg, the current for the VCO) and can be responsible for coarse tuning, while the analog section 15 is responsible for fine tuning. By adding the integrator 17, the analog section 15 can have a lower gain K P , which in turn allows for a smaller loop filter capacitor and therefore a smaller area. The integrator 17 is designed to maintain a low VCO gain K I while providing sufficient current to VCO 19. In this way, the VCO gain K VCO can be set so that the desired frequency can be achieved.

[0037] The VCO 19 may be a current starved ring voltage controlled oscillator. The VCO 19 may also be implemented differently, for example as an LC oscillator (LC VCO). In the case of an LC VCO, the voltage controls the frequency. For example, the VCO 19 may be configured to receive a current signal and generate a frequency signal (output clock f O ), the frequency signal has a frequency that depends on the bias current.

[0038] The feedback loop converts the output clock f generated by VCO 19 into O is coupled to the phase detector 13 via an optional feedback divider 18. The input clock f I is also applied to the frequency detector 13. The feedback divider 18 can generate the feedback signal f F , the feedback signal f F The frequency of the output clock f O The feedback signal f F and input clock f I is input to the phase detector 13 .

[0039] The phase detector 13 may be operable to generate a feedback signal f indicative of F With input clock f IThe difference between the first error signal UP and the second error signal DOWN. The first error signal UP indicates the feedback signal f F Is it lagging behind the input clock f I and the degree of hysteresis, and the second error signal DOWN indicates the feedback signal f F Is it ahead of the input clock f I And to what extent.

[0040] For example, the PLL may be a low bandwidth PLL, which may mean that the bandwidth of the PLL may be in the range of 1 / 10 of the input clock frequency.

[0041] Figure 2 The components of the integrator 17 are shown in more detail. The integrator 17 generates a current I OUT , the current I OUT The PLL further includes a current generator 41, which includes, for example, three analog cells 43, each of which is electrically connected to a corresponding one of the integrator cells 31.

[0042] The charge pump 46 is configured to receive the UP and DOWN pulses input from the phase detector 13. The time delay between the pulses indicates the phase error. The charge pump 46 may include a current mirror. The voltage P bias and N bias are the voltages generated by the current mirror of the charge pump 46. These voltages are used for the integrator unit 31 i The receiving transistor M P1 、M N1 Therefore, the flow through M P1 and M N1 The current is the mirror current of the charge pump 46. This current is used to connect the capacitor C I The voltage V C In this way, V C Controlled by the PLL phase error. Voltage V C The control transistor 413 is connected to the analog portion of the corresponding analog cell 43 for the current generator 41. Therefore, the voltage V C is converted into a current I output by the current generator 41 out Therefore, the phase error controls the current of the integrating portion 17 .

[0043] like Figure 2As shown, each of the analog units 43 of the current generator 41 may include a current mirror that can determine the current of the current bias transistor 411. The current bias transistor 411 for the analog part is connected in series with the control transistor 413 for the analog part. The gate electrode of the control transistor 413 is connected to V C .

[0044] The current generator 41 may further include a digital unit 45. The number M of the digital units 45 may correspond to the number of DAC (current generator) bits. The digital unit 45 includes a current bias transistor 412 for the digital portion, which is connected in series with a control transistor (switch) 414 for the digital portion. In addition, the gate electrode of the control transistor 414 is connected to the counter 42. Therefore, the maximum current flowing through the control transistor 413 or the control transistor 414 is determined by the current generated in the current mirror, and can be controlled by the gate voltage applied to the gate electrode of the control transistor 413 for the analog portion and the control transistor 414 for the digital portion, respectively.

[0045] As will be explained below, due to Figure 2 In the particular arrangement shown in , the current generator 41 can be configured to generate a current having an analog portion and a digital portion. The current of the digital portion may be higher than the analog portion, but it is not directly proportional to the phase error. In more detail, the current of the digital portion is controlled by a digital counter 42. Therefore, there may be no VCO gain or VCO gain K for this portion. I Probably low.

[0046] The current of the analog part can be low and is proportional to the phase error. Therefore, for the current of the analog part, there is a VCO gain K I According to a specific configuration, the analog unit 43 of the current generator comprises a current mirror which is controlled by the integrator core to generate a current of the analog part which depends on the phase error. The digital unit 45 of the current generator 41 also comprises a current mirror which is controlled by the decoder 42 to generate a current of the digital part. Figure 3A As discussed, the current of the digital part can be several times higher than the current of the analog part. In this way, a sufficiently high current can be generated to reach the operating point of the VCO 19. In particular, there can be a low VCO gain K of the integral part I , while achieving enough current to reach the operating point of the VCO. The achieved current is stable with respect to variations in process, voltage and temperature (PVT).

[0047] As further shown, the integration core includes three integrator cells 311, 312 and 313. At least three cells 311, 312 and 313 are used to provide a cell-sustaining oscillation. The cell-sustaining oscillator set by the three integrator cells is controlled by the phase error (e.g., by UP and DOWN pulses) and has two oscillation modes. Depending on the polarity of the phase error, the integrator core oscillates, for example, from VDD to GND or from GND to VDD. The polarity depends on whether UP is the leading edge or DOWN is the leading edge.

[0048] Integrator unit 31 I Each of the first digital input 32 and the second digital input 33 includes a first digital input 32 and a second digital input 33. For example, the first digital input 32 can be configured to receive a clock signal according to the input clock and the output clock f O Or feedback signal f F The phase difference between the signals.

[0049] Each of the integrator cells 31 may include a digital output 34 connected to a second digital input 33 of another of the integrator cells. Thus, each of the integrator cells controls another of the integrator cells. For example, the digital output 34 of the integrator cell 310 is connected to the second input 33 of the third integrator cell 312. The digital output 34 of the integrator cell 311 is connected to the second digital input 33 of the first integrator cell 310, and the digital output 34 of the third integrator cell 312 is connected to the second digital input 33 of the second integrator cell 311. Thus, the integrator cell 310 controls the integrator cell 312. The integrator cell 311 controls the integrator cell 310, and the integrator cell 312 controls the integrator cell 311. Thus, the integrator cells are connected as a ring.

[0050] According to the signals input to the first digital input and the second digital input, the voltage V C can be precharged to V DD or GND. As will be explained later, since all integrator units 31 I is used many times during operation, so precharging is required to ensure that the integrator unit 31 I rotation.

[0051] For example, the integrator 17 may further include a direction detector 44 that outputs a digital signal DIR based on the UP and DOWN signals. The direction detector 44 may detect a leading edge, such as which edge is leading, UP or DOWN, and set the DIR signal accordingly. For example, if DOWN is at a high level (i.e., the feedback signal f F Leading the input clock f I), the signal output by the direction detector 44 is set to a high level. If DOWN is at a low level (ie, the feedback signal f F Lagging behind the input clock f I ), the signal output by the direction detector 44 is at a low level. The signal DIR output by the direction detector 44 is fed to the first digital input of each of the integrator units 311. As will be explained below, the integrator unit 311 is selected according to the DIR level. i The oscillator mode.

[0052] The digital output signal output by the digital output 34 may indicate the i The first voltage signal V C is lower than or higher than a first predetermined value, the first predetermined value being, for example, VDD / 2. For example, as long as the voltage V output by the integrator unit 31 is C The digital outputs 34 of the integrator units are connected to a counter 42. For example, at each falling edge of the output signal output by the digital output 34, the counter 42 is increased. In addition, at each rising edge of the output signal output by the digital output 34, the counter 42 is decreased. Therefore, the counter 42 is implemented as an up / down counter.

[0053] like Figure 2 As further shown in FIG. 1 , each of the integrator units 311 may include a voltage signal P respectively output by the charge pump 46. bias and N bias Controlled receiving transistor M P1 and M N1 . Receiving transistor M P1 The source terminal of the receiving transistor M can be connected to VDD. N1 The source terminal of the receiving transistor M can be connected to GND. N1 and M P1 The drain terminal can be connected to the output voltage V C Output node 36.

[0054] The integrator unit may further include a second transistor M P2 and M N2 . Transistor M P2 The gate terminal of transistor M can be connected to a NOR circuit connected to the first digital input 32 and the second digital input 33. P2 The source terminal of transistor M can be connected to VDD. N2The gate terminal of transistor M can be connected to an AND circuit whose inputs are connected to the first digital input 32 and the second digital input 33. N2 The source terminal of the second transistor M is connected to the ground. N2 and M P2 The drain terminal of can be connected to node 36. Node 36 is connected to the supply voltage V C Node 36 is also connected to the digital output 34.

[0055] Figure 3A 1 shows various waveforms that may be generated during the operation of the PLL described above. In particular, as shown in graph a), from time t1 to t5, the first error signal UP is at a high level, while the second error signal DOWN is at a low level. This means that there is a phase error, and the feedback signal f F Lagging behind the input clock f I In the time between t5 and t6, both the error signals UP and DOWN are at a low level, indicating that there is no phase error and the system is in a locked state. In addition, between t6 and t11, the second error signal DOWN is at a high level, which means that the feedback signal f F Leading the input clock f I .

[0056] The upper part of the graph i) shows the output current Iout of the current generator 41. The dashed line indicates the digital part of the generated current. The lower part of the graph i) shows the analog part of the current. The current controlled by the control transistor 414 for the digital part (and therefore the counter 42) is referred to as the current of the digital part, while the current controlled by the control transistor 413 for the analog part (and therefore the voltage V corresponding to the phase error) is referred to as the current of the digital part. C ) is called the current of the analog part.

[0057] Graph b) shows the output signal DIR of the direction detector 44. When the second error signal DOWN is at a high level and the feedback signal f F Leading the input clock f I , the output signal of the direction detector 44 is set to a high level. When the direction detector 44 outputs a signal at a low level, the integrator units 310, ... 312 are precharged to VDD. When the direction detector 44 outputs a signal at a high level, the integrator units 310, ... 312 are precharged to GND.

[0058] Figure 3A The curve diagram c) shows the voltage V of the first integrator unit 310 C [0] behavior. During the time from t0 to t1, the voltage V C[0] decreases. Therefore, the current through the control transistor 413 of the analog section of the corresponding analog unit 43 for the current generator 41 increases. Due to the presence of the current mirror in the current generator 41, the maximum current flowing through the control transistor 413 is limited by the current source 415. At t1, the voltage V C [0] reaches a first predetermined value, for example VDD / 2. At this point, the current through the control transistor 413 for the analog section has reached a maximum. The first integrator unit enters the digital mode. Until t1, the first integrator unit 310 is in the analog mode. When in the digital mode, the integrator unit 311 provides the same amount of current as the digital generator 41. Therefore, the current bias transistors 411 and 412 can have the same size. As also shown in graph f), when V C [0] When a first predetermined value (eg VDD / 2) is reached, the output signal at the digital output 34 is set low.

[0059] At each falling edge of the signal D[0], D[1] or D[2] output at the digital output 34, the value of the counter 42 is increased. Therefore, the current generator 41 increases the digital current controlled by the control transistor 414 for the digital part. The current amounts generated by the control transistor 413 for the analog part and the control transistor 414 for the digital part are added and output as the output current I OUT The output is sent to the VCO 19. Therefore, the current generator 41 can be used as a digital-to-analog converter.

[0060] The signal D[0] generated by the first integrator unit 310 is output to the third integrator unit 312. Therefore, the voltage V generated in the third integrator unit 312 is C [2] is pulled up to VDD. Therefore, the signal D[2] output by the third integrator unit 312 to the second integrator unit 311 is set to a high level. In other words, as long as D[0] is in a low state, the integrator unit 312 is turned off, which means that no current flows through the control transistor 413 of the analog part of the corresponding analog unit 43 of the current generator 41. In addition, setting D[2] high turns on the second integrator unit 311, which has been precharged to VDD. Now, the second integrator unit 311 is in an effective analog mode and generates a current of the analog part between t1 and t2. In a manner similar to that discussed with reference to the first integrator unit 310 at the time between t0 and t1, the voltage V C [1] decreases. When the voltage V C When V[1] reaches a first predetermined value (e.g., VDD / 2), the output D[1] is pulled low, the counter is incremented, and the digital current generated by the current generator is increased by 1 bit. Therefore, at t2, the second integrator unit 311 is in digital mode. At the same time, VC [0] and D[0] are set to HIGH or VDD, respectively, and as long as D[1] is low, the first integrator unit 310 will be turned off. At t2, since the first integrator unit 310 controls the third integrator unit 312 and D[0] is HIGH, the third integrator unit 312 enters the active analog mode, such as generating the current of the analog part. Similarly, when V C [2] (i.e., the voltage generated in the third integrator unit 312) reaches a first predetermined value (e.g., VDD / 2), the third integrator unit 312 is in digital mode. In this case, D[2] is pulled low, the counter is incremented, and the digital current of the current generator is increased by 1 bit. Now, the second integrator unit is turned off and the voltage is pulled to VDD, the first integrator unit 310 is in active analog mode, and the entire process is repeated as described.

[0061] This process continues as long as the phase error exists. In other words, the unit is rotating while the phase error exists. Once the first error signal UP and the second error signal DOWN have the same logic level, this indicates that the PLL is locked. In this case, Figure 3A As shown in the timing in the graphs i) and a), for example between t5 and t6, the process stops and the current generator provides a constant current.

[0062] As already described, during operation, i.e. as long as the first error signal and the second error signal have different logic levels, one of the integrator units is in the active analog mode, another of the integrator units is in the digital mode, and the third of the integrator units is in the shutdown mode. The integrator unit in the shutdown mode is precharged to a second voltage value, e.g. VDD, and is ready for use in the next cycle.

[0063] The timing from t6 to t11 shows the situation where the first error signal UP is low and the second error signal DOWN is high. The direction detector 44 sets the signal DIR to high. According to an embodiment, the direction detector 44 may include a time hysteresis to avoid possible ringing on the DIR output signal. Due to this setting of DIR, the integrator units 310 to 312 are pre-charged to GND.

[0064] When any of the integrator units is active in analog mode, the output voltage V CFrom GND to VDD. When the voltage reaches a first predetermined value (e.g. VDD / 2), the digital output signal D output via the digital output 34 is set to a high level. On the rising edge of the signal D, the counter decreases the counter value. In a similar manner to that already discussed above, the first integrator unit 310 controls the third integrator unit 312, the second integrator unit 311 controls the first integrator unit 310, and the third integrator 312 controls the second integrator unit 311. As long as DIR is HIGH, the integrator units are first fully turned on, and then enter digital mode, and finally enter analog mode.

[0065] As already described, there are two oscillation modes, depending on whether the first error signal UP and the second error signal DOWN indicate that the feedback signal lags behind the input clock or leads the input clock. C From a second predetermined value (eg, VDD) down to GND or from GND up to a second predetermined value, eg, VDD.

[0066] Due to the combination of the above described integrating section 17 and the analog section 15 comprising, for example, two transistors 25, 27 and one resistor 28, the PLL is more robust than known devices. In particular, due to the presence of the analog section 15, there is no strict requirement for current matching in the current generator, since the analog section always has some gain providing current to the VCO. This gain is sufficient to cover possible current mismatches from the current generator.

[0067] Figure 3B Examples of current signals output by the current generator at different timings are shown. Figure 3B The current signal shown is Figure 3A The graph i) shown in FIG. 1 is an enlarged view of the graph i), so a detailed description thereof is omitted. Due to the presence of the digital portion of the current IOUT, the current can have a large value. Due to the large value of the current, even if the phase difference is indicated and the output clock f is determined O The current value of the digital part is relatively low, and the operating point of the VCO 19 can also be reached. In particular, due to the existence of the current of the digital part, the gain of the VCO 19 can be set to a relatively low value. Therefore, for example Figure 1 The capacitor 25 shown in FIG. 1 can be small. Thus, the space requirement is reduced.

[0068] Figure 4 The integrator 17 of a PLL according to another embodiment is shown. Figure 4 The integrator 17 shown includes Figure 2 The components are similar to the integrator 17 shown in FIG. Figure 2Unlike the integral part shown, only the first integrator unit 310 is connected to the current generator 41. Therefore, only the first integrator unit 310 is used to control the current of the analog part. Therefore, the current generated by the current generator 41 changes only on the rising edge of D[0] output by the first integrator unit 310. The current generator 41 may include only one analog unit 43 and a plurality of digital units 45. Each of the digital units 45 may include a current bias transistor 412 for the digital part and a control transistor 414 for the digital part. The number M of digital units may correspond to the number of bits of the DAC. The analog unit 43 may be in analog mode or shutdown mode.

[0069] When DIR is low, transistor 416 is off. Transistor 416 corresponds to an enable sink transistor, which can achieve the sinking of analog current. When DIR is low, transistor 417 is turned on. Transistor 417 is an enable source transistor, which can achieve the source of analog current. Therefore, the current is pushed to pin IOUT, and as long as there is a phase difference (for example, UP is high and DOWN is low), the total current will rise. Control voltage V C [0] The control source transistor 421 is controlled and in this way the amount of current that will be pushed to IOUT is controlled. Figure 2 In a similar manner as described above, the maximum current is limited by transistor 419. When the DIR signal is high, the sink transistor 416 is enabled to turn on and the source transistor 417 is enabled to turn off, which means that the analog current is pulled out from the node IOUT. This results in a reduction in current. In the same manner as described above, the signal V C [0] Controlling transistor 418 reduces the current through the transistor and thereby reduces the current through IOUT. Transistors 419, Mb2, Mb3, and 410 can be adjusted to cause the same amount of current to flow through 419 and 410.

[0070] Figure 4 The integrator unit 31 shown i Can be similar to Figure 2 The integrator unit 31 shown i The capacitors 51, 52, and 53 may be arranged behind the node 36. The capacitances of the capacitors 52 and 53 may be significantly smaller than the capacitance of the capacitor 51 connected to the current generator 41. Therefore, the space of the integrating portion 17 may be reduced.

[0071] include Figure 4 The PLL of the integrator section 71 is shown to have a reduced area.

[0072] Figure 5AAn integrated circuit 1 according to an embodiment is shown. The integrated circuit 1 comprises the phase-locked loop circuit 10 already described above. Since the phase-locked loop circuit 10 has a reduced area, the integrated circuit 1 may be a SOIC (“Small Outline Integrated Circuit”).

[0073] Figure 5B An electronic device 5 is shown that includes the phase-locked loop circuit 10 that has been described above. For example, the phase-locked loop circuit 10 can be used for a sensor front end that requires a small area high-performance phase-locked loop. Therefore, the electronic device 5 can be a sensor such as an ambient light sensor, a time-of-flight sensor, a biomedical application, or an electronic device for automotive applications.

[0074] Although embodiments of the present invention have been described above, it is apparent that other embodiments may be implemented. For example, other embodiments may include any subcombination of the features described in the claims or any subcombination of the elements described in the examples given above. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

[0075] Reference numerals list

[0076] 1 Integrated Circuit

[0077] 5. Electronic devices

[0078] 10 Phase-locked loop

[0079] 13 Phase / Frequency Detector

[0080] 15Simulation Department

[0081] 17 Integral

[0082] 18 Feedback Divider

[0083] 19 Voltage Controlled Oscillator

[0084] 21 Charge pump for analog part

[0085] 23 Loop filter of analog part

[0086] 25 Capacitors

[0087] 27 Capacitors

[0088] 28 Resistors

[0089] 311,312,…31 N Integrator unit

[0090] 32 First digital input

[0091] 33 Second digital input

[0092] 34 digital inputs

[0093] 35 points core

[0094] 36 nodes

[0095] 37 analog outputs

[0096] 41 Current Generator

[0097] 410 Biased Sinking Transistor

[0098] 411 Current bias transistor for analog part

[0099] 412 Current bias transistor for digital part

[0100] 413 Control transistor for analog part

[0101] 414 Control transistor for digital part

[0102] 415 Current Source

[0103] 416 Enable absorption transistor

[0104] 417 Energy Transistor

[0105] 418 Control Absorption Transistor

[0106] 419 Bias Source Transistor

[0107] 42 counter

[0108] 421 Control Source Transistor

[0109] 43 Analog Units

[0110] 44 direction detector

[0111] 45 digital units

[0112] 46 Charge Pump

[0113] f I Input Clock

[0114] f O Output Clock

[0115] f F Feedback signal

[0116] UP first update signal

[0117] DOWN Second update signal

Claims

1. A phase-locked loop circuit (10), comprising: Simulation Department (15); Integration section (17); as well as A voltage controlled oscillator (19) configured to receive the first current signal from the analog section (15) and the second current signal from the integration section (17), and configured to output an output clock (f O ); The integration section (17) is configured to receive a first update signal and a second update signal (UP, DOWN), each of which has a first update signal and a second update signal based on an input clock (f I ) and the output clock (f O ), the integrating section (17) comprises three integrator units (31) connected to each other to form a ring oscillator.

2. The phase-locked loop circuit (10) according to claim 1, wherein: Each of the integrator units (31) comprises a first digital input (32) configured to receive a digital input according to the input clock (f I ) and the output clock (f O ) between the phase difference signals.

3. The phase-locked loop circuit (10) according to claim 1 or 2, further comprising a current generator (41), which is electrically connected to at least one of the integrator units (31).

4. The phase-locked loop circuit (10) according to claim 3, wherein: The current generator (41) is configured to receive a first voltage signal from at least one of the integrator units (31) and to generate a first sub-signal of the second current signal, the first sub-signal being dependent on the input clock (f I ) and the output clock (f O ) is the phase difference between them.

5. The phase-locked loop circuit (10) according to claim 4, wherein: Each of the integrator units (31) comprises a digital output (34), which is connected to a second digital input (33) of another integrator unit (33), and a digital output signal output by the digital output (34) indicates whether the first voltage signal output by the integrator unit (31) is lower than a first predetermined value or higher than a first predetermined value.

6. The phase-locked loop circuit (10) according to claim 5, further comprising a counter, wherein: A digital output of at least one of the integrator units is also connected to the counter.

7. The phase-locked loop circuit (10) according to claim 6, wherein: When the digital output signal indicates that the first voltage signal changes to a value below the first predetermined value, the counter value of the counter changes in a first direction.

8. The phase-locked loop circuit (10) according to claim 6 or 7, wherein: When the digital output signal indicates that the first voltage signal changes to a value higher than the first predetermined value, the counter value of the counter changes in a second direction opposite to the first direction.

9. The phase-locked loop circuit (10) according to claim 6, wherein: A digital output of a first one of the integrator units is connected to the counter, and a counter value of the counter changes in a first direction when the digital output signal indicates that the first voltage signal changes to a value higher than the first predetermined value.

10. The phase-locked loop circuit (10) according to any one of claims 7 or 9, wherein: The current generator is further configured to receive a counter signal from the counter and to generate a second sub-signal of the second current signal, the first sub-signal and the second sub-signal being added.

11. The phase-locked loop circuit (10) according to any one of claims 3 to 10, wherein: The current generator (41) is configured to generate a constant current when the phase difference is zero.

12. The phase-locked loop circuit (10) according to any one of claims 5 to 11, wherein: Each of the integrator units (31) is configured to receive the digital output signal output from another of the integrator units (31), and is configured to set the level of the output voltage to a second predetermined value when the digital output signal indicates that the output voltage of the other of the integrator units changes to a value lower than the first predetermined value.

13. The phase-locked loop circuit (10) according to any one of the preceding claims, wherein: Each of the integrator units (31) is capable of operating in a first oscillation mode or a second oscillation mode, wherein in the first oscillation mode, the output voltage of the integrator unit (31) drops from the second predetermined value to ground (GND), and in the second oscillation mode, the output voltage of the integrator unit (31) rises from ground (GND) to the second predetermined value.

14. An integrated circuit (1) comprising a phase locked loop circuit (10) according to any one of the preceding claims.

15. An electronic device (5) comprising the phase-locked loop circuit (10) according to any one of claims 1 to 13.

16. The electronic device (5) according to claim 15, said electronic device being selected from the group consisting of sensors, ambient light sensors, time-of-flight sensors, biomedical applications or electronic devices for automotive applications.

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