Semiconductor light-receiving element and method for manufacturing semiconductor light-receiving element

Abstract

This semiconductor light-receiving element (100) is provided with: a semiconductor substrate (2); a multiplication layer (4) which is formed on the semiconductor substrate (2), is configured from a digital alloy structure in which first semiconductor layers (4a), which are configured from a layer thickness of N times (1 < = N < = 20) of a monoatomic layer, and second semiconductor layers (4b), which are configured from a layer thickness of M times (1 < = M < = 20) of the monoatomic layer and have a smaller band gap energy than the first semiconductor layers (4a), are alternately laminated a plurality of times, and amplifies photocarriers; a light absorbing layer (6) that is formed on the multiplying layer (4) and that absorbs incident light and generates photocarriers; and an electric field relaxation layer (5) formed between the multiplication layer (4) and the light absorption layer (6).

Description

Technical Field

[0001] The present disclosure relates to a semiconductor light receiving element and a method for manufacturing the semiconductor light receiving element. Background Art

[0002] In recent years, with the development of the information society, the optical communication network, which is its backbone, has grown significantly. In particular, with the leap forward of data centers that process large amounts of data, or the development of the fifth-generation mobile communication system, the speed and capacity of optical communications for both short-distance and long-distance communications have become particularly prominent. In optical communications, avalanche photodiodes (APDs) with excellent performance are used on the receiving side of communication data.

[0003] APDs are mainly used on the receiving side of long-distance transmissions because they generate carriers consisting of electron-hole pairs from optical signals received during data communication and amplify the carriers themselves. In addition, the use of APDs eliminates the need for an external carrier amplifier on the receiving side inside the communication device, which is necessary when using a conventional light-receiving element. Therefore, for example, even in short-distance communications, APDs can be used as light-receiving elements.

[0004] There are several operating principles of APDs. Among them, the SACM type APD structure (Separate Absorption, Charge and Multiplication Avalanche Photodiode: Separate Absorption, Charge and Multiplication Avalanche Photodiode) in which the layer that receives signal light and generates carriers (carrier generation layer) is separated from the layer that multiplies the generated carriers (multiplication layer) has excellent performance.

[0005] In optical communication, a layer for receiving signal light (light absorption layer) is formed mainly on an InP substrate by InGaAs, and a multiplication layer for multiplying the generated carriers is formed by AlInAs, and a layer called an electric field relaxation layer (AlInAs, etc.) is inserted between the AlInAs multiplication layer and the InGaAs light absorption layer to relax the electric field strength applied to both, thereby realizing the operation as an APD. When light is incident on the APD made by such a structure, photocarriers composed of electrons and holes are generated in the InGaAs light absorption layer, wherein the electrons are conducted to the AlInAs multiplication layer due to reverse bias. The electrons as photocarriers are multiplied by the avalanche amplification effect in the AlInAs multiplication layer, so that the received optical signal can be amplified.

[0006] The performance of APD is mainly determined by the noise during carrier multiplication, which depends on the constituent material of the multiplication layer. For example, in the Si-APD disclosed in non-patent document 1, a germanium (Ge) light absorption layer and a Si multiplication layer are used on a silicon (Si) substrate, which can achieve low noise in APD compared to the compound semiconductor AlInAs used as the constituent material of the multiplication layer.

[0007] In addition, Non-Patent Document 2 discloses that a binary compound semiconductor (AlAs, InAs) or a ternary compound semiconductor (AlAs) constituting an AlInAs multiplication layer composed of a compound semiconductor is used to form a semiconductor-based AlInAs multiplication layer. x In 1－x By applying a technology called Digital Alloy that controls the layer thickness at the atomic layer level, APDs using AlInAs can achieve lower noise than existing APDs using AlInAs.

[0008] The multiplication layer formed by repeating a layer whose thickness is controlled at the atomic layer level using the digital alloy technology disclosed in non-patent document 2 has a different quantum effect from that of the multiplication layer composed of a superlattice structure as disclosed in patent document 1. By controlling the electron orbit of the semiconductor material itself, it has a new physical property value different from that of the existing material. In particular, it has been reported that the AlInAs multiplication layer composed of a digital alloy structure in which AlAs and InAs are stacked at the atomic layer level has very low noise during avalanche multiplication operation compared to the existing AlInAs lattice-matched on the InP substrate.

[0009] Patent Document 1: Japanese Patent No. 2671569

[0010] Patent Document 2: U.S. Patent No. 6,326,650

[0011] Non-patent literature 1: M. Huang, et.al., "Germanium on Silicon Avalanche Photodiode." IEEE Journal of Selected Topics In Quantum Electronics, Vol. 24, No. 2, 3800911, 2018.

[0012] Non-patent document 2: J. Zheng, et al., "Digital Alloy InAlAs Avalanche Photodopdes," IEEE Journal of Lightwave Technology, Vol. 36, No. 17, pp. 3580-3585, 2018.

[0013] Non-patent document 3: DCHoughton et.al., "Comparison of chemical beam epitaxyand metalorganic chemical vapor deposition for highly strained multiplequantum well InGaAsP / InP 1.5μm lasers." J.Crystal Growth Vol.136, pp.56-63, 1994.

[0014] Patent document 2 discloses the application of a digital alloy type multiplication layer in the multiplication layer of an APD. However, in the APD described in patent document 2, the absorption layer that generates photocarriers and the multiplication layer that multiplies carriers are not separated, so the noise becomes larger, resulting in a decrease in the receiving sensitivity in the element structure.

[0015] In addition, in the Si-APD disclosed in non-patent document 1, it is necessary to crystal-grow Ge of about 1 μm on the Si substrate as a light absorption layer. However, due to the lattice mismatch between Ge and the Si substrate, crystal defects are easily generated, so it is difficult to grow thick crystals. In addition, due to the influence of crystal defects, the dark current tends to increase, so it is difficult to obtain stable device characteristics as an APD.

[0016] Based on a compound semiconductor using InP as a semiconductor material constituting the APD, in order to improve the performance of the APD, it is preferred to use the digital alloy technology disclosed in non-patent document 1, and apply the AlInAs multiplication layer composed of a digital alloy structure to the SACM type APD. However, both AlAs and InAs constituting the multiplication layer composed of the digital alloy structure are lattice mismatched with the InP substrate, so the crystal quality of the electric field relaxation layer and the light absorption layer grown on the upper surface side of the multiplication layer may be significantly reduced. Similar to the above-mentioned Si-APD, there is a concern that the dark current caused by crystal defects may increase, resulting in a reduction in the device characteristics of the APD.

[0017] Furthermore, since the AlInAs multiplication layer formed by the digital alloy structure produces a band gap difference between the layers on the upper surface side or the lower surface side of the multiplication layer, when the photocarriers generated when light is incident are conducted in the up and down directions relative to the substrate surface of the multiplication layer formed by the digital alloy structure, the band gap difference at the interface between the multiplication layer and the upper and lower layers may hinder the high-speed operation of the APD.

[0018] That is, the use of an AlInAs multiplication layer composed of a digital alloy structure alone as the multiplication layer of the APD cannot fully demonstrate the excellent characteristics of the APD, such as carrier responsiveness. Summary of the invention

[0019] The present disclosure has been made to solve the above-mentioned problems, and an object of the present disclosure is to obtain a semiconductor light receiving element having low noise and high receiving sensitivity and a method for manufacturing the semiconductor light receiving element.

[0020] The semiconductor light receiving element according to the present disclosure comprises:

[0021] Semiconductor substrates;

[0022] A multiplication layer is formed on the semiconductor substrate, and is composed of a digital alloy structure formed by alternately stacking a first semiconductor layer and a second semiconductor layer for multiple times, and amplifies the photocarriers, wherein the first semiconductor layer is composed of a layer thickness of N times (1≦N≦20) a single atomic layer, and the second semiconductor layer is composed of a layer thickness of M times (1≦M≦20) a single atomic layer and has a band gap energy smaller than the band gap energy of the first semiconductor layer;

[0023] A light absorbing layer, formed on the multiplication layer, absorbs incident light to generate the light carriers; and

[0024] The electric field relaxation layer is formed between the multiplication layer and the light absorption layer.

[0025] The method for manufacturing a semiconductor light-receiving element according to the present disclosure comprises the following steps:

[0026] On an n-type InP substrate, a step of sequentially epitaxially growing an n-type AlInAs buffer layer, an AlInAs multiplication layer composed of a digital alloy structure formed by alternately stacking an AlAs layer composed of N times the thickness of a single atomic layer and an InAs layer composed of M times the thickness of a single atomic layer, a p-type AlInAs electric field relaxation layer, an n-type InGaAs light absorption layer, an i-type AlInAs window layer, an n-type InP window layer, and a p-type InGaAs contact layer, wherein 1≦N≦20, 1≦M≦20; and

[0027] A step of forming a Zn selective diffusion region in a portion of the n-type InP window layer and the i-type AlInAs window layer.

[0028] According to the semiconductor light receiving element and the method for manufacturing the semiconductor light receiving element involved in the present disclosure, it is possible to obtain a semiconductor light receiving element with low noise and high receiving sensitivity and to easily manufacture the semiconductor light receiving element. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 This is a cross-sectional view showing the element structure of the semiconductor light-receiving element according to the first embodiment.

[0030] Figure 2 This is a cross-sectional view showing the element structure of the semiconductor light-receiving element according to the second embodiment.

[0031] Figure 3 This is a diagram for explaining the effective stress of the digital alloy structure in the case of the presence or absence of a strain relaxation layer in the semiconductor light-receiving element according to the second embodiment.

[0032] Figure 4 This is a cross-sectional view showing the element structure of the semiconductor light-receiving element according to the third embodiment.

[0033] Figure 5A , Figure 5B is a diagram for explaining the relationship between the band gap energy of the semiconductor light-receiving element involved in the third embodiment. Figure 5A This is a diagram without the first migration layer. Figure 5B This is a diagram of the case with the first migration layer.

[0034] Figure 6 This is a cross-sectional view showing the element structure of the semiconductor light-receiving element according to the fourth embodiment.

[0035] Fig. 7A , Figure 7B is a diagram for explaining the relationship between the band gap energy of the semiconductor light-receiving element involved in the fourth embodiment. Fig. 7A This is a diagram without the second migration layer. Figure 7B This is a diagram showing the case with a second migration layer.

[0036] Figure 8 This is a cross-sectional view showing the element structure of the semiconductor light-receiving element according to the fifth embodiment.

[0037] Fig. 9 It is a diagram showing the electric field intensity distribution in a direction perpendicular to the substrate.

[0038] Fig.10 The maximum electric field intensity E is calculated for the case where the outermost surface layer of the I-type AlInAs multiplication layer composed of the digital alloy structure is an AlAs layer and the case where it is an InAs layer. MAX A diagram for comparison. DETAILED DESCRIPTION

[0039] Implementation Method 1

[0040] <Element Structure of Semiconductor Light Receiving Element 100 According to Embodiment 1>

[0041] Figure 12 is a cross-sectional view showing the device structure of the semiconductor light-receiving device 100 according to Embodiment 1. As an example of the semiconductor light-receiving device 100 according to Embodiment 1, a SACM type APD is given.

[0042] The semiconductor light-receiving element 100 according to the first embodiment is composed of a plurality of semiconductor layers having a carrier concentration of 1 to 5×10 18 cm －3 The n-type AlInAs buffer layer 3 has a thickness of 0.1 to 0.5 μm, the i-type AlInAs multiplication layer 4 has a thickness of 0.05 to 0.2 μm and is composed of a digital alloy structure formed by alternately stacking multiple i-type AlAs layers (as an example, the layer thickness is 2 ML) and i-type InAs layers (as an example, the layer thickness is 2 ML), and the carrier concentration is 0.5 to 1×10 18 cm －3 The p-type AlInAs electric field relaxation layer 5 has a layer thickness of 0.05 to 0.15 μm and a carrier concentration of 1 to 5×10 15 cm －3 The n-type InGaAs light absorption layer 6 has a thickness of 1 to 1.5 μm, the i-type AlInAs window layer 7 has a thickness of 0.05 to 1 μm, and the carrier concentration is 0.1 to 5×10 15 cm －3 The n-type InP window layer 8 has a thickness of 0.5 to 1 μm and a carrier concentration of 1 to 5×10 18 cm －3 The p-type InGaAs contact layer 9 is formed in a circular shape and has a layer thickness of 0.1 to 0.5 μm.

[0043] The semiconductor light-receiving element 100 involved in embodiment 1 also includes: a Zn selective diffusion region 10 arranged on a portion of the n-type InP window layer 8 and the i-type AlInAs window layer 7, a SiNx surface protection film 11 arranged on the surface of the n-type InP window layer 8 including the surface of the Zn selective diffusion region 10, an n-type electrode 1 arranged on the back side of the n-type InP substrate 2, and a p-type electrode 12 arranged on the surface of the p-type InGaAs contact layer 9 in a circular shape.

[0044] The semiconductor light receiving element 100 involved in the first embodiment is characterized in that the multiplication layer is set as an i-type AlInAs multiplication layer 4 composed of a digital alloy structure, and a p-type AlInAs electric field relaxation layer 5 is provided between the i-type AlInAs multiplication layer 4 and the n-type InGaAs light absorption layer 6. In the description of each embodiment, except for AlInAs constituting the multiplication layer 4, the composition ratio of AlInAs and InGaAs constituting each layer is not explicitly stated, but it is preferred that both have a composition ratio that matches the n-type InP substrate 2 lattice.

[0045] In the above description, as an example of the multiplication layer of the SACM type APD, an i-type AlInAs multiplication layer 4 composed of a digital alloy structure formed by alternating multiple layers of two layers with a thickness of a single atomic layer (ML), namely, an i-type AlAs layer with a thickness of 2ML and an i-type InAs layer with a thickness of 2ML is listed. The thickness of the i-type AlAs layer only needs to be within the range of N times (1≦N≦20) of the single atomic layer, and the thickness of the i-type InAs layer only needs to be within the range of M times (1≦M≦20) of the single atomic layer. It is more appropriate if the thickness of the i-type AlAs layer is within the range of N times (1≦N≦5) of the single atomic layer, and the thickness of the i-type InAs layer is within the range of M times (1≦M≦5) of the single atomic layer. Regarding the i-type AlInAs multiplication layer 4 having a digital alloy structure, when the i-type AlAs layer and the i-type InAs layer are alternately stacked a plurality of times, the number of stacking times is preferably in the range of 5 to 300.

[0046] In the following description, two layers of semiconductor materials different from each other constituting the AlInAs multiplication layer composed of the digital alloy structure are sometimes referred to as the first semiconductor layer 4a and the second semiconductor layer 4b. The band gap energy Eg1 of the first semiconductor layer 4a is greater than the band gap energy Eg2 of the second semiconductor layer 4b, that is, the relationship Eg1>Eg2 holds. In the above example, the AlAs layer with a band gap energy of 2.12eV becomes the first semiconductor layer 4a, and the InAs layer with a band gap energy of 0.36eV ​​becomes the second semiconductor layer 4b.

[0047] <Method of Manufacturing Semiconductor Light Receiving Element 100 According to Embodiment 1>

[0048] First, a method for manufacturing a SACM type APD which is an example of the semiconductor light-receiving element 100 according to the first embodiment will be described below.

[0049] By using epitaxial crystal growth methods such as Metal Organic Vapor Phase Epitaxy (MOVPE) or Molecular Beam Epitaxy (MBE), an n-type AlInAs buffer layer 3, an i-type AlInAs multiplication layer 4 composed of a digital alloy structure formed by alternating multiple layers of i-type AlAs (layer thickness 2ML) and i-type InAs (layer thickness 2ML), a p-type AlInAs electric field relaxation layer 5, an n-type InGaAs light absorption layer 6, an i-type AlInAs window layer 7, an n-type InP window layer 8, and a p-type InGaAs contact layer 9 are sequentially crystal-grown on the surface of an n-type InP substrate 2.

[0050] When the MOVPE method is used as the epitaxial crystal growth method, the crystal growth temperature is preferably about 550° C., but may be in the temperature range of 500° C. to 600° C. inclusive.

[0051] In the wafer process after the epitaxial crystal growth described above, processing of the device region, film formation, and electrode formation are performed by reactive ion etching, CVD (Chemical Vapor Deposition), vapor deposition, etc., to form a device structure required to function as a SACM type APD.

[0052] The SiOx film is formed on the surface of the wafer after epitaxial crystal growth by CVD method etc. The SiOx film is an insulating film and functions as a diffusion mask.

[0053] Using photolithography and etching techniques, a circular pattern mask with a diameter of 40 μm is used for patterning, and a circular opening is set in the SiOx film. The SiOx film is used as a diffusion mask, and zinc (Zn) is diffused from the opening to the inside of the semiconductor layer, so that a Zn selective diffusion region 10 is formed in a part of the n-type InP window layer 8 and the i-type AlInAs window layer 7. The end portion of the semiconductor layer inside the Zn selective diffusion region 10 is located in the i-type AlInAs window layer 7. The Zn selective diffusion region 10 functions as a p-type conductive region. After the Zn selective diffusion region 10 is formed, the SiOx film is removed by wet etching or dry etching.

[0054] Next, using photolithography and etching techniques, the p-type InGaAs contact layer 9 is processed using reactive ion etching or the like so that the p-type InGaAs contact layer 9 remains on the Zn selective diffusion region 10 in a ring shape having a width of about 3.0 to 5.0 μm.

[0055] Thereafter, a SiNx surface protection film 11 is formed on the wafer surface by CVD method or the like. Then, the SiNx surface protection film 11 is removed only on the surface of the p-type InGaAs contact layer 9 by photolithography and etching techniques. The SiNx surface protection film 11 also functions as an anti-reflection film.

[0056] A metal material such as Ti / Au is formed on the surface of the p-type InGaAs contact layer 9 by vapor deposition or the like, thereby forming the p-type electrode 12 .

[0057] Finally, the back side of the n-type InP substrate 2 is ground, and then a metal material such as AuGeNi is formed into a film by vapor deposition or the like to form the n-type electrode 1 .

[0058] The above is a method for manufacturing the SACM type APD which is an example of the semiconductor light receiving element 100 according to the first embodiment.

[0059] <Operation of semiconductor light receiving element 100 according to first embodiment>

[0060] Next, the operation of the SACM type APD which is an example of the semiconductor light receiving element 100 according to the first embodiment manufactured by the above-described manufacturing method will be described.

[0061] First, a reverse bias voltage is applied from the outside so that the n-type electrode 1 provided on the back side of the n-type InP substrate 2 of the SACM type APD becomes positive and the p-type electrode 12 provided on the surface side becomes negative. The reverse bias voltage is set to a voltage value sufficient to generate avalanche amplification.

[0062] In a SACM type APD to which a reverse bias voltage is applied, when light of a wavelength band used in optical communication, i.e., a wavelength of 1.3 μm or 1.55 μm, is incident from the p-type electrode 12 side to the Zn selective diffusion region 10 serving as the p-type conductive region, the light is absorbed in the n-type InGaAs light absorption layer 6 to generate photocarriers (electron-hole pairs), and when a reverse bias voltage is applied, electrons move toward the n-type electrode 1 side and holes move toward the p-type electrode 12 side.

[0063] In the SACM type APD to which a reverse bias voltage is applied, the electric field strength is controlled by the p-type AlInAs electric field relaxation layer 5 in such a way that avalanche amplification occurs when electrons are conducted into the i-type AlInAs multiplication layer 4 composed of a digital alloy structure. In the i-type AlInAs multiplication layer 4 composed of a digital alloy structure, electrons are ionized to generate new electron-hole pairs, and the newly generated electrons and holes are both ionized, so that the electrons and holes are amplified avalanche-like, i.e., avalanche amplification. That is, the electrons as photocarriers are multiplied in the i-type AlInAs multiplication layer 4 due to the avalanche amplification effect, so that the received light signal can be amplified.

[0064] <Operation of the semiconductor light-receiving element according to the first embodiment>

[0065] In the SACM type APD (semiconductor photodetector) which is an electron multiplication type, when the photocarriers generated in the n-type InGaAs light absorption layer are multiplied in the multiplication layer, holes are multiplied in addition to electrons, and become an important factor of noise during the operation of the APD. When the amplitude of the noise is set to iNs, the basic charge of the electron is set to q, the average current value flowing in the avalanche region is set to I, the band is set to B, the avalanche multiplication rate is set to M, and the excess noise coefficient is set to F, the noise component that reduces the performance of the receiving sensitivity is as shown in the following formula (1).

[0066] i Ns 2 =2qIBM 2 F (1)

[0067] The excess noise coefficient F is expressed by the following equation (2) using the ionization rate ratio k indicating the multiplication rate ratio between holes and electrons.

[0068]

[0069] The ionization rate ratio k takes a value inherent to the material. When the ionization rate ratio k decreases, the electron multiplication ratio increases, so the excess noise coefficient F decreases, and the amplitude i of the noise decreases. Ns Therefore, the noise component N, which is the denominator of the S / N ratio when the APD is operating, becomes smaller, so the APD can obtain a high-sensitivity characteristic.

[0070] Since the ionization rate ratio k is a material-specific value, a semiconductor material that can be crystal-grown until a desired layer thickness is obtained while maintaining lattice matching with the substrate and has the smallest possible ionization rate ratio k is generally selected as the semiconductor material constituting the APD.

[0071] As the semiconductor material constituting the multiplication layer, a binary compound semiconductor (AlAs, InAs) or a ternary compound semiconductor (AlAs, InAs) as disclosed in Non-Patent Document 1 is used. x In 1－x As) in the case of a multilayer structure formed by crystal growth at the atomic layer level, the electron multiplication rate can be increased or the hole multiplication can be suppressed compared to ordinary semiconductor materials, thereby further reducing the value of the ionization rate ratio k.

[0072] As described above, a SACM type APD with low noise and high receiving sensitivity can be realized by setting it to the SACM type as described below: as the semiconductor material constituting the multiplication layer of the APD, a multiplication layer composed of a digital alloy structure is used, for example, AlInAs formed by stacking binary compound semiconductor materials such as AlAs and InAs with a layer thickness at the atomic layer level, and the electric field is controlled by an electric field relaxation layer in such a way that the electric field intensity applied to the multiplication layer is greater than the electric field applied to the light absorption layer.

[0073] In Embodiment 1, a case where AlInAs is used as an example of a semiconductor material constituting a multiplication layer of a SACM type APD is described. As a semiconductor material constituting a multiplication layer, for example, for semiconductor materials such as InGaAsP, AlGaInAs, AlAsSb, AlGaAsSb, AlInAsSb, AlGaInAsSb, etc. that can combine group III materials and group V materials for crystal growth, even if binary, ternary, or quaternary compound semiconductor materials (InP, AlAs, InGaAs, AlInAs, GaAsSb, AlGaInAs, AlGaAsSb, etc.) constituting the above materials are stacked at the atomic layer level, the same improvement effect can be obtained in the element characteristics of the SACM type APD.

[0074] In one of the above examples, a stacked structure of 2ML units is illustrated as the thickness of each layer constituting the digital alloy structure. However, as long as the stacked structure constituting the required multiplication layer can be crystal-grown with a critical film thickness, for example, a layer thickness of 5nm, which can be crystal-grown relative to the base, i.e., the n-type InP substrate 2, without generating crystal defects, it is not limited to a combination of one example, and can be a combination of any semiconductor materials. In addition, the above-mentioned i-type AlInAs multiplication layer 4 is a non-doped layer, but the multiplication layer is not limited to a non-doped layer. That is, the digital alloy structure itself as the multiplication layer can also be doped with n-type or p-type impurities.

[0075] In the above description, the case of forming a p-type conductive region by diffusion of Zn is taken as an example. However, as long as it is an atom that imparts p-type conductivity to the n-type InP window layer 8 and the i-type AlInAs window layer 7, in addition to Zn, cadmium (Cd), beryllium (Be), etc. that can become a p-type impurity can also be used as a p-type dopant. The Zn diffusion method can be a solid phase diffusion method using zinc oxide (ZnO), or a Zn vapor phase diffusion method using a crystal growth furnace, or a p-type contact layer crystal can be grown by crystal growth.

[0076] In the above description, as an example of a SACM type APD, a surface incident type structure in which light to be detected is incident from the p-type electrode 12 side to the Zn selective diffusion region 10 as a p-type conductive region is cited. However, the present disclosure is not limited to the surface incident type structure, but rather, even a back-incident type structure in which the n-type electrode 1 is opened in a circular pattern and light is incident from the back side of the n-type InP substrate 2, or an end-incident type structure in which light is incident from the end face of the n-type light absorbing layer 6, can expect the same effect as a SACM type APD.

[0077] <Effects of Embodiment 1>

[0078] As described above, according to the semiconductor photosensitive element and the method for manufacturing a semiconductor photosensitive element involved in embodiment 1, the multiplication layer is set to a digital alloy structure, and an electric field relaxation layer is provided between the multiplication layer and the light absorption layer, thereby achieving the effect of stably obtaining a semiconductor photosensitive element with low noise and high receiving sensitivity.

[0079] Implementation Method 2

[0080] <Element Structure of Semiconductor Light Receiving Element 110 According to Embodiment 2>

[0081] Figure 2 2 is a cross-sectional view showing the device structure of the semiconductor light-receiving device 110 according to Embodiment 2. As an example of the semiconductor light-receiving device 110 according to Embodiment 2, a SACM type APD is given.

[0082] The semiconductor light-receiving element 100 according to the second embodiment is formed by sequentially forming a semiconductor substrate 2 having a carrier concentration of 1 to 5×10 18 cm －3 The n-type AlInAs buffer layer 3 has a thickness of 0.1 to 0.5 μm, the i-type AlInAs multiplication layer 4 has a digital alloy structure composed of a plurality of i-type AlAs layers (as an example, a layer thickness of 2 ML) and an i-type InAs layer (as an example, a layer thickness of 2 ML) alternately stacked multiple times, has a thickness of 0.05 to 0.2 μm, the i-type AlInAs strain relief layer 21 has a thickness of 10 to 100 nm, and the carrier concentration is 0.5 to 1×10 18 cm －3 The p-type AlInAs electric field relaxation layer 5 has a layer thickness of 0.05 to 0.15 μm and a carrier concentration of 1 to 5×10 15 cm －3 The n-type InGaAs light absorption layer 6 has a thickness of 1 to 1.5 μm, the i-type AlInAs window layer 7 has a thickness of 0.05 to 1 μm, and the carrier concentration is 0.1 to 5×10 15 cm －3 The n-type InP window layer 8 has a thickness of 0.5 to 1 μm and a carrier concentration of 1 to 5×10 18 cm －3 The p-type InGaAs contact layer 9 is formed in a circular shape and has a layer thickness of 0.1 to 0.5 μm.

[0083] The semiconductor light receiving element 100 involved in embodiment 2 also includes: a Zn selective diffusion region 10 arranged on a portion of the n-type InP window layer 8 and the i-type AlInAs window layer 7, a SiNx surface protection film 11 arranged on the surface of the n-type InP window layer 8 including the surface of the Zn selective diffusion region 10, an n-type electrode 1 arranged on the back side of the n-type InP substrate 2, and a p-type electrode 12 arranged on the surface of the p-type InGaAs contact layer 9 in a circular shape.

[0084] The semiconductor light receiving element 110 involved in embodiment 2 is characterized in that the multiplication layer is set as an i-type AlInAs multiplication layer 4 composed of a digital alloy structure, and an i-type AlInAs strain relaxation layer 21 is set between the i-type AlInAs multiplication layer 4 and the p-type AlInAs electric field relaxation layer 5.

[0085] The manufacturing method of the semiconductor light receiving element 110 involved in embodiment 2 is different from that of embodiment 1 only in that: during epitaxial crystal growth, the i-type AlInAs strain relaxation layer 21 crystal is further grown between the i-type AlInAs multiplication layer 4 and the p-type AlInAs electric field relaxation layer 5, so the detailed description of the manufacturing method is omitted.

[0086] <Operation of semiconductor light receiving element 110 according to Embodiment 2>

[0087] In the element structure of APD, a stacked structure with a crystal growth layer thickness of about 2μm is required from the electric field relaxation layer to the p-type contact layer located on the outermost surface of the semiconductor layer on the upper surface side of the multiplication layer. In particular, when the APD is in operation, if the crystal quality of the multiplication layer and the light absorption layer corresponding to the active layer deteriorates, the dark current increases, and the noise caused by the dark current also increases. Therefore, in addition to the deterioration of the receiving sensitivity characteristics of the APD, there are also concerns about reliability. Therefore, in order to prevent the occurrence of crystal defects near the multiplication layer, it is important to reduce the stress, that is, the strain, of the stacked structure itself as much as possible, which is important for realizing a high-performance and high-reliability APD.

[0088] The multiplication layer composed of the digital alloy structure is equivalent to stacking the lattice-mismatched binary or ternary compound semiconductor materials whose lattice constants are inconsistent with the substrate, which is equivalent to alternately stacking the compressive strain and the tensile strain. In this case, the effective stress τ when the dislocation occurs can be calculated by the mechanical equilibrium model disclosed in the above-mentioned non-patent document 3. That is, as described in non-patent document 3 Figure 2As disclosed, if a stacked structure is constructed in such a way that the effective stress τ becomes below zero, and the material, layer thickness and sequence during the crystal growth of the element structure including the digital alloy structure are controlled, high-quality crystal growth without dislocations or crystal defects can be achieved, thereby obtaining an APD with excellent element characteristics.

[0089] According to Non-Patent Document 3, the effective stress τ in a structure in which compressive strain and tensile strain are alternately and repeatedly stacked, such as a multilayer quantum well structure, is represented by the following formula (3) and various parameters.

[0090]

[0091] Ψ: Angle between the interface and the sliding surface

[0092] λ: Angle between the dislocation line and the Burgers vector

[0093] ν: Poisson's ratio

[0094] μ x : Shear coefficient of the compressive strain layer

[0095] μ y : Shear coefficient of the tensile strain layer

[0096] μ xy : Average shear coefficient of the repeated stacking part

[0097] b: Burgers vector

[0098] cosθ: the angle between the dislocation line and the Burgers vector

[0099] β: core parameter

[0100] x: strain of the compressive strain layer

[0101] h: Layer thickness of the compressive strain layer

[0102] y: strain of the tensile strain layer

[0103] H: Layer thickness of tensile strain layer

[0104] Z: Thickness of strain relaxation layer

[0105] N: number of compressive strain layers

[0106] L: calculated value of Nh+(N-1)H

[0107] For the two cases of whether there is a strain relaxation layer with a thickness of 50 nm on the upper surface side of the AlInAs multiplication layer composed of a digital alloy structure with a thickness of 50 nm, in which the compressive strain layer is composed of an InAs layer and the tensile strain layer is composed of an AlAs layer, the effective stress value calculated based on formula (3) is as follows: Figure 3 As shown, the calculation parameters refer to Non-Patent Document 3. The InAs layer constituting the digital alloy structure of Embodiment 2 is used as a compressive strain layer, and the AlAs layer is used as a tensile strain layer, and the physical property values ​​of the respective compound semiconductor materials are used.

[0108] As for the effective stress τ when the AlInAs multiplication layer composed of the digital alloy structure is crystal-grown, the effective stress τ applied to the entire element structure rises suddenly because the InAs layer is highly compressive. On the other hand, the AlAs layer that undergoes crystal growth next to the InAs layer becomes tensile strain acting in the direction opposite to the compressive strain, and thus acts in a direction that relaxes the effective stress τ. However, the effective stress τ applied to the entire element structure rises slowly as the InAs layer and the AlAs layer are alternately stacked.

[0109] When the electric field relaxation layer and light absorption layer corresponding to the active layer of the SACM type APD are crystal-grown, the stress accumulated in the formation of the AlInAs multiplication layer composed of the digital alloy structure is inherited as it is. Without the application of the strain relaxation layer, when the crystal growth of the device structure requiring a layer thickness of about 2μm is performed, the effective stress τ exceeds zero, so the calculation results show that the crystal quality is easily deteriorated due to the generation of dislocations.

[0110] On the other hand, as in the SACM type APD which is an example of the semiconductor light receiving element 110 involved in the second embodiment, when a strain relaxation layer such as the i-type AlInAs strain relaxation layer 21 is inserted between the i-type AlInAs multiplication layer 4 and the p-type AlInAs electric field relaxation layer 5, the effective stress τ which rises during the crystal growth of the i-type AlInAs multiplication layer 4 composed of the digital alloy structure can be reduced by the strain relaxation effect of the strain relaxation layer during the crystal growth of the strain relaxation layer and the light absorption layer. That is, by inserting the strain relaxation layer, a SACM type APD composed of a high-quality semiconductor crystal growth layer can be manufactured without generating dislocations during the crystal growth of the entire element structure.

[0111] In Embodiment 2, an i-type AlInAs layer is used as an example of a strain relaxation layer. However, the semiconductor material is not limited to AlInAs as long as it is a semiconductor material that is lattice-matched with the substrate used. In addition, the strain relaxation layer may be doped with impurities to become, for example, a p-type or n-type conductivity type, instead of the above-mentioned non-doped layer.

[0112] If the effective stress τ of the entire element structure can be controlled so as not to exceed zero, there is no problem even if the strain relaxation layer itself is strained. In addition, even if the strain relaxation layer itself is strained, as long as the strain of the entire element structure is controlled in a manner opposite to the average strain of the digital alloy structure, a more excellent effect can be achieved.

[0113] <Effects of Embodiment 2>

[0114] As described above, according to the semiconductor photosensitive element involved in embodiment 2, an AlInAs strain relaxation layer is provided between the AlInAs multiplication layer and the AlInAs electric field relaxation layer, thereby being able to alleviate the stress generated by the formation of the i-type AlInAs multiplication layer composed of the digital alloy structure, thereby achieving the effect of obtaining a high-performance and highly reliable semiconductor photosensitive element.

[0115] Implementation 3

[0116] <Element Structure of Semiconductor Light Receiving Element 120 According to Embodiment 3>

[0117] Figure 4 2 is a cross-sectional view showing the device structure of the semiconductor light-receiving device 120 according to Embodiment 3. As an example of the semiconductor light-receiving device 120 according to Embodiment 3, a SACM type APD is given.

[0118] The semiconductor light receiving element 120 according to the third embodiment is formed by sequentially forming a plurality of n-type InP substrates 2 with a carrier concentration of 1 to 5×10 18 cm －3 The n-type AlInAs buffer layer 3 has a thickness of 0.1 to 0.5 μm, the i-type AlInAs multiplication layer 4 has a thickness of 0.05 to 0.2 μm and is composed of a digital alloy structure formed by alternately stacking multiple i-type AlAs layers (as an example, the layer thickness is 2ML) and i-type InAs layers (as an example, the layer thickness is 2ML), and the i-type AlInAs layer has a thickness of 15 nm. x Ga y In 1－x－y As (x = 0.25, y = 0.218) first migration layer 22, carrier concentration is 0.5 ~ 1 × 10 18 cm －3The p-type AlInAs electric field relaxation layer 5 has a layer thickness of 0.05 to 0.15 μm and a carrier concentration of 1 to 5×10 15 cm －3 The n-type InGaAs light absorption layer 6 has a thickness of 1 to 1.5 μm, the i-type AlInAs window layer 7 has a thickness of 0.05 to 1 μm, and the carrier concentration is 0.1 to 5×10 15 cm －3 The n-type InP window layer 8 has a thickness of 0.5 to 1 μm and a carrier concentration of 1 to 5×10 18 cm －3 The p-type InGaAs contact layer 9 is formed in a circular shape and has a layer thickness of 0.1 to 0.5 μm.

[0119] The semiconductor light receiving element 120 involved in embodiment 3 also includes: a Zn selective diffusion region 10 arranged on a portion of the n-type InP window layer 8 and the i-type AlInAs window layer 7, a SiNx surface protection film 11 arranged on the surface of the n-type InP window layer 8 including the surface of the Zn selective diffusion region 10, an n-type electrode 1 arranged on the back side of the n-type InP substrate 2, and a p-type electrode 12 arranged on the surface of the p-type InGaAs contact layer 9 in a circular shape.

[0120] The semiconductor light receiving element 120 according to the third embodiment is characterized in that the multiplication layer is an i-type AlInAs multiplication layer 4 having a digital alloy structure, and an i-type AlInAs multiplication layer 4 having a thickness of 15 nm is provided between the i-type AlInAs multiplication layer 4 and the p-type AlInAs electric field relaxation layer 5. x Ga y In 1－x－y As the first migration layer 22 this point.

[0121] The manufacturing method of the semiconductor light-receiving element 120 involved in the third embodiment is different from that in the first embodiment only in that an i-type AlInAs multiplication layer 4 and a p-type AlInAs electric field relaxation layer 5 composed of a digital alloy structure are further formed between the i-type AlInAs multiplication layer 4 and the p-type AlInAs electric field relaxation layer 5 during epitaxial crystal growth. x Ga y In 1－x－y As the crystal of the first migration layer 22 grows, the detailed description of the manufacturing method is omitted.

[0122] <Operation of semiconductor light receiving element 120 according to Embodiment 3>

[0123] The photocarriers, i.e., electrons and holes, generated by the incident light on the APD move in the direction opposite to their respective polarities in the light absorption layer to which a reverse bias voltage is applied. The electrons generated in the light absorption layer are conducted toward the multiplication layer, and after passing through the electric field relaxation layer, they reach the multiplication layer, generating an avalanche amplification effect in the multiplication layer. In the case of applying the multiplication layer 4 composed of a digital alloy structure, the energy band structure of the multiplication layer itself changes according to the semiconductor material of the combination of the first semiconductor layer 4a and the second semiconductor layer 4b constituting the digital alloy structure, and the position of the conduction band becomes higher than the electric field relaxation layer 5, which sometimes becomes an electron barrier ΔEc when the electrons are conducted to the multiplication layer 4 composed of the digital alloy structure.

[0124] In this state, electrons need energy to cross the electron potential barrier ΔEc in order to reach the multiplication layer 4 composed of the digital alloy structure. In particular, in the case of high-speed response at a low driving voltage, the electron potential barrier ΔEc may become an obstacle to the movement of electrons. Figure 4 As shown, by inserting a multiplication layer 4 composed of a digital alloy structure and an electric field relaxation layer 5, for example, a multiplication layer 4 composed of a digital alloy structure and a band gap energy Eg of the electric field relaxation layer 5 b The band gap energy Eg m Compound semiconductor material, i.e., i-type Al with a layer thickness of 15 nm x Ga y In 1－x－y By forming the first transition layer 22 with As (x=0.25, y=0.218), the electron barrier ΔEc when electrons are conducted to the multiplication layer 4 composed of the digital alloy structure can be reduced, thereby obtaining a SACM type APD capable of high-speed response.

[0125] Figure 5A , Figure 5B 2 is a diagram for explaining the relationship between the band gap energies of the respective layers of the semiconductor light receiving element 120 according to the third embodiment. Figure 5A A diagram showing a case where there is no first migration layer 22, Figure 5B The figure shows the case where there is a first migration layer 22. Figure 5A As shown, when the electric field relaxation layer 5 is in contact with the multiplication layer 4 having a digital alloy structure, electrons need to cross an electron barrier ΔEc in order to move from the electric field relaxation layer 5 to the multiplication layer 4 having a digital alloy structure.

[0126] On the other hand, Figure 5BAs shown, when the first migration layer 22 is provided between the electric field relaxation layer 5 and the multiplication layer 4 composed of the digital alloy structure, in order for electrons to move from the electric field relaxation layer 5 to the first migration layer 22, they only need to cross the electron potential barrier ΔEc1 which is smaller than the electron potential barrier ΔEc. In addition, in order for electrons to move from the first migration layer 22 to the multiplication layer 4 composed of the digital alloy structure, they only need to cross the electron potential barrier ΔEc2 which is smaller than the electron potential barrier ΔEc. As described above, it can be seen that by providing the first migration layer 22 between the electric field relaxation layer 5 and the multiplication layer 4 composed of the digital alloy structure, the effective electron potential barrier is reduced.

[0127] That is, the semiconductor light receiving element 120 involved in the third embodiment includes a first migration layer 22, which is formed between the multiplication layer 4 composed of the digital alloy structure and the electric field relaxation layer 5, and has a band gap energy Eg of the multiplication layer 4 composed of the digital alloy structure and a band gap energy Eg of the electric field relaxation layer 5. b The band gap energy Eg m , to alleviate the strain of the multiplication layer 4 composed of the digital alloy structure.

[0128] In the semiconductor light-receiving element 120 according to the third embodiment, i-type Al is used as an example of the first transition layer 22. x Ga y In 1－x－y However, as long as the band gap energy Eg of the multiplication layer 4 composed of the digital alloy structure and the band gap energy Eg of the electric field relaxation layer 5 are b The semiconductor material with a band gap energy value between 1 and 2 is not limited to the Al x Ga y In 1－x－y As layer, it can also be other semiconductor materials. In addition, if the first migration layer 22 is composed of semiconductor layers composed of the same layers as those constituting the digital alloy structure, control becomes easy. That is to say, as in the above example, when the digital alloy structure is composed of Al, In and As, if the first migration layer 22 is also composed of Al, In and As, control during crystal growth becomes easy. Among them, the first migration layer 22 can also be doped with impurities to become, for example, p-type or n-type conductivity, instead of a non-doped layer.

[0129] <Effects of Embodiment 3>

[0130] As described above, according to the semiconductor light-receiving element according to the third embodiment, an i-type AlInAs multiplication layer and a p-type AlInAs electric field relaxation layer having a digital alloy structure are provided between the i-type AlInAs multiplication layer and the p-type AlInAs electric field relaxation layer. x Ga y In 1－x－yAs first migration layer, the electron barrier generated between the i-type AlInAs multiplication layer and the electric field relaxation layer composed of the digital alloy structure is effectively reduced, thereby improving the carrier conductivity, so that a semiconductor light-receiving element capable of high-speed operation can be obtained.

[0131] Implementation 4

[0132] <Element Structure of Semiconductor Light Receiving Element 130 According to Embodiment 4>

[0133] Figure 6 1 is a cross-sectional view showing the device structure of the semiconductor light-receiving device 130 according to Embodiment 4. As an example of the semiconductor light-receiving device 130 according to Embodiment 4, a SACM type APD is given.

[0134] The semiconductor light-receiving element 130 according to the fourth embodiment is formed by sequentially forming a plurality of n-type InP substrates 2 with a carrier concentration of 1 to 5×10 18 cm －3 The n-type AlInAs buffer layer 3 has a thickness of 0.1 to 0.5 μm, and the i-type Al x Ga y In 1－x－y As (x = 0.25, y = 0.218) second migration layer 23, i-type AlInAs multiplication layer 4 with a layer thickness of 0.05 to 0.2 μm, composed of a digital alloy structure formed by alternately stacking multiple i-type AlAs layers (as an example, the layer thickness is 2 ML) and i-type InAs layers (as an example, the layer thickness is 2 ML), and a carrier concentration of 0.5 to 1×10 18 cm －3 The p-type AlInAs electric field relaxation layer 5 has a layer thickness of 0.05 to 0.15 μm and a carrier concentration of 1 to 5×10 15 cm －3 The n-type InGaAs light absorption layer 6 has a thickness of 1 to 1.5 μm, the i-type AlInAs window layer 7 has a thickness of 0.05 to 1 μm, and the carrier concentration is 0.1 to 5×10 15 cm －3 The n-type InP window layer 8 has a thickness of 0.5 to 1 μm and a carrier concentration of 1 to 5×10 18 cm －3 The p-type InGaAs contact layer 9 is formed in a circular shape and has a layer thickness of 0.1 to 0.5 μm.

[0135] The semiconductor light receiving element 130 involved in embodiment 4 also includes: a Zn selective diffusion region 10 arranged on a portion of the n-type InP window layer 8 and the i-type AlInAs window layer 7, a SiNx surface protection film 11 arranged on the surface of the n-type InP window layer 8 including the surface of the Zn selective diffusion region 10, an n-type electrode 1 arranged on the back side of the n-type InP substrate 2, and a p-type electrode 12 arranged on the surface of the p-type InGaAs contact layer 9 in a circular shape.

[0136] The semiconductor light receiving element 130 according to the fourth embodiment is characterized in that the multiplication layer is an i-type AlInAs multiplication layer 4 having a digital alloy structure, and an i-type AlInAs buffer layer 3 having a thickness of 15 nm is provided between the n-type AlInAs buffer layer 3 and the i-type AlInAs multiplication layer 4. x Ga y In 1－x－y As the second migration layer 23 this point.

[0137] The manufacturing method of the semiconductor light-receiving element 130 involved in the fourth embodiment is different from that in the first embodiment only in that an i-type AlInAs buffer layer 3 and an i-type AlInAs multiplication layer 4 are further formed between the n-type AlInAs buffer layer 3 and the i-type AlInAs multiplication layer 4 during epitaxial crystal growth. x Ga y In 1－x－y As the crystal of the second migration layer 23 is grown, the detailed description of the manufacturing method is omitted.

[0138] <Operation of the semiconductor light receiving element 130 according to the fourth embodiment>

[0139] In the semiconductor light receiving element 120 involved in Embodiment 3, the effect of improving the electron barrier ΔEc when the electrons of the photocarriers generated in the light absorption layer by incident light on the APD reach the multiplication layer through the electric field relaxation layer is shown. However, in the energy band structure of the i-type AlInAs multiplication layer 4 itself composed of the digital alloy structure, the position of the conduction band is lower than the n-type AlInAs buffer layer 3 on the substrate side or the electric field relaxation layer 5, which may become a barrier for electrons.

[0140] In such a state, the electrons amplified in the i-type AlInAs multiplication layer 4 composed of the digital alloy structure are conducted as carriers to the p-type InGaAs contact layer 9. Energy is required to cross the electron potential barrier between the n-type AlInAs buffer layer 3 and the n-type InP substrate 2, which may become an obstacle to the high-speed operation of the SACM type APD at low voltage.

[0141] like Figure 6As shown, in the SACM type APD, which is an example of the semiconductor light receiving element 130 involved in the fourth embodiment, a semiconductor light receiving element 130 having a band gap energy Eg of the i-type AlInAs multiplication layer 4 and a band gap energy Eg of the n-type AlInAs buffer layer 3 are inserted between the i-type AlInAs multiplication layer 4 and the n-type AlInAs buffer layer 3 composed of a digital alloy structure. s The band gap energy Eg n That is, Eg>Eg n >Eg s The semiconductor material of this relationship is Al x Ga y In 1－x－y The second transition layer 23 composed of As (x=0.25, y=0.218) and having a thickness of about 15 nm can reduce the electron barrier ΔEc when the electrons passing through the i-type AlInAs multiplication layer 4 are conducted to the p-type InGaAs contact layer 9, thereby achieving the effect of enabling high-speed operation.

[0142] Fig. 7A , Figure 7B 2 is a diagram for explaining the relationship between the band gap energies of the respective layers in the semiconductor light-receiving element according to the fourth embodiment. Fig. 7A A diagram showing a case where there is no second migration layer 23, Figure 7B The figure shows the case where there is a second migration layer 23. Fig. 7A As shown, when the multiplication layer 4 composed of the digital alloy structure is in contact with the buffer layer 3, electrons need to cross the electron barrier ΔEc′ in order to move from the multiplication layer 4 composed of the digital alloy structure to the buffer layer 3.

[0143] On the other hand, Figure 7B As shown, when the second migration layer 23 is provided between the multiplication layer 4 formed by the digital alloy structure and the buffer layer 3, in order for electrons to move from the multiplication layer 4 formed by the digital alloy structure to the second migration layer 23, they only need to cross the electron potential barrier ΔEc3 which is smaller than the electron potential barrier ΔEc'. In addition, in order for electrons to move from the second migration layer 23 to the buffer layer 3, they only need to cross the electron potential barrier ΔEc4 which is smaller than the electron potential barrier ΔEc'. As described above, it can be seen that by providing the second migration layer 23 between the multiplication layer 4 formed by the digital alloy structure and the buffer layer 3, the effective electron potential barrier is reduced.

[0144] Furthermore, by inserting the above-mentioned i-type Al x Ga y In 1－x－y The As second migration layer 23 also has the effect of reducing the stress accumulated in the i-type AlInAs multiplication layer 4 composed of the digital alloy structure.

[0145] In the fourth embodiment, i-type Al is used as an example of a semiconductor material constituting the second transition layer 23. x Ga y In 1－x－y As layer, but as long as the band gap energy Eg of the second transition layer 23 n , the band gap energy Eg of the i-type AlInAs multiplication layer 4, and the band gap energy Eg of the n-type AlInAs buffer layer 3 s Eg>Eg n >Eg s The semiconductor material of this relationship can be similarly applied. In addition, if the second migration layer 23 is composed of layers with the same composition as the layers constituting the digital alloy structure, control becomes easy. In addition, the second migration layer 23 can also be doped with impurities to become a p-type or n-type conductivity type, for example, instead of a non-doped layer as in an example.

[0146] <Effects of Embodiment 4>

[0147] As described above, according to the semiconductor photosensitive element involved in embodiment 4, since the second migration layer is set between the multiplication layer composed of the digital alloy structure and the n-type buffer layer, the electron potential barrier generated between the multiplication layer composed of the digital alloy structure and the n-type buffer layer is reduced, resulting in improved carrier conductivity, thereby achieving the effect of obtaining a semiconductor photosensitive element capable of high-speed operation.

[0148] Implementation method 5

[0149] <Element Structure of Semiconductor Light Receiving Element 140 According to Embodiment 5>

[0150] Figure 8 1 is a cross-sectional view showing the device structure of the semiconductor light receiving device 140 according to Embodiment 5. As an example of the semiconductor light receiving device 140 according to Embodiment 1, a SACM type APD is given.

[0151] The structure of each layer of the semiconductor light-receiving element 140 involved in Embodiment 5 is basically the same as the structure of each layer of the semiconductor light-receiving element 100 involved in Embodiment 1, but the detailed structure of the i-type AlInAs multiplication layer 4d composed of the digital alloy structure is different. Therefore, below, only the structure of the i-type AlInAs multiplication layer 4d composed of the digital alloy structure is described.

[0152] The i-type AlInAs multiplication layer 4d composed of a digital alloy structure has a layer thickness of 0.05 to 0.2 μm and is formed by alternately stacking multiple i-type AlAs layers (as an example, the layer thickness is 2ML) and i-type InAs layers (as an example, the layer thickness is 2ML). Figure 8As shown in FIG. 1 , the i-type AlAs layer is the last layer stacked, i.e., the layer on the outermost surface side, of the i-type AlInAs multiplication layer 4d composed of the digital alloy structure. Such a structure is applied because, of the two layers constituting the i-type AlInAs multiplication layer 4d composed of the digital alloy structure, i.e., the i-type AlAs layer and the i-type InAs layer, the i-type AlAs layer having a larger band gap energy is set as the layer on the outermost surface side.

[0153] The following is a more general description.

[0154] Two layers of different semiconductor materials constituting the i-type AlInAs multiplication layer 4d composed of a digital alloy structure are set as the first semiconductor layer 4a and the second semiconductor layer 4b. Here, the band gap energy Eg1 of the first semiconductor layer 4a is greater than the band gap energy Eg2 of the second semiconductor layer 4b, that is, it is set to Eg1>Eg2. Among them, in the above example, the AlAs layer with a band gap energy Eg1 of 2.12eV becomes the first semiconductor layer 4a, and the InAs layer with a band gap energy Eg2 of 0.36eV ​​becomes the second semiconductor layer 4b.

[0155] The i-type AlInAs multiplication layer 4d composed of the digital alloy structure has a layer thickness of 0.05 to 0.2 μm and is formed by alternately stacking the first semiconductor layer 4a and the second semiconductor layer 4b multiple times, but the last layer stacked, that is, the layer on the outermost surface side of the i-type AlInAs multiplication layer 4d composed of the digital alloy structure becomes the first semiconductor layer 4a. That is, the layer opposite to the p-type AlInAs electric field relaxation layer 5 in the i-type AlInAs multiplication layer 4d composed of the digital alloy structure becomes the first semiconductor layer 4a.

[0156] The method for manufacturing the semiconductor light receiving element 140 according to the fifth embodiment is substantially the same as the method for manufacturing the semiconductor light receiving element 100 according to the first embodiment, and thus a detailed description of the manufacturing method will be omitted.

[0157] <Function of Embodiment 5>

[0158] The electric field intensity distribution in the direction perpendicular to the n-type InP substrate 2 is as follows: Fig. 9 As shown. In the SACM type APD, the electric field strength applied to the i-type AlInAs multiplication layer 4d composed of the digital alloy structure is increased to multiply the carrier avalanche. On the other hand, in order not to multiply the carriers in the n-type InGaAs light absorption layer 6, the p-type AlInAs electric field relaxation layer 5 is used to control the electric field strength to reduce the electric field strength of the n-type InGaAs light absorption layer 6. In this case, the maximum electric field strength E of the i-type AlInAs multiplication layer 4d is maxThe band gap energy Eg of the i-type AlInAs multiplication layer 4d having a digital alloy structure is in a relationship shown in the following formula (4).

[0159]

[0160] From formula (4), it can be seen that the larger the band gap energy Eg of the i-type AlInAs multiplication layer 4d composed of the digital alloy structure, the greater the maximum electric field intensity E max For example, when the i-type AlInAs multiplication layer 4d formed by the digital alloy structure is composed of a binary compound semiconductor material of an InAs layer and an AlAs layer, the maximum electric field intensity E of the entire element can be increased by setting the AlAs layer with a larger band gap energy as the outermost surface layer of the digital alloy structure. max .

[0161] Fig.10 The maximum electric field intensity E is calculated for the case where the outermost surface layer of the i-type AlInAs multiplication layer 4d composed of the digital alloy structure is an AlAs layer and the case where it is an InAs layer. max Figure for comparison. Fig.10 It can be seen that the maximum electric field intensity E when the outermost surface layer is an AlAs layer max 4.4×10 5 kV / cm, whereas the maximum electric field strength E when the outermost layer is an InAs layer max 3.8×10 5 kV / cm, when the outermost surface layer is set as AlAs layer, a larger maximum electric field intensity E max .

[0162] In addition, since a semiconductor material with a larger band gap energy exists on the outermost surface of the multiplication layer, even when a local electric field is generated at the interface between the electric field relaxation layer and the multiplication layer, the resistance to the electric field is enhanced, and the electronic barrier ΔEc that hinders carrier conduction can be reduced.

[0163] In Embodiment 5, as an example, the structure in which the AlAs layer in the i-type AlInAs multiplication layer 4d composed of a digital alloy structure is set as the outermost surface layer is described. However, in the two semiconductor layers constituting the multiplication layer composed of the digital alloy structure, as long as the semiconductor layer with a larger band gap energy is set as the outermost surface layer, the same effect can be achieved. In addition, even if the semiconductor material is not limited, as long as the size relationship of the band gap energy is satisfied, the same effect can be achieved.

[0164] The two semiconductor layers constituting the multiplication layer composed of the digital alloy structure are not limited to the binary compound semiconductor materials shown in the above example. For example, Al x In 1－x As ternary compound semiconductor materials, or Al x Ga y In 1－x－y Furthermore, the multiplication layer may be doped with impurities to become a p-type or n-type conductivity type, instead of being a non-doped layer as shown in the example.

[0165] <Effects of Embodiment 5>

[0166] As described above, according to the semiconductor photosensitive element involved in embodiment 5, since the semiconductor layer with a larger band gap energy among the two semiconductor layers constituting the multiplication layer composed of the digital alloy structure is set as the outermost surface layer, the maximum electric field strength in the multiplication layer composed of the digital alloy structure can be increased, and the control width of the operable voltage can be widened, thereby achieving the effect of obtaining a semiconductor photosensitive element capable of high-speed operation.

[0167] The present disclosure describes various exemplary embodiments and examples, but various features, modes, and functions described in one or more embodiments are not limited to application in specific embodiments and can be applied to the embodiments alone or in various combinations.

[0168] Therefore, numerous modifications not shown in the examples are conceivable within the technical scope disclosed in the present specification, including, for example, the case where at least one component is modified, added, or omitted, and the case where at least one component is extracted and combined with components of other embodiments.

[0169] Description of Reference Numerals

[0170] 1…n-type electrode; 2…n-type InP substrate; 3…n-type AlInAs buffer layer; 4, 4d…i-type AlInAs multiplication layer; 4a…first semiconductor layer; 4b…second semiconductor layer; 5…p-type AlInAs electric field relaxation layer; 6…n-type InGaAs light absorption layer; 7…i-type AlInAs window layer; 8…n-type InP window layer; 9…p-type InGaAs contact layer; 10…Zn selective diffusion region; 11…SiNx surface protection film; 12…p-type electrode; 21…i-type AlInAs strain relaxation layer; 22…i-type Al x Ga y In 1－x－y As first migration layer; 23...i-type Al x Ga y In 1－x－yAs second migration layer; 100, 110, 120, 130, 140 ... semiconductor light receiving element.

Claims

1. A semiconductor light receiving element, characterized in that: have: Semiconductor substrates; A multiplication layer is formed on the semiconductor substrate, and is composed of a digital alloy structure formed by alternately stacking a first semiconductor layer and a second semiconductor layer for multiple times, and amplifies light carriers, wherein the first semiconductor layer is composed of a layer thickness of N times that of a single atomic layer, and the second semiconductor layer is composed of a layer thickness of M times that of a single atomic layer and has a band gap energy smaller than that of the first semiconductor layer, wherein 1≦N≦20, 1≦M≦20; a light absorbing layer, formed on the multiplication layer, absorbing incident light to generate the light carriers; and The electric field relaxation layer is formed between the multiplication layer and the light absorption layer.

2. The semiconductor light receiving element according to claim 1, wherein: The thickness of the first semiconductor layer is N times that of a single atomic layer, and the thickness of the second semiconductor layer is M times that of a single atomic layer, wherein 1≦N≦5, 1≦M≦5.

3. The semiconductor light receiving element according to claim 1 or 2, characterized in that: The first semiconductor layer and the second semiconductor layer are alternately stacked at a number of times greater than or equal to 5 and less than or equal to 300.

4. The semiconductor light-receiving element according to any one of claims 1 to 3, characterized in that: The first semiconductor layer and the second semiconductor layer are an AlAs layer and an InAs layer, respectively.

5. The semiconductor light-receiving element according to any one of claims 1 to 4, characterized in that: The light absorbing layer is composed of InGaAs.

6. The semiconductor light receiving element according to any one of claims 1 to 5, characterized in that The semiconductor light receiving element further includes a strain relaxation layer formed between the electric field multiplication layer and the electric field relaxation layer and relaxing a strain of the electric field multiplication layer.

7. The semiconductor light receiving element according to claim 6, characterized in that The strain relaxation layer is composed of a semiconductor material having the same composition as that of a semiconductor material constituting the multiplication layer.

8. The semiconductor light receiving element according to claim 6 or 7, characterized in that: The strain relaxation layer is composed of AlInAs.

9. The semiconductor light receiving element according to any one of claims 1 to 5, characterized in that The semiconductor light receiving element further includes: a first migration layer formed between the multiplication layer and the electric field relaxation layer, having a band gap energy value between the band gap energy of the multiplication layer and the band gap energy of the electric field relaxation layer, and relaxing the strain of the multiplication layer.

10. The semiconductor light receiving element according to claim 9, characterized in that The first migration layer is made of AlGaInAs.

11. The semiconductor light receiving element according to any one of claims 1 to 5, characterized in that Also available: a buffer layer formed between the semiconductor substrate and the multiplication layer; and The second migration layer is formed between the multiplication layer and the buffer layer, has a band gap energy value between the band gap energy of the multiplication layer and the band gap energy of the buffer layer, and relieves the strain of the multiplication layer.

12. The semiconductor light receiving element according to claim 11, characterized in that The second migration layer is made of AlGaInAs.

13. The semiconductor light receiving element according to any one of claims 1 to 5, characterized in that The layer of the multiplication layer facing the electric field relaxation layer is the first semiconductor layer.

14. A method for manufacturing a semiconductor light-receiving element, characterized in that: The following processes are available: On an n-type InP substrate, a step of sequentially epitaxially growing an n-type AlInAs buffer layer, an AlInAs multiplication layer composed of a digital alloy structure formed by alternately stacking an AlAs layer composed of N times the thickness of a single atomic layer and an InAs layer composed of M times the thickness of a single atomic layer, a p-type AlInAs electric field relaxation layer, an n-type InGaAs light absorption layer, an i-type AlInAs window layer, an n-type InP window layer, and a p-type InGaAs contact layer, wherein 1≦N≦20, 1≦M≦20; and The step of forming a Zn selective diffusion region in a portion of the n-type InP window layer and the i-type AlInAs window layer.

15. The method for manufacturing a semiconductor light-receiving element according to claim 14, wherein: The epitaxial crystal growth is performed by the MOVPE method or the MBE method.

16. The method for manufacturing a semiconductor light-receiving element according to claim 14, wherein: The epitaxial crystal growth is performed by the MOVPE method, and the crystal growth temperature is in the range of 500° C. to 600° C.

17. The method for manufacturing a semiconductor light-receiving element according to any one of claims 14 to 16, characterized in that: The thickness of the AlAs layer is N times that of a single atomic layer, and the thickness of the InAs layer is M times that of a single atomic layer, wherein 1≦N≦5, 1≦M≦5.

18. The method for manufacturing a semiconductor light-receiving element according to any one of claims 14 to 17, characterized in that: The number of times the AlAs layer and the InAs layer are alternately stacked is 5 or more and 300 or less.

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