Negative voltage testing device

Abstract

The invention discloses a negative voltage testing device. The negative voltage testing device comprises a device to be tested and a negative voltage generating circuit, wherein the to-be-tested device is provided with a first interface; the negative voltage generating circuit comprises a first power supply end, a first reference ground end, a capacitor and a first connecting end; the first end of the capacitor is electrically connected with a first power supply end through a first switch and is also electrically connected with a first reference ground end through a second switch; the first connecting end is electrically connected with the second end of the capacitor and is electrically connected with the first interface; when the first switch is switched on and the second switch is switched off, the first power supply end is used for charging the capacitor; when the first switch is turned off and the second switch is turned on, the second end of the capacitor outputs negative voltage to the first interface through the first connecting end. And the negative voltage resistance of the device to be tested is tested, so that the problem that the device is damaged due to the fact that the negative voltage is applied to the device in the application process of the device passing the test is solved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a negative voltage testing device. Background Art

[0002] IGBT (insulated gate bipolar transistor) and driver chips (also called driver ICs) are used in various electronic devices such as but not limited to terminal equipment and inverters due to their advantages such as high efficiency, high voltage resistance, large current handling capability and fast switching speed.

[0003] As various industries have higher requirements for the reliability of IGBTs (insulated gate bipolar transistors, also known as power devices) or driver chips (also known as driver ICs), it is necessary to test the various extreme capabilities of power devices or driver chips.

[0004] However, after a power device or driver chip has passed the test using a current test device, during the application of the power device or driver chip, there may still be a problem of damage to the power device or driver chip due to negative voltage being applied to the power device or driver chip. Summary of the invention

[0005] A series of simplified concepts are introduced in the Summary of the Invention, which will be further described in detail in the Detailed Description of the Invention. The Summary of the Invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0006] The present application aims to address the deficiencies in the prior art, and its main purpose is to provide a negative voltage testing device to test the negative voltage tolerance of a device under test, so as to improve the problem of device damage caused by negative voltage applied to the device during application of the device that has passed the test.

[0007] To achieve the above objectives, this application adopts the following technical solutions:

[0008] In response to the current problems, an embodiment of the present invention provides a negative voltage testing device on the one hand, which includes: a device to be tested and a negative voltage generating circuit; wherein the device to be tested has a first interface; the negative voltage generating circuit includes: a first power supply terminal, a first reference ground terminal, a capacitor and a first connection terminal; the first end of the capacitor is electrically connected to the first power supply terminal through a first switch, and the first end of the capacitor is also electrically connected to the first reference ground terminal through a second switch; the first connection terminal is electrically connected to the second end of the capacitor and is used to electrically connect to the first interface; when the first switch is turned on and the second switch is turned off, the first power supply terminal is used to charge the capacitor; when the first switch is turned off and the second switch is turned on, the second end of the capacitor outputs a negative voltage to the first interface through the first connection terminal.

[0009] The above embodiment has the following beneficial effects: by using a negative voltage generating circuit with a capacitor, when the first switch is turned on and the second switch is turned off, the first power supply end charges the capacitor; by using the principle that the voltage between the first end of the capacitor and the second end of the capacitor cannot change suddenly, when the first switch is turned off and the second switch is turned on, the first end of the capacitor is connected to the first reference ground end, so that the voltage of the first end of the capacitor is 0. At this time, since the voltage between the two ends of the capacitor cannot change suddenly, the voltage of the second end of the capacitor is a negative voltage, so that the second end of the capacitor outputs a negative voltage to the first interface through the first connection end, so as to realize the test of the negative voltage tolerance capability of the device to be tested, so as to test the limit negative voltage tolerance capability of the device to be tested, so as to improve the problem that the device that has passed the test is damaged due to the negative voltage applied to the device during the application process. And the negative voltage generating circuit can be built by a capacitor and two switches, which is low in cost, easy to implement, and easy to operate.

[0010] In some embodiments, another negative voltage testing device is provided, and the negative voltage generating circuit further includes: a first diode, an anode of the first diode is electrically connected to the second end of the capacitor, and a cathode of the first diode is electrically connected to the first reference ground end.

[0011] The above embodiment has the following beneficial effects: by connecting the first diode between the second end of the capacitor and the first reference ground terminal, the current can only flow unidirectionally from the second end of the capacitor to the first reference ground terminal, so that it can act as a charging circuit for the first power supply terminal to charge the capacitor, which not only reduces the resistance value of the charging circuit, but also avoids the defect of short circuit caused by direct connection between the two ends of the capacitor when the capacitor is in a discharging state.

[0012] In some embodiments, another negative voltage testing device is provided, wherein the first diode is a Zener diode.

[0013] The above embodiment has the following beneficial effects: by using a voltage regulator diode as the first diode, a clamping voltage can be provided to perform overvoltage protection.

[0014] In some embodiments, another negative voltage testing device is provided, and the negative voltage generating circuit also includes: a current limiting resistor and a second diode, the first end of the current limiting resistor is connected to the first reference ground terminal; the positive electrode of the second diode is connected to the second end of the current limiting resistor, and the negative electrode of the second diode is connected to the second end of the capacitor and the first connection terminal.

[0015] The above embodiment has the following beneficial effects: by adopting a current limiting resistor and a second diode to form a discharge circuit of the capacitor, the current of the discharge circuit can be limited to avoid overcurrent; at the same time, because the second diode can only allow the current to flow unidirectionally from the first end of the capacitor to the second end of the capacitor, the current limiting resistor does not serve as a charging circuit of the capacitor, thereby reducing the resistance value of the charging circuit.

[0016] In some embodiments, another negative voltage testing device is provided, which also includes: a control device, which is used to control the on and off of the first switch, and the on and off of the second switch; the control device is configured to: based on the target voltage value, control the duration of the first switch being on and the second switch being off, so that the voltage of the capacitor reaches the target voltage value; and control the first switch to be turned off and the second switch to be turned on, so that the second end of the capacitor outputs a negative voltage to the first interface through the first connection end.

[0017] The above embodiment has the following beneficial effects: the control device controls the duration of the first switch being turned on and the second switch being turned off based on the target voltage value, so that the voltage of the capacitor reaches the target voltage value; then the first switch is controlled to be turned off and the second switch is controlled to be turned on, so that the second end of the capacitor outputs a negative voltage to the first interface through the first connection end, thereby outputting negative voltages of different sizes to the device under test by controlling the charging time of the capacitor; when applied, the target voltage value can be gradually increased to gradually increase the charging time of the capacitor, so as to test the ultimate negative voltage tolerance capability of the device under test, and the test process is simple and easy to operate.

[0018] In some embodiments, another negative voltage testing device is provided, wherein the device under test further has a second interface; the negative voltage generating circuit further comprises: a second connection terminal, the second connection terminal is electrically connected to the first reference ground terminal and is used to electrically connect to the second interface of the device under test.

[0019] The above embodiment has the following beneficial effects: by further providing a second connection terminal electrically connected to the first reference ground terminal in the negative voltage generating circuit, the second interface of the device under test can be electrically connected to the second connection terminal to form a loop of the first connection terminal → first interface → second interface → second reference ground terminal, thereby facilitating the application of a negative voltage at the first interface of the device under test.

[0020] In some embodiments, another negative voltage testing device is provided, and the device to be tested is a power device or a driver chip.

[0021] The above embodiment has the following beneficial effects: in the actual application circuit of the power device or driver chip, due to the circuit topology or parasitic parameters, a negative voltage may be applied to the power device or driver chip, resulting in damage to the device. The negative voltage test device shown above is used to test the power device or driver chip, and the ultimate negative voltage tolerance of the power device or driver chip can be tested to improve the problem of device damage caused by negative voltage applied to the device during the application of the power device or driver chip that has passed the test.

[0022] In some embodiments, another negative voltage testing device is provided. When the device under test is a power device, the first interface is a gate of the power device, and one of a source and a drain of the power device is electrically connected to a second power supply terminal.

[0023] The above-mentioned embodiment has the following beneficial effects: by using the gate of the power device as the first interface of the device under test, one of the source and the drain of the power device is electrically connected to the second power supply terminal, thereby forming a loop of the first connection terminal → the first interface → the source or the drain → the second power supply terminal. Without using the second connection terminal in the negative voltage generating circuit, a negative voltage can be applied to the first interface of the device under test, thereby testing the ultimate negative voltage tolerance capability of the gate of the power device.

[0024] In some embodiments, another negative voltage testing device is provided. When the device to be tested is a power device, the first interface is a gate of the power device, and one of a source and a drain of the power device is electrically connected to the second connection terminal.

[0025] The above-mentioned embodiment has the following beneficial effects: by using the gate of the power device as the first interface of the device to be tested, one of the source and the drain of the power device is electrically connected to the second connection terminal, thereby forming a loop of the first connection terminal → the first interface → the source or the drain → the second connection terminal → the first reference ground terminal; even if the power device to be tested is not connected to the second power supply terminal, a negative voltage can be applied to the first interface of the device to be tested, and the ultimate negative voltage tolerance capability of the gate of the power device can be tested, so that the test scenario is not restricted.

[0026] In some embodiments, another negative voltage testing device is provided. When the device under test is a driver chip, the first interface is a floating ground terminal of the driver chip, and the second interface is a second reference ground terminal of the driver chip.

[0027] The above embodiment has the following beneficial effects: by using the floating ground terminal of the driver chip as the first interface of the device under test and the second reference ground terminal of the driver chip as the second interface of the device under test, a loop can be formed between the first connection terminal → floating ground terminal → second reference ground terminal → second connection terminal → first reference ground terminal, so as to apply a negative voltage to the floating ground terminal of the driver chip and test the ultimate negative voltage tolerance capability of the floating ground terminal of the driver chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The following drawings of the present invention are used to understand the present invention as part of the present invention. The embodiments of the present invention are shown in the drawings and the description thereof is used to explain the principle of the present invention.

[0029] In the attached figure:

[0030] Figure 1 A schematic block diagram of a negative voltage testing device according to an embodiment of the present invention is shown;

[0031] Figures 2 to 3 A circuit diagram of a negative voltage test device according to different specific embodiments of the present invention is shown;

[0032] Figure 4 A schematic block diagram of a negative voltage testing device according to another embodiment of the present invention is shown;

[0033] Figure 5 A circuit diagram of a negative voltage testing device according to another specific embodiment of the present invention is shown;

[0034] Figures 6 to 9 Shows circuit schematic diagrams of different specific implementations when the device under test is a power device;

[0035] Fig.10 A circuit schematic diagram is shown when the device under test is a driver chip. DETAILED DESCRIPTION

[0036] In the following description, a large number of specific details are provided to provide a more thorough understanding of the present invention. However, it is apparent to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features well known in the art are not described.

[0037] It should be understood that the present invention can be implemented in different forms and should not be construed as being limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present invention to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals throughout represent the same elements.

[0038] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0039] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be otherwise oriented (rotated or otherwise) and the spatial descriptors used herein are interpreted accordingly.

[0040] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0041] First, let's introduce the application scenarios of the negative voltage test device. Figure 1The negative voltage test device mainly includes a negative voltage generating circuit 100 and a device under test 200. The device under test 200 can be any device with negative voltage tolerance test requirements such as but not limited to power devices, driver devices, etc. The power devices or driver devices can be applied to electronic products such as but not limited to laptops, desktop computers, tablet computers, mobile terminals, smart wearable devices, inverters, power factor correction circuits, voltage converters, etc. The negative voltage generating circuit 200 is mainly used to generate negative voltage.

[0042] In some embodiments, a negative voltage test device is provided, referring to Figure 1 The negative voltage test device comprises: a device under test 200 and a negative voltage generating circuit 100; wherein the device under test 200 has a first interface 201; the negative voltage generating circuit 100 comprises: a first power supply terminal 101, a first reference ground terminal 102, a capacitor 103 and a first connection terminal 106; the first end of the capacitor 103 is electrically connected to the first power supply terminal 101 through a first switch 104, and the first end of the capacitor 103 is also electrically connected to the first reference ground terminal 102 through a second switch 105; the first connection terminal 106 is electrically connected to the second end of the capacitor 103, and is used to electrically connect to the first interface 201; when the first switch 104 is turned on and the second switch 105 is turned off, the first power supply terminal 101 is used to charge the capacitor 103; when the first switch 104 is turned off and the second switch 105 is turned on, the second end of the capacitor 103 outputs a negative voltage to the first interface 201 through the first connection terminal 106.

[0043] The above embodiment has the following beneficial effects: by using the negative voltage generating circuit 100 having the capacitor 103, when the first switch 104 is turned on and the second switch 105 is turned off, the first power supply terminal 101 charges the capacitor 103; by utilizing the principle that the voltage between the first end of the capacitor 103 and the second end of the capacitor 103 cannot suddenly change, when the first switch 104 is turned off and the second switch 105 is turned on, the first end of the capacitor 103 is connected to the first reference ground terminal 102, so that the voltage at the first end of the capacitor 103 suddenly changes to 0. At this time, since the voltage between the two ends of the capacitor 103 cannot suddenly change, the voltage at the second end of the capacitor 103 is a negative voltage, so that the second end of the capacitor 103 outputs a negative voltage to the first interface 201 through the first connection terminal 106, so as to realize the test of the negative voltage tolerance capability of the device under test 200, so as to test the ultimate negative voltage tolerance capability of the device under test 200, so as to improve the problem of device damage caused by negative voltage applied to the device during application of the device that has passed the test. Furthermore, the negative voltage generating circuit 100 can be constructed by using the capacitor 103 and two switches, which is low-cost, easy to implement, and easy to operate.

[0044] In some embodiments, another negative voltage test device is provided, referring to Figure 2 , the negative voltage generating circuit 100 further includes: a first diode, such as Figure 2 D1 in the figure represents the first diode. Figure 2 C1 in the figure represents capacitor 103, as Figure 2 VBUS in the figure represents the first power supply terminal 101 , the anode of the first diode is electrically connected to the second terminal of the capacitor 103 , and the cathode of the first diode is electrically connected to the first reference ground terminal 102 .

[0045] The above embodiment has the following beneficial effects: by connecting the first diode between the second end of the capacitor 103 and the first reference ground terminal 102, the current can only flow unidirectionally from the second end of the capacitor 103 to the first reference ground terminal 102, so that the first power supply terminal 101 can serve as a charging circuit for charging the capacitor 103, which can not only reduce the resistance value of the charging circuit, but also avoid the defect of short circuit caused by direct connection between the two ends of the capacitor 103 when the capacitor 103 is in a discharging state.

[0046] Regarding the type of the first diode, various types of diodes may be employed.

[0047] In some embodiments, another negative voltage test device is provided, referring to Figure 2 , the first diode is a Zener diode.

[0048] The above embodiment has the following beneficial effects: by using a voltage regulator diode as the first diode, a clamping voltage can be provided to perform overvoltage protection.

[0049] In some embodiments, another negative voltage test device is provided, referring to Figure 2 , the negative voltage generating circuit 100 further includes: a current limiting resistor and a second diode, such as Figure 2 R1 in the figure represents the current limiting resistor. Figure 2 D2 in the figure represents a second diode, a first end of the current limiting resistor is connected to the first reference ground terminal 102; a positive electrode of the second diode is connected to a second end of the current limiting resistor, and a negative electrode of the second diode is connected to a second end of the capacitor 103 and a first connection terminal 106 (such as Figure 2 ① in the figure represents the first connection terminal 106).

[0050] The above embodiment has the following beneficial effects: by adopting a current limiting resistor and a second diode to form a discharge circuit of the capacitor 103, the current of the discharge circuit can be limited to avoid overcurrent; at the same time, because the second diode can only allow the current to flow unidirectionally from the first end of the capacitor 103 to the second end of the capacitor 103, the current limiting resistor does not serve as a charging circuit of the capacitor 103, thereby reducing the resistance value of the charging circuit.

[0051] In some embodiments, another negative voltage test device is provided, referring to Figure 3 The negative voltage test device further includes: a control device 108, the control device 108 is used to control the first switch 104 (such as Figure 3 Q1 in the figure represents the on and off of the first switch 104, and the second switch 105 (such as Figure 3 Q2 in the figure represents the on and off of the second switch 105); the control device 108 is configured to: based on the target voltage value, control the duration of the first switch 104 being on and the second switch 105 being off, so that the voltage of the capacitor 103 reaches the target voltage value; and control the first switch 104 to be off and the second switch 105 to be on, so that the second end of the capacitor 103 outputs a negative voltage to the first interface 201 through the first connection terminal 106.

[0052] The above embodiment has the following beneficial effects: the control device 108 controls the duration of the first switch 104 being turned on and the second switch 105 being turned off based on the target voltage value, so that the voltage of the capacitor 103 reaches the target voltage value; then the first switch 104 is controlled to be turned off and the second switch 105 is controlled to be turned on, so that the second end of the capacitor 103 outputs a negative voltage to the first interface 201 through the first connection terminal 106, so that different negative voltages can be output to the device under test 200 by controlling the charging time of the capacitor 103; when applied, the target voltage value can be gradually increased to gradually increase the charging time of the capacitor 103, so as to test the ultimate negative voltage tolerance capability of the device under test 200, and the test process is simple and easy to operate.

[0053] In some embodiments, reference Figure 3 , the control device 108 can adopt a single chip microcomputer, thereby simplifying the structure of the control device 108.

[0054] In some embodiments, another negative voltage test device is provided, referring to Figure 3 The negative voltage generating circuit 100 further includes: a first driving circuit 109 and a second driving circuit 110, such as Figure 3 The driving circuit 1 in FIG. 1 represents the first driving circuit 109, as shown in FIG. Figure 3 The driving circuit 2 in the figure represents the second driving circuit 110. The first driving circuit 109 is connected between the control device 108 and the first switch 104. After the control device 108 generates a PWM signal, it is sent to the first driving circuit 109. After the first driving circuit 109 amplifies the received PWM signal, it drives the first switch 104 to be turned on or off. The second driving circuit 110 is connected between the control device 108 and the second switch 105. After the control device 108 generates a PWM signal, it is sent to the second driving circuit 110. After the second driving circuit 110 amplifies the received PWM signal, it drives the second switch 105 to be turned on or off.

[0055] The above embodiment has the following beneficial effects: by providing a driving circuit between the control device 108 and the switch, the PWM signal generated by the control device 108 is amplified to ensure stable and reliable turning on or off of the switch.

[0056] In some embodiments, reference Figure 3 The first switch 104 (Q1) can be an NMOS switch tube, and the second switch 105 (Q2) can also be an NMOS switch tube. This simplifies the difficulty of setting the first switch 104 (Q1) and the second switch 105 (Q2), and enables the first switch 104 (Q1) and the second switch 105 to support high-frequency on and off control.

[0057] In some other embodiments, the first switch 104 may also be a PMOS switch tube, and the second switch 105 may also be a PMOS switch tube.

[0058] The control method of turning on or off different types of switch tubes is specifically related to the type of PWM signal and driving circuit, and can be specifically adjusted to ensure that one of the first switch 104 and the second switch 105 is turned on while the other is turned off.

[0059] In some embodiments, another negative voltage test device is provided, referring to Figure 4 , the device under test 200 also has a second interface 202; the negative voltage generating circuit 100 also includes: a second connection terminal 107, the second connection terminal 107 is electrically connected to the first reference ground terminal 102, and is used to electrically connect the second interface 202 of the device under test 200.

[0060] The above embodiment has the following beneficial effects: by further providing a second connection terminal 107 electrically connected to the first reference ground terminal 102 in the negative voltage generating circuit 100, the second interface 202 of the device under test 200 can be electrically connected to the second connection terminal 107 to form a loop of the first connection terminal 106 → first interface 201 → second interface 202 → second reference ground terminal, thereby facilitating application of a negative voltage at the first interface 201 of the device under test 200.

[0061] In some embodiments, reference Figure 5 ② in the figure represents the second connection terminal 107. The single chip microcomputer controls the first drive circuit 109 and the second drive circuit 110 through time-sharing, thereby controlling the on and off of the first switch 104 (IGBT-Q1) and the second switch 105 (IGBT-Q2), and charges and discharges the capacitor 103 (C1). By utilizing the principle that the voltage across the capacitor 103 cannot change suddenly, a negative voltage is generated at the first connection terminal 106 (①) and the second connection terminal 107 (②), so as to test the negative voltage tolerance capability of the device under test 200.

[0062] In some embodiments, another negative voltage test device is provided, referring to Figure 6 to Figure 10 , the device under test 200 is a power device or a driver chip. Figure 6 to Figure 9 Q3 in FIG. 1 represents a power device.

[0063] The above embodiment has the following beneficial effects: in the actual application circuit of the power device or driver chip, due to the circuit topology or parasitic parameters, a negative voltage may be applied to the power device or driver chip, resulting in damage to the device. The negative voltage test device shown above is used to test the power device or driver chip, and the ultimate negative voltage tolerance of the power device or driver chip can be tested to improve the problem of device damage caused by negative voltage applied to the device during the application of the power device or driver chip that has passed the test.

[0064] In some embodiments, another negative voltage test device is provided, referring to Figure 6 When the device under test 200 is a power device, the first interface 201 is a gate of the power device, and one of the source and the drain of the power device is electrically connected to the second power supply terminal 203 .

[0065] The above embodiment has the following beneficial effects: by using the gate of the power device as the first interface 201 of the device under test 200, one of the source and the drain of the power device 200 is electrically connected to the second power supply terminal 203, thereby forming a loop of the first connection terminal 106 → the first interface 201 → the source or the drain → the second power supply terminal 203. Without using the second connection terminal 107 in the negative voltage generating circuit 100, a negative voltage can be applied to the first interface 201 of the device under test 200, thereby testing the ultimate negative voltage tolerance capability of the gate of the power device 200.

[0066] In some embodiments, another negative voltage test device is provided, referring to Figure 7 When the device under test 200 is a power device, the first interface 201 is the gate of the power device, and one of the source and the drain of the power device is electrically connected to the second connection terminal 107 (②) of the negative voltage generating circuit 100; wherein the second connection terminal 107 (②) is electrically connected to the first reference ground terminal 102.

[0067] The above embodiment has the following beneficial effects: by using the gate of the power device as the first interface 201 of the device under test 200, one of the source and the drain of the power device is electrically connected to the second connection terminal 107 (②), thereby forming a loop of the first connection terminal 106 (①) → the first interface 201 → the source or the drain → the second connection terminal 107 (②) → the first reference ground terminal 102. Even if the power device under test is not connected to the second power supply terminal 203, a negative voltage can be applied to the first interface 201 of the device under test 200 to test the ultimate negative voltage tolerance capability of the gate of the power device, thereby the test scenario is not restricted.

[0068] Below Figure 8 As an example, a charging process for charging capacitor 103 (C1) is introduced. At this time, IGBT-Q1 is turned on and IGBT-Q2 is turned off. Specifically, the microcontroller sends a PWM signal, the drive circuit 1 works, IGBT-Q1 is turned on, the capacitor 103 (C1) is charged, and the charging current i C1 The path is: VBUS→Q1→C1→D1→GND (first reference ground terminal 102), the voltage Vab=Va-Vb across the capacitor 103 (C1) is charged to the target voltage value, and the conduction time of the IGBT-Q1 can be controlled by setting the pulse width of the PWM signal sent by the microcontroller, that is, the charging time of the capacitor 103 (C1) is controlled, thereby achieving the size of the voltage Vab across the capacitor 103 (C1).

[0069] Below Fig. 9 As an example, a discharge process of capacitor 103 (C1) is introduced. At this time, IGBT-Q2 is turned on and IGBT-Q1 is turned off. Specifically, the microcontroller sends a PWM signal, the drive circuit 2 works, IGBT-Q2 is turned on, the capacitor 103 (C1) is discharged, and the discharge current i C2 The path is: C1→Q2→R1→D2→C1. Due to the characteristic that the capacitor 103 (C1) cannot change suddenly, the voltage across the capacitor 103 (C1) still maintains the target voltage value Vab=Va-Vb in the charging stage. Since the IGBT-Q2 is turned on, Va=0. At this time, Vb=-Vab, that is, a negative voltage appears. This negative voltage is applied to the first interface 201 of the IGBT-Q3 as the device under test 200, to test the negative voltage resistance of the IGBT-Q3. As mentioned above, the single-chip microcomputer can control the size of Vab by controlling the pulse width of the PWM signal. Different negative voltages appear at the first interface 201 and the second interface 202 of the IGBT-Q3, and the extreme negative voltage resistance can be tested.

[0070] In some embodiments, another negative voltage test device is provided, referring to Fig.10When the device under test 200 is a driver chip, the first interface 201 is a floating ground terminal of the driver chip, and the second interface 202 is a second reference ground terminal of the driver chip.

[0071] The above embodiment has the following beneficial effects: by using the floating ground terminal of the driver chip as the first interface 201 of the device under test 200 and the second reference ground terminal of the driver chip as the second interface 202 of the device under test 200, a loop can be formed between the first connection terminal 106 (①) → floating ground terminal → second reference ground terminal → second connection terminal 107 (②) → first reference ground terminal 102, so as to apply a negative voltage to the floating ground terminal of the driver chip, and test the ultimate negative voltage tolerance capability of the floating ground terminal of the driver chip.

[0072] In other embodiments, when the device under test 200 is a driver chip, the first interface 201 may be any pin terminal other than the floating ground terminal and the second reference ground terminal, so as to perform an ultimate negative voltage withstand capability test on various types of pins on the driver chip.

[0073] The present invention has been described by the above embodiments, but it should be understood that the above embodiments are only for the purpose of example and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, it can be understood by those skilled in the art that the present invention is not limited to the above embodiments, and more variations and modifications can be made according to the teachings of the present invention, and these variations and modifications all fall within the scope of the protection claimed by the present invention. The protection scope of the present invention is defined by the attached claims and their equivalents.

Claims

1. A negative voltage test device, characterized in that: include: The device under test has a first interface; A negative voltage generating circuit, the negative voltage generating circuit comprising: a first power supply terminal; A first reference ground terminal; a capacitor, wherein a first end of the capacitor is electrically connected to the first power supply end through a first switch, and the first end of the capacitor is also electrically connected to the first reference ground end through a second switch; and A first connection end, electrically connected to the second end of the capacitor and used to electrically connect to the first interface; Wherein, when the first switch is turned on and the second switch is turned off, the first power supply end is used to charge the capacitor; When the first switch is turned off and the second switch is turned on, the second end of the capacitor outputs a negative voltage to the first interface through the first connection end.

2. The negative voltage testing device according to claim 1, characterized in that: The negative voltage generating circuit further includes: A first diode, wherein an anode of the first diode is electrically connected to the second end of the capacitor, and a cathode of the first diode is electrically connected to the first reference ground end.

3. The negative voltage testing device according to claim 2, characterized in that: The first diode is a voltage regulator diode.

4. The negative voltage testing device according to claim 1, characterized in that: The negative voltage generating circuit further includes: a current limiting resistor, a first end of which is connected to the first reference ground end; and A second diode, wherein an anode of the second diode is connected to the second end of the current limiting resistor, and a cathode of the second diode is connected to the second end of the capacitor and the first connection end.

5. The negative voltage testing device according to claim 1, characterized in that: Also includes: A control device, used for controlling the on and off of the first switch and the on and off of the second switch; The control device is configured to: Based on a target voltage value, controlling the duration during which the first switch is turned on and the second switch is turned off so that the voltage of the capacitor reaches the target voltage value; as well as, The first switch is controlled to be turned off and the second switch is controlled to be turned on, so that the second end of the capacitor outputs a negative voltage to the first interface through the first connection end.

6. The negative voltage testing device according to claim 1, characterized in that: The device under test also has a second interface; The negative voltage generating circuit further includes: The second connection terminal is electrically connected to the first reference ground terminal and is used to electrically connect to the second interface of the device under test.

7. The negative voltage testing device according to claim 6, characterized in that: The device under test is a power device or a driver chip.

8. The negative voltage testing device according to claim 7, characterized in that: When the device under test is a power device, the first interface is a gate of the power device, and one of a source and a drain of the power device is electrically connected to a second power supply terminal.

9. The negative voltage testing device according to claim 7, characterized in that: When the device under test is a power device, the first interface is a gate of the power device, and one of a source and a drain of the power device is electrically connected to the second connection end.

10. The negative voltage testing device according to claim 7, characterized in that: When the device under test is a driver chip, the first interface is a floating ground terminal of the driver chip, and the second interface is a second reference ground terminal of the driver chip.

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