Clock signal transmission method and device, server, storage medium and program product

Abstract

The invention provides a clock signal transmission method and device, a server, a storage medium and a program product. The method comprises the following steps: under the condition of switching on a power supply, receiving signals of each processing card based on each signal detection pin, respectively determining the type of each processing card based on each signal, transmitting a clock signal to the first processing card based on a first clock signal transmission strategy when the processing card is the first processing card, and transmitting a clock signal to the second processing card based on a second clock signal transmission strategy when the processing card is the second processing card. And transmitting the clock signal to the second processing card based on the second clock signal transmission strategy. According to the method, the server can support clock signal synchronization of different types of processing cards at the same time, and the development cost of the server is reduced.

Description

Technical Field

[0001] The present application relates to the field of data processing, and in particular to a clock signal transmission method, device, server, storage medium and program product. Background Art

[0002] With the rapid development of data, various industries and fields have higher and higher requirements for data processing capabilities. As a data processing center, the server can realize different functions through processing cards. For example, embedded processor cards (such as DPU cards) can be used to perform data processing functions.

[0003] When the server realizes the data processing function through the processing card, it is necessary to provide a stable clock signal to the processing card to ensure the synchronization of data processing.

[0004] However, different processing cards have different clock signal synchronization requirements, and existing servers cannot adapt to the clock signal synchronization requirements of multiple processing cards at the same time, which increases the development cost of the server and affects the server development efficiency. Summary of the invention

[0005] The present application provides a clock signal transmission method, device, server, storage medium and program product to solve the technical problem that the relevant server cannot adapt to the clock signal synchronization requirements of multiple processing cards at the same time.

[0006] In a first aspect, the present application provides a clock signal transmission method, which is applied to a server, wherein a plurality of signal detection pin connectors are arranged on a mainboard of the server, and each of the signal detection pin connectors is respectively connected to a signal detection pin;

[0007] The clock signal transmission method comprises:

[0008] When the power is turned on, the signal of each processing card is received based on each signal detection pin;

[0009] Based on the signals, respectively determine the type of each processing card;

[0010] When the processing card is a first processing card, transmitting a clock signal to the first processing card based on a first clock signal transmission strategy;

[0011] When the processing card is a second processing card, the clock signal is transmitted to the second processing card based on a second clock signal transmission strategy.

[0012] Optionally, in the method as described above, when the processing card is a first processing card, transmitting the clock signal to the first processing card based on the first clock signal transmission strategy includes:

[0013] When the processing card is a first processing card, starting a clock generator and determining a working state of the server;

[0014] When the working state is a first state, the clock signal is sent to the first processing card through the clock generator; wherein the first state is used to indicate a standby state.

[0015] When the processing card is determined to be the first processing card by analyzing the signal of the processing card, the signal transmission mode is determined according to the working state of the server based on the characteristics of the first processing card. When the working state is the standby state, the clock signal synchronization of the first processing card is realized by starting and controlling the clock generator to send a clock signal to the first processing card, so that the first processing card can synchronize the data flow and the control flow to realize the data processing function.

[0016] Optionally, the method as described above, when the working state is the first state, after the clock generator sends the clock signal to the first processing card, further comprises:

[0017] When a start signal is received, the working state is updated to a second state; wherein the second state is used to indicate a start state.

[0018] Optionally, in the method as described above, when the processing card is a second processing card, transmitting the clock signal to the second processing card based on the second clock signal transmission strategy includes:

[0019] When the processing card is a second processing card and the working state of the server is a second state, starting a clock generator;

[0020] The clock signal is sent to the second processing card and the central processing unit through the clock generator.

[0021] When the processing card is determined to be the first processing card by analyzing the signal of the processing card, the signal transmission mode is determined according to the working state of the server based on the characteristics of the first processing card. Only when the working state is the power-on state, the clock signal is sent to the second processing card and the central processor through the clock generator to achieve clock signal synchronization of the second processing card, so that the second processing card can work normally.

[0022] Optionally, the method as described above, based on each of the signals, respectively determining the type of each of the processing cards, comprises:

[0023] When it is detected that the level of the signal changes within a preset time period, it is determined that the processing card corresponding to the signal is the first processing card.

[0024] The type of the current processing card is analyzed based on the signal change characteristics of the first processing card, and the processing card is determined to be the first processing card only when the signal level changes within a preset time period, thereby improving the recognition accuracy of the processing card type.

[0025] Optionally, the method as described above, based on each of the signals, respectively determining the type of each of the processing cards, further comprises:

[0026] When it is detected that the signal has no level change within a preset time period, it is determined that the processing card corresponding to the signal is the second processing card.

[0027] The type of the current processing card is analyzed based on the signal change characteristics of the first processing card. If the signal level does not change within a preset time, the processing card is determined to be the second processing card, thereby improving the efficiency of processing card type identification.

[0028] In a second aspect, the present application provides a clock signal transmission device, which is applied to a server, wherein a plurality of signal detection pin connectors are arranged on a mainboard of the server, and each of the signal detection pin connectors is respectively connected to a signal detection pin;

[0029] The clock signal transmission device comprises:

[0030] A signal receiving module, used for receiving signals from each processing card based on each of the signal detection pins when the power is turned on;

[0031] A signal detection module, used to determine the type of each processing card based on each signal;

[0032] A first transmission module, configured to transmit a clock signal to the first processing card based on a first clock signal transmission strategy when the processing card is a first processing card;

[0033] The second transmission module is configured to transmit the clock signal to the second processing card based on a second clock signal transmission strategy when the processing card is a second processing card.

[0034] In a third aspect, an embodiment of the present application provides a server, comprising: a mainboard, a processor, and a memory connected to the processor in communication; a plurality of signal detection pin connectors are provided on the mainboard, each of the signal detection pin connectors is connected to a signal detection pin, and the signal detection pin is used to receive a signal from a processing card;

[0035] The memory stores computer-executable instructions; the processor executes the computer-executable instructions stored in the memory, so that the processor executes the clock signal transmission method described in the first aspect and various possible designs of the first aspect.

[0036] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, in which computer execution instructions are stored. When a processor executes the computer execution instructions, the clock signal transmission method described in the first aspect and various possible designs of the first aspect is implemented.

[0037] In a fifth aspect, an embodiment of the present application provides a computer program product, including a computer program. When the computer program is executed by a processor, it implements the clock signal transmission method described in the first aspect and various possible designs of the first aspect.

[0038] The present application provides a clock signal transmission method, device, server, storage medium and program product. When the server is powered on, the server receives the signal of each processing card based on each signal detection pin, and determines the type of each processing card based on each signal. When the processing card is the first processing card, the server transmits the clock signal to the first processing card based on the first clock signal transmission strategy, and when the processing card is the second processing card, the server transmits the clock signal to the second processing card based on the second clock signal transmission strategy. In this way, the server can receive the signal of the processing card through the signal detection pin connected to each signal detection pin connector to determine the type of each processing card, thereby determining different signal transmission strategies based on the type of each processing card to transmit the clock signal to each processing card, so that the server can simultaneously support the clock signal synchronization of different types of processing cards, reducing the development cost of the server. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0040] Figure 1 A schematic diagram of a clock signal synchronization method in the prior art;

[0041] Figure 2 A schematic diagram of a clock signal transmission method according to an embodiment of the present invention;

[0042] Figure 3 A flowchart of step S103 of the clock signal transmission method provided in an embodiment of the present application;

[0043] Figure 4 A schematic diagram of clock signal transmission on a server motherboard provided in an embodiment of the present application;

[0044] Figure 5 Another schematic diagram of the process of step S103 of the clock signal transmission method provided in an embodiment of the present application;

[0045] Figure 6A flowchart of step S104 of the clock signal transmission method provided in an embodiment of the present application;

[0046] Figure 7 Another schematic diagram of clock signal transmission on a server motherboard provided in an embodiment of the present application;

[0047] Figure 8 A schematic diagram of the structure of a clock signal transmission device provided in an embodiment of the present application;

[0048] Fig. 9 A schematic diagram of the structure of a server provided in an embodiment of the present application.

[0049] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0050] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0051] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in one or more embodiments of this specification are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant laws, regulations and standards, and corresponding operation entrances shall be provided for users to choose to authorize or refuse.

[0052] Definition of terms:

[0053] Data Processing Unit (DPU) refers to a processor designed specifically for data centers. The data processor is used to undertake workloads such as virtualization, networking, storage, and security, freeing up central processing unit (CPU) resources to run more business applications. The DPU card contains a processor chip and an out-of-band management chip. The DPU card runs as an independent subsystem in the server system. When processing high-speed network data packets, the DPU card requires a precise clock signal to synchronize the data flow and control flow. The DPU card is usually connected to the server through a PCIe interface and has an independent hardware acceleration function. Based on this, the DPU card can also be called a special standard PCIe card.

[0054] PCIe refers to a high-speed serial computer expansion bus. Standard PCIe cards can be used to process high-speed network data packets and storage offload chips.

[0055] Complex Programmable Logic Device (CPLD).

[0056] With the rapid development of data, various industries and fields (such as virtualization, network, storage, security services, etc.) have higher and higher requirements for data processing capabilities. As a data processing center, the server can realize different functions through different processing cards. For example, embedded processor cards (such as DPU cards) can be used to realize data processing functions.

[0057] In the process of the server realizing the data processing function through the processing card, it is necessary to provide a stable clock signal to the processing card to ensure the synchronization of data processing.

[0058] However, different processing cards have different requirements for clock signal synchronization. Taking the DPU card and PCIe standard card as an example, when the server is in a normal startup working state, it needs to provide a clock signal to the PCIe standard card. When the server is in a standby state (such as shutdown or downtime), it still needs to provide a clock signal to the DPU card to achieve clock signal synchronization of the DPU card, ensure the normal operation of the DPU card, and bear the task load.

[0059] Based on this, general servers cannot adapt to the clock signal synchronization requirements of PCIe standard cards and DPU cards at the same time, that is, the PCIe slots on the same motherboard on the server usually cannot support PCIe standard cards and DPU cards at the same time. This increases the development cost of the server and affects the efficiency of server development.

[0060] Figure 1 A schematic diagram of a clock signal synchronization method in the prior art is provided as an example. Figure 1 When the server detects that a processing card is connected to the card slot and is in the power-on state, the clock generator can send a clock signal to the processing card. When the server is in the standby state (such as the shutdown state or the downtime state), the clock generator cannot output the clock signal, and the processing card connected to the card slot stops working. This causes the server to be unable to make the DPU work normally in the standby state.

[0061] If the server needs to meet the requirements of the DPU card clock signal, it is necessary to modify the hardware and circuits of the server motherboard and develop the server motherboard, which increases the development cost.

[0062] In view of the above problems, the embodiments of the present application provide a clock signal transmission method, device, server, storage medium and program product, the method comprising: when the server is powered on, receiving the signal of each processing card based on each signal detection pin, determining the type of each processing card based on each signal, transmitting the clock signal to the first processing card based on the first clock signal transmission strategy when the processing card is the first processing card, and transmitting the clock signal to the second processing card based on the second clock signal transmission strategy when the processing card is the second processing card. In this way, the server can receive the signal of the processing card through the signal detection pin connected to the signal detection pin connector to determine the type of each processing card, thereby determining different signal transmission strategies based on the type of each processing card to transmit the clock signal to each processing card, so that the server supports the clock signal synchronization of different types of processing cards at the same time, reducing the development cost of the server.

[0063] The above method can be applied to a server with a signal detection pin on the mainboard. The mainboard of the server is provided with a plurality of signal detection pin connectors, and each signal detection pin connector is connected to a signal detection pin (PIN).

[0064] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0065] Figure 2 A flowchart of a clock signal transmission method provided in an embodiment of the present application. Figure 2 , a clock signal transmission method, comprising the following steps:

[0066] S101, when the power is turned on, receiving the signal of each processing card based on each signal detection pin.

[0067] Specifically, a plurality of signal detection pin connectors are provided on the server motherboard, and each signal detection connector is connected to a signal detection pin, wherein the signal detection pin (PIN) can also be called a signal detection pin. The signal detection pin is mainly used to receive the signal of the processing card, so that the server can determine the type of each processing card based on the signal of the processing card.

[0068] Optionally, a card slot can be set on the server motherboard, and a signal detection pin connector and a signal detection connector can be set on the card slot, so that when a processing card is installed on the card slot, the type of the processing card currently installed on the card slot can be identified through the signal detection connector connected to the signal detection pin connector on the card slot.

[0069] Taking the processing card as a DPU card and a standard PCIe card as an example, the DPU card has a detection pin different from that of the standard PCIe card. By setting the signal detection pin, the signal change can be identified through the above pin, thereby determining the DPU card.

[0070] It is understandable that other pins may be provided on the server mainboard to realize the signal transmission function.

[0071] Specifically, when the power is on, the working state of the server includes a startup state and a non-startup state. Among them, the startup state is used to indicate that the server is connected to the power supply and is in a normal startup working state. The non-startup state is used to indicate that the server is connected to the power supply but is not normally started, such as a shutdown state or a downtime state. When the power is on, whether in the startup state or the non-startup state, the power supply will provide a small amount of electricity to the motherboard. Therefore, when the power is on, the server can receive a signal from the processing card by setting one or more pins.

[0072] It is understandable that when the power is not turned on, the server is in a power-off state and cannot receive the signal from the processing card.

[0073] S102: Based on the signals, determine the type of each processing card.

[0074] Specifically, based on the signal of the processing card received by each signal detection pin, the type of each processing card on the server mainboard is determined.

[0075] Exemplarily, the types of processing cards include a first processing card and a second processing card, and the signal of the first processing card received by the signal detector is different from the signal of the second processing card. Moreover, the first processing card and the second processing card have different requirements for clock signal synchronization of the server.

[0076] S103: When the processing card is a first processing card, transmit a clock signal to the first processing card based on a first clock signal transmission strategy.

[0077] Specifically, when the processing card is determined to be the first processing card based on the signal received by the signal detection needle, the clock signal is transmitted based on the first clock signal transmission strategy. The first clock signal transmission strategy is used to indicate the way in which the server transmits the clock signal to the first processing card when the installed processing card is the first processing card.

[0078] As an example but not limitation, during the clock signal transmission process, the type of each processing card can be determined by the CPLD set on the server motherboard, thereby determining the clock signal transmission strategy to control the clock generator to send the clock signal to the processing card, thereby achieving clock signal synchronization of each processing card, so that each processing card can work normally.

[0079] S104: When the processing card is a second processing card, transmit the clock signal to the second processing card based on a second clock signal transmission strategy.

[0080] Specifically, when it is determined that the processing card is the second processing card based on the signal received by the signal detection needle, the clock signal is transmitted to the second processing card based on the second clock signal transmission strategy to achieve clock signal synchronization of the second processing card. The second clock signal transmission strategy is used to indicate the way in which the server transmits the clock signal to the second processing card when the installed processing card is the second processing card.

[0081] The signal from the processing card is received by the signal detection needle to determine the type of the processing card, and then different signal transmission strategies are determined based on the type of the processing card to transmit the clock signal to the processing card, so that the server can simultaneously support the clock signal synchronization of different types of processing cards, reducing the development cost of the server.

[0082] Figure 3 This is a flow chart of step S103 of the clock signal transmission method provided in the embodiment of the present application. Figure 3 The clock signal transmission method step S103 comprises the following steps, including:

[0083] S1031, when the processing card is the first processing card, starting a clock generator and determining a working state of the server;

[0084] S1032. When the working state is a first state, send the clock signal to a first processing card through the clock generator; wherein the first state is used to indicate a standby state.

[0085] Specifically, the first processing card is used to indicate that when the server is in a standby state, the server needs to provide a clock signal to it to achieve clock signal synchronization. For example, the first processing card is a DPU card. Based on this, when the processing card is determined to be the first processing card based on the signal received by the signal detection needle, it is necessary to start the clock generator and determine the working state of the server. In this way, when the working state of the server is the first state, the clock signal can be sent to the first processing card through the clock generator, so that the first processing card synchronizes the data flow and the control flow based on the precise clock signal, that is, the first processing card works normally.

[0086] Figure 4 A schematic diagram of clock signal transmission on a server motherboard provided in an embodiment of the present application.

[0087] like Figure 4 The mainboard of the server shown is provided with a complex programmable logic device CPLD, a clock generator, a CPU and two card slots and corresponding signal detection connectors, each card slot is provided with a corresponding signal detection connector, and each signal detection connector is connected to a signal detection pin. At this time, the processing card installed on the card slot 1 is the first processing card, and the processing card installed on the card slot 2 is the second processing card.

[0088] When the server is connected to a power source, the power source will provide a small amount of power to the motherboard ( Figure 4 In the figure, the current is used as an example. At this time, the signal of the first processing card can be received based on the signal detection pin connected to the signal detection connector corresponding to the card slot 1, and the signal of the second processing card can be received based on the signal detection pin connected to the signal detection connector corresponding to the card slot 2, and the signal of the first processing card and the signal of the second processing card can be sent to the CPLD. The CPLD determines to send a clock signal to the first processing card on the card slot 1 based on the first clock signal transmission strategy according to the signal of the first processing card, and determines to send a clock signal to the second processing card on the card slot 2 based on the second clock signal transmission strategy according to the signal of the second processing card, and obtains the working status of the server at the same time.

[0089] When the server is in the standby state, the CPLD sends a first control signal to the clock generator to start the clock generator, and controls the clock generator to send a clock signal 1 to the first processing card on the card slot 1, so as to achieve clock synchronization of the first processing card on the card slot 1. At this time, the clock signal is not sent to the second processing card on the card slot 2 through the clock generator.

[0090] When the CPLD receives the startup instruction, the CPLD sends the startup instruction to the CPU to instruct the CPU to start, and at the same time updates the working state to the startup state.

[0091] At this time, the CPLD sends a second control signal and a third control signal to the clock generator to achieve clock synchronization of the second processing card on the card slot 2. The second control signal is used to control the clock generator to send a clock signal 2 to the second processing card on the card slot 2. The third control signal is used to control the clock generator to send a clock signal to the CPU.

[0092] Figure 5 Another flowchart of step S103 of the clock signal transmission method provided in the embodiment of the present application. Figure 5 After step S1032, the clock signal transmission method step S103 further includes the following steps:

[0093] S10323. When a start signal is received, update the working state to a second state; wherein the second state is used to indicate a start state.

[0094] Specifically, when the processing card on the card slot is determined to be the first processing card based on the signal received by the signal detection needle and the server receives the startup signal, the server working state is updated to the second state, that is, the startup state.

[0095] It is understandable that a clock generator can send a clock signal to one or more processing cards at the same time. Based on this, there can be one or more clock generators on the server motherboard. When the number of clock generators and processing cards is the same, a one-to-one mapping relationship between the clock generator processing cards can be established.

[0096] Figure 6 This is a flow chart of step S104 of the clock signal transmission method provided in the embodiment of the present application. Figure 6 , the clock signal transmission method step S104 includes:

[0097] S1041, when the processing card is a second processing card and the working state of the server is a second state, starting a clock generator;

[0098] S1042: Send the clock signal to the second processing card and the central processing unit through the clock generator.

[0099] Specifically, the second processing card is used to indicate that when the server is in the startup state, the server needs to provide a clock signal to it to achieve clock signal synchronization. That is to say, when the server is in the standby state, there is no need to provide a clock signal to the second processing card. When the signal detection needle receives that the processing card is the second processing card and the server is in the standby state, the clock generator is turned off and the clock signal is not sent to the second processing card through the clock generator.

[0100] Specifically, when the processing card is determined to be the second processing card based on the signal received by the signal detection needle, and when it is detected that the working state of the server is updated to the second state, it is determined that the server needs to send a clock signal to the currently installed second processing card. Based on this, the clock generator is started, and the clock signal is sent to the second processing card and the central processor through the clock generator.

[0101] Figure 7 Another schematic diagram of clock signal transmission on a server motherboard provided in an embodiment of the present application.

[0102] like Figure 7 The mainboard of the server shown in the figure is provided with a complex programmable logic device CPLD, a clock generator, a CPU and two card slots and corresponding signal detection connectors, and the signal detection connector corresponding to each card slot is respectively connected to a signal detection pin. At this time, the processing cards installed on the card slot 1 and the card slot 2 are both second processing cards.

[0103] When the server is connected to a power source, the power source will provide a small amount of power to the motherboard ( Figure 7 In the figure, the current is used as an example. At this time, the signal of the second processing card can be received based on the signal detection pin connected to the signal detection connector corresponding to the card slot 1, and the signal of the second processing card can be received based on the signal detection pin connected to the signal detection connector corresponding to the card slot 2, and the signal of the second processing card can be sent to the CPLD. The CPLD determines to send a clock signal to the second processing card on the card slot 1 based on the second clock signal transmission strategy according to the signal of the second processing card, and determines to send a clock signal to the second processing card on the card slot 2 based on the second clock signal transmission strategy according to the signal of the second processing card, and obtains the working status of the server at the same time.

[0104] When the server is in a standby state, the CPLD does not send a control signal to the clock generator, that is, the clock signal is not sent to the processing card on the card slot 1 or the card slot 2 through the clock generator.

[0105] When the CPLD receives the startup instruction, the CPLD sends the startup instruction to the CPU to instruct the CPU to start, and at the same time updates the working state to the startup state.

[0106] At this time, the CPLD sends a second control signal, a third control signal, and a fourth control signal to the clock generator to achieve clock synchronization of the second processing cards on the card slot 1 and the card slot 2. Among them, the second control signal is used to control the clock generator to send a clock signal 3 to the second processing card on the card slot 2. The third control signal is used to control the clock generator to send a clock signal 3 to the CPU. The fourth control signal is used to control the clock generator to send a clock signal 3 to the second processing card on the card slot 1.

[0107] In some embodiments, step S101 includes:

[0108] When it is detected that the level of the signal changes within a preset time period, it is determined that the processing card corresponding to the signal is the first processing card.

[0109] Specifically, when the power is turned on, whether in the startup state or the non-startup state, the power supply will provide a small amount of electricity to the mainboard. Based on this, the CPLD on the mainboard can work normally, and the signal received by the signal detection pin will be continuously pulled high due to the pull-up resistor of the mainboard. When the first processing card is installed, the signal received by the signal detection pin will be pulled low by the first processing card. In other words, the first processing card will cause the signal received by the signal detection pin to change from high to low.

[0110] Based on this, when the signal detector receives a signal with a level change within a preset time period, it can be determined that the current processing card is the first processing card.

[0111] The preset time length may be specifically set according to actual conditions, for example, the preset time length may be set to 10 ms, or the preset time length may be set to 1 s.

[0112] In some embodiments, step S102 further includes:

[0113] When it is detected that the signal has no level change within a preset time period, it is determined that the processing card corresponding to the signal is the second processing card.

[0114] Specifically, referring to the above, it can be seen that when the power is turned on, whether it is in the startup state or the non-startup state, the power supply will provide a small amount of electricity to the mainboard. Based on this, the CPLD can work normally. Due to the pull-up resistor of the mainboard, the signal received by the signal detection needle is a stable high level. When the first processing card is not installed (such as the second processing card is installed), the signal received by the signal detection needle will not be pulled low. In other words, when the signal received by the signal detection needle is a stable high level within a preset time, it can be determined that the installed processing card is the second processing card.

[0115] It should be noted that, for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the described order of actions, because according to the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily required by the present application.

[0116] It should be further noted that, although the various steps in the flow chart are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the flow chart may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these sub-steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0117] Figure 8 The clock signal transmission device can be applied to a server, and a plurality of signal detection connectors are arranged on the main board of the server, and each signal detection connector is connected to a signal detection pin.

[0118] See also Figure 8 , a clock signal transmission device, comprising:

[0119] The signal receiving module 801 is used to receive the signal of each processing card based on each signal detection pin when the power is turned on;

[0120] A signal detection module 802, configured to determine the type of each processing card based on each signal;

[0121] A first transmission module 803, configured to transmit a clock signal to the first processing card based on a first clock signal transmission strategy when the processing card is a first processing card;

[0122] The second transmission module 804 is configured to transmit the clock signal to the second processing card based on a second clock signal transmission strategy when the processing card is a second processing card.

[0123] In some embodiments, the first transmission module includes:

[0124] a first starting unit, used for starting a clock generator and determining a working state of the server when the processing card is a first processing card;

[0125] The first sending unit is used to send the clock signal to the first processing card through the clock generator when the working state is a first state; wherein the first state is used to indicate a standby state.

[0126] In some embodiments, the first transmission module further includes:

[0127] The state updating unit is used to update the working state to a second state when receiving a start signal; wherein the second state is used to indicate a start state.

[0128] In some embodiments, the second transmission module includes:

[0129] A second starting unit, used for starting a clock generator when the processing card is a second processing card and the working state of the server is a second state;

[0130] The second sending unit is used to send the clock signal to the second processing card and the central processing unit through the clock generator.

[0131] In some embodiments, the signal detection module is specifically configured to determine that the processing card corresponding to the signal is the first processing card when detecting that the level of the signal changes within a preset time period.

[0132] In some embodiments, the signal detection module is specifically configured to determine that the processing card corresponding to the signal is the second processing card when it is detected that the signal has no level change within a preset time period.

[0133] It should be understood that the above-mentioned device embodiments are only illustrative, and the device of the present application can also be implemented in other ways. For example, the division of units / modules in the above-mentioned embodiments is only a logical function division, and there may be other division methods in actual implementation. For example, multiple units, modules or components can be combined, or can be integrated into another system, or some features can be ignored or not executed.

[0134] In addition, unless otherwise specified, each functional unit / module in each embodiment of the present application may be integrated into one unit / module, each unit / module may exist physically separately, or two or more units / modules may be integrated together. The above-mentioned integrated unit / module may be implemented in the form of hardware or in the form of a software program module.

[0135] If the integrated unit / module is implemented in the form of hardware, the hardware may be a digital circuit, an analog circuit, etc. The physical implementation of the hardware structure includes but is not limited to transistors, memristors, etc. Unless otherwise specified, the processor may be any appropriate hardware processor, such as a CPU, a GPU, an FPGA, a DSP, an ASIC, etc. Unless otherwise specified, the storage unit may be any appropriate magnetic storage medium or magneto-optical storage medium, such as a resistive random access memory (RRAM), a dynamic random access memory (DRAM), a static random access memory (SRAM), an enhanced dynamic random access memory (EDRAM), a high-bandwidth memory (HBM), a hybrid memory cube (HMC), etc.

[0136] If the integrated unit / module is implemented in the form of a software program module and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a memory, including a number of instructions to enable a computer device (which can be a personal computer, server or network device, etc.) to execute all or part of the steps of the various embodiments of the present application. The aforementioned memory includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, disk or optical disk and other media that can store program codes.

[0137] Fig. 9 This is a schematic diagram of the structure of the server provided in the embodiment of the present application. Fig. 9 As shown, the server may include: a transceiver 901 , a processor 902 , a memory 903 , and a mainboard 904 .

[0138] like Fig. 9 As shown, the transceiver 901 , processor 902 , and memory 903 may all be disposed on a mainboard 904 .

[0139] The main board 904 is provided with a plurality of card slots 9041 ( Fig. 9Only two are shown in the figure), each card slot 9041 is provided with a signal detection pin connector 9043, each signal detection pin connector 9043 is respectively connected to a signal detection pin 9042, and the signal detection pin 9042 connected to the signal detection pin connector 9043 is used to receive the signal of the processing card installed on the card slot 9041. Each signal detection pin connector 9043 can be connected to the transceiver 901, the processor 902, and the memory 903 through the system bus.

[0140] The processor 902 executes the computer execution instructions stored in the memory, so that the processor 902 executes the scheme in the above embodiment. The processor 902 can be a general-purpose processor, including a central processing unit CPU, a network processor (network processor, NP), etc.; it can also be a digital signal processor DSP, an application-specific integrated circuit ASIC, a field programmable gate array FPGA or other programmable logic devices, discrete gates or transistor logic devices, and discrete hardware components.

[0141] The memory 903 is connected to the processor 902 via a system bus and completes communication between them. The memory 903 is used to store computer program instructions.

[0142] The transceiver 901 may be used to obtain a start signal, etc.

[0143] The system bus can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The system bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus. The transceiver is used to realize the communication between the database access device and other computers (such as clients, read-write libraries, and read-only libraries). The memory may include random access memory (RAM) and may also include non-volatile memory.

[0144] An embodiment of the present application further provides a computer-readable storage medium, in which computer instructions are stored. When the computer instructions are executed on a computer, the computer executes the technical solution of the clock signal transmission method in the above embodiment.

[0145] An embodiment of the present application also provides a computer program product, which includes a computer program stored in a computer-readable storage medium. At least one processor can read the computer program from the computer-readable storage medium. When at least one processor executes the computer program, the technical solution of the clock signal transmission method in the above embodiment can be implemented.

[0146] In the above embodiments, the description of each embodiment has its own emphasis. For parts not described in detail in a certain embodiment, please refer to the relevant description of other embodiments. The technical features of the above embodiments can be combined arbitrarily. In order to make the description concise, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0147] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0148] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A clock signal transmission method, characterized in that: Applied to a server, a plurality of signal detection pin connectors are arranged on a mainboard of the server, and each of the signal detection pin connectors is respectively connected to a signal detection pin; The clock signal transmission method comprises: When the power is turned on, the signal of each processing card is received based on each signal detection pin; Based on the signals, respectively determine the type of each processing card; When the processing card is a first processing card, transmitting a clock signal to the first processing card based on a first clock signal transmission strategy; When the processing card is a second processing card, the clock signal is transmitted to the second processing card based on a second clock signal transmission strategy.

2. The method according to claim 1, characterized in that When the processing card is a first processing card, transmitting a clock signal to the first processing card based on a first clock signal transmission strategy includes: When the processing card is a first processing card, starting a clock generator and determining a working state of the server; When the working state is a first state, the clock signal is sent to the first processing card through the clock generator; wherein the first state is used to indicate a standby state.

3. The method according to claim 2, characterized in that When the working state is the first state, after the clock signal is sent to the first processing card by the clock generator, the method further includes: When a start signal is received, the working state is updated to a second state; wherein the second state is used to indicate a start state.

4. The method according to claim 1 or 2, characterized in that: When the processing card is a second processing card, transmitting a clock signal to the second processing card based on a second clock signal transmission strategy includes: When the processing card is a second processing card and the working state of the server is a second state, starting a clock generator; The clock signal is sent to the second processing card and the central processing unit through the clock generator.

5. The method according to any one of claims 1 to 4, characterized in that Based on the signals, respectively determining the type of each processing card includes: When it is detected that the level of the signal changes within a preset time period, it is determined that the processing card corresponding to the signal is the first processing card.

6. The method according to any one of claims 1 to 4, characterized in that Based on the signals, respectively determining the type of each processing card, further comprising: When it is detected that the signal has no level change within a preset time period, it is determined that the processing card corresponding to the signal is the second processing card.

7. A clock signal transmission device, characterized in that: Applied to a server, a plurality of signal detection pin connectors are arranged on a mainboard of the server, and each of the signal detection pin connectors is respectively connected to a signal detection pin; The clock signal transmission device comprises: A signal receiving module, used for receiving signals from each processing card based on each of the signal detection pins when the power is turned on; A signal detection module, used to determine the type of each processing card based on each signal; A first transmission module, configured to transmit a clock signal to the first processing card based on a first clock signal transmission strategy when the processing card is a first processing card; The second transmission module is configured to transmit the clock signal to the second processing card based on a second clock signal transmission strategy when the processing card is a second processing card.

8. A server, characterized in that: include: A mainboard, a processor, and a memory communicatively connected to the processor; The mainboard is provided with a plurality of signal detection pin connectors, each of which is connected to a signal detection pin, and the signal detection pin is used to receive the signal of the processing card; The memory stores computer-executable instructions; The processor executes the computer-executable instructions stored in the memory to implement the method according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, which are used to implement the method according to any one of claims 1 to 6 when executed by a processor.

10. A computer program product, characterized in that The method comprises a computer program, which implements the method according to any one of claims 1 to 6 when being executed by a processor.

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