Solid state disk, operation method of solid state disk, storage system and data center

Abstract

The embodiment of the invention discloses a solid state disk, an operation method of the solid state disk, a storage system and a data center. The solid state disk comprises a flash memory module, a dynamic random access memory module and a controller. The dynamic random access memory module comprises a first storage area, first data and a check code of the first data are stored in the first storage area, and the code length of the first data is larger than the interface width of the dynamic random access memory module. The operation method of the solid state disk comprises the steps that the controller reads first data and a check code of the first data from a first storage area of the dynamic random access memory module, and the code length of the first data is larger than the interface width of the dynamic random access memory module. The code length of the first data is greater than the interface width of the dynamic random access memory module, so that the overall code length of the check code is reduced, and the interface width use efficiency of the dynamic random access memory module is improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and more specifically, to a solid state drive, a method for operating a solid state drive, a storage system, and a data center. Background Art

[0002] Solid State Disk (SSD), also known as Solid State Drive (SSD), has many advantages over Hard Disk Drive (HDD), such as stronger security for stored data, no need to worry about damaging the stored data when the SSD is shaken during use, and no data loss in the SSD due to sudden power failure during use. Based on this, SSDs are widely used in various working environments, such as enterprise-level servers with high reliability requirements and personal storage devices.

[0003] SSDs usually include flash memory, a controller, and dynamic random access memory. Flash memory is a non-volatile storage medium and a data storage medium. Flash memory can store data without power supply, but the read and write speed of flash memory is lower than the data transmission speed between the host and the SSD. Therefore, the dynamic random access memory is set as a cache. The data received by the SSD from the host is first cached in the dynamic random access memory, and then written from the dynamic random access memory to the flash memory. In order to achieve higher sequential write bandwidth, higher random read and write times per second (Input / Output Operations PerSecond, IOPS) and better system QoS, higher and higher cache interface width access is required. Currently, the cache interface width and frequency are generally increased to meet the system bandwidth access requirements. For example, the cache interface width is increased from 32 bits to 64 bits. Summary of the invention

[0004] In view of this, embodiments of the present invention provide a solid state drive controller, a solid state drive operation method, a storage system, and a data center, which can improve the utilization rate of the interface width of the cache.

[0005] One aspect of an embodiment of the present invention provides a solid state drive, comprising: a flash memory module; a dynamic random access memory (DRAM) module; and a controller. The DRAM module comprises a first storage area, the first storage area stores first data and a check code of the first data, and the code length of the first data is greater than the interface width of the DRAM module.

[0006] Another aspect of an embodiment of the present invention provides an operating method for a solid-state hard disk, wherein the solid-state hard disk includes a flash memory module, a DRAM module and a controller, and the method includes: the controller reads first data and a check code of the first data from a first storage area of ​​the DRAM module, and the code length of the first data is greater than the interface width of the DRAM module.

[0007] Another aspect of an embodiment of the present invention provides a storage system including the above-mentioned solid state drive.

[0008] Another aspect of an embodiment of the present invention provides a data center, including the above storage system.

[0009] According to the solid-state hard disk and its operating method provided by an embodiment of the present invention, when the first data in the first storage area of ​​the DRAM module is encoded with a check code, the first data sets the check code with a code length greater than the interface width of the DRAM module as the granularity, thereby reducing the number of check bits per unit byte of data, improving the efficiency of using the interface width of the DRAM module, and thereby improving the bandwidth utilization of the DRAM module. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0011] Figure 1 is a schematic block diagram of a solid state drive according to an embodiment of the present invention;

[0012] Figure 2 is a schematic block diagram of a flash memory unit according to an embodiment of the present invention;

[0013] Figure 3 is a schematic block diagram of a DRAM module according to an embodiment of the present invention;

[0014] Figure 4 is a schematic block diagram of a DRAM unit according to an embodiment of the present invention;

[0015] Figure 5 is a schematic diagram of partitioning of a DRAM module according to an embodiment of the present invention;

[0016] Figure 6 The data transmission between the solid state drive controller and the DRAM module in the related art is shown;

[0017] Figure 7 The data transmission between the solid state drive controller and the DRAM module in the embodiment of the present invention is shown. DETAILED DESCRIPTION

[0018] The present invention is described below based on embodiments, but the present invention is not limited to these embodiments. In the detailed description of the present invention below, some specific details are described in detail. It is possible for a person skilled in the art to fully understand the present invention without the description of these details. In order to avoid confusing the essence of the present invention, known methods, processes, flows, components and circuits are not described in detail.

[0019] In addition, persons of ordinary skill in the art will appreciate that the drawings provided herein are for illustration purposes and are not necessarily drawn to scale.

[0020] Unless the context clearly requires otherwise, the words "include", "comprising" and similar words throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, the meaning is "including but not limited to".

[0021] In the description of the present invention, it should be understood that the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0022] Figure 1 is a schematic block diagram of a solid-state drive. A solid-state drive can store data under the control of a host computer (such as a smartphone, desktop computer, game console, TV, tablet computer, or in-vehicle infotainment system). Figure 1 As shown, the solid state drive includes: a flash memory module, a controller, a dynamic random access memory (DRAM) module, and an interface. The solid state drive can use any of the following packages: package on package (POP), system-in-package (SIP), system-on-chip (SOC) package, multi-chip package (MCP), chip-on-board (COB) package, wafer-level manufacturing package (WFP), and wafer-level stacked package (WSP).

[0023] The interface is used to manage the communication between the SSD and the host. The communication includes a read operation (Read IO) for reading data from the SSD and a write operation (Write IO) for writing data to the SSD. The SSD can communicate with the host through at least one of the following communication protocols: Universal Serial Bus (USB), Serial Advanced Technology Attachment (SATA), Non-Volatile Memory Host Controller Interface Specification (NVMe), Serial Attached SCSI (SAS), High-Speed ​​Inter-Chip (HSIC), Small Computer System Interface (SCSI), PCI, PCIe, Gen 3.0, PCIe Gen.

[0024] Flash memory is a non-volatile random access storage medium that can store data without power supply. The flash memory module is connected to the controller via a bus. The flash memory module includes multiple flash memory cells (also known as flash memory particles). The flash memory cell includes storage cells arranged in an array, and the storage cells are addressed by word lines (Word Line) and bit lines (Bit Line). The storage cell is, for example, a floating gate transistor, including a floating gate, a control gate, a substrate, and a tunneling dielectric layer between the substrate and the floating gate. By controlling the voltage of the substrate and the voltage of the control gate, the charge in the substrate enters the floating gate through tunneling, or the charge in the floating gate enters the substrate through tunneling. The amount of charge in the floating gate determines the threshold voltage of the floating gate transistor. According to the interval in which the threshold voltage of the floating gate transistor is located, the information stored in the floating gate transistor is determined. The floating gate transistor can store 1-bit binary number (Single Level Cell, SLC), store 2-bit binary data (Multi-Level Cell, MLC), store 3-bit binary data (Trinary-Level Cell, TLC), or store 4-bit binary data (Quad Level Cell, QLC). The flash memory module is, for example, a NAND flash memory, and the flash memory unit is a NAND particle. Figure 2 FIG. 1 is a schematic block diagram of a flash memory unit according to an embodiment of the present invention. Figure 2 As shown, each flash memory unit includes multiple blocks, each block includes multiple pages, and each page includes multiple storage units. NAND flash memory performs write and read operations in units of pages and performs erase operations in units of blocks. Before performing a write operation, the block needs to be erased. The target data of the host's read and write operations is stored in the flash memory.

[0025] DRAM is a volatile storage medium. DRAM storage cells include transistors and capacitors. Each storage cell stores 1 bit of data. For example, when the capacitor stores charge, the storage cell stores "1", and when the capacitor does not store charge, the storage cell stores "0". DRAM modules are, for example, double data rate synchronous dynamic random access memory (Double Data Rate Synchronous DRAM, DDR SDRAM). DDR means that input / output (I / O) operations can be performed on both the rising and falling edges of the clock signal to transmit data.

[0026] The read and write speed of DRAM is greater than that of flash memory. Therefore, as a cache between the flash memory module and the host, the SSD improves the response speed of the host. When the host writes data to the SSD, the SSD interface receives the data, and the data is cached in the DRAM module. The controller then reads the data from the DRAM module and writes it to the target address in the flash memory module. When the host reads data from the SSD, the controller reads the data from the target address in the flash memory module, caches the data in the DRAM module, and sends the data cached in the DRAM module to the host through the interface.

[0027] The interface width of a DRAM module refers to the number of data bits that are simultaneously input to or output from the DRAM module during each read or write operation. For example, at the rising edge of the clock signal, the DRAM module simultaneously outputs 32 bits of data, so the interface width of the DRAM module is 32 bits. The interface width of a DRAM module is equal to the number of data IO ports of the DRAM module. The DRAM module also includes address signal ports, etc.

[0028] Figure 3 is a schematic block diagram of a DRAM module according to an embodiment of the present invention. A data bus, an address signal line, and a command signal line are provided between the DRAM module and the controller. Figure 3 As shown, the DRAM module includes n DRAM units (also called DRAM particles), where n is a positive integer, for example, n is 4, 8, 16, etc. Each DRAM unit has, for example, 8 data IO ports, which can simultaneously input / output 8 bits of data. Accordingly, the interface width of the DRAM module is 8*n, which can simultaneously input / output 8*n bits of data. It can be understood that the number of data IO ports of the DRAM unit can also be other values, such as 4, 16, etc.

[0029] Figure 4 is a schematic block diagram of a DRAM unit according to an embodiment of the present invention. Figure 4 As shown, the DRAM unit includes m blocks (Banks), where m is a positive integer, for example, m is 4, 8, 16, etc. Each Bank includes multiple memory cell arrays, and the memory cells are addressed by word lines and bit lines. The number of data bits that each Bank simultaneously inputs / outputs is equal to the number of data IO ports of the DRAM unit. For example, the DRAM unit includes 8 data IO ports, and the Bank includes 8 memory cell arrays, which can output 8 bits of data simultaneously. The m Banks perform read and write operations in an interleaving manner.

[0030] The bank performs a read operation based on the row address and column address, selects the target row in the memory cell array, and simultaneously reads the data in the memory cells at the intersection of the target row and multiple consecutive columns and stores them in the bank's buffer, that is, simultaneously reads out the data in multiple memory cells located at the target row and multiple consecutive columns. The buffer is, for example, a static random access memory (SRAM). The number of multiple consecutive columns is called the burst length. That is, at the same time, the data of the burst length bits are read from the memory cell array into the buffer. For example, the burst length is 2, 4, 8, 16, etc.

[0031] The controller, also known as the main control chip or main control, is the manager of the solid-state drive. It consists of a processor that executes firmware code and some hardware acceleration modules. The controller can implement functions such as software intermediate layer (Flash translation layer), wear leveling management, flash bad block management, garbage collection (Garbage Collection), checksum encoding, etc. The controller can implement the above functions through software, or hardware, or a combination of software and hardware. The operation of the controller requires system data, which is stored in the controller's read-only memory (ROM). Since DRAM has a faster access speed, when the solid-state drive is powered on, the system data is transferred from the read-only memory to the DRAM module.

[0032] The controller includes function modules 1-N, DDR physical layer circuit (DDR PHY), and DDR controller circuit (DDRController). The controller accesses and manages DRAM through the DDR physical layer circuit and the DDR controller circuit. Function modules 1-N are used to execute functions such as software middle layer, wear leveling management, bad block management, garbage collection, and checksum encoding.

[0033] Some nouns or terms used in describing the embodiments of the present invention are subject to the following explanations.

[0034] Flash Physical Address (FPA), also known as Physical Block Address (PBA), is used to identify the storage location of data in flash memory particles, and generally contains information such as Die, Plane, Block, and Page.

[0035] Logical Block Address (LBA) is a common mechanism used to indicate the location of data on computer data storage devices.

[0036] The global mapping table (L2P) is a global mapping table between the LBA index and the PBA of the flash memory. The global mapping table is stored in the read-only memory of the controller. When the SSD is powered on, the global mapping table is transferred from the read-only memory to the DRAM module.

[0037] Error Correction Coding (ECC) is an algorithm used to detect and correct errors in data transmission or storage. ECC can improve the reliability and integrity of data and prevent data damage or loss. ECC can use a variety of coding and correction algorithms, such as BCH (Bose Chaudhuri Hocquenghem) code, RS (Reed-solomon) code, and Low Density Parity Check Code (LDPC).

[0038] As described above, the I / O operation of the DRAM module can be performed once at the rising edge and once at the falling edge of each clock cycle. Therefore, the data transmission between the DRAM module and the controller is performed once at the rising edge and once at the falling edge of each clock cycle. The number of data bits transmitted each time is A*n (i.e., the interface width of the DRAM module), where n is the number of DRAM cells involved in the transmission and A is the number of data IO ports of the DRAM cell. In each data transmission, the data of the DRAM cell comes from a Bank of the DRAM cell.

[0039] Figure 6 The figure shows the setting method of the checksum of the data in the DRAM module in the related art, and the data transmission between the solid state drive controller and the DRAM module. Figure 6 As shown in the figure, the DRAM module includes 5 DRAM units: DRAM0 to DRAM4. Each DRAM unit can output 8 bits of data at the same time, so the interface width of the DRAM module is 40 bits. Among them, DRAM units DRAM0 to DRAM3 store data, and DRAM4 stores the check code corresponding to the data. The numbers 1-n on the left side of the DRAM module represent the data transmission sequence number, that is, the first data transmission to the nth data transmission. The data transmission is explained by taking the controller obtaining data from the DRAM module as an example. Figure 6 As shown, each time data is transmitted, the controller reads 32 bits of data and the ECC check code corresponding to the 32 bits of data from the DRAM module, that is, a set of check bits is set for every 32 bits of data in the DRAM module. Figure 6 The check code is set in the manner shown, 8 bits of the 40-bit interface width of the DRAM module are used to transmit the ECC check code, and the utilization rate of the interface width is 80%, which is relatively low.

[0040] According to the solid-state hard disk and its operation method provided by the embodiment of the present invention, the data in the DRAM module is set with a check code with a code length greater than the interface width of the DRAM module. The DRAM module includes a first storage area, the first storage area stores the first data and the check code of the first data, and the code length of the first data (that is, the number of bits of the first data) is greater than the interface width of the DRAM module. For example, the interface width of the DRAM module is 40 bits, and a group of check bits (that is, check codes) are set for every 152 bytes (Byte) of first data, the first data is 152Bytes, and the check code is 8Bytes. For another example, the interface width of the DRAM module is 40 bits, and a group of check bits are set for every 308Bytes of first data, the first data is 308Bytes, and the check code is 12Bytes.

[0041] According to the algorithm of the check code, a check code is set for X-bit data (the number of bits is Z). The larger X is, the smaller Z / (X+Z) is, that is, the larger the proportion of the number of data bits in the total number of bits, the smaller the number of check bits per byte of data.

[0042] The first storage area may be a partial storage area or the entire storage area of ​​the DRAM module, that is, the data in the DRAM module are all set with check codes in the above manner, or the data in a partial storage area of ​​the DRAM module are set with check codes in the above manner.

[0043] Figure 7 The embodiment of the present invention shows the setting method of the check code of the data in the DRAM module and the data transmission between the solid state drive controller and the DRAM module. Figure 7 In the embodiment shown, the DRAM module includes five DRAM units: DRAM0 to DRAM4. Each DRAM unit can simultaneously input / output 8 bits of data. The interface width of the DRAM module is 40 bits. The number of DRAM units in the DRAM module is not limited, and can also be 4, 8, 16, etc.

[0044] DRAM units DRAM0 to DRAM4 can store data and check codes. Each DRAM unit stores a portion of first data and a portion of the check code of the first data. Figure 7 As shown, the first data is 152Bytes, the check code is 8Bytes, 31Bytes of the first data and 1Byte of the check code are stored in DRAM0, 31Bytes of the first data and 1Byte of the check code are stored in DRAM1, 30Bytes of the first data and 2Bytes of the check code are stored in DRAM2, 30Bytes of the first data and 2Bytes of the check code are stored in DRAM3, and 30Bytes of the first data and 2Bytes of the check code are stored in DRAM4.

[0045] The numbers 1-N on the left side of the DRAM module represent the data transmission sequence number. Figure 7 As shown, in the 1st data transmission to the 30th data transmission, 150 bytes of the first data are transmitted from the DRAM module to the controller, in the 31st data transmission, 2 bytes of the first data are transmitted from the DRAM module to the controller, and 3 bytes of the check code of the first data are transmitted from the DRAM module to the controller, and in the 32nd data transmission, 5 bytes of the check code of the first data are transmitted from the DRAM module to the controller. That is, through 32 data transmissions, the controller receives 152 bytes of the first data and 8 bytes of the check code from the DRAM module.

[0046] The total number of bits of the first data and its check code is an integer multiple of the interface bandwidth of the DRAM module, and the integer is greater than or equal to 2. The controller receives the first data and its check code through multiple data transmissions.

[0047] In the embodiment of the present invention, the check code may be a BCH, RS or LDPC code, etc. The controller selects the type of the check code of the first data according to the reliability requirement of the first data.

[0048] by Figure 6 In the checksum setting method shown in the figure, through 32 data transmissions, the controller obtains 4*32Bytes of data and 32Bytes of checksum from the DRAM module, and every 4Bytes of data is corrected by 1Byte of checksum. Figure 7 In the verification code setting method shown, the controller obtains 152 bytes of data and 8 bytes of verification code from the DRAM module through 32 data transmissions, and the 152 bytes of data are corrected as a whole through the 8 bytes of verification code. The utilization rate of the interface width of the DRAM module is 95%. Therefore, the verification code setting method of the present application improves the utilization rate of the interface width of the DRAM module.

[0049] The above embodiment takes the DRAM module outputting data to the controller as an example. The above setting method of the check code is also used in the process of writing data to the DRAM module. The writing process is controlled by the controller, and the check code is generated by the controller, which can also improve the utilization rate of the interface width of the DRAM module.

[0050] In some embodiments, the first data is data received by the solid state drive from the host and cached in the DRAM module. The host transmits data to the solid state drive and sends an instruction to store the first data at a target address of the flash memory module. The first data is received through an interface of the solid state drive. The controller generates a check code for the first data, and the first data and the check code are cached as a data unit in a first storage area of ​​the DRAM module. The code length of the first data is greater than the interface width of the DRAM module.

[0051] In some embodiments, the first data is data cached from the flash memory module in the DRAM module during a garbage collection operation. Due to the erase-before-write feature of NAND flash memory, after a large number of write update operations, invalid pages containing expired file data will be generated in the NAND flash memory. When the number of free pages that can be written to the NAND flash memory is lower than a threshold, the solid-state drive controller will perform a garbage collection operation, that is, erase the flash memory blocks containing more invalid pages. Before erasing the flash memory block, the data in the valid pages of the flash memory block needs to be migrated to the DRAM module, and then written to the erased flash memory block or other flash memory blocks.

[0052] In some embodiments, the total number of bits of a data unit consisting of the first data and its check code is M times the interface width of the DRAM module, where M is a positive integer greater than or equal to 2.

[0053] In some embodiments, the total number of bits of a data unit consisting of the first data and its check code is S times the Burst length, where S is a positive integer greater than or equal to 2.

[0054] In some embodiments, the DRAM module further includes a second storage area, the second storage area stores second data and a check code of the second data, and the code length of the first data is different from the code length of the second data. For example, for the first data in the first storage area, a set of check bits is set for every X bits, and for the second data in the second storage area, a set of check bits is set for every Y bits, and X and Y are different. X is greater than Y, for example.

[0055] There are usually three types of data in the DRAM module: business data, system data required for controller operation (program space accessed by the controller's CPU Core or data managed by the CPU, etc.), and mapping tables (including but not limited to global mapping tables and table entries involved in FTL management). Business data includes: data cached in the DRAM module when the host performs read and write operations on the solid-state drive, and data cached in the DRAM module during garbage collection operations. Business data is usually stored in the flash memory module, and is cached in the DRAM module during read and write operations and garbage collection operations on the solid-state drive. According to an embodiment of the present application, different types of data use different check code setting methods. For example, business data is the first data of the present application, and a group of check bits is set for every X bits of first data, where X is greater than the interface width of the DRAM module. System data and mapping tables are second data, and a group of check bits is set for every Y bits of second data, where X is greater than Y. System data and mapping tables, for example, use Figure 6 The check code setting method shown is that the controller reads data and the corresponding check code from the DRAM module each time, and the sum of the code lengths of the data and the corresponding check code is equal to the interface width of the DRAM module.

[0056] Figure 5 1 is a partition diagram of a DRAM module according to an embodiment of the present invention. The DRAM module is divided into a first storage area 11, a second storage area 12, and a third storage area 13. The first storage area 11 is used to store first data (i.e., business data). One of the second storage area 12 and the third storage area 13 is used to store system data, and the other is used to store a mapping table.

[0057] In some embodiments, the second storage area 12 and the third storage area 13 may be used as one storage area, that is, the system data and the mapping table are provided with check codes at the same code length as the granularity.

[0058] like Figure 3 As shown in Figure 1, in the same I / O operation of the DRAM module, data comes from multiple DRAM units. Figure 5 As shown, the first storage area 11 includes a portion of DRAM unit 1, a portion of DRAM unit 2, ..., a portion of DRAM unit n. The second storage area 12 and the third storage area 13 are similar and will not be described in detail.

[0059] According to an embodiment of the present invention, the data code length originally cached in the DRAM module is expanded, and combined with a reasonable check bit length (satisfying DRAM reliability), the bandwidth utilization rate when accessing the DRAM module is improved, thereby effectively improving the bandwidth access efficiency of the DRAM module of the entire solid-state drive as a whole, reducing the system's power consumption, and the overall system cost.

[0060] The embodiment of the present invention further provides a storage system. The storage system includes the solid state drive of the above embodiment. The storage system is deployed in a data center, for example.

[0061] An embodiment of the present invention further provides a data center, including the above storage system. The data center is used, for example, to provide cloud services. The data center also includes a server. A data center is a large-scale collaborative network of specific devices used to transmit, accelerate, display, calculate, and store data information on a network infrastructure. Data centers are, for example, financial data centers, enterprise data centers, and Internet cloud data centers.

[0062] The above-mentioned product can execute the method provided by the embodiment of the present invention, and has the functional modules and beneficial effects corresponding to the execution method. For technical details not fully described in this embodiment, please refer to the method provided by the embodiment of the present invention.

[0063] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A solid state hard disk, comprising: Flash memory module; Dynamic Random Access Memory (DRAM) module; as well as Controller, The DRAM module includes a first storage area, the first storage area stores first data and a check code of the first data, and a code length of the first data is greater than an interface width of the DRAM module.

2. The solid state drive according to claim 1, wherein: The first data is data received from a host and cached in the DRAM module.

3. The solid state drive according to claim 1, wherein: The first data is data cached from the flash memory module to the DRAM module during a garbage collection operation.

4. The solid state drive according to claim 1, wherein: The DRAM module includes a plurality of DRAM units, each of which includes a plurality of banks, and each of which stores a portion of the first data and a portion of a check code of the first data.

5. The solid state drive according to any one of claims 1 to 4, wherein: The DRAM module further includes a second storage area, the second storage area stores second data and a check code of the second data, and the code length of the first data is different from the code length of the second data.

6. The solid state drive according to claim 5, wherein: The second data is a global mapping table and / or system data of the controller.

7. A method for operating a solid state drive, the solid state drive comprising a flash memory module, a dynamic random access memory (DRAM) module and a controller, the method comprising: The controller reads first data and a check code of the first data from a first storage area of ​​the DRAM module, wherein a code length of the first data is greater than an interface width of the dynamic random access memory.

8. The operating method according to claim 7, wherein: The first data is data received from a host and cached in the DRAM module.

9. The operating method according to claim 7, wherein: The first data is data cached from the flash memory module to the DRAM module during a garbage collection operation.

10. The operating method according to claim 7, wherein: The DRAM module includes a plurality of DRAM units, each of which includes a plurality of banks, and each of which stores a portion of the first data and a portion of a check code of the first data.

11. The operating method according to any one of claims 7 to 10, further comprising: The controller reads second data and a check code of the second data from a second storage area of ​​the DRAM module, and a code length of the first data is different from a code length of the second data.

12. The operating method according to claim 11, wherein: The second data is a global mapping table and / or system data of the controller.

13. A storage system comprising: A solid state drive according to any one of claims 1 to 6.

14. A data center, comprising: The storage system according to claim 13.

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