Data processing system, data processing method and core particle

Abstract

The invention provides a data processing system, a data processing method and a core particle, and the data processing system comprises a data storage module which carries out the data width conversion of input sideband data, and stores the sideband data in the data storage module in the form of a sideband data packet; and the data analysis module is used for receiving the sideband data packet output by the data storage module, and sending the sideband data packet to an output interface according to the content of the sideband data packet, or completing the access of a local register according to the content of the sideband data packet. According to the data processing system, the data processing method and the core particle provided by the invention, a universal transmission method is provided for data in a universal core particle interconnection technology protocol.

Description

Technical Field

[0001] The present invention belongs to the technical field of data processing, and in particular relates to a data processing system, a data processing method and a core particle. Background Art

[0002] Chiplets are modular chips made with different processes that are integrated together using packaging technology like Lego blocks, improving performance while achieving low cost and high yield. How to interconnect chiplets at high speed is the key to the implementation of chiplet technology. The established Universal Chiplet Interconnect Express (UCIe) protocol covers the physical layer, communication electrical signal standards, number of channels, contact spacing, etc. However, there is no systematic implementation method for data transmission within the physical layer, adaptation layer, and protocol layer. Summary of the invention

[0003] The object of the present invention is to provide a data processing system, a data processing method and a core particle, which can simply and efficiently realize the transmission of sideband data between core particles.

[0004] To achieve the above object, the present invention provides a data processing system, comprising at least:

[0005] a data storage module, converting the input sideband data into data width, and storing the sideband data in the data storage module in the form of a sideband data packet; and

[0006] The data parsing module receives the sideband data packet output by the data storage module, sends the sideband data packet to the output interface according to the content of the sideband data packet, or completes the access to the local register according to the content of the sideband data packet.

[0007] In an embodiment of the present invention, the data storage module is a first-in-first-out queue, and the width of the first-in-first-out queue is equal to the maximum length of the sideband data packet.

[0008] In one embodiment of the present invention, the first-in-first-out queue is configured as a synchronous mode or an asynchronous mode according to a clock domain required when the sideband data is input into and output from the data processing system.

[0009] In one embodiment of the present invention, the data processing system further includes a data generation module, which forms a sideband data packet of the current layer and sends the formed sideband data packet of the current layer to the data analysis module for analysis and processing.

[0010] In one embodiment of the present invention, the length of the sideband data packet of the current layer is equal to the width of the first-in-first-out queue.

[0011] In one embodiment of the present invention, the data parsing module includes a data parsing unit, and the data parsing unit parses the sideband data packet output by the data storage module to obtain the sending type or access type of the sideband data packet.

[0012] In one embodiment of the present invention, the data parsing module includes a sending unit, which, when the sideband data packet is of a sending type, sends the sideband data output by the data storage module to the physical layer or to a remote end via a serial line, and directly sends the sideband data packet of the current layer generated by the data generation module to an output interface.

[0013] In one embodiment of the present invention, the data parsing module includes an access unit, which, when the sideband data packet is an access type, accesses a local register and packages the feedback data in accordance with the format of the sideband data packet fixed by the universal chip interconnect technology protocol to form a feedback data packet.

[0014] The present invention also provides a data processing method, which at least comprises the following steps:

[0015] Using the data storage module to convert the input sideband data into data width, and storing the sideband data in the data storage module in the form of a sideband data packet; and

[0016] The data parsing module is used to receive the sideband data packet output by the data storage module, and the sideband data packet is sent to the output interface according to the content of the sideband data packet, or the local register is accessed according to the content of the sideband data packet.

[0017] In one embodiment of the present invention, the data storage module is a first-in-first-out queue. When the first-in-first-out queue is writing the sideband data, the first-in-first-out queue detects an interface signal and uses the rising edge of the interface signal as the starting position of the sideband data packet.

[0018] In one embodiment of the present invention, the data processing method further includes the following steps:

[0019] After receiving the sideband data packet, query the operation code information in the first byte of the sideband data packet to obtain the length of the sideband data packet.

[0020] In one embodiment of the present invention, the data processing method further includes the following steps:

[0021] After the length of the sideband data packet is acquired, the end position of the sideband data packet is determined according to the length of the sideband data packet and the length of data received in each cycle.

[0022] In one embodiment of the present invention, the data processing method further includes the following steps:

[0023] After completing the reception of one of the sideband data packets, determining that the length of the sideband data packet is less than the width of the first-in-first-out queue;

[0024] If the length of the sideband data packet is less than the width of the FIFO queue, then padding the sideband data packet with data until the length of the sideband data packet is equal to the width of the FIFO queue, thus completing the writing of the current data packet; and

[0025] If the length of the sideband data packet is equal to the width of the FIFO queue, no data padding is performed, ie, the writing of the current data packet is completed.

[0026] In one embodiment of the present invention, the moment when the detection interface signal and the data packet check signal are both at high level is used as the starting position of the sideband data packet.

[0027] In one embodiment of the present invention, the data processing method comprises the following steps:

[0028] When the FIFO queue is not an empty queue and the data packet processing signal is at a low level, start reading the sideband data packet from the FIFO queue; and

[0029] When the sideband data packet is read out, the data packet processing signal is set to a high level, and a signaling is fed back to the input interface.

[0030] The present invention also provides a core particle, the core particle uses a universal core particle interconnection technology protocol, and any one of the data processing systems described above is arranged in a physical layer or an adaptation layer in the core particle high-speed interconnection protocol.

[0031] In summary, the data processing system, data processing method and core particle provided by the present invention can be applied to the adaptation layer or physical layer in the general core particle interconnection technology protocol, and can simply and efficiently realize the reception, parsing and processing of sideband data, while having error recovery capability and clock conversion function, and completing the return of signaling. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0033] Figure 1 It is a schematic diagram of the protocol layer interconnection structure in the universal chip interconnection technology of an embodiment of the present application.

[0034] Figure 2 It is a structural block diagram of a data processing system in one embodiment of the present application.

[0035] Figure 3 It is a timing diagram of some signals of a data storage module when writing data in one embodiment of the present application.

[0036] Figure 4 It is a timing diagram of some signals when the data storage module reads data in one embodiment of the present application.

[0037] Figure 5 It is a structural block diagram of a data analysis module in one embodiment of the present application.

[0038] Description of labels:

[0039] 101. Protocol layer; 102. Adaptation layer; 103. Physical layer; 104. Remote end; 105. FDI interface; 106. RDI interface; 107. Serial line; 201. Data storage module; 202. Data parsing module; 2021. Parsing unit; 2022. Sending unit; 2023. Access unit; 203. Data generation module; 204. Input interface; 205. Output interface. DETAILED DESCRIPTION

[0040] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thoroughly and comprehensively understood.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0042] In the description of the present invention, it should be understood that the orientations or positional relationships indicated by the terms "center", "upper", "lower", "front", "back", "left", "right", etc. are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0043] See also Figure 1As shown, the chiplets are modular chips of different processes, which are integrated together using packaging technology like Lego blocks, to achieve low cost and high yield while improving performance. How to make the chiplets interconnected at high speed is the key to the implementation of chiplet technology. The established Universal Chiplet Interconnect Express (UCIe) protocol is a specification standard. It is a layered protocol. The protocol layers within it have their own functions, which is convenient for general use and reuse, and clarifies the functions to be supported by each layer. Among them, the universal chiplet interconnect technology includes a protocol layer (Protocol layer) 101, an adapter layer (Adapter layer) 102 and a physical layer (Physical Layer) 103. Among them, the FDI interface 105 is the connection interface between the protocol layer 101 and the adapter layer 102, and the RDI interface 106 is the connection interface between the adapter layer 102 and the physical layer 103. Data is transmitted between the protocol layer 101, the adaptation layer 102 and the physical layer 103 through the FDI interface 105 and the RDI interface 106, and can be transmitted to the remote end 104 through the serial line 107 connected to the physical layer 103. The transmitted data mainly includes clock data, mainband data, and sideband data. The data transmitted by the FDI interface and the RDI interface also include flow control related signals, link status and power consumption status management related handshake signals, error reporting signals, data link layer packet (DLLP) data (unique to the FDI interface), and negotiated link rate, width, protocol and Flit format reporting (unique to the FDI interface).

[0044] See also Figure 1 As shown, the established universal chip interconnection technology protocol covers the physical layer 103, communication electrical signal standards, channel quantity, contact spacing, etc. The present invention provides a data processing system, a data processing method and a chip, wherein the data processing system is located in the adaptation layer 102 or the physical layer 103, and the data processing system and the data processing method define the processing method of the data in the adaptation layer 102 or the physical layer 103, and provide a universal sideband data processing method for the data in the adaptation layer 102 and the physical layer 103 in the universal chip interconnection technology.

[0045] See also Figure 1 and Figure 2As shown, in one embodiment of the present invention, the data processing system includes a data storage module 201, a data parsing module 202 and a data generating module 203. The data storage module 201 performs data width conversion on the sideband data inputted by the input interface 204, and stores the sideband data in the data storage module 201 in the form of a sideband data packet. When the data processing system is set in the adaptation layer 102 between the FDI interface 105 and the RDI interface 106, the data storage module 201 performs data width conversion on the sideband data inputted by the FDI interface 105, and stores the sideband data in the data storage module 201 in the form of a sideband data packet. When the data processing system is set in the physical layer 103 between the RDI interface 106 and the serial line 107, the data storage module 201 performs data width conversion on the sideband data inputted by the RDI interface 106, and stores the sideband data in the data storage module 201 in the form of a sideband data packet. The data analysis module 202 is electrically connected to the output end of the data storage module 201, receives the sideband data packet output by the data storage module 201, and sends the sideband data packet to the output interface 205 according to the content of the sideband data packet, or completes the access to the local register according to the content of the sideband data packet. The data generation module 203 forms the sideband data packet of this layer. The output end of the data generation module 203 is electrically connected to the data analysis module 202, and sends the formed sideband data packet of this layer to the data analysis module 202 for analysis and processing.

[0046] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, the data storage module 201 is, for example, a first-in-first-out queue, and the parameters in the first-in-first-out queue can be configured. On the one hand, the width of the first-in-first-out queue can be determined according to the maximum length of the sideband data packet. That is, the width of the first-in-first-out queue is set to be equal to the maximum length of the sideband data packet. In this embodiment, for example, the width of the first-in-first-out queue is set to 128 bits. On the other hand, the depth of the first-in-first-out queue can be determined according to the setting of the local sideband data access signaling, so as to ensure that the required amount of sideband data can be stored in the first-in-first-out queue.

[0047] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, the first-in-first-out queue can be configured as a synchronous mode or an asynchronous mode. When the first-in-first-out queue is configured as a synchronous mode, the read clock and the write clock of the first-in-first-out queue are the same clock. When the first-in-first-out queue is configured as an asynchronous mode, the read clock and the write clock of the first-in-first-out queue are inconsistent, and the read clock and the write clock are independent of each other. In the present application, the first-in-first-out queue is flexibly configured as a synchronous mode or an asynchronous mode according to the clock domain required when the sideband data is input into the data processing system and output from the data processing system.

[0048] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, it should be noted that when the FIFO queue is configured in asynchronous mode, the write pointer of the FIFO queue is encoded using Gray code, and after completing the cross-clock domain processing, it is used in the read pointer clock domain. In synchronous mode, the write pointer is directly used in the read pointer domain.

[0049] See also Figure 2 and Figure 3 As shown, in one embodiment of the present invention, when a first-in-first-out queue is used to perform data width conversion and store data, the data length received in each cycle is first set, that is, the setting of the NC value. In this embodiment, the value of NC is set to, for example, 32. In other embodiments, the value of NC can also be 16 or 8. Therefore, the data processing system in the present application can be flexibly adapted to interfaces with different parameters and has strong adaptability.

[0050] See also Figure 2 and Figure 3 As shown, in one embodiment of the present invention, when the first-in-first-out queue is writing the sideband data, first, the first-in-first-out queue detects the interface signal lp_cfg_vld, and uses the rising edge of the interface signal lp_cfg_vld as the starting position of the sideband data packet. That is, the sideband data packet is received at the rising edge of the interface signal lp_cfg_vld. Since the first-in-first-out queue is not allowed to be repeatedly set to a low level when receiving the same sideband data packet, and when receiving different sideband data packets, the interface signal lp_cfg_vld can be continuously set to a high level or the interface signal lp_cfg_vld can be interrupted. Therefore, if there is an error in the operation code information in the data packet, resulting in an error in the cycle count when receiving the sideband data packet, the cycle of receiving the sideband data packet can be counted again when the interface signal lp_cfg_vld is detected at the next rising edge, so that the data storage module 201 can return to normal when an error occurs in the received data.

[0051] See also Figure 2 and Figure 3 As shown, in one embodiment of the present invention, after receiving the sideband data packet, the operation code information in the first byte of the sideband data packet is queried to obtain the length of the sideband data packet. The operation code information is stored in the first byte of the sideband data packet. There is a fixed mapping relationship between the operation code information and the data packet length, so the length of the current sideband data packet can be parsed through the operation code information. Among them, the sideband data packet is set to have two lengths, namely 64 bits or 128 bits.

[0052] See also Figure 2and Figure 3 As shown, in one embodiment of the present invention, after obtaining the length of the sideband data packet, the end position of the sideband data packet is determined according to the length of the sideband data packet and the length of the data received in each cycle. If the length of the sideband data packet is 64 bits, and the length of the data received in each cycle is 32, that is, NC=32, the sideband data packet can be received and completed within two cycles. If the length of the sideband data packet is 128 bits, and the length of the data received in each cycle is 32, that is, NC=32, the sideband data packet can be received and completed within four cycles. When a sideband data packet is received, the first-in-first-out stack enable signal push_fifo_en is set to a high level.

[0053] See also Figure 2 and Figure 3 As shown, in one embodiment of the present invention, after completing the reception of a sideband data packet, it is determined that the length of the sideband data packet is less than the width of the first-in-first-out queue. If the length of the sideband data packet is less than the width of the first-in-first-out queue, data is added to the sideband data packet until the length of the sideband data packet is equal to the width of the first-in-first-out queue, that is, the writing of the current data packet is completed. If the length of the sideband data packet is equal to the width of the first-in-first-out queue, no data is added, that is, the writing of the current data packet is completed. After completing the writing of the current data packet, the data packet check signal packet_nxt_chk is set to a high level, and then prepare to receive the next sideband data packet. Specifically, if the length of the sideband data packet is 128 bits, no data needs to be added, that is, the writing of the current sideband data packet is completed. If the length of the sideband data packet is 64 bits, the high bit of the sideband data packet is added with 64 bits of data, and the added data is, for example, binary 0, to complete the writing of the current sideband data packet.

[0054] It should be noted that since the width of the FIFO queue is the length of the largest sideband packet, there is no situation where the length of the sideband packet is greater than the width of the FIFO queue.

[0055] See also Figure 2 and Figure 3 As shown, in another embodiment of the present invention, the starting position of the sideband data packet is determined by the detection interface signal lp_cfg_vld and the data packet check signal packet_nxt_chk, that is, the moment when the detection interface signal lp_cfg_vld and the data packet check signal packet_nxt_chk are both high level is used as the starting position of the sideband data packet. Afterwards, the process of writing the sideband data packet is performed.

[0056] See also Figure 2 and Figure 4As shown, in one embodiment of the present invention, when reading sideband data from a first-in-first-out queue, it is determined whether the first-in-first-out queue is an empty queue and whether the data packet processing signal packet_processing is at a low level. If the first-in-first-out queue is not an empty queue and the data packet processing signal packet_processing is at a low level, a sideband data packet is read from the first-in-first-out queue. After the sideband data packet is read, the data packet processing signal packet_processing is set to a high level. While the data packet processing signal packet_processing is set to a high level, a signaling pl_cfg_crd is fed back to the input interface 204 to inform the input interface 204 that the data sideband packet is read out. This method of feeding back a signaling pl_cfg_crd to the input interface 204 after reading a sideband data packet has a simple signaling feedback mechanism.

[0057] It should be noted that if the FIFO queue is an empty queue or the packet processing signal packet_processing is at a high level, the process of reading the sideband data packet from the FIFO queue will not be performed.

[0058] See also Figure 2 and Figure 4 As shown, in one embodiment of the present invention, if the first-in-first-out queue is in asynchronous mode, the signaling fed back to the input interface 204 needs to be processed across clock domains, and the signaling fed back to the input interface 204 needs to be converted to the first-in-first-out queue write clock domain, and then fed back to the input interface 204.

[0059] See also Figure 2 and Figure 4 As shown, in one embodiment of the present invention, after the sideband data packet is read out from the first-in-first-out queue, it is transferred to the data parsing module 202, and the data parsing module 202 parses and processes the sideband data packet. After the data parsing module 202 completes the processing of the sideband data packet, it feeds back a data packet processing completion signal to the first-in-first-out queue. When any of the fed-back data packet processing completion signals is valid, the data packet processing signal packet_processing is set to a low level. At this time, if the first-in-first-out queue is not an empty queue, the sideband data packet can be read out from the first-in-first-out queue again. Among them, the data packet processing completion signal can be a data sending completion signal sb_send_done, or a data access completion signal apb_cfg_done.

[0060] See also Figure 2As shown, in one embodiment of the present invention, the data processing system further includes a data generation module 203, and the data generation module 203 generates a sideband data packet of this layer. If the data processing system is set in the adaptation layer 102, the data generation module 203 generates a sideband data packet of the adaptation layer 102. If the data processing system is set in the physical layer 103, the data generation module 203 generates a sideband data packet of the physical layer 103. The output end of the data generation module 203 is directly electrically connected to the data analysis module 202, and the data generation module 203 sends the sideband data packet of this layer to the data analysis module 202 for analysis and processing. There is no need to send the sideband data packet of this layer to the first-in-first-out queue for cache, thereby reducing resource consumption and design complexity.

[0061] See also Figure 2 As shown, in one embodiment of the present invention, the length of the sideband data packet of the current layer generated by the data generation module 203 is equal to the width of the first-in-first-out queue. In this embodiment, the length of the sideband data packet of the current layer generated by the data generation module 203 is equal to 128 bits. When the data length in the sideband data packet of the current layer is less than the width of the first-in-first-out queue, data is padded into the sideband data packet of the current layer until the length of the sideband data packet of the current layer is equal to the width of the first-in-first-out queue. That is, if there is no valid data in the upper 64 bits of the sideband data packet of the current layer, the upper bits of the sideband data packet of the current layer are padded with 64 bits of data, and the padded data is, for example, binary 0.

[0062] See also Figure 2 As shown, in one embodiment of the present invention, the data analysis module 202 is electrically connected to the output end of the data storage module 201 and the output end of the data generation module 203, and analyzes and processes the sideband data packet output by the data storage module 201 and the sideband data packet of the current layer output by the data generation module 203.

[0063] See also Figure 5 As shown, in one embodiment of the present invention, the data parsing module 202 includes a parsing unit 2021, a sending unit 2022 and an access unit 2023. The parsing unit 2021 parses the sideband data packet output by the data storage module 201 to obtain the sending type or access type of the sideband data packet. The sending type includes sending the sideband data packet to the physical layer 103 or sending it to the remote end 104 through the serial line 107. The access type includes completing the access to the register in the adaptation layer 102 or completing the access to the register in the physical layer 103.

[0064] For details, please refer to Figure 5As shown, the parsing unit 2021 parses the 57th to 55th bits (bit57-bit55) of the sideband data packet, and obtains the sending type or access type of the sideband data packet through the value dstid of the 57th to 55th bits.

[0065] If dstid=010b, it indicates that the sideband data packet needs to be forwarded to the physical layer 103 through the RDI interface 106 .

[0066] If dstid=1xxb, it indicates that the sideband data packet needs to be sent to the remote end 104 via the serial line 107 .

[0067] If dstid=001b, it indicates that access to the register in the adaptation layer 102 needs to be completed.

[0068] If dstid=010b, it indicates that access to the register in the physical layer 103 needs to be completed.

[0069] See also Figure 5 As shown, in one embodiment of the present invention, when the sideband data packet output by the data storage module 201 is of the sending type, the sideband data is sent to the physical layer 103 or to the remote end 104 through the serial line 107 through the sending unit 2022. And when sending the sideband data packet, if it is necessary to forward the sideband data packet to the physical layer 103 through the RDI interface 106, the sideband data packet can be directly forwarded. If it is necessary to send the sideband data packet to the remote end 104 through the serial line 107, the parallel sideband data packet is first converted into a serialized data packet, and then sent bit by bit. When the sending unit 2022 completes the sending of the sideband data packet, it sends a data sending completion signal sb_send_done to the data storage module 201, and the data parsing module 202 can read the sideband data packet from the data storage module 201 again.

[0070] See also Figure 5 As shown, in one embodiment of the present invention, the sideband data packet of the current layer generated by the data generation module 203 is directly sent to the sending unit 2022, and is sent to the output interface through the sending unit 2022. If the sending unit 2022 simultaneously receives the sideband data packet output by the data storage module 201 and the sideband data packet of the current layer generated by the data generation module 203, the sideband data packet of the current layer generated by the data generation module 203 is sent first.

[0071] See also Figure 5As shown, in one embodiment of the present invention, when the sideband data packet output by the data storage module 201 is of the access type, the local register is accessed through the access unit 2023. That is, the register in the adaptation layer 102 is accessed in the adaptation layer 102, and the register in the physical layer 103 is accessed in the physical layer 103. When accessing the local register, the register access is performed according to the timing of the register access interface. In this embodiment, the interface of the local register is, for example, an Advanced Peripheral Bus (APB) interface, then when accessing the register, the sideband data packet is converted into the timing of the APB interface to access the register.

[0072] See also Figure 5 As shown, in one embodiment of the present invention, after completing the access to the local register, the feedback data is packaged in the format of the sideband data packet specified in the UCIe protocol to form a feedback data packet, and a data completion packet is fed back to the input interface 204. At the same time, a data access completion signal apb_cfg_done is sent to the data storage module 201, and the data parsing module 202 can read the sideband data packet from the data storage module 201 again. The access unit 2023 can automatically complete the access to the local register according to the result of the parsing unit 2021, and feed back a feedback data packet that complies with the protocol specification.

[0073] In summary, the present invention provides a data processing system, a data processing method and a core particle, wherein the data processing system includes a data storage module, a data analysis module and a data generation module. Among them, the data storage module performs data width conversion on the sideband data input by the input interface, and stores the sideband data in the data storage module in the form of a sideband data packet. The data analysis module is electrically connected to the output end of the data storage module, receives the sideband data packet output by the data storage module, sends the sideband data packet to the output interface according to the content of the sideband data packet, or completes the access of the local register according to the content of the sideband data packet. The data generation module forms the sideband data packet of this layer, and the output end of the data generation module is electrically connected to the data analysis module, and sends the formed sideband data packet of this layer to the data analysis module for analysis and processing. The data processing system provided by the present invention can be applied to the adaptation layer or physical layer in the general core particle interconnection technology protocol, and realizes the reception, analysis and processing of sideband data in a simple and efficient manner, and has error recovery capability and clock conversion function, and completes the return of signaling.

[0074] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A data processing system, characterized in that: At least: A data storage module converts the input sideband data into data width and stores the sideband data in the data storage module in the form of a sideband data packet; as well as The data parsing module receives the sideband data packet output by the data storage module, sends the sideband data packet to the output interface according to the content of the sideband data packet, or completes the access to the local register according to the content of the sideband data packet.

2. A data processing system according to claim 1, characterized in that: The data storage module is a first-in-first-out queue, and the width of the first-in-first-out queue is equal to the maximum length of the sideband data packet.

3. A data processing system according to claim 2, characterized in that: The first-in-first-out queue is configured as a synchronous mode or an asynchronous mode according to a clock domain required when the sideband data is input into and output from the data processing system.

4. A data processing system according to claim 2, characterized in that: The data processing system further includes a data generating module, which forms a sideband data packet of the current layer and sends the formed sideband data packet of the current layer to the data parsing module for parsing and processing.

5. A data processing system according to claim 4, characterized in that: The length of the sideband data packet of the current layer is equal to the width of the first-in-first-out queue.

6. A data processing system according to claim 1, characterized in that: The data parsing module includes a data parsing unit, which parses the sideband data packet output by the data storage module to obtain a sending type or an access type of the sideband data packet.

7. A data processing system according to claim 4, characterized in that: The data parsing module includes a sending unit, which sends the sideband data output by the data storage module to the physical layer or to the remote end through a serial line when the sideband data packet is of a sending type, and directly sends the sideband data packet of the current layer generated by the data generation module to the output interface.

8. A data processing system according to claim 1, characterized in that: The data parsing module includes an access unit, which accesses a local register when the sideband data packet is of access type, and packages the feedback data in a sideband data packet format fixed by a universal chiplet interconnect technology protocol to form a feedback data packet.

9. A data processing method, characterized in that: At least the following steps are included: Using a data storage module to convert the input sideband data into data width, and storing the sideband data in the data storage module in the form of a sideband data packet; as well as The data parsing module is used to receive the sideband data packet output by the data storage module, and the sideband data packet is sent to the output interface according to the content of the sideband data packet, or the local register is accessed according to the content of the sideband data packet.

10. A data processing method according to claim 9, characterized in that: The data storage module is a first-in-first-out queue. When the first-in-first-out queue is writing the sideband data, the first-in-first-out queue detects an interface signal and uses the rising edge of the interface signal as the starting position of the sideband data packet.

11. A data processing method according to claim 9, characterized in that: The data processing method further comprises the following steps: After receiving the sideband data packet, query the operation code information in the first byte of the sideband data packet to obtain the length of the sideband data packet.

12. A data processing method according to claim 11, characterized in that: The data processing method further comprises the following steps: After the length of the sideband data packet is acquired, the end position of the sideband data packet is determined according to the length of the sideband data packet and the length of data received in each cycle.

13. A data processing method according to claim 10, characterized in that: The data processing method further comprises the following steps: After completing the reception of one of the sideband data packets, determining that the length of the sideband data packet is less than the width of the first-in-first-out queue; If the length of the sideband data packet is less than the width of the FIFO queue, then padding the sideband data packet with data until the length of the sideband data packet is equal to the width of the FIFO queue, thus completing the writing of the current data packet; and If the length of the sideband data packet is equal to the width of the FIFO queue, no data padding is performed, ie, the writing of the current data packet is completed.

14. A data processing method according to claim 9, characterized in that: The moment when the detection interface signal and the data packet check signal are both at high level is taken as the starting position of the sideband data packet.

15. A data processing method according to claim 10, characterized in that: The data processing method comprises the following steps: When the FIFO queue is not an empty queue and the data packet processing signal is at a low level, starting to read the sideband data packet from the FIFO queue; as well as When the sideband data packet is read out, the data packet processing signal is set to a high level, and a signaling is fed back to the input interface.

16. A core particle, characterized in that The core particle uses a universal core particle interconnection technology protocol, and the data processing system according to any one of claims 1 to 8 is arranged in a physical layer or an adaptation layer in the core particle high-speed interconnection protocol.

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