Chip operation reliability determination method and device, computer equipment, readable storage medium and program product

Abstract

The invention relates to a chip operation reliability determination method and device, computer equipment, a computer readable storage medium and a computer program product, relates to the technical field of chip reliability operation analysis, and can improve the accuracy of a chip operation reliability analysis result. The method comprises the following steps: acquiring historical operation data of a chip, and performing feature extraction on the historical operation data of the chip to obtain a first chip feature reflecting an operation state and chip performance of the chip; acquiring real-time operation data of the chip, and performing feature intersection on the first chip feature and the real-time operation data of the chip to obtain a second chip feature reflecting the comprehensive operation performance of the chip; performing model training on a machine learning model by using the second chip feature, and obtaining a trained operation reliability prediction model corresponding to the chip when a training ending condition is met; and obtaining a chip operation reliability prediction result of the chip based on the trained operation reliability prediction model.

Description

Technical Field

[0001] The present application relates to the technical field of chip reliability operation analysis, and in particular to a chip operation reliability determination method, apparatus, computer equipment, computer-readable storage medium, and computer program product. Background Art

[0002] With the rapid development of electronic technology, the performance and reliability of chips as the core components of electronic devices are crucial to the operation of the entire system. Therefore, how to ensure the stable operation of chips in complex and changing working environments has become an important issue in the field of chip design and manufacturing.

[0003] Among the related technologies, there are statistical reliability analysis technologies for chip operation reliability analysis, which is to predict the reliability performance of chips under different process variations by measuring and statistically analyzing a large number of chip samples and establishing a probability distribution model of process parameters. There are also artificial intelligence and machine learning technologies that help discover potential reliability problem patterns by learning from a large amount of chip reliability data, providing designers with valuable references and predictions.

[0004] However, although the application of statistical reliability analysis technology, artificial intelligence, and machine learning technology in chip reliability analysis has improved the accuracy and efficiency of prediction to a certain extent, due to limited generalization ability, the established prediction model is often only applicable to specific chip types or process conditions. For new chips or process variations, the model's predictive ability is affected and it cannot effectively predict the chip's operational reliability. Summary of the invention

[0005] Based on this, it is necessary to provide a chip operation reliability determination method, device, computer equipment, computer readable storage medium and computer program product to address the above technical problems.

[0006] In a first aspect, the present application provides a method for determining chip operation reliability, comprising:

[0007] Acquire historical operation data of a chip, perform feature extraction on the historical operation data of the chip, and obtain a first chip feature reflecting an operation state and chip performance of the chip;

[0008] Acquire real-time operation data of the chip, perform feature cross-talk between the first chip feature and the real-time operation data of the chip, and obtain a second chip feature reflecting the comprehensive operation performance of the chip;

[0009] Performing model training on the machine learning model using the second chip feature, and obtaining a trained operation reliability prediction model corresponding to the chip when a training end condition is met;

[0010] A chip operation reliability prediction result of the chip is obtained based on the trained operation reliability prediction model.

[0011] In one embodiment, extracting features from the historical operation data of the chip to obtain a first chip feature reflecting the operation state and chip performance of the chip includes:

[0012] Processing the historical operation data of the chip according to a preset data preprocessing method to obtain processed historical operation data, wherein the data preprocessing method includes at least one of outlier filtering, missing value supplementation, data denoising, and data formatting;

[0013] Determining performance parameters reflecting the processing speed, power consumption, and temperature of the chip from the processed historical operation data, and determining resource occupancy parameters of the chip from the processed historical operation data;

[0014] The performance parameter and the resource occupancy parameter are calculated and quantified to obtain a first chip characteristic reflecting an average processing speed, a maximum power consumption, a temperature fluctuation range, and a resource utilization rate of the chip.

[0015] In one embodiment, performing feature cross-talk between the first chip feature and the real-time operation data of the chip to obtain a second chip feature reflecting the comprehensive operation performance of the chip includes:

[0016] Determining target potential correlation features related to the first chip features from the real-time operation data of the chip, and performing cluster analysis based on the target potential correlation features to obtain target correlation features;

[0017] Combining the obtained target-related features to obtain a corresponding first feature set, and combining the first chip features to obtain a corresponding second feature set;

[0018] Traversing each element in the first feature set, during the traversal process, multiplying the currently traversed element with each element in the second feature set, and performing weighted summation on the obtained multiplication results to obtain a combined feature corresponding to the currently traversed element; wherein each multiplication result has a corresponding weight, and the weight is adjusted according to the prediction error of the machine learning model;

[0019] The combined feature corresponding to each element in the first feature set is determined as a second chip feature reflecting the comprehensive operating performance of the chip.

[0020] In one embodiment, determining a target potential associated feature related to the first chip feature from the real-time operation data of the chip includes:

[0021] Based on the principal component analysis method, determining potential correlation indicators from multiple data indicators corresponding to the real-time operation data of the chip;

[0022] For each of the potential correlation indicators, calculating a correlation coefficient between the potential correlation indicator and a feature indicator corresponding to the first chip feature;

[0023] According to the magnitude of the coefficients of the correlation coefficients, the potential correlation indicators are sorted in descending order, and the first K potential correlation indicators are used as target potential correlation indicators; K is a positive integer greater than or equal to 1;

[0024] The real-time operation data under the target potential association index is obtained from the real-time operation data of the chip as the target potential association feature.

[0025] In one embodiment, performing cluster analysis based on the target potential association features to obtain target association features includes:

[0026] Determine a target data set consisting of all target potential associated features; each data point in the target data set corresponds to one of the target potential associated features;

[0027] Based on the data distribution characteristics of the target data set, M data points are selected from the target data set as initial cluster centers; M is a positive integer greater than or equal to 2;

[0028] Clustering the target data set based on the initial cluster centers to obtain a plurality of clusters, and determining a cluster representative feature corresponding to each of the clusters;

[0029] A plurality of target-related features are obtained according to the cluster representative features of each of the plurality of clusters.

[0030] In one embodiment, the step of performing model training on a machine learning model using the second chip feature includes:

[0031] Acquire an operation reliability label of the chip under the real-time operation data; the operation reliability label indicates the chip operation reliability when the chip has the real-time operation data;

[0032] Inputting the second chip feature into the machine learning model for forward propagation to obtain a prediction output of the model;

[0033] Calculating a loss function value based on a prediction error between the prediction output and the operational reliability label;

[0034] Execute a back propagation algorithm based on the loss function value to determine the gradient of the model parameters of the machine learning model;

[0035] Estimate the mean of the gradient by exponentially weighted moving average to get the first-order moment estimate, and estimate the mean of the square of the gradient by exponentially weighted moving average to get the second-order moment estimate;

[0036] According to the adaptive deviation correction and momentum attenuation factor adjustment, the first-order moment estimation and the second-order moment estimation are subjected to deviation correction, and the update amount of each model parameter is calculated in combination with the global learning rate, and the model parameters of the machine learning model are updated;

[0037] Return to execute inputting the second chip feature into the machine learning model for forward propagation, obtaining the predicted output of the model, iteratively adjusting the model parameters of the machine learning model until the training end condition is met, and obtaining a trained machine learning model.

[0038] In a second aspect, the present application further provides a device for determining chip operation reliability, comprising:

[0039] A historical feature extraction module, used to obtain historical operation data of a chip, perform feature extraction on the historical operation data of the chip, and obtain a first chip feature reflecting the operation state and chip performance of the chip;

[0040] A feature crossover module, used to obtain real-time operation data of the chip, perform feature crossover on the first chip feature and the real-time operation data of the chip, and obtain a second chip feature reflecting the comprehensive operation performance of the chip;

[0041] A model training module, used to perform model training on a machine learning model using the second chip characteristics, and obtain a trained operation reliability prediction model corresponding to the chip when a training end condition is met;

[0042] The model prediction module is used to obtain the chip operation reliability prediction result of the chip based on the trained operation reliability prediction model.

[0043] In a third aspect, the present application further provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the following steps are implemented:

[0044] Acquire historical operation data of a chip, perform feature extraction on the historical operation data of the chip, and obtain a first chip feature reflecting an operation state and chip performance of the chip;

[0045] Acquire real-time operation data of the chip, perform feature cross-talk between the first chip feature and the real-time operation data of the chip, and obtain a second chip feature reflecting the comprehensive operation performance of the chip;

[0046] Performing model training on the machine learning model using the second chip feature, and obtaining a trained operation reliability prediction model corresponding to the chip when a training end condition is met;

[0047] A chip operation reliability prediction result of the chip is obtained based on the trained operation reliability prediction model.

[0048] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the following steps are implemented:

[0049] Acquire historical operation data of a chip, perform feature extraction on the historical operation data of the chip, and obtain a first chip feature reflecting an operation state and chip performance of the chip;

[0050] Acquire real-time operation data of the chip, perform feature cross-talk between the first chip feature and the real-time operation data of the chip, and obtain a second chip feature reflecting the comprehensive operation performance of the chip;

[0051] Performing model training on the machine learning model using the second chip feature, and obtaining a trained operation reliability prediction model corresponding to the chip when a training end condition is met;

[0052] A chip operation reliability prediction result of the chip is obtained based on the trained operation reliability prediction model.

[0053] In a fifth aspect, the present application further provides a computer program product, including a computer program, which implements the following steps when executed by a processor:

[0054] Acquire historical operation data of a chip, perform feature extraction on the historical operation data of the chip, and obtain a first chip feature reflecting an operation state and chip performance of the chip;

[0055] Acquire real-time operation data of the chip, perform feature cross-talk between the first chip feature and the real-time operation data of the chip, and obtain a second chip feature reflecting the comprehensive operation performance of the chip;

[0056] Performing model training on the machine learning model using the second chip feature, and obtaining a trained operation reliability prediction model corresponding to the chip when a training end condition is met;

[0057] A chip operation reliability prediction result of the chip is obtained based on the trained operation reliability prediction model.

[0058] The above-mentioned chip operation reliability determination method, device, computer equipment, computer-readable storage medium and computer program product can obtain the historical operation data of the chip, perform feature extraction on the historical operation data of the chip, and obtain the first chip feature reflecting the operation status and chip performance of the chip; obtain the real-time operation data of the chip, perform feature crossover on the first chip feature and the real-time operation data of the chip, and obtain the second chip feature reflecting the comprehensive operation performance of the chip; then use the second chip feature to train the machine learning model, and obtain the trained operation reliability prediction model corresponding to the chip when the training end condition is met; and then the chip operation reliability prediction result of the chip can be obtained based on the trained operation reliability prediction model. In this embodiment, on the one hand, by obtaining the historical operation data and real-time operation data of the target chip, and performing feature extraction and feature crossover, the operation status and performance changes of the chip can be more comprehensively reflected, which is helpful to capture the performance degradation trend and potential problems of the chip during long-term operation; on the other hand, by introducing historical operation data, the model can learn more information about the performance changes of the chip, thereby enhancing the generalization ability of the model, so that the model can better adapt to the chip reliability analysis needs under different process conditions and working environments, and effectively improve the accuracy of the chip operation reliability prediction results under different conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0060] Figure 1 A schematic diagram of a flow chart of a method for determining chip operation reliability in one embodiment;

[0061] Figure 2 A schematic diagram of a flow chart of a step of obtaining a first chip feature in an embodiment;

[0062] Figure 3 A structural block diagram of a device for determining chip operation reliability in one embodiment;

[0063] Figure 4 is an internal structure diagram of a computer device in one embodiment;

[0064] Figure 5The figure is a diagram of the internal structure of another computer device in one embodiment. DETAILED DESCRIPTION

[0065] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0066] In one embodiment, Figure 1 As shown, a method for determining chip operation reliability is provided. This embodiment takes the method applied to a terminal as an example. It can be understood that the method can also be applied to a server, and can also be applied to a system including a terminal and a server, and is implemented through the interaction between the terminal and the server. In this embodiment, the method includes the following steps:

[0067] S101, acquiring historical operation data of a chip, performing feature extraction on the historical operation data of the chip, and obtaining a first chip feature reflecting the operation status and chip performance of the chip.

[0068] As an example, the chip may be an enhanced chip, such as a high-voltage, high-speed, high-integration type chip.

[0069] In actual applications, the historical operation data of the chip can be collected, wherein the historical operation data of the chip can be the operation data collected during the past operation of the chip. The historical operation data of the chip can be the historical operation data of the same chip, or the historical operation data of the chip of the same model or type. In some optional embodiments, the historical operation data of the chip can be collected from a preset data source, and the preset data source can include at least one of a chip operation log and a monitoring system. Of course, the preset data source also includes other types of data collection systems, such as performance monitoring tools, hardware sensor data, etc., depending on the actual application scenario.

[0070] After acquiring the historical operation data, feature extraction can be performed on the historical operation data, and chip features that can reflect the operation status and chip performance of the chip can be obtained according to the extraction results. For the sake of distinction, the chip features obtained based on the analysis of the chip's past historical operation data are referred to as first chip features.

[0071] S102, acquiring real-time operation data of the chip, performing feature cross-talk between the first chip feature and the real-time operation data of the chip, and obtaining a second chip feature reflecting the comprehensive operation performance of the chip.

[0072] In this step, the real-time operation data of the chip can also be obtained, and then the first chip feature and the real-time operation data of the chip are cross-featured. According to the result of the feature cross-combination, the chip feature that can reflect the comprehensive performance of the chip operation is obtained. For the convenience of distinction, the chip feature obtained after feature cross-feature is called the second chip feature.

[0073] Among them, feature crossing, also known as combined features, refers to the cross-combination of two or more features of different types or dimensions to generate new features. Feature crossing can capture the impact of multiple features on the target variable when they appear at the same time, thereby enhancing the model's expressiveness and prediction accuracy.

[0074] S103, using the second chip feature to perform model training on the machine learning model, and obtaining a trained operation reliability prediction model corresponding to the chip when the training end condition is met.

[0075] After acquiring the second chip feature, the second chip feature can be used to train the machine learning model. In a specific implementation, the second chip feature is used to supervise the machine learning model, and the model parameters are updated by introducing an adaptive learning rate adjustment strategy during the training process. In some exemplary embodiments, the machine learning model can be any of the following: a neural network, a linear classifier, a support vector machine, a decision tree, a random forest, a naive Bayes, and a reinforcement learning model.

[0076] When the training end condition is met, a trained operation reliability prediction model corresponding to the chip can be obtained, and the operation reliability prediction model can be used to predict the operation reliability of the chip under a characteristic environment.

[0077] S104, obtaining a chip operation reliability prediction result of the chip based on the trained operation reliability prediction model.

[0078] In some embodiments, the user can determine the target operating environment of the chip, which can be the operating environment in which the chip is deployed, and the target operating environment can be characterized by corresponding operating environment parameters. Then, the operating data of the chip in the target operating environment can be input into the operating reliability prediction model, and the model predicts the performance of the chip in the target operating environment and outputs the chip operating reliability prediction result.

[0079] In the above chip operation reliability determination method, the historical operation data of the chip can be obtained, and the feature extraction of the historical operation data of the chip can be performed to obtain the first chip feature reflecting the operation status and chip performance of the chip; the real-time operation data of the chip is obtained, and the first chip feature is cross-featured with the real-time operation data of the chip to obtain the second chip feature reflecting the comprehensive operation performance of the chip; then the machine learning model is trained using the second chip feature, and the trained operation reliability prediction model corresponding to the chip is obtained when the training end condition is met; and then the chip operation reliability prediction result of the chip can be obtained based on the trained operation reliability prediction model. In this embodiment, on the one hand, by obtaining the historical operation data and real-time operation data of the target chip, and performing feature extraction and feature cross-feature, the operation status and performance changes of the chip can be more comprehensively reflected, which is helpful to capture the performance degradation trend and potential problems of the chip during long-term operation; on the other hand, by introducing historical operation data, the model can learn more information about the performance changes of the chip, thereby enhancing the generalization ability of the model, so that the model can better adapt to the chip reliability analysis needs under different process conditions and working environments, and effectively improve the accuracy of the chip operation reliability prediction results under different conditions.

[0080] In some exemplary embodiments, Figure 2 As shown, in step S102, real-time operation data of the chip is obtained, and the first chip feature is cross-referenced with the real-time operation data of the chip to obtain a second chip feature reflecting the comprehensive operation performance of the chip, which may include the following steps:

[0081] S201, processing the historical operation data of the chip according to a preset data preprocessing method to obtain processed historical operation data, the data preprocessing method including at least one of outlier filtering, missing value supplementation, data denoising, and data formatting.

[0082] In some embodiments, for outlier filtering, a corresponding filtering threshold can be defined based on statistical distribution, and outliers can be removed based on the filtering threshold; for missing value filling, mean filling, interpolation, etc. can be selected to fill missing values ​​according to the characteristics of the data; for data denoising, filtering, smoothing and other techniques can be used to reduce the noise in the data to reduce the impact of noise on subsequent analysis; for data formatting, the data can be converted into a unified format and unit to facilitate subsequent processing and analysis.

[0083] In some embodiments, since missing values ​​may affect subsequent data updating and processing, missing value supplementation may be performed first, and then outlier filtering and data denoising may be performed. After completing the aforementioned steps, data formatting may be performed.

[0084] S202, determining performance parameters reflecting chip processing speed, power consumption, and temperature from the processed historical operation data, and determining resource occupancy parameters of the chip from the processed historical operation data.

[0085] The resource occupancy parameter may include one or more of the following: resource utilization of a central processing unit (CPU), resource utilization of a memory, and resource utilization of storage resources.

[0086] In practical applications, after obtaining the processed historical operation data, the processed historical operation data can be analyzed and processed. In some embodiments, the target parameters can be read directly from the processed historical operation data, such as the CPU utilization, memory occupancy, temperature, etc. for performance parameters. For features that need to be obtained by calculation, such as processing speed, power consumption, and storage resource utilization, statistical methods (such as mean, median, standard deviation, maximum value, minimum value, etc.) can be used to analyze the data of a specific time period, where the processing speed can be evaluated based on the task completion time or the number of transactions processed per second, the power consumption can be evaluated based on the change in energy consumption per unit time, and the storage resource utilization can be evaluated based on the occupancy of the storage space.

[0087] S203, calculating and quantifying the performance parameters and resource occupancy parameters to obtain a first chip characteristic reflecting an average processing speed, maximum power consumption, temperature fluctuation range, and resource utilization of the chip.

[0088] Among them, the average processing speed reflects the average rate at which the chip processes tasks within a preset time; the maximum power consumption reflects the maximum energy consumed by the chip during operation; the temperature fluctuation range reflects the amplitude of the chip temperature change; the resource utilization rate can reflect the use of resources, for example, the CPU utilization rate reflects the use of CPU resources.

[0089] In this step, for the calculation and quantification of performance parameters and resource occupancy parameters, the average processing speed can be determined by calculating the average completion time of all tasks in a specified time period; the maximum power consumption can be determined by filtering out the maximum value from the power consumption data; the temperature fluctuation range can be determined by calculating the maximum and minimum values ​​in the temperature data and based on the difference between the two; the resource utilization rate can be determined by calculating the ratio of the time occupied by the CPU in executing tasks to the total CPU execution time. It should be noted that in the entire process, the consistency of the timestamp can be maintained when processing data so as to correctly analyze the data in a specific time period.

[0090] Furthermore, the average processing speed, maximum power consumption, temperature fluctuation range and resource utilization of the chip can be determined as the first chip characteristics.

[0091] In this embodiment, by extracting and quantifying key features from the historical operation data of the chip, such as average processing speed, maximum power consumption, temperature fluctuation range, and resource utilization, and by converting the data into a feature set that is highly descriptive of the chip's operating status and performance, the first chip features can more accurately reflect the actual performance and behavior of the chip, providing strong support for subsequent analysis and prediction.

[0092] In some exemplary embodiments, the first chip feature may include multiple features. In step S102, the first chip feature is cross-referenced with the real-time operation data of the chip to obtain a second chip feature reflecting the comprehensive operation performance of the chip, which may include the following steps:

[0093] S1021, determining a target potential correlation feature related to the first chip feature from the real-time operation data of the chip, and performing cluster analysis based on the target potential correlation feature to obtain a target correlation feature.

[0094] In practical applications, after obtaining the real-time operation data of the chip, the target potential correlation feature related to the first chip feature can be determined from the real-time operation data, wherein the target potential correlation feature can be understood as a feature that is correlated with the past performance of the chip. Then, the target potential correlation feature can be clustered and classified and analyzed differentially to obtain the target correlation feature.

[0095] S1022, combining the obtained target-related features to obtain a corresponding first feature set, and combining the first chip features to obtain a corresponding second feature set.

[0096] Then, each target-related feature can be combined to obtain a first feature set, which can include one or more elements, each of which is obtained based on a combination of at least two target-related features. On the other hand, each first chip feature can be combined to obtain a second feature set, which can include one or more elements, each of which is obtained based on a combination of at least two first chip features.

[0097] S1023, traversing each element in the first feature set, during the traversal process, multiplying the currently traversed element with each element in the second feature set, performing weighted summation on the multiplication results, and obtaining a combined feature corresponding to the currently traversed element.

[0098] Among them, each multiplication result has a corresponding weight, and the weight is adjusted according to the prediction error of the machine learning model.

[0099] In a specific implementation, after obtaining the first feature set, each element in the first feature set can be traversed. During the traversal process, the currently traversed element is multiplied with each element in the second feature set to obtain the multiplication result of the currently traversed element and each element in the second feature set. For example, if the second feature set includes X elements, the currently traversed element in the first feature set can be multiplied with X elements respectively to obtain X multiplication results. Each multiplication result can be assigned a weight variable, which can be adaptively optimized and adjusted according to the prediction error during the training process of the machine learning model. Then, the weighted sum of the obtained multiplication results can be obtained to obtain the combined feature corresponding to the currently traversed element.

[0100] Specifically, in the process of traversing the first feature set, each element will be multiplied with each element in the second set, and a weight variable will be assigned to each multiplication result. It should be noted that these weight variables are initially determined by equal weight initialization (that is, all weights are set to the same value, which can be a random value within a certain range and is not currently specified). During the model training process, these weight variables will be adaptively adjusted according to the prediction error. Specifically, the gradient of the weight variable will be calculated based on the prediction error, and the value of the weight variable will be updated based on the gradient through the back propagation method. This process will be repeated until the prediction error reaches an acceptable level or other stopping conditions are met. In other words, when training the model based on each batch of second chip features, the weight of the multiplication result can be adjusted according to the last model training situation to update the second chip features of the current batch.

[0101] S1024: Determine the combined feature corresponding to each element in the first feature set as a second chip feature reflecting the comprehensive operating performance of the chip.

[0102] After obtaining the combined features corresponding to the elements in the first feature set, the combined features corresponding to the elements can be determined as the second chip features reflecting the comprehensive operating performance of the chip.

[0103] In this embodiment, in the process of multiplying feature combinations and weighted summing them, weight variables are introduced and adaptive optimization adjustments are performed based on the prediction error. The weight optimization mechanism can automatically adjust the contribution of different feature combinations to the second chip feature that reflects the comprehensive performance of the chip operation, thereby improving the accuracy and robustness of the model.

[0104] In some exemplary embodiments, determining a target potential associated feature related to a first chip feature from the real-time operation data of the chip may include the following steps:

[0105] Based on the principal component analysis method, potential correlation indicators are determined from multiple data indicators corresponding to the real-time operation data of the chip; for each potential correlation indicator, the correlation coefficient between the potential correlation indicator and the feature indicator corresponding to the first chip feature is calculated; according to the coefficient size of each correlation coefficient, each potential correlation indicator is sorted in descending order, and the first K potential correlation indicators are used as target potential correlation indicators; the real-time operation data under the target potential correlation indicator is obtained from the real-time operation data of the chip as the target potential correlation feature.

[0106] Wherein, K is a positive integer greater than or equal to 1.

[0107] In a specific implementation, the real-time operation data of the chip has multiple corresponding data indicators, and the first chip feature is the value under the corresponding feature indicator. The first chip feature can be determined based on the real-time operation data under some or all of the multiple data indicators. Based on the professional knowledge and experience in the field of chip design, the staff can determine the candidate data indicators that may be associated with the data indicators corresponding to the first chip feature among the multiple data indicators corresponding to the real-time operation data, such as memory access delay, power supply voltage fluctuation, network delay, cache hit rate, etc. One or more. Afterwards, based on the principal component analysis method, the potential correlation indicators are determined from the manually screened candidate data indicators. The principal component analysis method is used here as a preprocessing step, the purpose of which is to extract the main information components from the real-time operation data of the chip.

[0108] Afterwards, in order to further improve the accuracy of feature extraction, the correlation between each extracted potential correlation indicator and the characteristic indicator corresponding to the first chip feature can be analyzed, that is, a correlation evaluation can be performed. Specifically, the correlation coefficient between each potential correlation indicator and each characteristic indicator can be calculated. The correlation coefficient can quantify the degree of correlation between a potential correlation indicator and a characteristic indicator.

[0109] In one embodiment, the correlation between each potential correlation indicator and the characteristic indicator corresponding to the first chip characteristic can be evaluated based on the Pearson correlation coefficient. (where j = 1, 2, ..., m), the Pearson correlation coefficient between it and the characteristic index Y corresponding to the first chip characteristic It can be calculated by the following formula:

[0110]

[0111] in, represents the i-th observation value of the j-th potential association indicator, represents the average value of the jth potential correlation index, represents the i-th observed value of the feature index corresponding to the first chip feature, represents the average value of the characteristic index corresponding to the first chip feature, and n represents the number of observations.

[0112] Then, based on the correlation evaluation results, target potential correlation features that are highly correlated with the feature indicators of the first chip feature are screened out. In some embodiments, the correlation coefficients corresponding to the potential correlation indicators can be sorted in descending order from large to small, wherein the sorting result will reflect the strength of the correlation between each potential correlation indicator and the feature indicator corresponding to the first chip feature. Then, the target potential correlation indicator can be extracted from the sorting results according to a preset ratio (such as the first 80%), and the real-time operation data under the target potential correlation indicator can be obtained from the real-time operation data of the chip as the target potential correlation feature. These selected features will be used for subsequent model building work.

[0113] In this embodiment, through correlation quantification and feature sorting, features with low correlation with target features are removed, key information is retained, and the accuracy of analysis is improved.

[0114] In some exemplary embodiments, performing cluster analysis based on target potential association features to obtain target association features may include the following steps:

[0115] Determine a target data set consisting of target potential associated features; based on the data distribution characteristics of the target data set, select M data points from the target data set as initial cluster centers; cluster the target data set based on the initial cluster centers to obtain multiple clusters, and determine the cluster representative features corresponding to each cluster; obtain multiple target associated features based on the cluster representative features of the multiple clusters.

[0116] Wherein, M is a positive integer greater than or equal to 2.

[0117] In practical applications, after obtaining multiple target potential correlation features, a target data set consisting of target potential correlation features can be obtained, and each data point in the target data set corresponds to a target potential correlation feature. Then, the initial cluster center can be selected based on the data distribution characteristics to reduce the algorithm's dependence on the initial selection and improve the stability and accuracy of the clustering results. After determining the initial cluster center, the target data set can be clustered based on the initial cluster center to obtain multiple cluster clusters.

[0118] Specifically, for each data point in the target data set, the distance between the data point and each initial cluster center is calculated respectively, and the data point is assigned to the cluster with the closest distance, for example, the distance between the data point and the cluster center is calculated, and the data point is assigned to the nearest cluster. Afterwards, for each cluster formed, the average value of all data points in the cluster on the weighted feature dimension is calculated according to the feature weight to form a new cluster center. For example, when calculating the cluster center, instead of simply taking the average value of all data points in the cluster on each feature dimension, the value of each feature dimension can be weighted according to the feature weight and then the average value is taken. Specifically, for each cluster and each feature dimension, the sum of all weighted data points on the dimension is calculated, and then divided by the total number of weighted data points to obtain the weighted average value. Afterwards, the weighted average value is used as the value of the new cluster center on the corresponding feature dimension, so that the new cluster center formed takes into account the importance of different features to the clustering results. Repeating the steps until the preset convergence conditions are met, multiple clusters can be obtained.

[0119] Furthermore, a representative feature can be selected from each currently formed cluster as a cluster representative feature, and multiple target-related features can be obtained based on the cluster representative features of each of the multiple clusters. For example, the center or average value corresponding to each cluster can be used as the cluster representative feature.

[0120] In this embodiment, the initial cluster center is selected based on the data distribution characteristics, which can reduce the algorithm's sensitivity to the initial selection, thereby reducing the risk of falling into a local optimal solution, which helps to improve the stability and accuracy of the clustering results. Considering feature weights when calculating cluster centers can make the clustering process more focused on features that have an important impact on the clustering results. In this way, the formation of cluster centers will be more in line with the actual distribution of the data, so that the cluster representative features can more accurately reflect the inherent structure and characteristics of the data.

[0121] In one embodiment, in step S103, using the second chip feature to perform model training on the machine learning model may include the following steps:

[0122] Obtain the operational reliability label of the chip under real-time operational data; input the second chip feature into the machine learning model for forward propagation to obtain the predicted output of the model; calculate the loss function value based on the prediction error between the predicted output and the operational reliability label; execute the back propagation algorithm based on the loss function value to determine the gradient of the model parameters of the machine learning model; estimate the mean of the gradient by exponentially weighted moving average to obtain a first-order moment estimate, and estimate the mean of the square of the gradient by exponentially weighted moving average to obtain a second-order moment estimate; perform bias correction on the first-order moment estimate and the second-order moment estimate according to the adaptive bias correction and momentum attenuation factor adjustment, and calculate the update amount of each model parameter in combination with the global learning rate, and update the model parameters of the machine learning model; return to execute the input of the second chip feature into the machine learning model for forward propagation to obtain the predicted output of the model, iteratively adjust the model parameters of the machine learning model until the training end conditions are met, and obtain a trained machine learning model.

[0123] Among them, the operation reliability label represents the chip operation reliability when the chip has real-time operation data.

[0124] In practical applications, the second chip feature can be input into the machine learning model for forward propagation to obtain the model's predicted output, which can be understood as the chip's operational reliability predicted by the machine learning model based on the second chip feature. Then, the prediction error between the predicted output and the pre-acquired operational reliability label can be determined, and the loss function value can be calculated based on the prediction error.

[0125] Afterwards, the back propagation algorithm can be executed based on the loss function value to determine the gradient of the model parameters of the machine learning model, the mean of the gradient is estimated by exponentially weighted moving average to obtain the first-order moment estimate, the mean of the square of the gradient is estimated by exponentially weighted moving average to obtain the second-order moment estimate, and then the first-order moment estimate and the second-order moment estimate are corrected for deviations.

[0126] In the prior art, deviation correction usually uses a fixed decay rate to calculate the deviation correction term of the moving average. In this embodiment, in order to further improve the adaptability and stability of the algorithm, an adaptive deviation correction method is introduced. This method dynamically adjusts the decay rate of the deviation correction term according to the statistical characteristics of the gradient. Specifically, when the gradient distribution changes greatly, the decay rate will be increased to correct the deviation faster; and when the gradient distribution is relatively stable, the decay rate will be appropriately reduced to maintain the stability of the estimate. In addition, for the adjustment of the momentum decay factor, it is considered that different momentum strengths may be required in different training stages to accelerate convergence or jump out of the local optimum. Therefore, this embodiment also designs a strategy to dynamically adjust the momentum decay factor. This adjustment can be based on the rate of change of the gradient, the rate of decline of the loss function, or the improvement of the model performance. For example, when the loss function decreases slowly, the momentum decay factor will be appropriately increased to strengthen the momentum effect; and when the loss function fluctuates greatly, the momentum decay factor will be appropriately reduced to stabilize the training process.

[0127] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0128] Based on the same inventive concept, the embodiment of the present application also provides a chip operation reliability determination device for implementing the chip operation reliability determination method involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in one or more embodiments of the chip operation reliability determination device provided below can refer to the limitations of the chip operation reliability determination method above, and will not be repeated here.

[0129] In an exemplary embodiment, Figure 3 As shown, a device for determining chip operation reliability is provided, comprising:

[0130] A historical feature extraction module 301 is used to obtain historical operation data of a chip, perform feature extraction on the historical operation data of the chip, and obtain a first chip feature reflecting the operation state and chip performance of the chip;

[0131] A feature crossover module 302 is used to obtain real-time operation data of the chip, perform feature crossover on the first chip feature and the real-time operation data of the chip, and obtain a second chip feature reflecting the comprehensive operation performance of the chip;

[0132] A model training module 303 is used to perform model training on a machine learning model using the second chip feature, and obtain a trained operation reliability prediction model corresponding to the chip when a training end condition is met;

[0133] The model prediction module 304 is used to obtain the chip operation reliability prediction result of the chip based on the trained operation reliability prediction model.

[0134] In one embodiment, the historical feature extraction module 301 is used to:

[0135] Processing the historical operation data of the chip according to a preset data preprocessing method to obtain processed historical operation data, wherein the data preprocessing method includes at least one of outlier filtering, missing value supplementation, data denoising, and data formatting;

[0136] Determining performance parameters reflecting the processing speed, power consumption, and temperature of the chip from the processed historical operation data, and determining resource occupancy parameters of the chip from the processed historical operation data;

[0137] The performance parameter and the resource occupancy parameter are calculated and quantified to obtain a first chip characteristic reflecting an average processing speed, a maximum power consumption, a temperature fluctuation range, and a resource utilization rate of the chip.

[0138] In one embodiment, the feature intersection module 302 is used to:

[0139] Determining target potential correlation features related to the first chip features from the real-time operation data of the chip, and performing cluster analysis based on the target potential correlation features to obtain target correlation features;

[0140] Combining the obtained target-related features to obtain a corresponding first feature set, and combining the first chip features to obtain a corresponding second feature set;

[0141] Traversing each element in the first feature set, during the traversal process, multiplying the currently traversed element with each element in the second feature set, and performing weighted summation on the obtained multiplication results to obtain a combined feature corresponding to the currently traversed element; wherein each multiplication result has a corresponding weight, and the weight is adjusted according to the prediction error of the machine learning model;

[0142] The combined feature corresponding to each element in the first feature set is determined as a second chip feature reflecting the comprehensive operating performance of the chip.

[0143] In one embodiment, the feature intersection module 302 is used to:

[0144] Based on the principal component analysis method, determining potential correlation indicators from multiple data indicators corresponding to the real-time operation data of the chip;

[0145] For each of the potential correlation indicators, calculating a correlation coefficient between the potential correlation indicator and a feature indicator corresponding to the first chip feature;

[0146] According to the magnitude of the coefficients of the correlation coefficients, the potential correlation indicators are sorted in descending order, and the first K potential correlation indicators are used as target potential correlation indicators; K is a positive integer greater than or equal to 1;

[0147] The real-time operation data under the target potential association index is obtained from the real-time operation data of the chip as the target potential association feature.

[0148] In one embodiment, the feature intersection module 302 is used to:

[0149] Determine a target data set consisting of all target potential associated features; each data point in the target data set corresponds to one of the target potential associated features;

[0150] Based on the data distribution characteristics of the target data set, M data points are selected from the target data set as initial cluster centers; M is a positive integer greater than or equal to 2;

[0151] Clustering the target data set based on the initial cluster centers to obtain a plurality of clusters, and determining a cluster representative feature corresponding to each of the clusters;

[0152] A plurality of target-related features are obtained according to the cluster representative features of each of the plurality of clusters.

[0153] In one embodiment, the model training module 303 is used to:

[0154] Acquire an operation reliability label of the chip under the real-time operation data; the operation reliability label indicates the chip operation reliability when the chip has the real-time operation data;

[0155] Inputting the second chip feature into the machine learning model for forward propagation to obtain a prediction output of the model;

[0156] Calculating a loss function value based on a prediction error between the prediction output and the operational reliability label;

[0157] Execute a back propagation algorithm based on the loss function value to determine the gradient of the model parameters of the machine learning model;

[0158] Estimate the mean of the gradient by exponentially weighted moving average to get the first-order moment estimate, and estimate the mean of the square of the gradient by exponentially weighted moving average to get the second-order moment estimate;

[0159] According to the adaptive deviation correction and momentum attenuation factor adjustment, the first-order moment estimation and the second-order moment estimation are subjected to deviation correction, and the update amount of each model parameter is calculated in combination with the global learning rate, and the model parameters of the machine learning model are updated;

[0160] Return to execute inputting the second chip feature into the machine learning model for forward propagation, obtaining the predicted output of the model, iteratively adjusting the model parameters of the machine learning model until the training end condition is met, and obtaining a trained machine learning model.

[0161] Each module in the above-mentioned chip operation reliability determination device can be implemented in whole or in part by software, hardware and a combination thereof. Each of the above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the corresponding operations of each of the above modules.

[0162] In an exemplary embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as shown in FIG. Figure 4 As shown. The computer device includes a processor, a memory, an input / output interface (Input / Output, referred to as I / O) and a communication interface. Among them, the processor, the memory and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store the operation data of the chip. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a method for determining the reliability of chip operation is implemented.

[0163] In an exemplary embodiment, a computer device is provided. The computer device may be a terminal, and its internal structure diagram may be as shown in FIG. Figure 5As shown. The computer device includes a processor, a memory, an input / output interface, a communication interface, a display unit and an input device. The processor, the memory and the input / output interface are connected through a system bus, and the communication interface, the display unit and the input device are connected to the system bus through the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be implemented through WIFI, a mobile cellular network, near field communication (NFC) or other technologies. When the computer program is executed by the processor, a chip operation reliability determination method is implemented. The display unit of the computer device is used to form a visually visible picture, which can be a display screen, a projection device or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covering the display screen, or a button, trackball or touchpad set on the computer device shell, or an external keyboard, touchpad or mouse.

[0164] Those skilled in the art will understand that Figure 4 and Figure 5 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0165] In one embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the steps in the above-mentioned method embodiments when executing the computer program.

[0166] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments are implemented.

[0167] In one embodiment, a computer program product is provided, including a computer program, which implements the steps in the above method embodiments when executed by a processor.

[0168] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.

[0169] A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., but are not limited to this.

[0170] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0171] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A method for determining chip operation reliability, characterized in that: The method comprises: Acquire historical operation data of a chip, perform feature extraction on the historical operation data of the chip, and obtain a first chip feature reflecting an operation state and chip performance of the chip; Acquire real-time operation data of the chip, perform feature cross-talk between the first chip feature and the real-time operation data of the chip, and obtain a second chip feature reflecting the comprehensive operation performance of the chip; Performing model training on the machine learning model using the second chip feature, and obtaining a trained operation reliability prediction model corresponding to the chip when a training end condition is met; A chip operation reliability prediction result of the chip is obtained based on the trained operation reliability prediction model.

2. The method according to claim 1, characterized in that The extracting features from the historical operation data of the chip to obtain a first chip feature reflecting the operation state and chip performance of the chip includes: Processing the historical operation data of the chip according to a preset data preprocessing method to obtain processed historical operation data, wherein the data preprocessing method includes at least one of outlier filtering, missing value supplementation, data denoising, and data formatting; Determining performance parameters reflecting the processing speed, power consumption, and temperature of the chip from the processed historical operation data, and determining resource occupancy parameters of the chip from the processed historical operation data; The performance parameter and the resource occupancy parameter are calculated and quantified to obtain a first chip characteristic reflecting an average processing speed, a maximum power consumption, a temperature fluctuation range, and a resource utilization rate of the chip.

3. The method according to claim 1, characterized in that The performing feature cross-talk between the first chip feature and the real-time operation data of the chip to obtain a second chip feature reflecting the comprehensive operation performance of the chip includes: Determining target potential correlation features related to the first chip features from the real-time operation data of the chip, and performing cluster analysis based on the target potential correlation features to obtain target correlation features; Combining the obtained target-related features to obtain a corresponding first feature set, and combining the first chip features to obtain a corresponding second feature set; Traversing each element in the first feature set, during the traversal process, multiplying the currently traversed element with each element in the second feature set, and performing weighted summation on the obtained multiplication results to obtain a combined feature corresponding to the currently traversed element; wherein each multiplication result has a corresponding weight, and the weight is adjusted according to the prediction error of the machine learning model; The combined features corresponding to the elements in the first feature set are determined as second chip features reflecting the comprehensive operating performance of the chip.

4. The method according to claim 3, characterized in that The step of determining a target potential associated feature related to the first chip feature from the real-time operation data of the chip comprises: Based on the principal component analysis method, determining potential correlation indicators from multiple data indicators corresponding to the real-time operation data of the chip; For each of the potential correlation indicators, calculating a correlation coefficient between the potential correlation indicator and a feature indicator corresponding to the first chip feature; According to the magnitude of the coefficients of the correlation coefficients, the potential correlation indicators are sorted in descending order, and the first K potential correlation indicators are used as target potential correlation indicators; K is a positive integer greater than or equal to 1; The real-time operation data under the target potential association index is obtained from the real-time operation data of the chip as the target potential association feature.

5. The method according to claim 4, characterized in that The cluster analysis is performed based on the target potential correlation features to obtain the target correlation features, including: Determine a target data set consisting of all target potential associated features; each data point in the target data set corresponds to one of the target potential associated features; Based on the data distribution characteristics of the target data set, M data points are selected from the target data set as initial cluster centers; M is a positive integer greater than or equal to 2; Clustering the target data set based on the initial cluster centers to obtain a plurality of clusters, and determining a cluster representative feature corresponding to each of the clusters; A plurality of target-related features are obtained according to the cluster representative features of each of the plurality of clusters.

6. The method according to any one of claims 1 to 5, characterized in that The using the second chip feature to perform model training on the machine learning model includes: Acquire an operation reliability label of the chip under the real-time operation data; the operation reliability label indicates the chip operation reliability when the chip has the real-time operation data; Inputting the second chip feature into the machine learning model for forward propagation to obtain a prediction output of the model; Calculating a loss function value based on a prediction error between the prediction output and the operational reliability label; Execute a back propagation algorithm based on the loss function value to determine the gradient of the model parameters of the machine learning model; Estimate the mean of the gradient by exponentially weighted moving average to get the first-order moment estimate, and estimate the mean of the square of the gradient by exponentially weighted moving average to get the second-order moment estimate; According to the adaptive deviation correction and momentum attenuation factor adjustment, the first-order moment estimation and the second-order moment estimation are subjected to deviation correction, and the update amount of each model parameter is calculated in combination with the global learning rate, and the model parameters of the machine learning model are updated; Return to execute inputting the second chip feature into the machine learning model for forward propagation, obtain the predicted output of the model, iteratively adjust the model parameters of the machine learning model until the training end condition is met, and obtain a trained machine learning model.

7. A device for determining chip operation reliability, characterized in that: The device comprises: A historical feature extraction module, used for acquiring historical operation data of a chip, performing feature extraction on the historical operation data of the chip, and obtaining a first chip feature reflecting the operation state and chip performance of the chip; A feature crossover module, used to obtain real-time operation data of the chip, perform feature crossover on the first chip feature and the real-time operation data of the chip, and obtain a second chip feature reflecting the comprehensive operation performance of the chip; A model training module, used to perform model training on a machine learning model using the second chip characteristics, and obtain a trained operation reliability prediction model corresponding to the chip when a training end condition is met; The model prediction module is used to obtain the chip operation reliability prediction result of the chip based on the trained operation reliability prediction model.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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