Clock signal parameter measurement method and related equipment

Abstract

The embodiment of the invention provides a parameter measurement method of a clock signal and related equipment. The parameter measurement method of the clock signal comprises the following steps: acquiring power consumption simulation data and signal simulation data of a to-be-tested design in a plurality of pre-silicon test scenes; determining normalized dynamic power consumption of each pre-silicon test scene according to the power consumption simulation data of each pre-silicon test scene; according to the signal simulation data of each pre-silicon test scene, determining an enabling state of a clock signal of each pre-silicon test scene, the clock signal having a plurality of enabling states; and determining the weight of each enabling state of the clock signal according to the normalized dynamic power consumption and the enabling state of the clock signal of each pre-silicon test scene based on the normalized dynamic power consumption, the various enabling states of the clock signal and the linear relation among the weight of the enabling state. And the calculation precision of post-silicon dynamic power consumption can be improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer technology, and specifically to a method for measuring parameters of a clock signal, and related equipment. Background Art

[0002] As the complexity of the circuits in integrated circuit products increases, the power consumption of the chip is also increasing. The increase in chip power consumption will lead to an increase in chip heat generation and a decrease in reliability. The existing solution for shielding chip power consumption requires the chip to have the function of real-time and accurate monitoring of the current power consumption of the chip. Therefore, how to improve the accuracy of power consumption calculation has become a problem that needs to be solved urgently by those skilled in the art. Summary of the invention

[0003] In view of this, an embodiment of the present application provides a method for measuring parameters of a clock signal, and related equipment, to improve the accuracy of power consumption calculation.

[0004] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions:

[0005] The present application provides a method for measuring parameters of a clock signal, including:

[0006] Get simulation data for the design under test in multiple pre-silicon test scenarios;

[0007] Determine simulated dynamic power consumption and theoretical dynamic power consumption of each pre-silicon test scenario according to simulation data of each pre-silicon test scenario;

[0008] Based on the nonlinear relationship among the simulated dynamic power consumption, the theoretical dynamic power consumption, and the normalized dynamic power consumption of the clock signal, the simulated dynamic power consumption of each pre-silicon test scenario and the normalized dynamic power consumption of the clock signal corresponding to the theoretical dynamic power consumption are determined respectively, and the normalized dynamic power consumption of the clock signal of each pre-silicon test scenario is obtained;

[0009] and, determining an enable state of a clock signal of each pre-silicon test scenario according to simulation data of each pre-silicon test scenario, wherein the clock signal has a plurality of enable states;

[0010] The weights of the various enable states of the clock signal are determined based on the normalized dynamic power consumption of the clock signal, the various enable states of the clock signal, and the linear relationship between the weights of the enable states.

[0011] Optionally, the theoretical dynamic power consumption is the dynamic power consumption corresponding to the flip signal of the design under test; the nonlinear relationship is a nonlinear dynamic power consumption model modeled using the flip signal and clock signal of the design under test; wherein, the clock signal has a global impact on the design under test, and the global impact is represented by the normalized dynamic power consumption of the clock signal and expressed as a multiplication factor in the nonlinear dynamic power consumption model.

[0012] Optionally, determining the simulated dynamic power consumption of each pre-silicon test scenario according to the simulation data of each pre-silicon test scenario includes:

[0013] For any pre-silicon test scenario, a waveform file of the pre-silicon test scenario is obtained from simulation data of the pre-silicon test scenario; power consumption analysis is performed on the waveform file by an electronic design automation tool for power consumption analysis to obtain simulated dynamic power consumption of the pre-silicon test scenario;

[0014] Determining the theoretical dynamic power consumption of each pre-silicon test scenario according to the simulation data of each pre-silicon test scenario includes:

[0015] For any pre-silicon test scenario, the theoretical dynamic power consumption of the pre-silicon test scenario is determined based on the toggle rates of each toggle signal of the pre-silicon test scenario and the predetermined toggle weights of each toggle signal; wherein the linear weighted result of the toggle rates and toggle weights of each toggle signal is expressed as the theoretical dynamic power consumption.

[0016] Optionally, based on the nonlinear relationship among the simulated dynamic power consumption, the theoretical dynamic power consumption, and the normalized dynamic power consumption of the clock signal, respectively determining the simulated dynamic power consumption of each pre-silicon test scenario and the normalized dynamic power consumption of the clock signal corresponding to the theoretical dynamic power consumption, and obtaining the normalized dynamic power consumption of the clock signal of each pre-silicon test scenario includes:

[0017] For any pre-silicon test scenario, the simulated dynamic power consumption of the pre-silicon test scenario is divided by the theoretical dynamic power consumption of the pre-silicon test scenario to obtain the normalized dynamic power consumption of the clock signal of the pre-silicon test scenario.

[0018] Optionally, the determining the weights of various enable states of the clock signal based on the normalized dynamic power consumption of the clock signal, various enable states of the clock signal, and the linear relationship between the weights of the enable states includes:

[0019] The weights of the various enable states of the clock signal are determined based on that a linear weighted result between the various enable states of the clock signal and the weights of the enable states represents the normalized dynamic power consumption of the clock signal.

[0020] Optionally, the multiple enabled states of the clock signal include an on state and an off state of the clock signal; the weights of the various enabled states of the clock signal include: a weight of the on state of the clock signal, and a weight of the off state of the clock signal;

[0021] The linear weighted result between the various enabled states of the clock signal and the weights of the enabled states represents the normalized dynamic power consumption of the clock signal. Determining the weights of the various enabled states of the clock signal includes:

[0022] The linear weighted result between various enabled states of the clock signal and the weights of the enabled states represents the normalized dynamic power consumption of the clock signal, and the weights of various enabled states of the clock signal are determined through matrix operations; wherein, in the matrix operations, the value of the weight of the on state represents the proportion of maskable power consumption to the total power consumption of the design under test, and the value of the weight of the off state represents the proportion of non-maskable power consumption to the total power consumption of the design under test.

[0023] Optionally, the linear weighted result between various enable states of the clock signal and the weights of the enable states represents the normalized dynamic power consumption of the clock signal, and determining the weights of various enable states of the clock signal through matrix operation includes:

[0024] Constructing an enable state matrix, wherein the enable state matrix represents the on state and the off state of the clock signal in each pre-silicon test scenario; wherein the state value of the clock signal in the on state is configured as the zeroth value to shield the shieldable power consumption, and the state value of the clock signal in the off state is configured as the first value to not shield the shieldable power consumption;

[0025] and, constructing a power consumption vector based on the normalized dynamic power consumption of the clock signal for each pre-silicon test scenario;

[0026] With the goal of minimizing the difference between the power consumption prediction vector and the power consumption vector, the weight of the on state and the weight of the off state of the clock signal are predicted according to the enable state matrix and the power consumption vector; wherein the power consumption prediction vector is the product of the enable state matrix and the weight vector, the weight vector is composed of the predicted weight of the on state and the weight of the off state of the clock signal, and the weight of the enable state and the weight of the off state of the clock signal are non-negative numbers.

[0027] Optionally, the step of minimizing the difference between the power consumption prediction vector and the power consumption vector and predicting the weight of the enabled state and the weight of the disabled state of the clock signal according to the enabled state matrix and the power consumption vector comprises:

[0028] The weight of the enabled state and the weight of the disabled state of the clock signal are predicted according to the enable state matrix and the power consumption vector by using a non-negative least squares algorithm with the goal of minimizing the difference between the predicted power consumption vector and the power consumption vector.

[0029] Optionally, the step of determining the flip weights of the flip signals includes:

[0030] Based on the weighted sum relationship between the simulated dynamic power consumption and the flip rate and flip weight of the flip signal, the simulated dynamic power consumption of each pre-silicon test scenario and the flip rate of the multiple flip signals in each pre-silicon test scenario are fitted to obtain the flip weights of the multiple flip signals of the design to be tested.

[0031] Optionally, the simulated dynamic power consumption of each pre-silicon test scenario and the flip rates of the multiple flip signals in each pre-silicon test scenario are fitted based on the weighted sum relationship between the dynamic power consumption and the flip rate and flip weight of the flip signal to obtain the flip weights of the multiple flip signals of the design to be tested, including:

[0032] According to the number of the plurality of pre-silicon test scenarios and the number of the plurality of flip signals, construct a flip rate matrix to represent the flip rates of the plurality of flip signals in each pre-silicon test scenario;

[0033] and, constructing a dynamic power consumption vector according to the number of the plurality of pre-silicon test scenarios to represent the simulated dynamic power consumption of each of the pre-silicon test scenarios;

[0034] With the goal of minimizing the difference between the dynamic power consumption prediction vector and the dynamic power consumption vector, the flip weights of the multiple flip signals are predicted based on the flip rate matrix and the dynamic power consumption vector; wherein the dynamic power consumption prediction vector is the product of the flip rate matrix and the flip weight vector, the flip weight vector is composed of the predicted flip weights of each flip signal, and the flip weights of the multiple flip signals are non-negative numbers.

[0035] The embodiment of the present application also provides a method for obtaining dynamic power consumption, including:

[0036] Acquire operation data of the design to be tested when it is running after silicon operation, wherein the operation data at least includes an enable state of a clock signal;

[0037] Determine the normalized dynamic power consumption of the clock signal according to the enable state of the clock signal and the predetermined weight of the enable state of the clock signal; wherein the weight of the enable state of the clock signal is determined based on the parameter measurement method of the clock signal as described above;

[0038] The post-silicon dynamic power consumption of the design under test is determined based at least on the normalized dynamic power consumption of the clock signal.

[0039] Optionally, the operation data further includes: the flip rate of each flip signal of the design to be tested;

[0040] The dynamic power consumption acquisition method further includes:

[0041] Determine the theoretical dynamic power consumption of the design to be tested according to the toggle rates of the toggle signals and the predetermined toggle weights of the toggle signals;

[0042] Determining the post-silicon dynamic power consumption of the design under test at least according to the normalized dynamic power consumption of the clock signal includes:

[0043] The post-silicon dynamic power consumption of the design to be tested is determined according to the normalized dynamic power consumption of the clock signal and the theoretical dynamic power consumption of the design to be tested.

[0044] The present application also provides a clock signal parameter acquisition device, comprising:

[0045] A simulation data acquisition module, used to acquire simulation data of the design under test in multiple pre-silicon test scenarios;

[0046] A power consumption calculation module, used to determine the simulated dynamic power consumption and theoretical dynamic power consumption of each pre-silicon test scenario according to the simulation data of each pre-silicon test scenario;

[0047] An impact degree calculation module is used to determine the simulated dynamic power consumption of each pre-silicon test scenario and the normalized dynamic power consumption of the clock signal corresponding to the theoretical dynamic power consumption based on the nonlinear relationship between the simulated dynamic power consumption, the theoretical dynamic power consumption, and the normalized dynamic power consumption of the clock signal, and obtain the normalized dynamic power consumption of the clock signal of each pre-silicon test scenario;

[0048] A state determination module, used to determine the enable state of the clock signal of each pre-silicon test scenario according to the simulation data of each pre-silicon test scenario, wherein the clock signal has multiple enable states;

[0049] The weight calculation module is used to determine the weights of various enable states of the clock signal based on the normalized dynamic power consumption of the clock signal, various enable states of the clock signal and the linear relationship between the weights of the enable states.

[0050] The embodiment of the application also provides a dynamic power consumption acquisition device, including

[0051] An operation data acquisition module, used to acquire operation data of the design to be tested when it is running after silicon operation, wherein the operation data at least includes an enable state of a clock signal;

[0052] A power consumption impact acquisition module, used to determine the normalized dynamic power consumption of the clock signal according to the enable state of the clock signal and the predetermined weight of the enable state of the clock signal; wherein the weight of the enable state of the clock signal is determined based on the parameter measurement method of the clock signal as described above;

[0053] A dynamic power consumption calculation module is used to determine the post-silicon dynamic power consumption of the design to be tested based on at least the normalized dynamic power consumption of the clock signal.

[0054] An embodiment of the present application also provides a computing device, including a memory and a processor, wherein the memory stores computer instructions, and the processor calls the computer instructions stored in the memory to execute the clock signal parameter measurement method as described above, or the dynamic power consumption acquisition method as described above.

[0055] An embodiment of the present application also provides a storage medium, which stores computer instructions. When the computer instructions are executed, the parameter measurement method of the clock signal as described above, or the dynamic power consumption acquisition method as described above is implemented.

[0056] An embodiment of the present application also provides a computer program product, including computer instructions, which, when executed, implement the clock signal parameter measurement method as described above, or the dynamic power consumption acquisition method as described above.

[0057] The clock signal parameter measurement method provided in the embodiment of the present application obtains simulation data of the design to be tested in multiple pre-silicon test scenarios; determines the simulated dynamic power consumption and theoretical dynamic power consumption of each pre-silicon test scenario based on the simulation data of each pre-silicon test scenario; based on the nonlinear relationship among the simulated dynamic power consumption, the theoretical dynamic power consumption, and the normalized dynamic power consumption of the clock signal, determines the simulated dynamic power consumption of each pre-silicon test scenario and the normalized dynamic power consumption of the clock signal corresponding to the theoretical dynamic power consumption, and obtains the normalized dynamic power consumption of the clock signal of each pre-silicon test scenario; and, based on the simulation data of each pre-silicon test scenario, determines the enable state of the clock signal of each pre-silicon test scenario, wherein the clock signal has multiple enable states; based on the linear relationship between the normalized dynamic power consumption of the clock signal, various enable states of the clock signal, and the weights of the enable states, determines the weights of various enable states of the clock signal.

[0058] In this way, by accurately obtaining the state of the clock signal that affects the overall power consumption of the design to be tested, and the weights of the multiple states of the clock signal during the simulation process, the influence of the multiple states of the clock signal can be introduced into the calculation formula when calculating the post-silicon dynamic power consumption. At the same time, the clock signal can shield part of the power consumption of the design to be tested. Then, when calculating the overall power consumption of the design to be tested, according to the enable state of the clock signal, the power consumption of the shielded part of the design to be tested is excluded from the calculation formula. Thereby avoiding the erroneous calculation of the power consumption value of the clock signal into the calculation result of the overall power consumption of the design to be tested when calculating the post-silicon dynamic power consumption, so as to improve the calculation accuracy of the post-silicon dynamic power consumption. And the weights of the multiple states of the clock signal obtained by fitting and calculating multiple sets of data have higher accuracy, which further ensures the calculation accuracy of the post-silicon dynamic power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0060] Figure 1 A schematic diagram of a first flow chart of a method for measuring parameters of a clock signal provided in an embodiment of the present application;

[0061] Figure 2 A second flow chart of the method for measuring parameters of a clock signal provided in an embodiment of the present application;

[0062] Figure 3 A third flow chart of the method for measuring parameters of a clock signal provided in an embodiment of the present application;

[0063] Figure 4 A schematic diagram of a partial structure of a design to be tested provided in an embodiment of the present application;

[0064] Figure 5 A flow chart of a method for obtaining dynamic power consumption is provided for an embodiment of the present application;

[0065] Figure 6 A schematic diagram of the structure of a clock signal parameter acquisition device provided in an embodiment of the present application;

[0066] Figure 7 A schematic diagram of the structure of a dynamic power consumption acquisition device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0067] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0068] As the chip scale expands, the power consumption of the chip is also increasing. Excessive power consumption of the chip will lead to increased heat generation and decreased reliability. Therefore, whether the power consumption of the chip is reasonable is an important consideration in integrated circuit design. Chip design not only pursues high performance and small area, but also has comprehensive requirements for performance, area, and power consumption. Low-power design that reduces chip power consumption has become an important technology in chip design.

[0069] One low-power solution is to monitor the current power consumption of the chip in real time and adjust the frequency and voltage of the chip according to the current power consumption of the chip. Specifically, TDP (Thermal Design Power) is the thermal design power consumption index of the chip, which is used to identify how much heat the chip is designed to dissipate to ensure that it can work stably at the nominal frequency. Without exceeding TDP, the maximum operating frequency and maximum operating voltage need to be set to achieve optimal performance. Otherwise, the clock frequency and voltage can only be set by retaining a large margin, which will cause performance loss. When adjusting the frequency and voltage of the chip, it is usually combined with AVFS (Adaptive Voltage Frequency Scaling) or DVFS (Dynamic Voltage Frequency Scaling) technology. This low-power solution requires that the chip has the function of accurately monitoring the current power consumption of the chip in real time.

[0070] The power consumption of a chip consists of dynamic power consumption and background power consumption. Dynamic power consumption consists of switch power consumption and short-circuit power consumption. Background power consumption is exponentially related to voltage and temperature.

[0071] Dynamic power consumption accounts for a large proportion of chip power consumption, but as the process changes, background power consumption also accounts for a large proportion. Since the overall background power consumption is exponentially related to voltage and temperature, and the technology for measuring voltage and temperature is simple and highly accurate, the background power consumption can be accurately calculated by real-time monitoring of temperature and voltage.

[0072] There are many factors that affect the dynamic power consumption of a chip, including chip voltage, chip manufacturing process, chip circuit scale, clock frequency, signal flip rate, circuit working status, etc., which will affect the dynamic power consumption of the chip. Therefore, estimating dynamic power consumption is relatively difficult and requires the establishment of a reasonable mathematical model.

[0073] Furthermore, the dynamic power consumption of the chip is mainly composed of the flip power consumption and short-circuit power consumption within the chip. The calculation formula of the flip power consumption is: P switch =C eff ×V 2 ×F. The formula for calculating short-circuit power consumption is: The calculation formula of dynamic power consumption is to sum the flip power consumption and short-circuit power consumption, that is, P dyn =P switch +P short Among them, C eff is the effective capacitance, V is the power supply voltage, F is the frequency, t sc is the short circuit time, V t is the transistor threshold voltage, and τ is the transistor gain factor.

[0074] After further simplifying the calculation formula of dynamic power consumption, we can get the formula: P dyn =(C m ×V+C b )×V 2 ×F, where C b =C eff ,

[0075] In the above formula, information such as effective capacitance and short-circuit time cannot be measured in the chip, so they can be combined into C m and C b These two parameters can be obtained through post-silicon testing. The voltage value V of the chip can be directly obtained by directly measuring the voltage of the circuit. The frequency F is proportional to the dynamic power consumption, so as long as the frequency F can be accurately obtained, the dynamic power consumption can be estimated more accurately.

[0076] In a method for power consumption estimation, the simulated dynamic power consumption of the design to be tested, which can be accurately obtained during the simulation process, and the flip rates of multiple flip signals, are used to calculate the flip weights related to the flip rate of the flip signal based on the linear relationship between the dynamic power consumption of the design to be tested and the signal flip. Since the simulated dynamic power consumption used to obtain the flip weight is accurate, when the design to be tested is used after silicon, the post-silicon dynamic power consumption of the design to be tested, calculated by using the flip weight and the flip rate of the flip signal that is accurately measured, and the post-silicon dynamic power consumption of the design to be tested are both accurate values. This avoids using the estimated dynamic power consumption value with a large error to calculate the post-silicon dynamic power consumption when calculating the post-silicon dynamic power consumption, thereby improving the calculation accuracy of the post-silicon dynamic power consumption.

[0077] However, among the flip signals used in the above method, some flip signals not only affect the power consumption of the design under test, but also affect the power consumption of the chip as a whole, and the impact on the power consumption of the chip as a whole is positively correlated with the signal flip rate, for example, the clock gating signal that controls the function module to obtain the clock signal. Therefore, it is sometimes difficult to simulate accurate power consumption using a linear model alone.

[0078] To solve the above problems, the present application provides a method for measuring the parameters of a clock signal, which introduces the clock signal that affects the overall power consumption of the chip into the formula for calculating the power consumption of the chip to more accurately calculate the power consumption of the chip. As an optional implementation, Figure 1 FIG. 1 is a flow chart of a signal measurement method provided in an embodiment of the present application. Figure 1 As shown, the method for measuring parameters of a clock signal provided in an embodiment of the present application includes the following steps.

[0079] Step S10: Obtain power consumption simulation data and signal simulation data of the design to be tested in multiple pre-silicon test scenarios.

[0080] It should be noted that the design to be tested is the program code or digital circuit obtained during the design phase of the above chip. The circuit to be tested that needs to measure the post-silicon power consumption refers to the circuit of the post-silicon electronic components obtained after the chip is manufactured.

[0081] It should be noted that the design to be tested is the program code or digital circuit obtained during the design phase of the above-mentioned chip. The pre-silicon is the time node before the actual sample of the design to be tested is obtained during the production and manufacturing process of the chip; the pre-silicon test scenario is the simulation test scenario used for the design to be tested before silicon. Correspondingly, post-silicon is the time node after the actual sample of the design to be tested is obtained during the production and manufacturing process of the chip. The post-silicon circuit to be tested refers to the circuit of the electronic components after silicon obtained after the chip is manufactured.

[0082] Afterwards, it is necessary to determine the normalized dynamic power consumption of each pre-silicon test scenario based on the power consumption simulation data of each pre-silicon test scenario.

[0083] Specifically, it includes step S20: determining the simulated dynamic power consumption of each pre-silicon test scenario according to the power consumption simulation data of each pre-silicon test scenario, and determining the theoretical dynamic power consumption according to the signal simulation data of each pre-silicon test scenario.

[0084] Regarding the acquisition method of the simulated dynamic power consumption and the theoretical dynamic power consumption, in an optional implementation, as Figure 2 As shown, step S20 includes step S21 and step S22.

[0085] Step S21: for any pre-silicon test scenario, obtain a waveform file of the pre-silicon test scenario from the power consumption simulation data of the pre-silicon test scenario; perform power consumption analysis on the waveform file using an electronic design automation tool for power consumption analysis to obtain the simulated dynamic power consumption of the pre-silicon test scenario.

[0086] Step S22: For any pre-silicon test scenario, based on the flip rate of each flip signal of the pre-silicon test scenario and the predetermined flip weight of each flip signal, determine the theoretical dynamic power consumption of the pre-silicon test scenario. The linear weighted result of the flip rate and flip weight of each flip signal is expressed as the theoretical dynamic power consumption.

[0087] It should be noted that the simulated dynamic power consumption is the dynamic power consumption value directly obtained by the electronic design automation tool during the simulation process of the design to be tested; the theoretical dynamic power consumption is the dynamic power consumption value obtained by obtaining the preset information value in the design to be tested and calculating according to the formula during the simulation process. In an optional implementation, the theoretical dynamic power consumption is the dynamic power consumption corresponding to the flip signal of the design to be tested.

[0088] Furthermore, in the method of using a flip signal to determine the dynamic power consumption of the design to be tested as described above, there is a signal that cannot be calculated that affects the power consumption of the entire chip, such as a clock signal, and its impact on the dynamic power consumption of the design to be tested. Therefore, in the pre-silicon test scenario for calculating the flip weight of the flip signal, it is necessary to turn off all the clock signals and then obtain the flip rate of the flip signal. In this way, the theoretical dynamic power consumption calculated by the flip weight is the dynamic power consumption that does not include the influence of the clock signal. The simulated dynamic power consumption is the dynamic power consumption affected by the clock signal obtained based on the power consumption simulation data.

[0089] The signal simulation data includes multiple state data of the design under test during the test, and these data are used to calculate the theoretical dynamic power consumption of the design under test in subsequent steps. Specifically, in an optional implementation, the signal simulation data includes: the number of flips of multiple flip signals of the design under test in each pre-silicon test scenario. The flip number is used to subsequently calculate the flip rate of the flip signal in each pre-silicon test scenario.

[0090] Furthermore, in an optional implementation, the power consumption simulation data includes: a waveform fsdb file of the design to be tested in a pre-silicon test scenario. The waveform fsdb file is a file representing the complete spectrum width of a waveform in digital signal processing, and is used in electronic design automation tools to store and analyze simulation results of digital circuits. The waveform fsdb file can effectively process a large amount of waveform data, which is convenient for designing and verifying complex digital systems. The simulated dynamic power consumption of the design to be tested during the simulation process can be accurately obtained through the waveform fsdb file.

[0091] Please continue to refer to Figure 1 The parameter measurement method of the clock signal also includes step S30: based on the nonlinear relationship among the simulated dynamic power consumption, the theoretical dynamic power consumption, and the normalized dynamic power consumption of the clock signal, respectively determine the simulated dynamic power consumption of each pre-silicon test scenario and the normalized dynamic power consumption of the clock signal corresponding to the theoretical dynamic power consumption, and obtain the normalized dynamic power consumption of the clock signal of each pre-silicon test scenario.

[0092] It should be noted that in the design to be tested, the signal that affects the overall power consumption of the design to be tested is related to the clock signal, such as a clock gating signal. The clock gating signal is a signal used to reduce the power consumption of a digital circuit. Different states of clock gating can control the transmission of clock signals, such as preventing the transmission of all clock signals or preventing the transmission of part of the clock signals, thereby temporarily turning off the clock signal when the circuit does not need to work, thereby reducing dynamic power consumption.

[0093] Based on the number of flips included in the above signal simulation data, in an optional implementation, the nonlinear relationship is a nonlinear dynamic power consumption model modeled using the flip signal and clock signal of the design under test. The clock signal has a global impact on the design under test, and the global impact is represented by the normalized dynamic power consumption of the clock signal and expressed as a multiplication factor in the nonlinear dynamic power consumption model.

[0094] Based on the nonlinear relationship between the simulated dynamic power consumption, the theoretical dynamic power consumption, and the normalized dynamic power consumption of the clock signal, and the idea of ​​expressing the multiplication factor in the nonlinear dynamic power consumption model, a formula representing the simulated dynamic power consumption can be obtained, as shown below:

[0095] Pdyn (j) = P norm_dyn (j)*P L (j)

[0096] Among them, P dyn (j) is the simulated dynamic power consumption, P L (j) is the theoretical dynamic power consumption, P norm_dyn (j) is the normalized dynamic power consumption of the clock signal. The normalized dynamic power consumption of the clock signal is a degree value rather than a specific power consumption value, so the above formula can be normalized to improve the accuracy of subsequent acquisition of the normalized dynamic power consumption of the clock signal.

[0097] Specifically, the method for normalizing the normalized dynamic power consumption of the clock signal, in an optional implementation, is as follows: Figure 2 As shown, the step S30 includes step S31: for any pre-silicon test scenario, the simulated dynamic power consumption of the pre-silicon test scenario is divided by the theoretical dynamic power consumption of the pre-silicon test scenario to obtain the normalized dynamic power consumption of the clock signal of the pre-silicon test scenario. At this time, the above formula changes to:

[0098]

[0099] Please continue to refer to Figure 1 The method for measuring the parameters of the clock signal further includes step S40: determining the enable state of the clock signal of each pre-silicon test scenario according to the signal simulation data of each pre-silicon test scenario, and the clock signal has multiple enable states.

[0100] It should be noted that, as can be seen from the above formula, the normalized dynamic power consumption of the above clock signal is the comprehensive consideration of the impact of the clock signal on the power consumption of the design under test. Clock signals, such as clock gating signals, have multiple states, and each different state has a different impact on the power consumption of the design under test. Therefore, it is also necessary to consider separating the impact of different clock signal states on the power consumption of the design under test.

[0101] Specifically, in an optional implementation, the multiple enabled states of the clock signal include: an on state and an off state of the clock signal. The weights of the various enabled states of the clock signal include: a weight of the on state of the clock signal and a weight of the off state of the clock signal.

[0102] Step S50: determining the weights of various enable states of the clock signal based on the normalized dynamic power consumption of the clock signal, various enable states of the clock signal and the linear relationship between the weights of the enable states.

[0103] As can be seen from the foregoing, the clock signal has multiple enabled states, and the enabled states of the clock signals have different influences on the dynamic power consumption of the design under test, and the influences are linearly proportional. Therefore, in an optional implementation, Figure 2 As shown, step S50 includes step S22.

[0104] Thus, the formula based on step S51 and the enabled state and the weight of the enabled state is: And P dyn (j)=(CE×CE_weight0+CE_weight1)P L (j), so based on the above formula, the following transformation can be performed:

[0105]

[0106]

[0107] P norm _ dyn (j)=CE×CE_weight0+CE_weight1

[0108] Wherein, CE is the enable state of the clock signal. In an optional implementation, when the clock signal is in the on state, the value of CE is the zeroth value (such as 0), and when the clock signal is in the off state, the value of CE is the first value (such as 1). CE_weight0 is the weight of the on state of the clock signal, and CE_weight1 is the weight of the off state of the clock signal.

[0109] It should be noted that, in order to calculate the weight of the enable state, it is necessary to obtain the normalized dynamic power consumption of the clock signal and various enable states of the clock signal in multiple pre-silicon test scenarios. Assume that the number of the multiple pre-silicon test scenarios is M. At this time, corresponding to each pre-silicon test scenario, a total of M above formulas can be obtained, that is, M P norm_dyn (j)=CE×CE_weight0+CE_weight1, which is used to calculate the weights of various enabling states, wherein j in the formula=0, 1, 2, ...M-1, representing M pre-silicon test scenarios.

[0110] By substituting the normalized dynamic power consumption of the clock signal in each pre-silicon test scenario and the various enable states of the clock signal into the above M formulas, the weights of the various enable states of the clock signal can be solved. The weights of the various enable states can be used to calculate the post-silicon dynamic power consumption based on the above formula according to the various enable states of the clock signal when the design to be tested is used post-silicon.

[0111] Furthermore, in an optional implementation, if Figure 2As shown, the step S51 includes: based on the linear weighted result between various enabled states of the clock signal and the weights of the enabled states, representing the normalized dynamic power consumption of the clock signal, determining the weights of various enabled states of the clock signal through matrix operations. Wherein, in the matrix operations, the value of the weight of the on state represents the proportion of the total power consumption of the design to be tested that can be masked, and the value of the weight of the off state represents the proportion of the total power consumption of the design to be tested that cannot be masked.

[0112] It should be noted that, in an optional implementation, the clock signal is a clock gating signal, and the function of the clock gating signal is to shield the clock signal of the functional module of the circuit to be tested, so as to shield the power consumption of the functional module. However, at the same time, the clock signals of some functional modules in the design to be tested cannot be shielded by the clock gating signal, so the dynamic power consumption of the design to be tested can be divided into a part that can be shielded by the clock gating signal and a part that cannot be shielded by the clock gating signal. Therefore, the weight CE_weight0 of the on state of the clock signal represents: the proportion of the power consumption that can be shielded when the clock signal is in the on state to the total power consumption of the design to be tested; the weight CE_weight1 of the off state of the clock signal represents: the proportion of the power consumption that cannot be shielded when the clock signal is in the off state to the total power consumption weight of the design to be tested.

[0113] Furthermore, based on the above formula P norm_dyn (j) = CE × CE_weight0 + CE_weight1, in an optional implementation, such as Figure 3 As shown, the specific calculation method of step S51 includes the following steps.

[0114] Step S511: construct an enable state matrix, wherein the enable state matrix represents the on state and off state of the clock signal in each pre-silicon test scenario, wherein the state value of the clock signal in the on state is configured as the zeroth value to shield the shieldable power consumption, and the state value of the clock signal in the off state is configured as the first value to not shield the shieldable power consumption.

[0115] The method for constructing the enable state matrix is ​​to summarize the enable states of all clock signals into an enable state matrix C. The data of each row of the enable state matrix C is the enable state of all the clock signals in a pre-silicon test scenario; each column of the enable state matrix C is the enable state of the clock signal in different pre-silicon test scenarios. Specifically, the enable state matrix C is: where c j is the enable state of the clock signal in the jth pre-silicon test scenario, c j A value of 0 indicates on, and 1 indicates off.

[0116] Since the weight CE_weight1 of the off state of the clock signal is not multiplied by the on state of the clock signal, for the convenience of fitting, the CE_weight1 in the formula can be regarded as 1*CE_weight1, so as to facilitate subsequent fitting. At this time, the values ​​of the second column in the enable state matrix C are all 1. Furthermore, the value of the on state of the clock signal can be 0, so that the values ​​of the first column in the enable state matrix C are all 0. In this way, when the enable state of the clock signal is the enabled state, its corresponding value is 0, which means that CE_weigh0 does not participate in the calculation of power consumption, and when the enable state of the clock signal is the off state, its corresponding value is 1, which means that CE_weigh0 participates in the calculation of power consumption. Since CE_weight1 represents the proportion of non-shieldable power consumption to the total power consumption weight of the design to be tested, it cannot be multiplied by 0 and must participate in the calculation of power consumption.

[0117] Step S512: construct a power consumption vector according to the normalized dynamic power consumption of the clock signal of each pre-silicon test scenario.

[0118] Construct power consumption vector P n The method is to summarize the normalized dynamic power consumption of the clock signal of each pre-silicon test scenario into a column vector with M rows and 1 column. Specifically, the power consumption vector P n for: Among them, P j is the simulated dynamic power consumption in the jth pre-silicon test scenario, j=0, 1, 2, …, M-1.

[0119] Step S513: with the goal of minimizing the difference between the power consumption prediction vector and the power consumption vector, predict the weight of the on state and the weight of the off state of the clock signal according to the enable state matrix and the power consumption vector.

[0120] Among them, the power consumption prediction vector is the product of the enable state matrix and the weight vector, and the weight vector is composed of the weight of the on state and the weight of the off state of the predicted clock signal, and the weight of the on state and the weight of the off state of the clock signal are non-negative numbers.

[0121] Specifically, the weight vector CW is to summarize the weights of the on state and the off state of each clock signal into a column vector. The weight vector CW is specifically: Among them, cw i CE_weight is the weight of the flip rate of the i-th flip signal i , i=0,1.

[0122] It should be noted that, in the design to be tested, the enable state of the clock signal only masks the power consumption but cannot increase the power consumption. Therefore, the linear fitting method for the above-mentioned enable state matrix operation needs to use a linear fitting method with a non-negative result, such as non-negative least squares (NNLS), non-negative matrix factorization (NMF), regularized least squares (Regularized Least Squares) and other linear fitting methods.

[0123] In an optional implementation, the step S513 includes: using a non-negative least squares algorithm, with the goal of minimizing the difference between the predicted power consumption vector and the power consumption vector, predicting the weight state of the on state and the weight of the off state of the clock signal according to the enable state matrix and the power consumption vector. The formula of the non-negative least squares algorithm is:

[0124] where C∈R M×2 ,CW∈R 2 ,P∈R M

[0125] Using the non-negative least squares algorithm, on the basis of achieving a non-negative result, the difference between the predicted power consumption vector and the power consumption vector can also be minimized, that is, the residual sum of squares of the weights of different enable states of the calculated clock signal is reduced. The residual sum of squares is a commonly used indicator to measure the goodness of model fit in statistics and regression analysis. It represents the sum of squares of the difference between the model prediction value and the post-silicon observation value, and is used to evaluate the prediction accuracy of the model. The smaller the residual sum of squares, the better the model fitting effect. Therefore, using the non-negative least squares algorithm, an accurate fitting result can be obtained.

[0126] In this way, by accurately obtaining the state of the clock signal that affects the overall power consumption of the design to be tested, and the weights of the multiple states of the clock signal during the simulation process, the influence of the multiple states of the clock signal can be introduced into the calculation formula when calculating the post-silicon dynamic power consumption. At the same time, the clock signal can shield part of the power consumption of the design to be tested. Then, when calculating the overall power consumption of the design to be tested, according to the enable state of the clock signal, the power consumption of the shielded part of the design to be tested is excluded from the calculation formula. Thereby avoiding the erroneous calculation of the power consumption value of the clock signal into the calculation result of the overall power consumption of the design to be tested when calculating the post-silicon dynamic power consumption, so as to improve the calculation accuracy of the post-silicon dynamic power consumption. And the weights of the multiple states of the clock signal obtained by fitting and calculating multiple sets of data have higher accuracy, which further ensures the calculation accuracy of the post-silicon dynamic power consumption.

[0127] Further, in an optional implementation, in step S22, the flip rate of the flip signal of the design to be tested can be obtained through the waveform fsdb file in the simulation process. However, for the circuit to be tested when it is used after silicon, there is no waveform fsdb file or other data file. Therefore, Figure 4 As shown, the design to be tested 10 includes multiple counters, namely counters 11 to counter 17. Each counter corresponds to a flip signal of a functional module in the design to be tested, namely flip signal 0 to flip signal 6. Each time a flip signal flips, the counter corresponding to the flip signal is accumulated by 1, and the counting result of the counter is stored in the register as the flip number of the flip signal for software to read. In the simulation process, the flip number of the flip signal can be read as signal simulation data.

[0128] It should be noted that, in an optional implementation, the design to be tested also includes the counter as described above, and the toggle rates of the multiple toggle signals in each pre-silicon test scenario are also obtained through the simulated counter.

[0129] Further, based on the obtained flipping number, in an optional implementation, such as Figure 2 As shown, before executing the step S22, step S221 is also included: for any pre-silicon test scenario, according to the signal simulation data of the pre-silicon test scenario, the number of flips per unit time of each flip signal in the pre-silicon test scenario is obtained as the flip rate of each flip signal in the pre-silicon test scenario. After obtaining the flip rates of multiple flip signals of the design to be tested, these flip signals are recorded as ACT_rate0, ACT_rate1, ACT_rate2, etc., and so on.

[0130] In an optional implementation, for any pre-silicon test scenario, the number of flips per unit time of each flip signal in the pre-silicon test scenario can be obtained according to the signal simulation data of the pre-silicon test scenario, as the flip rate of each flip signal in the pre-silicon test scenario. For example, when calculating the flip rate, a preset time window can be set, and the number of flips of the flip signal in the time window can be counted, and then the number of signal flips of the flip signal in a time period can be calculated, which is converted into a flip rate. Further, the time of the time window for counting the number of flips of the flip signal can be set as a unit time. For example, the time of the time window is uniformly set to 1us, so as to detect the number of flips of each flip signal within 1us to calculate the flip rate. For example, a flip signal flips once within 1us, and the flip rate of the flip signal is 1 time / 1us=1MHz, and the unit of the count value of the number of flips is MHz. For example, if a signal flips 200 times within 1us, the flip rate of the signal is 200MHz.

[0131] It should be noted that, in an optional implementation, the flip signal includes a bus control signal and / or a read-write enable signal of the design to be tested. When selecting multiple flip signals of the design to be tested, it is necessary to select a flip signal that can fully reflect the flip activity of the design to be tested. Such flip signals are usually some signals related to data transmission, and can continuously jump and flip with the transmission of the flip signal, such as the control signal used to manage and coordinate the data transmission between the master device and the slave device in the AXI (Advanced eXtensible Interface, an on-chip bus) protocol, such as AWVALID (Address Write VALID) signal, ARVALID (Address Read VALID) signal, RVALID (Read Data VALID) signal, and WVALID (Write Data VALID) signal, or some read enable signals and write enable signals, such as WEN (Write Enable), REN (Read Enable), etc.

[0132] Furthermore, in order to predetermine the flip weights of each flip signal, in an optional implementation, as Figure 2 As shown, before executing the step S22, step S222 is also included: based on the linear relationship between the dynamic power consumption and signal flipping of the design to be tested, the simulated dynamic power consumption of each pre-silicon test scenario and the flipping rate of the multiple flipping signals in each pre-silicon test scenario are fitted to obtain the flipping weights of the multiple flipping signals of the design to be tested. The flipping weights are used to determine the theoretical dynamic power consumption of the design to be tested.

[0133] Since there are multiple flip signals in a design under test, the impact of each flip signal on the dynamic power consumption of the entire design under test is different, and the impact of the flip signal is linearly proportional to the size of the circuit associated with the flip signal. Therefore, in an optional implementation, Figure 3 As shown, the step S222 may include: based on the weighted sum relationship between the dynamic power consumption of the design to be tested and the flip rate and flip weight of the flip signal, fitting the simulated dynamic power consumption of each pre-silicon test scenario and the flip rate of the multiple flip signals in each pre-silicon test scenario to obtain the flip weights of the multiple flip signals of the design to be tested.

[0134] At this time, the formula for the dynamic power consumption of the design under test is Where ACT_rate i That is, the flip rate of the i-th flip signal; ACT_weight i That is, the weight value corresponding to the i-th flip signal, that is, the flip weight; N is the number of flip signals of the design to be tested.

[0135] Further, the number N of all flip signals in the design to be tested is a number value obtained based on experience, and in an optional implementation, the value of N needs to be greater than 16. Optionally, the value of N is 32. In an optional implementation, the number M of the pre-silicon test scenarios is greater than the number N of all flip signals in the design to be tested. Optionally, the number M of the pre-silicon test scenarios is more than twice the number N of all flip signals in the design to be tested.

[0136] After the obtained simulated dynamic power consumption in each pre-silicon test scenario and the flip rate of multiple flip signals in each pre-silicon test scenario are substituted into the above formula, the flip weights of the multiple flip signals can be solved. The flip weights of the multiple flip signals can be used to calculate the post-silicon dynamic power consumption of the design to be tested based on the above formula according to the flip rate of the multiple flip signals of the design to be tested when the design to be tested is used, and then the post-silicon dynamic power consumption of the design to be tested is obtained.

[0137] Furthermore, based on the above formula In an alternative implementation, Figure 3 As shown, the specific calculation method of step S222 includes the following steps.

[0138] Step S223: constructing a toggle rate matrix according to the number M of the plurality of pre-silicon test scenarios and the number N of the plurality of toggle signals to represent the toggle rates of the plurality of toggle signals of the design to be tested in each pre-silicon test scenario.

[0139] The method for constructing the flip rate matrix is ​​to aggregate all flip signals into a flip rate matrix A. The data of each row of the flip rate matrix A is the flip rate of all flip signals in a pre-silicon test scenario; each column of the flip rate matrix A is the flip rate of the same flip signal in different pre-silicon test scenarios. Specifically, the flip rate matrix A is: where a j,i is the toggle rate of the i-th toggle signal in the j-th pre-silicon test scenario.

[0140] Step S224: constructing a dynamic power consumption vector according to the number of the plurality of pre-silicon test scenarios to represent the simulated dynamic power consumption of each of the pre-silicon test scenarios.

[0141] The method for constructing the dynamic power consumption vector P is to aggregate the simulated dynamic power consumption of each pre-silicon test scenario into a column vector with M rows and 1 column. Specifically, the dynamic power consumption vector P is: Among them, P j is the simulated dynamic power consumption in the jth pre-silicon test scenario, j=0, 1, 2, …, M-1.

[0142] Step S225: With the goal of minimizing the difference between the dynamic power consumption prediction vector and the dynamic power consumption vector, predict the flip weights of the multiple flip signals according to the flip rate matrix and the dynamic power consumption vector. The dynamic power consumption prediction vector is the product of the flip rate matrix and the flip weight vector, the flip weight vector is composed of the predicted flip weights of each flip signal, and the flip weights of the multiple flip signals are non-negative numbers.

[0143] Specifically, the flip weight vector W is to aggregate the flip weights of each flip signal into a column vector with N rows and 1 column. The flip weight vector W is specifically: Among them, w i ACT_weight is the weight of the flip rate of the i-th flip signal i , i=0,1,2,…N-1.

[0144] Furthermore, the above M formulas After expansion, a flip rate matrix operation P=A*W calculated by the flip rate matrix A, the dynamic power consumption vector P and the flip weight vector W can be obtained. Specifically, the flip rate matrix operation is: By performing a linear fit on the flip rate matrix operation, the flip weight ACT_weight of each flip signal can be obtained. i .

[0145] It should be noted that, in the design to be tested, the flipping of the flipping signal only consumes energy and generates power consumption, but cannot generate energy. Therefore, the linear fitting method for the above flipping rate matrix operation needs to use a linear fitting method with a non-negative result, such as non-negative least squares (NNLS), non-negative matrix factorization (NMF), regularized least squares (Regularized Least Squares) and other linear fitting methods.

[0146] Further, in an optional implementation, the step S225 includes: using a non-negative least squares algorithm to minimize the difference between the dynamic power consumption prediction vector and the dynamic power consumption vector, and predicting the flip weights of the multiple flip signals according to the flip rate matrix and the dynamic power consumption vector.

[0147] Using the non-negative least squares algorithm, on the basis of achieving a non-negative result, the difference between the dynamic power consumption prediction vector and the dynamic power consumption vector can also be minimized, that is, the residual sum of squares of the calculated flip weights is reduced. The residual sum of squares is a commonly used indicator for measuring the goodness of model fit in statistics and regression analysis. It represents the sum of squares of the difference between the model prediction value and the post-silicon observation value, and is used to evaluate the prediction accuracy of the model. The smaller the residual sum of squares, the better the model fit effect. Therefore, using the non-negative least squares algorithm, an accurate fitting result can be obtained.

[0148] The embodiment of the present application also provides a method for obtaining dynamic power consumption, which accurately calculates the dynamic power consumption of the design to be tested based on the weights of various enable states of the clock signal obtained by the clock signal parameter measurement method as described above. As an optional implementation, Figure 5 FIG. 1 is a flow chart showing a method for obtaining dynamic power consumption according to an embodiment of the present application. Figure 5 As shown, the dynamic power consumption acquisition method provided in the embodiment of the present application includes the following steps.

[0149] Step S61: obtaining operation data of the design to be tested when it is running post-silicon, wherein the operation data at least includes an enable state of a clock signal.

[0150] Step S621: Determine the normalized dynamic power consumption of the clock signal according to the enable state of the clock signal and the predetermined weight of the enable state of the clock signal, wherein the weight of the enable state of the clock signal is determined based on the parameter measurement method of the clock signal as described above.

[0151] Step S63: determining the post-silicon dynamic power consumption of the design under test at least according to the normalized dynamic power consumption of the clock signal.

[0152] Furthermore, in an optional implementation, the operation data also includes: the flip rate of each flip signal of the design to be tested. The dynamic power consumption acquisition method also includes step S622: determining the theoretical dynamic power consumption of the design to be tested according to the flip rate of each flip signal and the predetermined flip weight of each flip signal.

[0153] At this time, the step S63 includes: determining the post-silicon dynamic power consumption of the design to be tested according to the normalized dynamic power consumption of the clock signal and the theoretical dynamic power consumption of the design to be tested.

[0154] It should be noted that, based on the parameters obtained above, the formula for determining the post-silicon dynamic power consumption of the design to be tested is:

[0155]

[0156] The embodiment of the present application also provides a clock signal parameter acquisition device to accurately calculate dynamic power consumption. As an optional implementation, Figure 6 The structure of the clock signal parameter acquisition device provided in the embodiment of the present application is shown. Figure 6 As shown, the clock signal parameter acquisition device provided in the embodiment of the present application includes the following modules.

[0157] A simulation data acquisition module 100 is used to acquire power consumption simulation data and signal simulation data of the design under test in multiple pre-silicon test scenarios;

[0158] The power consumption calculation module 200 is used to determine the simulated dynamic power consumption of each pre-silicon test scenario according to the power consumption simulation data of each pre-silicon test scenario, and to determine the theoretical dynamic power consumption according to the signal simulation data of each pre-silicon test scenario;

[0159] The impact degree calculation module 300 is used to determine the simulated dynamic power consumption of each pre-silicon test scenario and the normalized dynamic power consumption of the clock signal corresponding to the theoretical dynamic power consumption based on the nonlinear relationship between the simulated dynamic power consumption, the theoretical dynamic power consumption, and the normalized dynamic power consumption of the clock signal, and obtain the normalized dynamic power consumption of the clock signal of each pre-silicon test scenario;

[0160] A state determination module 400, for determining an enable state of a clock signal of each pre-silicon test scenario according to signal simulation data of each pre-silicon test scenario, wherein the clock signal has multiple enable states;

[0161] The weight calculation module 500 is used to determine the weights of various enable states of the clock signal based on the normalized dynamic power consumption of the clock signal, various enable states of the clock signal and the linear relationship between the weights of the enable states.

[0162] Further, in an optional implementation, the power consumption calculation module 200 includes:

[0163] For any pre-silicon test scenario, a waveform file of the pre-silicon test scenario is obtained from the power consumption simulation data of the pre-silicon test scenario; power consumption analysis is performed on the waveform file through an electronic design automation tool for power consumption analysis to obtain the simulated dynamic power consumption of the pre-silicon test scenario.

[0164] For any pre-silicon test scenario, the theoretical dynamic power consumption of the pre-silicon test scenario is determined based on the toggle rates of each toggle signal of the pre-silicon test scenario and the predetermined toggle weights of each toggle signal; wherein the linear weighted result of the toggle rates and toggle weights of each toggle signal is expressed as the theoretical dynamic power consumption.

[0165] Furthermore, in an optional implementation, the impact degree calculation module 300 includes:

[0166] For any pre-silicon test scenario, the simulated dynamic power consumption of the pre-silicon test scenario is divided by the theoretical dynamic power consumption of the pre-silicon test scenario to obtain the normalized dynamic power consumption of the clock signal of the pre-silicon test scenario.

[0167] Further, in an optional implementation, the multiple enable states of the clock signal include an on state and an off state of the clock signal; the weights of the various enable states of the clock signal include: the weight of the on state of the clock signal, and the weight of the off state of the clock signal. The weight calculation module 500 includes: representing the normalized dynamic power consumption of the clock signal based on the linear weighted result between the various enable states of the clock signal and the weights of the enable states, and determining the weights of the various enable states of the clock signal through matrix operations; wherein, in the matrix operations, the value of the weight of the on state represents the proportion of the total power consumption of the design to be tested that can be masked, and the value of the weight of the off state represents the proportion of the total power consumption of the design to be tested that cannot be masked.

[0168] Further, in an optional implementation, the weight calculation module 500 includes: constructing an enable state matrix, the enable state matrix representing the on state and off state of the clock signal in each pre-silicon test scenario; wherein the state value of the clock signal in the on state is configured as the zeroth value to shield the maskable power consumption, and the state value of the clock signal in the off state is configured as the first value to not shield the maskable power consumption.

[0169] And, constructing a power consumption vector according to the normalized dynamic power consumption of the clock signal of each pre-silicon test scenario.

[0170] With the goal of minimizing the difference between the power consumption prediction vector and the power consumption vector, the weight of the on state and the weight of the off state of the clock signal are predicted according to the enable state matrix and the power consumption vector; wherein the power consumption prediction vector is the product of the enable state matrix and the weight vector, and the weight vector is composed of the predicted weight of the on state and the weight of the off state of the clock signal, and the weight of the on state and the weight of the off state of the clock signal are non-negative numbers.

[0171] Furthermore, in an optional implementation, the parameter measurement device of the clock signal also includes a flip weight determination module, which is used to fit the simulated dynamic power consumption of the various pre-silicon test scenarios and the flip rate of the multiple flip signals in each pre-silicon test scenario based on the weighted sum relationship between the simulated dynamic power consumption and the flip rate and flip weight of the flip signal, so as to obtain the flip weights of the multiple flip signals of the design to be tested.

[0172] Furthermore, in an optional implementation, the parameter measurement device of the clock signal also includes a flip weight acquisition module, which is used to construct a flip rate matrix according to the number of the multiple pre-silicon test scenarios and the number of the multiple flip signals to represent the flip rates of the multiple flip signals in each pre-silicon test scenario; and, according to the number of the multiple pre-silicon test scenarios, construct a dynamic power consumption vector to represent the simulated dynamic power consumption of each pre-silicon test scenario; with the goal of minimizing the difference between the dynamic power consumption prediction vector and the dynamic power consumption vector, predict the flip weights of the multiple flip signals according to the flip rate matrix and the dynamic power consumption vector; wherein the dynamic power consumption prediction vector is the product of the flip rate matrix and the flip weight vector, the flip weight vector is composed of the predicted flip weights of each flip signal, and the flip weights of the multiple flip signals are non-negative numbers.

[0173] The embodiment of the present application also provides a dynamic power consumption measurement device to calculate the dynamic power consumption of the design to be tested. As an optional implementation, Figure 7 The structure of the dynamic power consumption measurement device provided by the embodiment of the present application is shown. Figure 7 As shown, the dynamic power consumption measurement device provided in the embodiment of the present application includes the following modules.

[0174] An operation data acquisition module 600 is used to acquire operation data of the design to be tested when it is running after silicon operation, wherein the operation data at least includes an enable state of a clock signal;

[0175] The power consumption impact acquisition module 700 is used to determine the normalized dynamic power consumption of the clock signal according to the enable state of the clock signal and the predetermined weight of the enable state of the clock signal; wherein the weight of the enable state of the clock signal is determined based on the parameter measurement method of the clock signal as described above;

[0176] The dynamic power consumption calculation module 800 is used to determine the post-silicon dynamic power consumption of the design under test based on at least the normalized dynamic power consumption of the clock signal.

[0177] Furthermore, in an optional implementation, the dynamic power consumption measurement device further includes: a theoretical dynamic power consumption acquisition module, which is used to determine the theoretical dynamic power consumption of the design to be tested according to the flip rate of each flip signal and the predetermined flip weight of each flip signal.

[0178] The post-silicon dynamic power consumption acquisition module is used to determine the post-silicon dynamic power consumption of the design to be tested according to the normalized dynamic power consumption of the clock signal and the theoretical dynamic power consumption of the design to be tested.

[0179] An embodiment of the present application also provides a computing device, including a memory and a processor, wherein the memory stores computer instructions, and the processor calls the computer instructions stored in the memory to execute the clock signal parameter measurement method as described above, or the dynamic power consumption acquisition method as described above.

[0180] An embodiment of the present application also provides a storage medium, which stores computer instructions. When the computer instructions are executed, the parameter measurement method of the clock signal as described above, or the dynamic power consumption acquisition method as described above is implemented.

[0181] An embodiment of the present application also provides a computer program product, including computer instructions, which, when executed, implement the clock signal parameter measurement method as described above, or the dynamic power consumption acquisition method as described above.

[0182] Although the embodiments of the present application are disclosed above, the present application is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be subject to the scope defined by the claims.

Claims

1. A method for measuring parameters of a clock signal, characterized in that: include: Obtain power consumption simulation data and signal simulation data of the design under test in multiple pre-silicon test scenarios; Determining normalized dynamic power consumption of each pre-silicon test scenario based at least on power consumption simulation data of each pre-silicon test scenario; Determining, according to signal simulation data of each pre-silicon test scenario, an enable state of a clock signal of each pre-silicon test scenario, wherein the clock signal has multiple enable states; Based on the normalized dynamic power consumption, the various enable states of the clock signal and the linear relationship between the weights of the enable states, the weights of the various enable states of the clock signal are determined.

2. The method for measuring parameters of a clock signal according to claim 1, wherein: The step of determining the normalized dynamic power consumption of each pre-silicon test scenario at least according to the power consumption simulation data of each pre-silicon test scenario comprises: Determine the simulated dynamic power consumption of each pre-silicon test scenario based on the power consumption simulation data of each pre-silicon test scenario, and determine the theoretical dynamic power consumption based on the signal simulation data of each pre-silicon test scenario; Based on the nonlinear relationship among the simulated dynamic power consumption, the theoretical dynamic power consumption, and the normalized dynamic power consumption of the clock signal, the simulated dynamic power consumption of each pre-silicon test scenario and the normalized dynamic power consumption of the clock signal corresponding to the theoretical dynamic power consumption are determined respectively, and the normalized dynamic power consumption of the clock signal of each pre-silicon test scenario is obtained; The theoretical dynamic power consumption is the dynamic power consumption corresponding to the flip signal of the design under test; the nonlinear relationship is a nonlinear dynamic power consumption model modeled using the flip signal and clock signal of the design under test; wherein the clock signal has a global impact on the design under test, and the global impact is represented by the degree of power consumption impact of the clock signal and is expressed as a multiplication factor in the nonlinear dynamic power consumption model.

3. The method for measuring parameters of a clock signal according to claim 2, characterized in that: Determining the simulated dynamic power consumption of each pre-silicon test scenario according to the power consumption simulation data of each pre-silicon test scenario includes: For any pre-silicon test scenario, a waveform file of the pre-silicon test scenario is obtained from power consumption simulation data of the pre-silicon test scenario; power consumption analysis is performed on the waveform file by an electronic design automation tool for power consumption analysis to obtain simulated dynamic power consumption of the pre-silicon test scenario; Determining the theoretical dynamic power consumption of each pre-silicon test scenario according to the signal simulation data of each pre-silicon test scenario includes: For any pre-silicon test scenario, the theoretical dynamic power consumption of the pre-silicon test scenario is determined based on the toggle rates of each toggle signal of the pre-silicon test scenario and the predetermined toggle weights of each toggle signal; wherein the linear weighted result of the toggle rates and toggle weights of each toggle signal is expressed as the theoretical dynamic power consumption.

4. The method for measuring parameters of a clock signal according to claim 3, characterized in that: The method of determining the normalized dynamic power consumption of the clock signal corresponding to the simulated dynamic power consumption and the theoretical dynamic power consumption of each pre-silicon test scenario based on the nonlinear relationship among the simulated dynamic power consumption, the theoretical dynamic power consumption, and the normalized dynamic power consumption of the clock signal, respectively, and obtaining the normalized dynamic power consumption of the clock signal of each pre-silicon test scenario includes: For any pre-silicon test scenario, the simulated dynamic power consumption of the pre-silicon test scenario is divided by the theoretical dynamic power consumption of the pre-silicon test scenario to obtain the normalized dynamic power consumption of the clock signal of the pre-silicon test scenario.

5. The method for measuring parameters of a clock signal according to any one of claims 2 to 4, characterized in that: The determining the weights of various enable states of the clock signal based on the normalized dynamic power consumption of the clock signal, various enable states of the clock signal and the linear relationship between the weights of the enable states includes: The weights of the various enable states of the clock signal are determined based on that a linear weighted result between the various enable states of the clock signal and the weights of the enable states represents the normalized dynamic power consumption of the clock signal.

6. The method for measuring parameters of a clock signal according to claim 5, characterized in that: The multiple enabled states of the clock signal include an on state and an off state of the clock signal; the weights of the various enabled states of the clock signal include: a weight of the on state of the clock signal, and a weight of the off state of the clock signal; The linear weighted result between the various enabled states of the clock signal and the weights of the enabled states represents the normalized dynamic power consumption of the clock signal. Determining the weights of the various enabled states of the clock signal includes: The linear weighted result between various enabled states of the clock signal and the weights of the enabled states represents the normalized dynamic power consumption of the clock signal, and the weights of various enabled states of the clock signal are determined through matrix operations; wherein, in the matrix operations, the value of the weight of the on state represents the proportion of maskable power consumption to the total power consumption of the design under test, and the value of the weight of the off state represents the proportion of non-maskable power consumption to the total power consumption of the design under test.

7. The method for measuring parameters of a clock signal according to claim 6, characterized in that: The linear weighted result between the various enabled states of the clock signal and the weights of the enabled states represents the normalized dynamic power consumption of the clock signal. The weights of the various enabled states of the clock signal are determined by matrix operation, including: Constructing an enable state matrix, wherein the enable state matrix represents the on state and the off state of the clock signal in each pre-silicon test scenario; wherein the state value of the clock signal in the on state is configured as the zeroth value to shield the shieldable power consumption, and the state value of the clock signal in the off state is configured as the first value to not shield the shieldable power consumption; and, constructing a power consumption vector based on the normalized dynamic power consumption of the clock signal for each pre-silicon test scenario; With the goal of minimizing the difference between the power consumption prediction vector and the power consumption vector, the weight of the on state and the weight of the off state of the clock signal are predicted according to the enable state matrix and the power consumption vector; wherein the power consumption prediction vector is the product of the enable state matrix and the weight vector, and the weight vector is composed of the predicted weight of the on state and the weight of the off state of the clock signal, and the weight of the on state and the weight of the off state of the clock signal are non-negative numbers.

8. The method for measuring parameters of a clock signal according to claim 3, characterized in that: The step of determining the flip weight of each flip signal comprises: Based on the weighted sum relationship between the simulated dynamic power consumption and the flip rate and flip weight of the flip signal, the simulated dynamic power consumption of each pre-silicon test scenario and the flip rate of the multiple flip signals in each pre-silicon test scenario are fitted to obtain the flip weights of the multiple flip signals of the design to be tested.

9. The method for measuring parameters of a clock signal according to claim 8, characterized in that: The weighted summation relationship between the dynamic power consumption and the flip rate and flip weight of the flip signal is based on the dynamic power consumption, and the simulated dynamic power consumption of each pre-silicon test scenario and the flip rate of the multiple flip signals in each pre-silicon test scenario are fitted to obtain the flip weights of the multiple flip signals of the design to be tested, including: According to the number of the plurality of pre-silicon test scenarios and the number of the plurality of flip signals, construct a flip rate matrix to represent the flip rates of the plurality of flip signals in each pre-silicon test scenario; and, constructing a dynamic power consumption vector according to the number of the plurality of pre-silicon test scenarios to represent the simulated dynamic power consumption of each of the pre-silicon test scenarios; With the goal of minimizing the difference between the dynamic power consumption prediction vector and the dynamic power consumption vector, the flip weights of the multiple flip signals are predicted based on the flip rate matrix and the dynamic power consumption vector; wherein the dynamic power consumption prediction vector is the product of the flip rate matrix and the flip weight vector, the flip weight vector is composed of the predicted flip weights of each flip signal, and the flip weights of the multiple flip signals are non-negative numbers.

10. A method for obtaining dynamic power consumption, characterized in that: include: Acquire operation data of the design to be tested when it is running after silicon operation, wherein the operation data at least includes an enable state of a clock signal; Determine the normalized dynamic power consumption of the clock signal according to the enable state of the clock signal and the predetermined weight of the enable state of the clock signal; wherein the weight of the enable state of the clock signal is determined based on the parameter measurement method of the clock signal according to any one of claims 1 to 9; The post-silicon dynamic power consumption of the design under test is determined based at least on the normalized dynamic power consumption of the clock signal.

11. The method for obtaining dynamic power consumption according to claim 10, characterized in that: The operation data also includes: the flip rate of each flip signal of the design to be tested; The dynamic power consumption acquisition method further includes: Determine the theoretical dynamic power consumption of the design to be tested according to the toggle rates of the toggle signals and the predetermined toggle weights of the toggle signals; Determining the post-silicon dynamic power consumption of the design under test at least according to the normalized dynamic power consumption of the clock signal includes: The post-silicon dynamic power consumption of the design to be tested is determined according to the normalized dynamic power consumption of the clock signal and the theoretical dynamic power consumption of the design to be tested.

12. A clock signal parameter acquisition device, characterized in that: include A simulation data acquisition module, used to acquire power consumption simulation data and signal simulation data of the design under test in multiple pre-silicon test scenarios; A power consumption calculation module, used to determine the simulated dynamic power consumption of each pre-silicon test scenario according to the power consumption simulation data of each pre-silicon test scenario, and to determine the theoretical dynamic power consumption according to the signal simulation data of each pre-silicon test scenario; An impact degree calculation module is used to determine the simulated dynamic power consumption of each pre-silicon test scenario and the normalized dynamic power consumption of the clock signal corresponding to the theoretical dynamic power consumption based on the nonlinear relationship between the simulated dynamic power consumption, the theoretical dynamic power consumption, and the normalized dynamic power consumption of the clock signal, and obtain the normalized dynamic power consumption of the clock signal of each pre-silicon test scenario; A state determination module, used to determine the enable state of the clock signal of each pre-silicon test scenario according to the signal simulation data of each pre-silicon test scenario, wherein the clock signal has multiple enable states; The weight calculation module is used to determine the weights of various enable states of the clock signal based on the normalized dynamic power consumption of the clock signal, various enable states of the clock signal and the linear relationship between the weights of the enable states.

13. A dynamic power consumption acquisition device, characterized in that: include An operation data acquisition module, used to acquire operation data of the design to be tested when it is running after silicon operation, wherein the operation data at least includes an enable state of a clock signal; A power consumption impact acquisition module, used to determine the normalized dynamic power consumption of the clock signal according to the enable state of the clock signal and the predetermined weight of the enable state of the clock signal; wherein the weight of the enable state of the clock signal is determined based on the parameter measurement method of the clock signal according to any one of claims 1 to 9; A dynamic power consumption calculation module is used to determine the post-silicon dynamic power consumption of the design to be tested based on at least the normalized dynamic power consumption of the clock signal.

14. A computing device, characterized in that It comprises a memory and a processor, the memory stores computer instructions, and the processor calls the computer instructions stored in the memory to execute the parameter measurement method of the clock signal as described in any one of claims 1 to 9, or the dynamic power consumption acquisition method as described in any one of claims 10 to 11.

15. A storage medium, characterized in that: The storage medium stores computer instructions, and when the computer instructions are executed, the method for measuring parameters of a clock signal according to any one of claims 1 to 9 or the method for obtaining dynamic power consumption according to any one of claims 10 to 11 is implemented.

16. A computer program product, characterized in that The method comprises computer instructions, which, when executed, implement the method for measuring parameters of a clock signal as described in any one of claims 1 to 9, or the method for obtaining dynamic power consumption as described in any one of claims 10 to 11.

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