Circuit design layout and scanning electron microscope image registration method and device

Abstract

The invention provides a circuit design layout and scanning electron microscope image registration method and device, and belongs to the technical field of semiconductors. The registration method for the circuit design layout and the scanning electron microscope image comprises the following steps: acquiring a first circuit design layout and the scanning electron microscope image, wherein the first circuit design layout comprises a plurality of first graphs; performing image processing on each first graph in the first circuit design layout to generate a scanning electron microscope simulation graph corresponding to each first graph so as to obtain a simulation electron microscope image; and registering the simulated electron microscope image and the scanning electron microscope image to obtain a matching result. The scanning electron microscope simulation scanning graph is close to the scanning graph in the scanning electron microscope image in morphology, so that the scanning electron microscope image and the simulation electron microscope image can be matched efficiently, quickly and accurately, and the matching efficiency and accuracy are improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for aligning a circuit design layout with a scanning electron microscope image, a device for aligning a circuit design layout with a scanning electron microscope image, a machine-readable storage medium and an electronic device. Background Art

[0002] In the semiconductor lithography process, in order to monitor the quality of the lithography process, it is usually necessary to measure the critical dimension (CD) of the pattern formed by the photoresist. The measurement personnel use the design layout to establish a measurement menu, and the critical dimension scanning electron microscope (Critical Dimension Scanning Electron Microscope, CD-SEM) that measures the critical dimension performs automatic measurement according to the measurement menu. During the measurement process, the design layout needs to be aligned with the SEM image to locate the pre-set area for measurement.

[0003] The existing registration of design layouts with SEM images is slow and has a high probability of error. Summary of the invention

[0004] The purpose of the embodiments of the present invention is to provide a method for aligning a circuit design layout and a scanning electron microscope image, a device for aligning a circuit design layout and a scanning electron microscope image, a machine-readable storage medium and an electronic device. The method for aligning a circuit design layout and a scanning electron microscope image can efficiently, quickly and accurately match the scanning electron microscope image with the first circuit design layout, thereby improving the matching efficiency and accuracy.

[0005] In order to achieve the above-mentioned object, the first aspect of the present application provides a method for registering a circuit design layout and a scanning electron microscope image, comprising:

[0006] Acquire a first circuit design layout and a scanning electron microscope image, wherein the first circuit design layout includes a plurality of first graphics;

[0007] Performing image processing on each first graphic in the first circuit design layout to generate a scanning electron microscope simulation graphic corresponding to each first graphic to obtain a simulated electron microscope image;

[0008] Based on the distribution of each SEM simulation image in the simulated SEM image, determining an actual matching range in the simulated SEM image;

[0009] Within the actual matching range, the simulated electron microscope image and the scanning electron microscope image are registered to obtain a matching result.

[0010] In an embodiment of the present application, the image processing is performed on each first graphic in the first circuit design layout to generate a scanning electron microscope simulation graphic corresponding to each first graphic to obtain a simulated electron microscope image, including:

[0011] Performing angle cutting processing on the line ends of each first graphic in the first circuit design layout to form a plurality of second graphics to obtain a second circuit design layout;

[0012] Extracting the edges of each second graphic in the second circuit design layout, and performing expansion processing on the edges of each second graphic to form a plurality of contour graphics, so as to obtain a third circuit design layout;

[0013] Merging each second graphic in the second circuit design layout with the corresponding outline graphic in the third circuit design layout to obtain a plurality of initial simulation graphics to obtain a fourth circuit design layout;

[0014] The image blurring and pixel homogenization processing are performed on each initial simulation pattern in the fourth circuit design layout to generate a scanning electron microscope simulation pattern corresponding to each first pattern to obtain a simulated electron microscope image.

[0015] In an embodiment of the present application, the steps of respectively merging each second graphic in the second circuit design layout with the corresponding outline graphic in the third circuit design layout to obtain a plurality of initial simulation graphics to obtain a fourth circuit design layout include:

[0016] Based on the preset first coefficient, adjusting the pixel value of each second graphic in the second circuit design layout to obtain a new second circuit design layout;

[0017] Based on the preset second coefficient, adjusting the pixel values ​​of each contour image in the third circuit design layout to obtain a new third circuit design layout; wherein the sum of the preset first coefficient and the preset second coefficient is 1;

[0018] Each second graphic in the new second circuit design layout is merged with the corresponding outline graphic in the new third circuit design layout to obtain a plurality of initial simulation graphics, so as to obtain a fourth circuit design layout.

[0019] In the embodiment of the present application, the actual matching range is determined in the simulated electron microscope image based on the distribution of each scanning electron microscope simulated image in the simulated electron microscope image, including:

[0020] Determining a first direction and a second direction in the simulated electron microscope image, wherein the first direction is perpendicular to the second direction;

[0021] Based on the distribution of each SEM simulation image in the simulated SEM image, determining whether each SEM simulation image is periodically arranged in the first direction and / or the second direction;

[0022] When it is determined that the scanning electron microscope simulation images are periodically arranged in the first direction and / or the second direction, the actual matching range is determined based on the arrangement period of the scanning electron microscope simulation images.

[0023] In the embodiment of the present application, registering the simulated electron microscope image with the scanning electron microscope image to obtain a matching result includes:

[0024] The simulated electron microscope image is shifted multiple times according to different preset shift amounts to obtain multiple simulated electron microscope shift images;

[0025] respectively calculating the similarity between each simulated electron microscope offset image and the scanning electron microscope image to obtain a plurality of correlation values;

[0026] Based on the multiple correlation values, a matching result is obtained.

[0027] In the embodiment of the present application, the simulated electron microscope image has a plurality of pixel points distributed in an array;

[0028] The registering the simulated electron microscope image with the scanning electron microscope image to obtain a matching result includes:

[0029] Accumulating pixel values ​​of pixel points in each row and pixel points in each column in the simulated electron microscope image to obtain a plurality of pixel accumulation values;

[0030] Determine whether there is one and only one maximum value among the plurality of pixel accumulated values;

[0031] When it is determined that there is only one maximum value in the plurality of pixel accumulated values, one-dimensional matching is performed on the simulated electron microscope image and the scanning electron microscope image in the column direction and the row direction to obtain a matching result;

[0032] When it is determined that there is more than one maximum value in the plurality of pixel accumulated values, two-dimensional matching is performed on the simulated electron microscope image and the scanning electron microscope image in the column direction and the row direction to obtain a matching result.

[0033] In the embodiment of the present application, the one-dimensional matching of the simulated electron microscope image and the scanning electron microscope image in the column direction and the row direction to obtain the matching result includes:

[0034] The simulated electron microscope image is shifted multiple times according to different preset shift amounts to obtain multiple simulated electron microscope shift images;

[0035] The similarity between each simulated electron microscope offset image and the scanning electron microscope image is calculated using a first similarity calculation method to obtain a plurality of one-dimensional matching correlation values;

[0036] A matching result is obtained based on the multiple one-dimensional matching correlation values.

[0037] In the embodiment of the present application, the first similarity calculation method is used to respectively calculate the similarity between each simulated electron microscope offset image and the scanning electron microscope image to obtain multiple one-dimensional matching correlation values, including:

[0038] For each simulated EM migration image, perform the following steps:

[0039] Accumulating pixel values ​​of each row and each column of pixels in the simulated electron microscope offset image respectively to obtain a plurality of first row pixel accumulation values ​​and a plurality of first column pixel accumulation values;

[0040] Accumulating pixel values ​​of each row and each column of the scanning electron microscope image to obtain a plurality of second row pixel accumulation values ​​and a plurality of second column pixel accumulation values;

[0041] Calculate the product of each first row pixel accumulation value and the corresponding second row pixel accumulation value respectively to obtain a plurality of first products;

[0042] Calculate the product of each first column pixel accumulation value and the corresponding second column pixel accumulation value to obtain a plurality of second products;

[0043] The sum of the plurality of first products and the plurality of second products is calculated to obtain correlation values ​​of each simulated electron microscope offset image, so as to obtain a plurality of one-dimensional matching correlation values.

[0044] In the embodiment of the present application, the two-dimensional matching of the simulated electron microscope image and the scanning electron microscope image in the column direction and the row direction to obtain the matching result includes:

[0045] The simulated electron microscope image is shifted multiple times to obtain multiple simulated electron microscope shifted images;

[0046] The similarity between each simulated electron microscope offset image and the scanning electron microscope image is calculated using a second similarity calculation method to obtain a plurality of two-dimensional matching correlation values;

[0047] A matching result is obtained based on the multiple two-dimensional matching correlation values.

[0048] In the embodiment of the present application, the second similarity calculation method is used to respectively calculate the similarity between each simulated electron microscope offset image and the scanning electron microscope image to obtain multiple two-dimensional matching correlation values, including:

[0049] For each simulated EM migration image, perform the following steps:

[0050] respectively calculating the product of the pixel value of each pixel point in the simulated electron microscope offset image and the pixel value of the corresponding pixel point in the scanning electron microscope image to obtain a plurality of third products;

[0051] The sum of the plurality of third products is calculated to obtain correlation values ​​of the respective simulated electron microscope offset images, thereby obtaining a plurality of two-dimensional matching correlation values.

[0052] In the embodiment of the present application, obtaining a matching result based on the multiple correlation values ​​includes:

[0053] Compare each correlation value with a preset threshold value to obtain a comparison result;

[0054] Determine whether the comparison result has a correlation value not less than a preset threshold;

[0055] In the case where it is determined that the comparison result has a correlation value not less than a preset threshold, determining a corresponding offset based on a maximum value among the correlation values ​​not less than the preset threshold to obtain a matching result;

[0056] When it is determined that the comparison result does not have a correlation value that is not less than a preset threshold, the matching result is obtained as a matching failure.

[0057] A second aspect of the present application provides a circuit design layout and a scanning electron microscope image registration device, comprising:

[0058] An acquisition module, used to acquire a first circuit design layout and a scanning electron microscope image, wherein the first circuit design layout includes a plurality of first graphics;

[0059] A generating module, used for performing image processing on each first graphic in the first circuit design layout, generating a scanning electron microscope simulation graphic corresponding to each first graphic, so as to obtain a simulated electron microscope image;

[0060] A determination module, configured to determine an actual matching range in the simulated electron microscope image based on the distribution of each scanning electron microscope simulated image in the simulated electron microscope image;

[0061] The matching module is used to register the simulated electron microscope image with the scanning electron microscope image within the actual matching range to obtain a matching result.

[0062] A third aspect of the present application provides an electronic device, the electronic device comprising:

[0063] at least one processor;

[0064] a memory connected to the at least one processor;

[0065] The memory stores instructions that can be executed by the at least one processor, and the at least one processor implements the above-mentioned circuit design layout and scanning electron microscope image registration method by executing the instructions stored in the memory.

[0066] A fourth aspect of the present application provides a machine-readable storage medium having instructions stored thereon, which, when executed by a processor, configure the processor to execute the above-mentioned circuit design layout and scanning electron microscope image registration method.

[0067] Through the above technical solution, by acquiring a first circuit design layout and a scanning electron microscope image, the first circuit design layout includes a plurality of first graphics; performing image processing on each first graphic in the first circuit design layout, generating a scanning electron microscope simulation graphic corresponding to each first graphic, so as to obtain a simulated electron microscope image; and registering the simulated electron microscope image with the scanning electron microscope image to obtain a matching result. By generating a simulated electron microscope image through image processing of the first circuit design layout, the simulated electron microscope image includes a plurality of scanning electron microscope simulation scanning graphics, and the morphology of the scanning electron microscope simulation scanning graphics is close to the scanning graphics in the scanning electron microscope image, so that the scanning electron microscope image and the simulated electron microscope image can be matched efficiently, quickly and accurately, thereby improving the matching efficiency and accuracy.

[0068] Other features and advantages of the embodiments of the present invention will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] The accompanying drawings are used to provide a further understanding of the embodiments of the present invention and constitute a part of the specification. Together with the following specific implementations, they are used to explain the embodiments of the present invention, but do not constitute a limitation on the embodiments of the present invention. In the accompanying drawings:

[0070] Figure 1 A schematic diagram of a flow chart of a method for registering a circuit design layout and a scanning electron microscope image according to an embodiment of the present application is shown;

[0071] Figure 2 A schematic diagram schematically shows a circuit design layout according to an embodiment of the present application;

[0072] Figure 3 A schematic diagram of a circuit design layout after corner cutting according to an embodiment of the present application is schematically shown;

[0073] Figure 4 Schematically shows a schematic diagram of an outline graph according to an embodiment of the present application;

[0074] Figure 5A schematic diagram schematically shows a diagram after the graphic and the contour are overlapped according to an embodiment of the present application;

[0075] Figure 6 A schematic diagram schematically shows an image after blurring and pixel homogenization according to an embodiment of the present application;

[0076] Figure 7 A schematic diagram schematically shows that the patterns according to an embodiment of the present application are arranged periodically in the first direction X and the second direction Y;

[0077] Figure 8 A schematic diagram showing that a graph according to an embodiment of the present application does not change in the second direction Y, but has periodic changes in the first direction X;

[0078] Fig. 9 Schematic diagram showing that the graph according to the embodiment of the present application does not change in the first direction X, but has periodic changes in the second direction Y;

[0079] Fig.10 A schematic diagram of a scanning electron microscope image according to an embodiment of the present application is shown;

[0080] Fig.11 A schematic diagram showing another scanning electron microscope image according to an embodiment of the present application is shown;

[0081] Fig.12 A table diagram showing the pixel values ​​of the first row and the first column of 5 rows×5 columns of pixels in a simulated electron microscope image according to an embodiment of the present application is shown;

[0082] Fig.13 A table diagram showing pixel values ​​of the second row and second column of 5 rows×5 columns of pixels in a simulated electron microscope image according to an embodiment of the present application is shown;

[0083] Fig.14 A schematic diagram showing the pixel values ​​of the third row and the third column of 5 rows×5 columns of pixels in a simulated electron microscope image according to an embodiment of the present application is shown;

[0084] Fig.15 A schematic diagram of the structure of a circuit design layout and a scanning electron microscope image registration device according to an embodiment of the present application is shown;

[0085] Fig.16 The internal structure diagram of a computer device according to an embodiment of the present application is schematically shown.

[0086] Description of Reference Numerals

[0087] 100-first circuit design layout; 101-first figure; 110-second circuit design layout; 111-second figure; 120-third circuit design layout; 121-contour figure; 130-fourth circuit design layout; 131-fourth figure; 140-simulated electron microscope image; 141-scanning electron microscope simulation figure; 410-acquisition module; 420-generation module; 430-determination module; 440-matching module; A01-processor; A02-network interface; A03-internal memory; A04-display screen; A05-input device; A06-non-volatile storage medium; B01-operating system; B02-computer program. DETAILED DESCRIPTION

[0088] The specific implementation of the embodiment of the present invention is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described here is only used to illustrate and explain the embodiment of the present invention, and is not used to limit the embodiment of the present invention.

[0089] It should be noted that if the embodiments of the present application involve directional indications (such as up, down, left, right, front, back...), the directional indications are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0090] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present application, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or suggesting their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0091] Please see Figure 1 , Figure 1 The following is a schematic diagram of a method for aligning a circuit design layout and a scanning electron microscope image according to an embodiment of the present application. This embodiment provides a method for aligning a circuit design layout and a scanning electron microscope image, comprising the following steps:

[0092] Step 210: Acquire a first circuit design layout 100 and a scanning electron microscope image, wherein the first circuit design layout 100 includes a plurality of first graphics 101;

[0093] In this embodiment, please see Figure 2 , Figure 2A schematic diagram of a circuit design layout according to an embodiment of the present application is schematically shown. Figure 2 As shown, a first circuit design layout 100 is provided, and the first circuit design layout 100 includes a plurality of first graphics 101. The first circuit design layout 100 is an initial design layout of a structure that needs to be dimensionally measured. Fig.10 and Fig.11 , Fig.10 A schematic diagram of a scanning electron microscope image according to an embodiment of the present application is shown; Fig.11 A schematic diagram of another scanning electron microscope image according to an embodiment of the present application is shown. The scanning electron microscope image includes a scanning electron microscope image of a photoresist pattern on a wafer, specifically a scanning electron microscope image of a structure that needs to be sized, and the scanning electron microscope image includes a plurality of scanning patterns. The scanning electron microscope image is compared in size with the first circuit design layout 100 to achieve registration.

[0094] Step 220: performing image processing on each first graphic 101 in the first circuit design layout 100 to generate a scanning electron microscope simulation graphic 141 corresponding to each first graphic 101 to obtain a simulated electron microscope image 140;

[0095] In this embodiment, the above-mentioned image processing of each first graphic 101 refers to a series of image processing to generate a simulated electron microscope image 140, and the simulated electron microscope image 140 includes a plurality of scanning electron microscope simulation graphics 141. These scanning electron microscope simulation graphics 141 are obtained by simulating scanning electron microscope images of each first graphic 101.

[0096] In some embodiments, the image processing of each first graphic 101 in the first circuit design layout 100 to generate a scanning electron microscope simulation graphic 141 corresponding to each first graphic 101 to obtain a simulated electron microscope image 140 includes the following steps:

[0097] First, the line ends of each first graphic 101 in the first circuit design layout 100 are chamfered to form a plurality of second graphics 111 to obtain a second circuit design layout 110;

[0098] In this embodiment, please see Figure 3 , Figure 3A schematic diagram of a circuit design layout after corner cutting according to an embodiment of the present application is schematically shown. The corner cutting process is performed so that the line end is arc-shaped. The line end of the first figure 101 includes a first side and a second side opposite to each other in the width direction of the first figure 101, the first figure 101 has a first vertex located on the first side, and the first figure 101 has a second vertex located on the second side. The corner cutting process is performed on the line ends of several first figures 101, including: performing a first area removal on the first side of the line end of the first figure 101, the first area includes a first vertex, the first area includes a first triangle, and the first triangle has a first side length in the width direction of the first figure 101; performing a second area removal on the second side of the line end of the first figure 101, the second area includes a second vertex, the second area includes a second triangle, and the second triangle has a second side length in the width direction of the first figure 101. It should be noted that the sum of the first side length and the second side length is less than the width of the first figure 101. Specifically, the size of the first side length and the second side length can be adjusted according to actual conditions so that the second figure 111 after corner cutting is closer to the electron microscope image.

[0099] Then, extracting the edges of each second graphic 111 in the second circuit design layout 110, and performing expansion processing on the edges of each second graphic 111 to form a plurality of outline graphics 121, so as to obtain a third circuit design layout 120;

[0100] In this embodiment, please see Figure 4 , Figure 4 The schematic diagram of the contour graphic 121 according to the embodiment of the present application is schematically shown. The edge extraction process and the edge expansion process are respectively performed on a plurality of the second graphics 111 to form a plurality of contour graphics 121, so that the second circuit design layout 110 is generated as the third circuit design layout 120. The contour graphic 121 is the edge line of the second graphic 111 after the expansion process. The edge extraction process and the edge expansion process are performed on the plurality of the second graphics 111 so that the edge line of the contour graphic 121 approaches the edge line of the graphic in the scanning electron microscope image. The above-mentioned edge extraction process and edge expansion process can be realized by using the existing technology, and will not be described in detail here.

[0101] Then, each second graphic 111 in the second circuit design layout 110 is merged with the corresponding outline graphic 121 in the third circuit design layout 120 to obtain a plurality of initial simulation graphics, so as to obtain a fourth circuit design layout 130;

[0102] In this embodiment, please see Figure 5 , Figure 5The schematic diagram schematically shows the overlapped processing of the graphic and the outline according to the embodiment of the present application. The above-mentioned merging refers to the overlap processing of the second graphic 111 and the corresponding outline graphic 121 to form a fourth graphic 131, that is, the initial simulation graphic.

[0103] In some embodiments, in order to make the grayscale of the merged image close to the grayscale of the SEM image, the second circuit design layout 110 and the third circuit design layout 120 may be grayscale adjusted before merging. Specifically, the steps of merging each second graphic 111 in the second circuit design layout 110 with the corresponding outline graphic 121 in the third circuit design layout 120 to obtain a plurality of initial simulation graphics to obtain the fourth circuit design layout 130 include the following steps:

[0104] The first step is to adjust the pixel value of each second graphic 111 in the second circuit design layout 110 based on the preset first coefficient to obtain a new second circuit design layout 110;

[0105] The second step is to adjust the pixel values ​​of each contour image in the third circuit design layout 120 based on the preset second coefficient to obtain a new third circuit design layout 120; wherein the sum of the preset first coefficient and the preset second coefficient is 1;

[0106] In this embodiment, the preset first coefficient and the second coefficient may be set according to actual conditions, and the value range of the first coefficient and the second coefficient may be 0 to 1. The adjustment of the pixel value refers to multiplying the pixel value of each second graphic 111 or the pixel value of each contour image by the corresponding coefficient to obtain a new pixel value.

[0107] In the third step, each second graphic 111 in the new second circuit design layout 110 is merged with the corresponding outline graphic 121 in the new third circuit design layout 120 to obtain a plurality of initial simulation graphics, so as to obtain a fourth circuit design layout 130.

[0108] In this embodiment, the above merging is to add the grayscale values ​​of each second graphic 111 in the new second circuit design layout 110 and the corresponding contour graphic 121 in the new third circuit design layout 120. For example, if the grayscale value of a pixel of the second graphic 111 in the second circuit design layout 110 is 0, the grayscale value of the pixel of the corresponding contour graphic in the third circuit design layout 120 is 255. The first coefficient is 0.2, and the second coefficient is 0.8, so after merging, it is 0.2*0+0.8*255=204.

[0109] By multiplying the grayscale value of the second circuit design layout 110 by a first coefficient, and multiplying the third circuit design layout 120 by a second coefficient, the sum of the first coefficient and the second coefficient is 1; the second circuit design layout 110 multiplied by the first coefficient and the third circuit design layout 120 multiplied by the second coefficient are merged, the contour graphic 121 and the second graphic 111 correspond one by one, and a fourth circuit design layout 130 is generated, so that the grayscale of the merged image can be close to the grayscale of the scanning electron microscope image, so that the generated fourth circuit design layout 130 is close to the scanning electron microscope image, which is conducive to fast and accurate alignment.

[0110] Finally, image blurring and pixel homogenization are performed on each initial simulation graphic in the fourth circuit design layout 130 to generate a scanning electron microscope simulation graphic 141 corresponding to each first graphic 101 to obtain a simulated electron microscope image 140 .

[0111] In this embodiment, please see Figure 6 , Figure 6 The schematic diagram after the image blurring and pixel equalization processing according to the embodiment of the present application is schematically shown. By performing image blurring processing on each initial analog graphic in the fourth circuit design layout 130, the details in the image are reduced, so that the image looks softer and smoother. The above-mentioned image blurring processing method can be low-pass filtering, mean blurring, motion blurring, etc., which belongs to the prior art and will not be repeated here. Performing pixel equalization processing on each initial analog graphic in the fourth circuit design layout 130 can adjust the grayscale distribution of the image so that the contrast of the image is enhanced, which makes it easier to distinguish different areas in the image and the details are more prominent. The above-mentioned pixel equalization processing can be histogram equalization, which adjusts the histogram of the image so that the pixel values ​​are more evenly distributed in the entire grayscale range. It transforms the grayscale histogram of the original image so that the transformed histogram is as close to the uniform distribution as possible. It can also be implemented by filtering and other methods. Pixel equalization processing belongs to the prior art and will not be repeated here. The fourth circuit design layout 130 is subjected to blurring processing and pixel homogenization processing, so that the simulated electron microscope image 140 is closer to the scanning electron microscope image.

[0112] By performing angle cutting processing on the line ends of each first graphic 101 in the first circuit design layout 100, a plurality of second graphics 111 are formed to obtain a second circuit design layout 110;

[0113] The edges of each second graphic 111 in the second circuit design layout 110 are extracted, and the edges of each second graphic 111 are expanded to form a plurality of contour graphics 121 to obtain a third circuit design layout 120; each second graphic 111 in the second circuit design layout 110 is respectively merged with the corresponding contour graphics 121 in the third circuit design layout 120 to obtain a plurality of initial simulation graphics to obtain a fourth circuit design layout 130; each initial simulation graphic in the fourth circuit design layout 130 is subjected to image blurring and pixel uniformization processing to generate a scanning electron microscope simulation graphic 141 corresponding to each first graphic 101 to obtain a simulated electron microscope image 140. The simulated electron microscope image 140 is made closer to the scanning electron microscope image, which is conducive to rapid and accurate registration.

[0114] Then, the simulated electron microscope image 140 and the scanning electron microscope image can be registered to obtain a matching result. The registration is to match and align the simulated electron microscope image 140 with the scanning electron microscope image. The above registration can also be performed by first performing a matching range reduction process, that is, the simulated electron microscope image 140 and the scanning electron microscope image are registered to obtain a matching result.

[0115] Step 230: determining an actual matching range in the simulated electron microscope image 140 based on the distribution of each SEM simulated image in the simulated electron microscope image 140;

[0116] In this embodiment, since the distribution of the SEM simulation image may be periodically arranged, during registration, only the images in one period may be registered, thus reducing the matching range to within one period.

[0117] It should be noted that, in a specific implementation, the matching range reduction processing may be performed on the first circuit design layout 100, the second circuit design layout 110, the third circuit design layout 120, the fourth circuit design layout 130 or the simulated electron microscope image 140, that is, in the above-mentioned image processing process, the matching range reduction processing may be performed on any one of the first circuit design layout 100, the second circuit design layout 110, the third circuit design layout 120, the fourth circuit design layout 130 or the simulated electron microscope image 140, so that when the scanning electron microscope image is subsequently matched with the simulated electron microscope image 140, the matching range is reduced, thereby improving the matching efficiency.

[0118] Specifically, the actual matching range is determined in the simulated electron microscope image 140 based on the distribution of each scanning electron microscope simulation image in the simulated electron microscope image 140, including the following steps:

[0119] The first step is to determine a first direction and a second direction in the simulated electron microscope image 140, wherein the first direction is perpendicular to the second direction;

[0120] In this embodiment, the first direction and the second direction are respectively set to a first direction X and a second direction Y, the first direction X and the second direction Y are perpendicular to each other, and the first direction X and the second direction Y are parallel to the surface of the simulated electron microscope image 140 .

[0121] The second step is to determine whether the scanning electron microscope simulation images are periodically arranged in the first direction and / or the second direction based on the distribution of the scanning electron microscope simulation images in the simulated electron microscope image 140;

[0122] In this embodiment, the range reduction direction is determined based on the change trend of each SEM simulation image in the simulated SEM image 140 in the first direction and the change trend in the second direction, and the range reduction direction is the first direction and / or the second direction. If a plurality of SEM simulation images are periodically arranged in one or both of the first direction X and the second direction Y, and the range reduction direction is the first direction X and / or the second direction Y, the matching range can be reduced to one period; if a plurality of graphics do not change in the first direction X and the second direction Y, the matching range can be reduced to the direction in which the graphics change.

[0123] The third step is to determine the actual matching range based on the arrangement period of the scanning electron microscope simulation images when it is determined that the scanning electron microscope simulation images are arranged periodically in the first direction and / or the second direction.

[0124] In this embodiment, if the arrangement is periodic, the matching range can be reduced to the direction where the pattern changes, and the actual matching range is reduced to within one period.

[0125] Step 240: within the actual matching range, align the simulated electron microscope image 140 with the scanning electron microscope image to obtain a matching result.

[0126] In this embodiment, please refer to Figure 7 , Figure 7 The schematic diagram shows that the patterns according to the embodiment of the present application are arranged periodically in the first direction X and the second direction Y. In this case, the scanning electron microscope image and the simulated electron microscope image 140 are matched only within a period of the first direction X and the second direction Y. Please refer to Figure 8 , Figure 8The schematic diagram shows that the pattern according to the embodiment of the present application does not change in the second direction Y, but has periodic changes in the first direction X. In this case, only the scanning electron microscope image and the simulated electron microscope image 140 are matched along the first direction X. Please refer to Fig. 9 , Fig. 9 The schematic diagram shows that the figure according to the embodiment of the present application does not change in the first direction X, but has periodic changes in the second direction Y. At this time, only the scanning electron microscope image and the simulated electron microscope image 140 need to be matched along the second direction Y.

[0127] By performing the matching range reduction process, the actual matching range is made smaller, so that when the scanning electron microscope image is matched with the simulated electron microscope image 140, the matching range is reduced, and the matching efficiency is further improved.

[0128] It should be noted that, in specific implementation, the matching range reduction process may not be performed, that is, the scanning electron microscope image and the simulated electron microscope image 140 may be directly fully matched without determining the actual matching range.

[0129] In some embodiments, registering the simulated electron microscope image 140 with the scanning electron microscope image to obtain a matching result includes:

[0130] First, the simulated electron microscope image 140 is shifted multiple times according to different preset shift amounts to obtain multiple simulated electron microscope shifted images;

[0131] In this embodiment, the above-mentioned offset can be pre-set, and each offset is different, including the case where the offset is 0. The offset is 0, which means that no offset is made, that is, the simulated electron microscope offset image is the simulated electron microscope image 140. It should be noted that the offset is generally much smaller than the size of the simulated electron microscope image 140, and the offset range is the registration range, that is, when the matching range is reduced, the offset range is the actual matching range; when the matching range is not reduced, the offset range is the range of the simulated electron microscope image 140. For example, the registration range is (-100, -100) to (100, 100), then the offset is any amount within this range, for example, the offset can be (-100, -100), (0, 0), (100, 100), etc. The above-mentioned offset is to offset the pixel value of the entire simulated electron microscope image 140. For example, the simulated electron microscope image 140 is 3*3 pixels, the pixels in the first row are a, b, c, the pixels in the second row are d, e, f, and the pixels in the third row are g, h, i. If the pixels are offset upward by one unit, the pixels in the first row become d, e, f, the pixels in the second row are g, h, i, and the pixels in the third row are 0, 0, 0, that is, the vacant places can be filled with zeros after the offset.

[0132] Then, the similarity between each simulated electron microscope offset image and the scanning electron microscope image is calculated respectively to obtain a plurality of correlation values;

[0133] In this embodiment, the similarity between the simulated electron microscope offset image and the scanning electron microscope image can be calculated using an existing image similarity calculation method. For example, the Pearson correlation coefficient between the corresponding pixel values ​​of the simulated electron microscope offset image and the scanning electron microscope image can be calculated to measure the similarity between the images. The closer the Pearson correlation coefficient is, the more similar the images are.

[0134] Finally, a matching result is obtained based on the multiple correlation values.

[0135] In this embodiment, whether the match is successful can be determined based on the correlation value to obtain a matching result. The matching result includes a successful match and a failed match; if the correlation value between the scanning electron microscope image and the simulated electron microscope offset image is greater than a preset value, the match is successful; if the correlation value between the scanning electron microscope image and the simulated electron microscope offset image is less than a preset value, the match fails. The correlation value is used to characterize the degree of matching between the simulated electron microscope offset image and the scanning electron microscope image. Under the premise that the correlation value is greater than the preset value, the higher the correlation value, the higher the matching degree between the simulated electron microscope offset image and the scanning electron microscope image. The matching result is successful, that is, the scanning electron microscope image can match the simulated scanning pattern 141 on the simulated electron microscope offset image; the matching result fails, that is, the scanning electron microscope image cannot match the simulated scanning pattern 141 on the simulated electron microscope offset image, that is, the formed photoresist pattern is abnormal.

[0136] In some embodiments, obtaining a matching result based on the multiple relevance values ​​comprises the following steps:

[0137] The first step is to compare each correlation value with a preset threshold value to obtain a comparison result;

[0138] In this embodiment, the preset threshold value may be preset according to actual conditions. Each correlation value may be not less than the preset threshold value, or may be less than the preset threshold value. The comparison result includes the comparison of each correlation value.

[0139] The second step is to determine whether the comparison result has a correlation value that is not less than a preset threshold;

[0140] When it is determined that the comparison result has a correlation value that is not less than a preset threshold, the corresponding offset is determined based on the maximum value of the correlation values ​​that are not less than the preset threshold to obtain a matching result; when it is determined that the comparison result does not have a correlation value that is not less than the preset threshold, the matching result is a matching failure.

[0141] In this embodiment, if there is a correlation value that is not less than the preset threshold, it means that the match is successful. Accordingly, a simulated electron microscope offset image with the largest correlation value can be found, which is the most similar simulated electron microscope offset image, and then the corresponding offset can be determined. If all correlation values ​​are less than the preset threshold, it means that the match fails.

[0142] By performing multiple offsets on the simulated electron microscope image 140 according to different preset offset amounts, multiple simulated electron microscope offset images are obtained, and the similarity between each simulated electron microscope offset image and the scanning electron microscope image is calculated to obtain multiple correlation values, and matching results are obtained based on the multiple correlation values. The matching result can be accurately obtained through the similarity, which helps to improve the registration accuracy. By comparing each correlation value with a preset threshold value, the matching result can be quickly determined based on the comparison result.

[0143] In some embodiments, the simulated electron microscope image 140 has a plurality of pixel points distributed in an array; the registering the simulated electron microscope image 140 with the scanning electron microscope image to obtain a matching result comprises the following steps:

[0144] First, pixel values ​​of each row and each column of the simulated electron microscope image 140 are accumulated to obtain a plurality of pixel accumulation values;

[0145] In this embodiment, the plurality of pixel accumulated values ​​include a pixel accumulated value of each row and a pixel accumulated value of each column.

[0146] It should be noted that when the matching range reduction process is performed, the above-mentioned pixel value accumulation is performed within the actual matching range after the matching range reduction process; when the matching range reduction process is not performed, the above-mentioned pixel value accumulation is performed within the matching range that has not been reduced.

[0147] for example: Fig.12 A table diagram of the first row and first column pixel values ​​of 5 rows×5 columns of pixels in a simulated electron microscope image 140 according to an embodiment of the present application is shown, where each row of pixels corresponds to a first row pixel cumulative value, and each column of pixels corresponds to a first column pixel cumulative value. The first row pixel cumulative values ​​corresponding to row1, row2, row3, row4, and row5 are 50, 220, 360, 220, and 50, respectively; the first column pixel cumulative values ​​corresponding to column1, column 2, column 3, column 4, and column 5 are 0, 200, 500, 200, and 0, respectively.

[0148] Then, determining whether there is one and only one maximum value among the plurality of pixel accumulated values;

[0149] In this embodiment, the above judgment is to perform a single cumulative analysis on the simulated electron microscope image 140; if the result of the single cumulative analysis meets the preset conditions, that is, there is only one maximum value, the simulated electron microscope image 140 and the scanning electron microscope image are matched in one dimension; if the result of the single cumulative analysis does not meet the preset conditions, the simulated electron microscope image 140 and the scanning electron microscope image are matched in two dimensions.

[0150] Then, when it is determined that there is only one maximum value among the plurality of pixel accumulated values, one-dimensional matching is performed on the simulated electron microscope image 140 and the scanning electron microscope image in the column direction and the row direction to obtain a matching result;

[0151] In this embodiment, a single cumulative analysis is performed on the simulated electron microscope image 140, and the result of the single cumulative analysis meets the preset conditions. The simulated electron microscope image 140 and the scanning electron microscope image are matched in one dimension in the column direction and the row direction, so that the calculation process of the correlation value between the simulated electron microscope image 140 and the scanning electron microscope image is simple, making the matching process more efficient.

[0152] For example: In the above example, Fig.12 It is shown in the figure that the first row pixel cumulative value 360 ​​corresponding to row3 of the simulated electron microscope image 140 is a maximum value among the pixel cumulative values, and then the simulated electron microscope image 140 and the scanning electron microscope image are matched in one dimension in the column direction and the row direction. One-dimensional matching is to compress the image in one direction first, which can greatly reduce the amount of calculation and improve the matching efficiency.

[0153] In some embodiments, performing one-dimensional matching of the simulated electron microscope image 140 and the scanning electron microscope image in the column direction and the row direction to obtain a matching result includes the following steps:

[0154] The first step is to shift the simulated electron microscope image 140 multiple times according to different preset shift amounts to obtain multiple simulated electron microscope shift images;

[0155] In this embodiment, the offset may be pre-set, and each offset is different, including the case where the offset is 0. When the offset is 0, it means that no offset is performed, that is, the simulated electron microscope offset image is the simulated electron microscope image 140. It should be noted that the offset is generally much smaller than the size of the simulated electron microscope image 140, and the offset range is the registration range, that is, when the matching range is reduced, the offset range is the actual matching range; when the matching range is not reduced, the offset range is the range of the simulated electron microscope image 140.

[0156] The second step is to use the first similarity calculation method to calculate the similarity between each simulated electron microscope offset image and the scanning electron microscope image, and obtain a plurality of one-dimensional matching correlation values;

[0157] Specifically, the first similarity calculation method is used to respectively calculate the similarity between each simulated electron microscope offset image and the scanning electron microscope image to obtain a plurality of one-dimensional matching correlation values, including:

[0158] First, for each simulated EM shift image, perform the following steps:

[0159] Then, pixel values ​​of each row and each column of pixels in the simulated electron microscope offset image are accumulated to obtain a plurality of first row pixel accumulation values ​​and a plurality of first column pixel accumulation values;

[0160] Then, pixel values ​​of each row and each column of the scanning electron microscope image are accumulated to obtain a plurality of second row pixel accumulated values ​​and a plurality of second column pixel accumulated values;

[0161] Then, the product of each first row pixel accumulation value and the corresponding second row pixel accumulation value is calculated respectively to obtain a plurality of first products;

[0162] Then, the product of each first column pixel accumulation value and the corresponding second column pixel accumulation value is calculated respectively to obtain a plurality of second products;

[0163] Finally, the sum of the plurality of first products and the plurality of second products is calculated to obtain correlation values ​​of each simulated electron microscope offset image, so as to obtain a plurality of one-dimensional matching correlation values.

[0164] In this embodiment, first, pixel values ​​of each row and each column of the simulated electron microscope offset image with an offset of 0, that is, the simulated electron microscope image 140, are accumulated to obtain a number of first pixel accumulation values, which include a number of first row pixel accumulation values ​​and a number of first column pixel accumulation values; pixel values ​​of each row and each column of the scanning electron microscope image are accumulated to obtain a number of second pixel accumulation values, which include a number of second row pixel accumulation values ​​and a number of second column pixel accumulation values; a first product of a number of the first row pixel accumulation values ​​and the corresponding second row pixel accumulation values ​​is obtained; a second product of the first column pixel accumulation value and the corresponding second column pixel accumulation value is obtained; the first correlation value is the sum of the first products and the second products to obtain a first correlation value. Then, pixel values ​​of each row and each column of other simulated electron microscope offset images are accumulated to obtain a plurality of third row pixel accumulation values ​​and a plurality of third column pixel accumulation values; a third product of a plurality of third row pixel accumulation values ​​and corresponding second row pixel accumulation values ​​is obtained; a fourth product of a plurality of third column pixel accumulation values ​​and corresponding second column pixel accumulation values ​​is obtained; a second correlation value is obtained, and the second correlation value is the sum of a plurality of third products and a plurality of fourth products, to obtain a plurality of second correlation values. The first correlation value and a plurality of second correlation values ​​constitute a plurality of one-dimensional matching correlation values.

[0165] The third step is to obtain a matching result based on the multiple one-dimensional matching correlation values.

[0166] In this embodiment, the process of obtaining the matching result is the same as the process of obtaining the matching result based on the multiple correlation values ​​described above, and will not be described in detail here.

[0167] For example: Assume Fig.13 The simulated electron microscope image 140 shown in FIG. 1 is shifted to the left. Fig.13 A table diagram of the second row and second column pixel values ​​of 5 rows×5 columns of pixels in a simulated electron microscope image 140 according to an embodiment of the present application is shown, where each row of pixels corresponds to a second row pixel cumulative value, and each column of pixels corresponds to a second column pixel cumulative value.

[0168] In this embodiment, the second row pixel cumulative values ​​corresponding to row1, row2, row3, row4, and row5 are 50, 220, 360, 220, and 50 respectively; the second column pixel cumulative values ​​corresponding to column1, column 2, column 3, column 4, and column 5 are 200, 500, 200, 0, and 0 respectively.

[0169] Obtain a first product of several first row pixel accumulation values ​​and corresponding second row pixel accumulation values; obtain a second product of the first column pixel accumulation values ​​and corresponding second column pixel accumulation values; obtain a first correlation value, which is the sum of several first products and several second products.

[0170] Fig.12 The accumulated values ​​of the first row of pixels corresponding to row1, row2, row3, row4, and row5 are Fig.13 The accumulated values ​​of the pixels in the second row corresponding to row1, row2, row3, row4, and row5 correspond one to one. Fig.12 The accumulated values ​​of the first column of pixels corresponding to column 1, column 2, column 3, column 4, and column 5 are equal to Fig.13 The accumulated values ​​of the second columns of pixels corresponding to column 1, column 2, column 3, column 4, and column 5 correspond one to one. The first correlation value=0×200+200×500+500×200+200×0+0×0=200000.

[0171] Fig.14 A schematic diagram of the third row and third column pixel values ​​of 5 rows×5 columns of pixels in the simulated electron microscope image 140 according to an embodiment of the present application is shown, and each column of pixels corresponds to a second column of pixel cumulative values. After the offset, the first row pixel cumulative values ​​corresponding to row1, row2, row3, row4, and row5 of the simulated electron microscope image 140 are 50, 220, 360, 220, and 50, respectively; the first column pixel cumulative values ​​corresponding to column1, column 2, column 3, column 4, and column 5 are 200, 500, 200, 0, and 0, respectively.

[0172] Obtain a third product of several third row pixel accumulation values ​​and corresponding second row pixel accumulation values; obtain a fourth product of the third column pixel accumulation values ​​and corresponding second column pixel accumulation values; obtain a second correlation value, which is the sum of several third products and several fourth products.

[0173] Fig.14 The accumulated value of the third row of pixels corresponding to row1, row2, row3, row4, and row5 is Fig.13 The accumulated values ​​of the pixels in the second row corresponding to row1, row2, row3, row4, and row5 correspond one to one. Fig.14 The accumulated values ​​of the pixels in the third column corresponding to column 1, column 2, column 3, column 4, and column 5 are equal to Fig.13 The accumulated values ​​of the second columns of pixels corresponding to column 1, column 2, column 3, column 4, and column 5 correspond one to one. The second correlation value=0×0+200×200+500×500+200×200+0×0=290000.

[0174] If the second correlation value is greater than the first correlation value, the matching range after the analog electron microscope image 140 is offset has a higher matching degree with the scanning electron microscope image; if the second correlation value is less than the first correlation value, the matching range of the analog electron microscope image 140 that is not offset has a higher matching degree with the scanning electron microscope image. The second correlation value is 290000, the first correlation value is 200000, and the second correlation value is greater than the first correlation value, so the matching range after the analog electron microscope image 140 is offset has a higher matching degree with the scanning electron microscope image. If the analog electron microscope image 140 is offset several times within the matching range and the correlation value is the largest, it means that the offset range of the analog electron microscope image 140 matches the scanning electron microscope image. If several second correlation values ​​and the first correlation value are all less than the preset value, it means that the scanning electron microscope image cannot match the analog electron microscope image 140.

[0175] Finally, when it is determined that there is more than one maximum value in the plurality of pixel accumulated values, two-dimensional matching is performed on the simulated electron microscope image 140 and the scanning electron microscope image in the column direction and the row direction to obtain a matching result.

[0176] In some embodiments, performing two-dimensional matching of the simulated electron microscope image 140 and the scanning electron microscope image in the column direction and the row direction to obtain a matching result includes the following steps:

[0177] First, the simulated electron microscope image 140 is shifted multiple times to obtain multiple simulated electron microscope shifted images;

[0178] In this embodiment, the offset may be pre-set, and each offset is different, including the case where the offset is 0. When the offset is 0, it means that no offset is performed, that is, the simulated electron microscope offset image is the simulated electron microscope image 140. It should be noted that the offset is generally much smaller than the size of the simulated electron microscope image 140, and the offset range is the registration range, that is, when the matching range is reduced, the offset range is the actual matching range; when the matching range is not reduced, the offset range is the range of the simulated electron microscope image 140.

[0179] Then, a second similarity calculation method is used to respectively calculate the similarity between each simulated electron microscope offset image and the scanning electron microscope image to obtain a plurality of two-dimensional matching correlation values;

[0180] In this embodiment, a third correlation value of two-dimensional matching between the simulated electron microscope image 140 and the scanning electron microscope image is obtained; after the simulated electron microscope image 140 is shifted several times, a fourth correlation value of the shifted simulated electron microscope image 140 and the scanning electron microscope image is obtained; several fourth correlation values ​​are compared with the third correlation value, and the shift with the largest correlation value is obtained to match the scanning electron microscope image. The third correlation value and multiple fourth correlation values ​​constitute multiple two-dimensional matching correlation values.

[0181] Specifically, the second similarity calculation method is used to respectively calculate the similarity between each simulated electron microscope offset image and the scanning electron microscope image to obtain a plurality of two-dimensional matching correlation values, including:

[0182] For each simulated EM migration image, perform the following steps:

[0183] The first step is to calculate the product of the pixel value of each pixel point in the simulated electron microscope offset image and the pixel value of the corresponding pixel point in the scanning electron microscope image to obtain a plurality of third products;

[0184] The second step is to calculate the sum of the multiple third products to obtain the correlation value of each simulated electron microscope offset image, and obtain multiple two-dimensional matching correlation values.

[0185] In this embodiment, a plurality of pixels of the simulated electron microscope image 140 correspond to a plurality of pixels of the scanning electron microscope image in a one-to-one manner in the row and column directions, and the sum of the products of the pixel values ​​of the plurality of pixels of the simulated electron microscope image 140 and the pixel values ​​of the corresponding pixels of the scanning electron microscope image is obtained as the third correlation value. A plurality of pixels of the simulated electron microscope image 140 after displacement correspond to a plurality of pixels of the scanning electron microscope image in a one-to-one manner in the row and column directions, and the sum of the products of the pixel values ​​of the plurality of pixels of the simulated electron microscope image 140 after displacement and the pixel values ​​of the corresponding pixels of the scanning electron microscope image is obtained as the fourth correlation value.

[0186] Finally, a matching result is obtained based on the multiple two-dimensional matching correlation values.

[0187] In this embodiment, the process of obtaining the matching result is the same as the process of obtaining the matching result based on the multiple correlation values ​​described above, and will not be described in detail here.

[0188] Assuming that the matching range of the simulated electron microscope image 140 has 5 rows × 5 columns of pixels, and the matching range of the scanning electron microscope image has 5 rows × 5 columns of pixels, the calculation of the third correlation value needs to be calculated 5 × 5 = 25 times. Accumulate the pixel values ​​of each row and each column of the simulated electron microscope image 140 to obtain a number of pixel accumulation values; if there is only one maximum value among the several pixel accumulation values, perform one-dimensional matching in the column direction and the row direction on the simulated electron microscope image 140 and the scanning electron microscope image; if there is more than one maximum value among the several pixel accumulation values, perform two-dimensional matching on the simulated electron microscope image 140 and the scanning electron microscope image. Two-dimensional matching is pixel-by-pixel comparison, for example, 10*10 needs to be compared 100 times. One-dimensional matching is to compress 10*10 to 10 in one direction, so that only 10 comparisons are required. Compared with two-dimensional matching, one-dimensional matching can greatly reduce the amount of calculation and improve matching efficiency.

[0189] In the above implementation process, the first circuit design layout 100 and the scanning electron microscope image are obtained, wherein the first circuit design layout 100 includes a plurality of first graphics 101; scanning electron microscope image simulation is performed on each first graphic 101 in the first circuit design layout 100 to generate scanning electron microscope simulation graphics 141 corresponding to each first graphic 101 to obtain a simulated electron microscope image 140; the simulated electron microscope image 140 is registered with the scanning electron microscope image to obtain a matching result. The first circuit design layout 100 is generated into a simulated electron microscope image 140 through image processing, wherein the simulated electron microscope image 140 includes a plurality of scanning electron microscope simulation scanning graphics, and the morphology of the scanning electron microscope simulation scanning graphics is close to the scanning graphics in the scanning electron microscope image, so that the scanning electron microscope image and the simulated electron microscope image 140 can be matched efficiently, quickly and accurately, thereby improving the matching efficiency and accuracy.

[0190] After the above registration, if the matching result is successful, the matching coordinates are outputted, and if the matching result is unsuccessful, a matching failure result is outputted. Fig.10 The SEM image in the figure is a successful match. Fig.11 The scanning electron microscope image in the matching result fails. The first graphic 101 corresponding to the matching coordinates is overlapped with the scanning graphic, and the size of the scanning graphic is measured. The size of the scanning graphic is measured based on the first circuit design layout 100, and the first graphic 101 corresponding to the matching coordinates is overlapped with the scanning graphic, that is, the first graphic 101 corresponding to the matching coordinates in the first circuit design layout 100 is overlapped and measured with the scanning graphic in the scanning electron microscope image. The matching position of the scanning electron microscope image and the design layout is accurate and efficient, and the size measurement result of the scanning graphic can be quickly obtained, which improves work efficiency.

[0191] Figure 1 FIG. 1 is a flow chart of a method for registering a circuit design layout and a scanning electron microscope image in one embodiment. It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0192] Please see Fig.15 , Fig.15 The schematic diagram of the structure of a circuit design layout and a scanning electron microscope image registration device according to an embodiment of the present application is schematically shown. This embodiment provides a circuit design layout and a scanning electron microscope image registration device, including: an acquisition module 410, a generation module 420, a determination module 430 and a matching module 440, wherein:

[0193] An acquisition module 410 is used to acquire a first circuit design layout 100 and a scanning electron microscope image, wherein the first circuit design layout 100 includes a plurality of first graphics 101;

[0194] A generating module 420 is used to perform image processing on each first graphic 101 in the first circuit design layout 100 to generate a scanning electron microscope simulation graphic 141 corresponding to each first graphic 101 to obtain a simulated electron microscope image 140;

[0195] A determination module 430, configured to determine an actual matching range in the simulated electron microscope image 140 based on the distribution of each SEM simulated image in the simulated electron microscope image 140;

[0196] The matching module 440 is used to register the simulated electron microscope image 140 with the scanning electron microscope image within the actual matching range to obtain a matching result.

[0197] The circuit design layout and scanning electron microscope image registration device includes a processor and a memory. The above-mentioned acquisition module 410, generation module 420, determination module 430 and matching module 440 are all stored in the memory as program units, and the processor executes the above-mentioned program units stored in the memory to realize corresponding functions.

[0198] The processor includes a kernel, which calls the corresponding program unit from the memory. One or more kernels can be set, and the registration efficiency and accuracy can be improved by adjusting the kernel parameters.

[0199] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM, and the memory includes at least one memory chip.

[0200] An embodiment of the present invention provides a storage medium on which a program is stored. When the program is executed by a processor, the registration method of the circuit design layout and the scanning electron microscope image is implemented.

[0201] An embodiment of the present invention provides a processor, which is used to run a program, wherein the program executes the registration method of the circuit design layout and the scanning electron microscope image when running.

[0202] In one embodiment, a computer device is provided. The computer device may be a terminal, and its internal structure diagram may be as follows: Fig.16 As shown. The computer device includes a processor A01, a network interface A02, a display screen A04, an input device A05 and a memory (not shown in the figure) connected through a system bus. Among them, the processor A01 of the computer device is used to provide computing and control capabilities. The memory of the computer device includes an internal memory A03 and a non-volatile storage medium A06. The non-volatile storage medium A06 stores an operating system B01 and a computer program B02. The internal memory A03 provides an environment for the operation of the operating system B01 and the computer program B02 in the non-volatile storage medium A06. The network interface A02 of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor A01, a method for aligning a circuit design layout and a scanning electron microscope image is implemented. The display screen A04 of the computer device can be a liquid crystal display or an electronic ink display, and the input device A05 of the computer device can be a touch layer covered on the display screen, or a key, trackball or touchpad set on the computer device housing, or an external keyboard, touchpad or mouse, etc.

[0203] Those skilled in the art will understand that Fig.16 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0204] In one embodiment, the circuit design layout and scanning electron microscope image registration device provided in the present application can be implemented in the form of a computer program, and the computer program can be used in Fig.16 The computer device shown in the figure is run. The memory of the computer device can store various program modules constituting the registration device of the circuit design layout and the scanning electron microscope image, for example, Fig.15 The acquisition module 410, the generation module 420, the determination module 430 and the matching module 440 are shown. The computer program composed of various program modules enables the processor to execute the steps in the calling method of the file system of each embodiment of the present application described in this specification.

[0205] Fig.16 The computer device shown can be Fig.15 In the circuit design layout and SEM image registration device shown, the acquisition module 410 executes step 210 , the generation module 420 executes step 220 , the determination module 430 executes step 230 , and the matching module 440 executes step 240 .

[0206] The embodiment of the present application provides a device, which includes a processor, a memory, and a program stored in the memory and executable on the processor. When the processor executes the program, the following steps are implemented:

[0207] Acquire a first circuit design layout 100 and a scanning electron microscope image, wherein the first circuit design layout 100 includes a plurality of first graphics 101;

[0208] Performing image processing on each first graphic 101 in the first circuit design layout 100 to generate a scanning electron microscope simulation graphic 141 corresponding to each first graphic 101 to obtain a simulated electron microscope image 140;

[0209] Based on the distribution of each SEM simulation image in the simulated SEM image 140, determining an actual matching range in the simulated SEM image 140;

[0210] Within the actual matching range, the simulated electron microscope image 140 is registered with the scanning electron microscope image to obtain a matching result.

[0211] In one embodiment, the image processing is performed on each first graphic 101 in the first circuit design layout 100 to generate a scanning electron microscope simulation graphic 141 corresponding to each first graphic 101 to obtain a simulated electron microscope image 140, including:

[0212] Performing corner cutting processing on the line ends of each first graphic 101 in the first circuit design layout 100 to form a plurality of second graphics 111 to obtain a second circuit design layout 110;

[0213] Extracting the edges of each second graphic 111 in the second circuit design layout 110, and performing expansion processing on the edges of each second graphic 111 to form a plurality of outline graphics 121, so as to obtain a third circuit design layout 120;

[0214] Merging each second graphic 111 in the second circuit design layout 110 with the corresponding outline graphic 121 in the third circuit design layout 120 to obtain a plurality of initial simulation graphics, so as to obtain a fourth circuit design layout 130;

[0215] The image blurring and pixel homogenization processes are performed on each initial simulation graphic in the fourth circuit design layout 130 to generate a scanning electron microscope simulation graphic 141 corresponding to each first graphic 101 to obtain a simulated electron microscope image 140 .

[0216] In one embodiment, the steps of respectively merging each second graphic 111 in the second circuit design layout 110 with the corresponding outline graphic 121 in the third circuit design layout 120 to obtain a plurality of initial simulation graphics to obtain a fourth circuit design layout 130 include:

[0217] Based on the preset first coefficient, the pixel value of each second graphic 111 in the second circuit design layout 110 is adjusted to obtain a new second circuit design layout 110;

[0218] Based on the preset second coefficient, the pixel values ​​of each contour image in the third circuit design layout 120 are adjusted to obtain a new third circuit design layout 120; wherein the sum of the preset first coefficient and the preset second coefficient is 1;

[0219] Each second graphic 111 in the new second circuit design layout 110 is merged with the corresponding outline graphic 121 in the new third circuit design layout 120 to obtain a plurality of initial simulation graphics, so as to obtain a fourth circuit design layout 130 .

[0220] In one embodiment, the actual matching range is determined in the simulated electron microscope image 140 based on the distribution of each scanning electron microscope simulated image in the simulated electron microscope image 140, including:

[0221] Determining a first direction and a second direction in the simulated electron microscope image 140, wherein the first direction is perpendicular to the second direction;

[0222] Based on the distribution of each SEM simulation image in the simulated SEM image 140, determining whether each SEM simulation image is periodically arranged in the first direction and / or the second direction;

[0223] When it is determined that the scanning electron microscope simulation images are periodically arranged in the first direction and / or the second direction, the actual matching range is determined based on the arrangement period of the scanning electron microscope simulation images.

[0224] In one embodiment, registering the simulated electron microscope image 140 with the scanning electron microscope image to obtain a matching result includes:

[0225] The simulated electron microscope image 140 is shifted multiple times according to different preset shift amounts to obtain multiple simulated electron microscope shifted images;

[0226] respectively calculating the similarity between each simulated electron microscope offset image and the scanning electron microscope image to obtain a plurality of correlation values;

[0227] Based on the multiple correlation values, a matching result is obtained.

[0228] In one embodiment, the simulated electron microscope image 140 has a plurality of pixel points distributed in an array;

[0229] The registering the simulated electron microscope image 140 with the scanning electron microscope image to obtain a matching result includes:

[0230] Accumulating pixel values ​​of each row of pixels and each column of pixels in the simulated electron microscope image 140 to obtain a plurality of pixel accumulation values;

[0231] Determine whether there is one and only one maximum value among the plurality of pixel accumulated values;

[0232] When it is determined that there is only one maximum value in the plurality of pixel accumulated values, one-dimensional matching is performed on the simulated electron microscope image 140 and the scanning electron microscope image in the column direction and the row direction to obtain a matching result;

[0233] When it is determined that there is more than one maximum value in the plurality of pixel accumulated values, two-dimensional matching is performed on the simulated electron microscope image 140 and the scanning electron microscope image in the column direction and the row direction to obtain a matching result.

[0234] In one embodiment, performing one-dimensional matching of the simulated electron microscope image 140 and the scanning electron microscope image in the column direction and the row direction to obtain a matching result includes:

[0235] The simulated electron microscope image 140 is shifted multiple times according to different preset shift amounts to obtain multiple simulated electron microscope shifted images;

[0236] The similarity between each simulated electron microscope offset image and the scanning electron microscope image is calculated using a first similarity calculation method to obtain a plurality of one-dimensional matching correlation values;

[0237] A matching result is obtained based on the multiple one-dimensional matching correlation values.

[0238] In one embodiment, the first similarity calculation method is used to respectively calculate the similarity between each simulated electron microscope offset image and the scanning electron microscope image to obtain a plurality of one-dimensional matching correlation values, including:

[0239] For each simulated EM migration image, perform the following steps:

[0240] Accumulating pixel values ​​of each row and each column of pixels in the simulated electron microscope offset image respectively to obtain a plurality of first row pixel accumulation values ​​and a plurality of first column pixel accumulation values;

[0241] Accumulating pixel values ​​of each row and each column of the scanning electron microscope image to obtain a plurality of second row pixel accumulation values ​​and a plurality of second column pixel accumulation values;

[0242] Calculate the product of each first row pixel accumulation value and the corresponding second row pixel accumulation value respectively to obtain a plurality of first products;

[0243] Calculate the product of each first column pixel accumulation value and the corresponding second column pixel accumulation value to obtain a plurality of second products;

[0244] The sum of the plurality of first products and the plurality of second products is calculated to obtain correlation values ​​of each simulated electron microscope offset image, so as to obtain a plurality of one-dimensional matching correlation values.

[0245] In one embodiment, performing two-dimensional matching of the simulated electron microscope image 140 and the scanning electron microscope image in the column direction and the row direction to obtain a matching result includes:

[0246] The simulated electron microscope image 140 is shifted multiple times to obtain multiple simulated electron microscope shifted images;

[0247] The similarity between each simulated electron microscope offset image and the scanning electron microscope image is calculated using a second similarity calculation method to obtain a plurality of two-dimensional matching correlation values;

[0248] A matching result is obtained based on the multiple two-dimensional matching correlation values.

[0249] In one embodiment, the second similarity calculation method is used to respectively calculate the similarity between each simulated electron microscope offset image and the scanning electron microscope image to obtain a plurality of two-dimensional matching correlation values, including:

[0250] For each simulated EM migration image, perform the following steps:

[0251] respectively calculating the product of the pixel value of each pixel point in the simulated electron microscope offset image and the pixel value of the corresponding pixel point in the scanning electron microscope image to obtain a plurality of third products;

[0252] The sum of the plurality of third products is calculated to obtain correlation values ​​of the respective simulated electron microscope offset images, thereby obtaining a plurality of two-dimensional matching correlation values.

[0253] In one embodiment, obtaining a matching result based on the multiple correlation values ​​includes:

[0254] Compare each correlation value with a preset threshold value to obtain a comparison result;

[0255] Determine whether the comparison result has a correlation value not less than a preset threshold;

[0256] In the case where it is determined that the comparison result has a correlation value not less than a preset threshold, determining a corresponding offset based on a maximum value among the correlation values ​​not less than the preset threshold to obtain a matching result;

[0257] When it is determined that the comparison result does not have a correlation value that is not less than a preset threshold, the matching result is obtained as a matching failure.

[0258] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0259] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0260] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0261] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0262] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0263] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0264] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0265] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0266] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the claims of the present application.

Claims

1. A registration method for a circuit design layout and a scanning electron microscope image, characterized in that: include: Acquire a first circuit design layout and a scanning electron microscope image, wherein the first circuit design layout includes a plurality of first graphics; Performing image processing on each first graphic in the first circuit design layout to generate a scanning electron microscope simulation graphic corresponding to each first graphic to obtain a simulated electron microscope image; Based on the distribution of each SEM simulation image in the simulated SEM image, determining an actual matching range in the simulated SEM image; Within the actual matching range, the simulated electron microscope image and the scanning electron microscope image are registered to obtain a matching result.

2. The registration method of circuit design layout and scanning electron microscope image according to claim 1, characterized in that: The performing image processing on each first graphic in the first circuit design layout to generate a scanning electron microscope simulation graphic corresponding to each first graphic to obtain a simulated electron microscope image includes: Performing angle cutting processing on the line ends of each first graphic in the first circuit design layout to form a plurality of second graphics to obtain a second circuit design layout; Extracting the edges of each second graphic in the second circuit design layout, and performing expansion processing on the edges of each second graphic to form a plurality of contour graphics, so as to obtain a third circuit design layout; Merging each second graphic in the second circuit design layout with the corresponding outline graphic in the third circuit design layout to obtain a plurality of initial simulation graphics to obtain a fourth circuit design layout; The image blurring and pixel homogenization processing are performed on each initial simulation pattern in the fourth circuit design layout to generate a scanning electron microscope simulation pattern corresponding to each first pattern to obtain a simulated electron microscope image.

3. The registration method of circuit design layout and scanning electron microscope image according to claim 2, characterized in that: The method of merging the second graphics in the second circuit design layout with the corresponding outline graphics in the third circuit design layout to obtain a plurality of initial simulation graphics to obtain a fourth circuit design layout comprises: Based on the preset first coefficient, adjusting the pixel value of each second graphic in the second circuit design layout to obtain a new second circuit design layout; Based on the preset second coefficient, adjusting the pixel values ​​of each contour image in the third circuit design layout to obtain a new third circuit design layout; wherein the sum of the preset first coefficient and the preset second coefficient is 1; Each second graphic in the new second circuit design layout is merged with the corresponding outline graphic in the new third circuit design layout to obtain a plurality of initial simulation graphics, so as to obtain a fourth circuit design layout.

4. The registration method of circuit design layout and scanning electron microscope image according to claim 1, characterized in that: The method of determining the actual matching range in the simulated electron microscope image based on the distribution of each scanning electron microscope simulated image in the simulated electron microscope image comprises: Determining a first direction and a second direction in the simulated electron microscope image, wherein the first direction is perpendicular to the second direction; Based on the distribution of each SEM simulation image in the simulated SEM image, determining whether each SEM simulation image is periodically arranged in the first direction and / or the second direction; When it is determined that the scanning electron microscope simulation images are arranged periodically in the first direction and / or the second direction, the actual matching range is determined based on the arrangement period of the scanning electron microscope simulation images.

5. The registration method of circuit design layout and scanning electron microscope image according to claim 1, characterized in that: The registering the simulated electron microscope image with the scanning electron microscope image to obtain a matching result includes: The simulated electron microscope image is shifted multiple times according to different preset shift amounts to obtain multiple simulated electron microscope shift images; respectively calculating the similarity between each simulated electron microscope offset image and the scanning electron microscope image to obtain a plurality of correlation values; Based on the multiple correlation values, a matching result is obtained.

6. The registration method of circuit design layout and scanning electron microscope image according to claim 1, characterized in that: The simulated electron microscope image has a plurality of pixel points distributed in an array; The registering the simulated electron microscope image with the scanning electron microscope image to obtain a matching result includes: Accumulating pixel values ​​of pixel points in each row and pixel points in each column in the simulated electron microscope image to obtain a plurality of pixel accumulation values; Determine whether there is one and only one maximum value among the plurality of pixel accumulated values; When it is determined that there is only one maximum value in the plurality of pixel accumulated values, one-dimensional matching is performed on the simulated electron microscope image and the scanning electron microscope image in the column direction and the row direction to obtain a matching result; When it is determined that there is more than one maximum value in the plurality of pixel accumulated values, two-dimensional matching is performed on the simulated electron microscope image and the scanning electron microscope image in the column direction and the row direction to obtain a matching result.

7. The registration method of circuit design layout and scanning electron microscope image according to claim 6, characterized in that: The one-dimensional matching of the simulated electron microscope image and the scanning electron microscope image in the column direction and the row direction to obtain the matching result includes: The simulated electron microscope image is shifted multiple times according to different preset shift amounts to obtain multiple simulated electron microscope shift images; The similarity between each simulated electron microscope offset image and the scanning electron microscope image is calculated using a first similarity calculation method to obtain a plurality of one-dimensional matching correlation values; A matching result is obtained based on the multiple one-dimensional matching correlation values.

8. The registration method of circuit design layout and scanning electron microscope image according to claim 7, characterized in that: The first similarity calculation method is used to calculate the similarity between each simulated electron microscope offset image and the scanning electron microscope image, and obtain multiple one-dimensional matching correlation values, including: For each simulated EM migration image, perform the following steps: Accumulating pixel values ​​of each row and each column of pixels in the simulated electron microscope offset image respectively to obtain a plurality of first row pixel accumulation values ​​and a plurality of first column pixel accumulation values; Accumulating pixel values ​​of each row and each column of the scanning electron microscope image to obtain a plurality of second row pixel accumulation values ​​and a plurality of second column pixel accumulation values; Calculate the product of each first row pixel accumulation value and the corresponding second row pixel accumulation value respectively to obtain a plurality of first products; Calculate the product of each first column pixel accumulation value and the corresponding second column pixel accumulation value to obtain a plurality of second products; The sum of the plurality of first products and the plurality of second products is calculated to obtain correlation values ​​of each simulated electron microscope offset image, so as to obtain a plurality of one-dimensional matching correlation values.

9. The registration method of circuit design layout and scanning electron microscope image according to claim 6, characterized in that: The performing two-dimensional matching of the simulated electron microscope image and the scanning electron microscope image in the column direction and the row direction to obtain a matching result includes: The simulated electron microscope image is shifted multiple times to obtain multiple simulated electron microscope shifted images; The similarity between each simulated electron microscope offset image and the scanning electron microscope image is calculated using a second similarity calculation method to obtain a plurality of two-dimensional matching correlation values; A matching result is obtained based on the multiple two-dimensional matching correlation values.

10. The registration method of circuit design layout and scanning electron microscope image according to claim 9, characterized in that: The second similarity calculation method is used to calculate the similarity between each simulated electron microscope offset image and the scanning electron microscope image, and obtain multiple two-dimensional matching correlation values, including: For each simulated EM migration image, perform the following steps: respectively calculating the product of the pixel value of each pixel point in the simulated electron microscope offset image and the pixel value of the corresponding pixel point in the scanning electron microscope image to obtain a plurality of third products; The sum of the plurality of third products is calculated to obtain correlation values ​​of the respective simulated electron microscope offset images, thereby obtaining a plurality of two-dimensional matching correlation values.

11. The registration method of circuit design layout and scanning electron microscope image according to claim 5, characterized in that: The obtaining of a matching result based on the multiple correlation values ​​includes: Compare each correlation value with a preset threshold value to obtain a comparison result; Determine whether the comparison result has a correlation value not less than a preset threshold; In the case where it is determined that the comparison result has a correlation value not less than a preset threshold, determining a corresponding offset based on a maximum value among the correlation values ​​not less than the preset threshold to obtain a matching result; When it is determined that the comparison result does not have a correlation value that is not less than a preset threshold, the matching result is obtained as a matching failure.

12. A device for registering a circuit design layout and a scanning electron microscope image, characterized in that: include: An acquisition module, used to acquire a first circuit design layout and a scanning electron microscope image, wherein the first circuit design layout includes a plurality of first graphics; A generating module, used for performing image processing on each first graphic in the first circuit design layout, generating a scanning electron microscope simulation graphic corresponding to each first graphic, so as to obtain a simulated electron microscope image; A determination module, configured to determine an actual matching range in the simulated electron microscope image based on the distribution of each scanning electron microscope simulated image in the simulated electron microscope image; The matching module is used to register the simulated electron microscope image with the scanning electron microscope image within the actual matching range to obtain a matching result.

13. An electronic device, characterized in that: The electronic device includes: at least one processor; a memory connected to the at least one processor; The memory stores instructions that can be executed by the at least one processor, and the at least one processor implements the circuit design layout and scanning electron microscope image registration method described in any one of claims 1 to 11 by executing the instructions stored in the memory.

14. A machine-readable storage medium having instructions stored thereon, characterized in that: When the instruction is executed by a processor, the processor is configured to execute the registration method of a circuit design layout and a scanning electron microscope image according to any one of claims 1 to 11.

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