Topological link optimization method and device, electronic equipment and medium

Abstract

The invention discloses a topological link optimization method and device, electronic equipment and a medium, which are used for autonomously simulating and optimizing a topological link of a low-speed signal, saving the cost and improving the optimization efficiency. The method comprises the following steps: extracting first topological information of a topological link of a target signal; adding component parameters in the first topological information to generate second topological information, and reconstructing a topological link of the target signal by using the second topological information; and optimizing the reconstructed topological link by adjusting component parameters in the second topological information to obtain an optimized topological link of the target signal.

Description

Technical Field

[0001] The present invention relates to the field of data processing technology, and in particular to a topology link optimization method, device, electronic equipment and medium. Background Art

[0002] There are many low-speed signals in the hardware system that are used to communicate with peripheral devices, and their speed is generally between 100K and 100M. In PCB design, topology describes the connection relationship between components, the routing sequence and routing structure of the routing, etc. Although the speed of low-speed signals is not high, due to the mismatch between the internal resistance of the chip and the impedance of the PCB transmission line, the low-speed signal will be reflected and crosstalked during the transmission process, which will lead to the degradation of signal quality. Therefore, it is necessary to simulate and optimize the topological link of the low-speed signal.

[0003] Currently, the simulation of the topological link of low-speed signals requires users to manually adjust parameters for optimization, which is time-consuming and labor-intensive. Not only is the cost of topological link optimization high, but it is also inefficient. Summary of the invention

[0004] The present invention provides a topology link optimization method, device, electronic device and medium, which are used to autonomously simulate and optimize the topology link of low-speed signals, save costs and improve optimization efficiency.

[0005] In a first aspect, an embodiment of the present invention provides a method for optimizing a topology link, the method comprising:

[0006] Extracting first topology information of a topology link of a target signal;

[0007] Adding component parameters to the first topology information to generate second topology information, and using the second topology information to rebuild the topology link of the target signal;

[0008] The reconstructed topology link is optimized by adjusting the component parameters in the second topology information to obtain the optimized topology link of the target signal.

[0009] The autonomous optimization method provided in this embodiment adds adjustable component parameters to the topology information of the original topology link, and reconstructs and optimizes the original topology link by autonomously adjusting the component parameters, thereby realizing autonomous adjustment to optimize the topology structure, saving topology optimization time, improving topology optimization efficiency, saving labor costs, and being universal, simpler and more convenient.

[0010] As an optional implementation manner, the topology link includes at least one sub-topology link corresponding to a protocol type; and the first topology information of the topology link for extracting the target signal includes:

[0011] According to the position relationship and routing information of the components in each sub-topology link, each sub-topology link is split into a trunk link and at least one branch link connected to the trunk link;

[0012] Extracting topology information of each sub-topology link according to the connection relationship between the trunk link of each sub-topology link and the branch link;

[0013] A topology information table is constructed according to the topology information of each sub-topology link, and the topology information table is determined as the first topology information of the topology link of the target signal.

[0014] This embodiment represents the extracted topology information by constructing a topology information table, and then generates second topology information. The topology information is stored in the form of a table, and the topology structure is represented by the relationship between rows and columns, which can make the adjustment of component parameters simpler and more convenient.

[0015] As an optional implementation, it includes:

[0016] Add the string resistance value and / or the routing length to the first topology information to generate second topology information;

[0017] By adjusting the string resistance value and / or the routing length in the second topology information, the reconstructed topology link is optimized to obtain the optimized topology link of the target signal.

[0018] This embodiment optimizes the topological link by adding the resistance value of the series resistance and the length of the wiring. By adjusting the resistance value of the series resistance and the length of the wiring, the topological link can be autonomously adjusted. Only the resistance value or the length of the wiring needs to be adjusted, which can minimize the changes to the optimized circuit and improve the optimization efficiency of the topological link.

[0019] As an optional implementation manner, adding component parameters to the first topology information to generate second topology information, and using the second topology information to reconstruct the topology link of the target signal includes:

[0020] Adding the resistance value of the series resistor to the first topology information generates the second topology information, and using the second topology information to reconstruct the topology link of the target signal; wherein the reconstructed topology link includes at least one sub-topology link corresponding to a protocol type;

[0021] The series resistance is located on the routing lines of any two devices in the sub-topology link; and / or,

[0022] The series resistance is located on the trunk routing corresponding to the intersection node between the trunk routing and the branch routing in the sub-topology link, and the trunk routing corresponding to the intersection node represents the trunk routing before the target signal is transmitted to the branch routing.

[0023] The series resistance added in this embodiment is set on the routing of any two devices in the sub-topology link, or on the main routing corresponding to the node where the main routing and the branch routing intersect, which can ensure that the changes to the optimized circuit are minimized while achieving the optimization adjustment of the topology link, and at the same time can improve the optimization efficiency as much as possible and reduce the optimization cost.

[0024] As an optional implementation manner, the optimizing the reconstructed topology link by adjusting the component parameters in the second topology information to obtain the optimized topology link of the target signal includes:

[0025] Simulating the reconstructed topology link to obtain a simulation signal;

[0026] According to the signal quality of the simulation signal, the component parameters in the second topology information are iteratively adjusted until the number of iterations reaches a threshold or the signal quality meets a preset condition, and the adjustment is stopped to obtain the optimized topology link.

[0027] This embodiment adjusts the parameters of components through iterative adjustment, thereby ensuring that the signal quality of the optimized topology link meets the preset conditions, and realizes autonomous topology optimization through iterative adjustment, thereby improving the optimization efficiency.

[0028] As an optional implementation manner, the signal quality of the simulation signal is determined in the following manner:

[0029] Determining a data sequence according to a corresponding relationship between time and amplitude included in the simulation signal;

[0030] According to the variation rule of the simulation signal waveform, the data sequence is segmented to obtain a plurality of data segments;

[0031] The signal quality of the simulation signal is determined according to whether the characteristic parameters of the data sequences in different data segments meet the corresponding quality standards.

[0032] This embodiment uses a method of segmenting signal waveform data to determine whether the signal quality meets the standard, thereby making the determination of signal quality simpler and easier to implement while ensuring the accuracy of the determination.

[0033] As an optional implementation manner, the component parameters to be adjusted in the second topology information are determined in the following manner:

[0034] Determine the components to be adjusted according to the predefined priority order of the components;

[0035] According to the components to be adjusted, the parameters of the components to be adjusted in the second topology information are determined, and the reconstructed topology link is optimized by adjusting the component parameters.

[0036] This embodiment adjusts components in sequence based on priority setting, thereby optimizing topology links, which can effectively shorten the time of topology optimization and improve the efficiency of topology optimization.

[0037] In a second aspect, an embodiment of the present invention provides a topology link optimization device, including:

[0038] A topology extraction unit, used to extract first topology information of a topology link of a target signal;

[0039] A topology reconstruction unit, configured to add component parameters to the first topology information to generate second topology information, and to use the second topology information to reconstruct a topology link of the target signal;

[0040] The topology optimization unit is used to optimize the reconstructed topology link by adjusting the component parameters in the second topology information to obtain the optimized topology link of the target signal.

[0041] In a third aspect, an embodiment of the present invention further provides an electronic device, including a processor and a memory, wherein the memory is used to store a program executable by the processor, and the processor is used to read the program in the memory and perform the following steps:

[0042] Extracting first topology information of a topology link of a target signal;

[0043] Adding component parameters to the first topology information to generate second topology information, and using the second topology information to rebuild the topology link of the target signal;

[0044] The reconstructed topology link is optimized by adjusting the component parameters in the second topology information to obtain the optimized topology link of the target signal.

[0045] In a fourth aspect, an embodiment of the present invention further provides a computer storage medium on which a computer program is stored, and when the program is executed by a processor, it is used to implement the steps of any one of the methods described in the first aspect above.

[0046] In a fifth aspect, the present application provides a computer program product, comprising: a computer program code, when the computer program code is run on a computer, the computer executes any one of the methods described in the first aspect.

[0047] These and other aspects of the present application will be more clearly understood in the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0049] Figure 1 A flowchart of a topology link optimization method provided by an embodiment of the present invention;

[0050] Figure 2 A schematic diagram of a topology link provided in an embodiment of the present invention;

[0051] Figure 3 A schematic diagram of an optimized topology link provided by an embodiment of the present invention;

[0052] Figure 4 A schematic diagram of a topology reconstruction process provided by an embodiment of the present invention;

[0053] Figure 5 A flowchart of a low-speed signal simulation and optimization method provided by an embodiment of the present invention;

[0054] Figure 6 A flowchart of a method for implementing topology optimization provided by an embodiment of the present invention;

[0055] Figure 7 A waveform segmentation schematic diagram under an ideal state provided by an embodiment of the present invention;

[0056] Figures 8A-8B A schematic diagram of a problematic waveform provided by an embodiment of the present invention;

[0057] Figures 9A-9C A timing relationship diagram provided for an embodiment of the present invention;

[0058] Fig.10 A flow chart of a method for determining signal quality provided by an embodiment of the present invention;

[0059] Fig.11 A schematic diagram of a topology link optimization device provided by an embodiment of the present invention;

[0060] Fig.12 A schematic diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0061] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0062] In the embodiments of the present invention, the term "and / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent three situations: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0063] The application scenarios described in the embodiments of the present invention are intended to more clearly illustrate the technical solutions of the embodiments of the present invention, and do not constitute a limitation on the technical solutions provided by the embodiments of the present invention. It is known to those skilled in the art that with the emergence of new application scenarios, the technical solutions provided by the embodiments of the present invention are also applicable to similar technical problems. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0064] Before introducing the topology link optimization method provided in the embodiment of the present application, in order to facilitate understanding, the technical background of the embodiment of the present application is first introduced in detail below.

[0065] In hardware systems, especially in computer networks and PCB (Printed Circuit Board) design, the concept of topology is widely used. The topology in computer networks mainly includes the following types: bus topology, which is a physical structure with shared access. All devices are directly connected to the public bus through the corresponding hardware interface. The channel utilization rate is high, but the number of connected nodes should not be too many, and the failure of the bus itself may cause the system to crash; star topology, which is a radial interconnection structure with a central node as the center and several peripheral nodes connected. This structure is easy to install, simple in structure, and easy to maintain and manage, but the failure of the central node may cause the entire network to fail to work; ring topology, all sites are connected to each other in series to form a closed structure. This structure is suitable for real-time control LAN systems; tree topology, similar to an inverted tree, with the root at the top and branches below. This topology is easy to expand and isolate faults, but the entire network is highly dependent on the root; hybrid topology, combining the advantages of the above basic topologies to form a more complex connection form to improve the performance and reliability of the network.

[0066] In PCB design, topology refers to the connection relationship between components, as well as the wiring sequence and wiring structure of the routing, the location and resistance of the series resistance, etc., which also follow the principles and characteristics of the above basic topology. In PCB design, choosing the right topology is crucial to solving the transmission line effect, ensuring signal integrity and system performance. Common topologies include point-to-point, daisy chain, star, remote cluster, etc. Each structure has its specific advantages and applicable scenarios. Among them, the point-to-point topology is simple, the impedance characteristics of the entire network are easy to control, and the timing relationship is also easy to control. It is common in high-speed bidirectional transmission signal lines. The daisy chain topology is the simplest structure to achieve multi-load interconnection, and the PCB routing is simple. In the star topology, although the PCB wiring is more complicated and the impedance is not easy to control, the timing is easier to control, as long as the wiring length from the driver end to each receiving end is consistent. The star topology requires a good signal matching design at the receiving end and eliminates terminal reflections. The remote cluster topology can be regarded as a variation of the star topology. It requires that the PCB wiring length from the driver end to the cross T point be much longer than the PCB wiring length from the cross T point to each receiving end. At the same time, the distance from the cross T point to each receiving end should be as equal as possible. The signal matching design can be done at the cross T point.

[0067] There are many low-speed signals in the hardware system for communicating with peripheral devices, and their speed is generally between 100K and 100M. Common low-speed signal protocols include: I2C (Inter-Integrated Circuit) protocol, NCSI (Network Controller Sideband Interface) protocol, eMMC (embedded Multi Media Card) communication protocol, etc. Low-speed signals mainly include I2C, SMBUS (System Management Bus), UART / RS232 (Universal Asynchronous Receiver / RS-232 Standard Interface), SPI (Serial Peripheral Interface), JTAG (Joint Test Action Group), LPC (Linear Predictive Coding). These signal types have their own characteristics and uses. For example, the I2C bus supports speeds up to 20M, but the protocol stipulates that the maximum capacitive load that a bus can accept is 470uF, and generally no more than ten devices. SMBUS is based on the I2C bus specification, but there are some differences. UART / RS232 involves level standards and signal classification, and is used for multi-device processing. SPI involves level standards and signal classification, as well as multi-device processing. JTAG, LPC and other signal types also have their own characteristics and uses. These low-speed signal types play an important role in electronic communication and data processing. Each of them is complex or simple, and needs to be selected and used according to specific application scenarios and needs.

[0068] The standards for low-speed signals involve many aspects, including the frequency, transmission rate, rising edge / falling edge time of the signal, etc. These standards jointly define the characteristics of low-speed signals to ensure their stable and reliable transmission in the circuit. The effective frequency of a low-speed signal is not a fixed value, but is related to the trace length of the signal and the effective wavelength of the signal. When the trace length is greater than 1 / 6 of the effective wavelength of the signal, the signal is defined as a high-speed signal; otherwise, it is a low-speed signal. When the signal transmission rate is less than 1Gbps, the signal is considered a low-speed signal. If the rising edge / falling edge time of the signal is greater than 500ps, the signal is considered a low-speed signal. Low-speed signals are not prone to signal distortion during transmission, which requires the design and manufacture of low-speed circuit boards to have basic accuracy and stability.

[0069] Common topology types for low-speed signals include point-to-point, daisy chain, T-type topology, etc. The common topology for high-speed signals is point-to-point, and high-speed signals do not pay attention to the waveform of the signal during topology optimization. The topology of low-speed signals is usually more complex than that of high-speed signals, and low-speed signals need to pay attention to the waveform of the signal during topology optimization, such as whether the level meets the requirements. Therefore, the optimization of the topology of high-speed signals cannot be directly applied to low-speed signals, and it is necessary to provide targeted topology optimization solutions for the complex topology of low-speed signals.

[0070] On the one hand, no matter how complex the low-speed signal topology is, there are only two devices communicating at the same time. Although the signal rate is not high, due to the mismatch between the chip internal resistance and the PCB transmission line impedance, the signal will be reflected and crosstalked during the transmission process, which will lead to the degradation of signal quality, such as the amplitude exceeding the limit, the rising and falling edges are non-monotonic, and the timing does not meet the requirements. The service life of the load chip and whether the signal can be correctly identified and the data transmission can be completed are closely related to the signal quality. Therefore, the quality of low-speed signals in the hardware system needs to be focused on and optimized. On the other hand, due to the flexibility and diversity of peripheral devices and configurations, the types, standards and topologies of low-speed signals are also varied. With the continuous updating and iteration of high-performance hardware devices, the design requirements of high-speed signals are getting higher and higher, which leads to designers often focusing more on high-speed signals when facing limited design time, while ignoring the quality optimization of low-speed signals. In order to ensure the efficiency and comprehensiveness of the design, a method that can quickly extract, simulate and optimize low-speed signals is needed. Current simulation platforms, such as cadence, hyperlink, ADS and other software, have provided functions for extracting signal topology, simulating and optimizing signals. However, the setting of simulation parameters and modification of optimization parts need to be manually set and optimized, and the judgment of simulation results needs to be made by designers. For example, it is necessary to manually modify parameters at the corresponding position of the topology or add series resistance routing, etc. When faced with a large number of low-speed signals that need to be simulated and optimized, it is usually impossible to consider them thoroughly due to cumbersome operations and time issues.

[0071] The simulation methods provided by the existing low-speed signal simulation platform cannot perform fast and autonomous simulation. Topology extraction, model import, simulation and optimization, each step is separate, and each step requires manual setting and operation, which is time-consuming and labor-intensive. The signal protocols, chip models, and topological layouts used by each hardware system are different, resulting in diversity and uncertainty in the topology extraction, simulation, and optimization processes, which require the intervention of designers. Existing simulation methods are based on topologies extracted directly from PCB files. If there are signal quality problems in the topology and the routing length, string resistance position, and resistance value need to be optimized, the simulation platform cannot be modified and added autonomously, and the participation of designers is also required. Faced with a large number of low-speed signal topology optimization is time-consuming and labor-intensive.

[0072] In order to solve the above technical problems, an embodiment of the present application provides a topology link optimization method for solving the problem of inefficiency in manually setting the topology optimization of low-speed signals. The core idea is to add adjustable component parameters to the topology information of the original topology link, and rebuild the topology link of the low-speed signal. The reconstructed topology link is optimized by autonomously adjusting the component parameters, thereby realizing autonomous adjustment to optimize the topology structure of the low-speed signal.

[0073] It should be noted that the "first" and "second" in this embodiment are only used for distinction and do not indicate the order, that is, the "first topology information" and "second topology information" in this embodiment are both topology information extracted from the topology link, and "first" and "second" are only used to distinguish the topology information of different topology links, and do not indicate that there is a chronological order between the topology information.

[0074] like Figure 1 As shown, the implementation process of the topology link optimization method provided in this embodiment is as follows:

[0075] Step 100: extracting first topology information of a topology link of a target signal;

[0076] Optionally, the target signal in this embodiment includes but is not limited to low-speed signals, high-speed signals, etc., and can be autonomously adjusted and optimized for the topological link of any signal. This embodiment does not impose too many restrictions on the target signal.

[0077] In some embodiments, the first topology information of the topology link of the target signal is extracted in the following manner:

[0078] According to the circuit schematic and PCB file, the first topology information of the topological link of the target signal is extracted. In implementation, the circuit schematic is used to provide auxiliary functions, such as extracting the position number, pin number, and connection relationship between components in the topological link; the PCB file can not only extract the above information, but also extract information such as the length of the trace, the impedance value of the trace, the size and position of the via, etc. Since the circuit schematic and PCB file contain the topological structure of the low-speed signal and the high-speed signal, when extracting the first topology information of the topological link of the target signal, the first topology information of the topological link of the target signal can be extracted according to the communication protocol used for the transmission of the target signal, wherein different communication protocols are represented as different trace names in the topological link, and the communication protocol used by the target signal is determined by the trace name, thereby extracting the first topology information of the topological link of the target signal.

[0079] In some embodiments, the topology link includes at least one sub-topology link corresponding to a protocol type; the first topology information of the topology link of the target signal is extracted specifically by the following steps:

[0080] Step 1) splitting each sub-topology link into a trunk link and at least one branch link connected to the trunk link according to the position relationship and routing information of components in each sub-topology link;

[0081] This splitting method can split a complex topological link into multiple simple topological links. The topological link can be split through the communication protocol to obtain multiple sub-topological links. Each sub-topological link includes at least one trunk link, or at least one trunk link and a branch link connected to the trunk link. By disassembling the topological link, the complete topological link can be split into multiple basic link units, which is convenient for optimizing the topological link. Describing the topological types of different links in this way is more scalable and universal.

[0082] Optionally, when splitting each sub-topology link, the splitting is based on the topology name, that is, each sub-topology link is split into topology links corresponding to different topology names. For example, there may be multiple I2C topology links in a sub-topology link, but multiple I2C topology links can be split according to the topology name, where the naming format of the topology name, such as I2C_1, represents a topology name. In this embodiment, different topology links under the same communication protocol type can be distinguished according to the topology name, so that the sub-topology links corresponding to the same protocol type are disassembled according to the topology name.

[0083] It should be noted that the topology type and the communication protocol type in this embodiment are not in a one-to-one correspondence. For example, the signal of the I2C protocol may use a daisy chain or a star topology; the SPI protocol and the NCSI protocol may also use a daisy chain topology.

[0084] Step 2) extracting topology information of each sub-topology link according to the connection relationship between the trunk link of each sub-topology link and the branch link;

[0085] During implementation, after splitting the topology link into multiple sub-topology links, the corresponding topology information is extracted based on the parameter values ​​of components and the length of the routing on the trunk link and branch links in each sub-topology link.

[0086] Step 3) construct a topology information table according to the topology information of each sub-topology link, and determine the topology information table as the first topology information of the topology link of the target signal.

[0087] In implementation, after extracting the topological information in each sub-topological link, the complex topological link can be standardized and structured by constructing a topological information table, and the component parameters and routing length and other information in each sub-topological link can be described in the form of a trunk link + branch link, thereby obtaining the first topological information of the target signal. The first topological information in this embodiment is a table-structured topological information, which is a structured topological information table obtained by splitting and organizing the complex topological link, which can well integrate different topological types, solve the topological optimization problems of different topological types, simplify and format the complex optimization problems, and has strong versatility.

[0088] Optionally, this embodiment can split each sub-topology link according to the routing order of the target signal transmission according to the sub-topology links corresponding to different protocol types in the topology link of the target signal, obtain a trunk link and at least one branch link connected to the trunk link, extract the topology information of the trunk link and the branch link in each sub-topology link, and obtain the first topology information. Based on the positions and parameter values ​​of the components in the extracted trunk link and branch link, as well as the routing length, routing order and other information, a topology information table is generated in a fixed format and stored. It should be noted that some empty tables can be reserved in the topology information table on the trunk link and / or branch link for subsequent addition of component parameters, so as to rebuild and optimize the topology link of the target signal.

[0089] Optionally, in this embodiment, the first topology information of the topology link of the target signal extracted is expressed as the topology information of the original topology link of the target signal, that is, the topology information of the topology link before optimization. After extracting the first topology information of the topology link of the target signal, the first topology information can also be organized into a topology information table according to the sequence and length of the routing between components, as shown below:

[0090] Table 1 Topology information table

[0091]

[0092]

[0093] In the example of the above table, the first five columns represent the basic information of the topology link, indicating the first device on the trunk of the topology link, and each row corresponding to the topology name is a branch on the trunk. In PCB design, there may be multiple topologies using the same protocol, but there will be distinctions, such as the I2C protocol, but the topology names will have similar names such as I2C_1, I2C_2, I2C_3, etc. Figure 2 As shown, this embodiment also provides a topology link schematic diagram, and a topology link is constructed based on the topology information corresponding to the first protocol type and the topology name in the above Table 1, that is, a topology link is constructed according to the first 5 rows of information in Table 1. It should be noted that the above table is only an example of a topology information table, and other design methods also belong to the protection scope of the present invention. The present invention does not impose too many restrictions on the number of rows and columns of the table, and the specific content in each cell, and can be defined according to the actual circuit routing characteristics.

[0094] The topology information table in this embodiment has two characteristics. One characteristic is that the structure of the topology information table can integrate various topological structures. Through the topology information table, the topological information of topological links of different topological types can be represented, and various topological structures can be integrated and summarized to unify the topological types of all low-speed signals. For common topological types, such as daisy chain, T-type topology, and one-to-one topology, this table can be used to represent them. The only difference is that the number of information rows occupied by the same topological name is different. Another characteristic is that adjustable component parameters can be added to the structure of the topology information table. Since the topological information of the low-speed signal directly extracted from the PCB file will not fill the entire topological information table, empty cells are reserved in the topological information table, and the adjusted parameter values ​​are filled in for the component parameters to be added, and 0 or empty is filled in the corresponding cells for the parts to be deleted. Multiple topologies can be formed according to the content filled in and deleted, thereby optimizing the topological link of the target signal. The topological information table of this embodiment is the key to signal simulation and optimization. The purpose of topological optimization is achieved by modifying the component parameters in the table. The design structure of the topological information table helps to generate the second topological information according to the first topological information, thereby simplifying the topological reconstruction.

[0095] In implementation, since there are only two devices interacting at the same time in the topological link of the low-speed signal, the topological link can be split according to the interaction relationship, and then the topological information of each segment can be summarized into a topological information table according to the relationship between the master and the slave (such as active device A is the host and active device B is the slave). There is an unavailable area in the topological information table, and the corresponding data can be filled in any other position. The extracted topological information is filled in the corresponding cell according to the corresponding routing sequence. If the cell has no corresponding topological information, fill in 0 or leave it empty. It should be noted that the concept of master and slave in this embodiment is only to illustrate the interaction relationship between the two devices in the topological link of the low-speed signal, and does not limit the device to a host or a slave. The device in this embodiment can also be of other types as long as it meets the requirement that only two devices are interacting at the same time. This embodiment does not impose too many restrictions on this.

[0096] Optionally, this embodiment can also determine the topology type of the topology link of the target signal according to the number of branch lines, the length of the trunk line, and the length of the branch lines of the topology link corresponding to the same protocol type and the same topology name. When optimizing the topology link of the target signal, the topology link can be optimized by adding component parameters based on the existing topology link, or the topology type of the topology link can be modified to optimize the topology link. This embodiment does not impose too many restrictions on the specific optimization method.

[0097] Optionally, this embodiment may also split the topology link into a one-to-one topology structure according to the first topology information, that is, one active device corresponds to one active device, and may also form multiple topology information tables according to the one-to-one topology structure obtained by splitting. For example, the sub-topology link corresponding to the same protocol type in Table 1 is split into multiple topology links, such as splitting to obtain a topology link from an active device A to an active device B.

[0098] The protocol type in this embodiment refers to the type of communication protocol used for target signal transmission. For example, the protocol type of low-speed signal includes but is not limited to I2C, NCSI, eMMC, etc.

[0099] Step 101: Add component parameters to the first topology information to generate second topology information, and use the second topology information to rebuild the topology link of the target signal;

[0100] Optionally, the components in this embodiment include but are not limited to series resistors, routing, etc., and the component parameters in this embodiment include but are not limited to series resistor values, routing length, etc.

[0101] In implementation, after the first topology information is extracted, component parameters, such as series resistance value, routing length and other information, may be added to the topology information table to generate second topology information, thereby reconstructing the topology link.

[0102] Step 102: Optimize the reconstructed topology link by adjusting the component parameters in the second topology information to obtain the optimized topology link of the target signal.

[0103] In some embodiments, the added components include series resistance and / or routing; the series resistance value and / or routing length are added to the first topology information to generate second topology information; the reconstructed topology link is optimized by adjusting the series resistance value and / or routing length in the second topology information to obtain the optimized topology link of the target signal.

[0104] During implementation, adjustable string resistance, routing, etc. can be added to the first topology information, wherein adding string resistance causes the least change to the topology link, and is more convenient to implement during later reconstruction and topology optimization. In addition to optimizing the topology link by adding or deleting string resistance, this embodiment can also modify the structure of the topology link by modifying the routing sequence and routing length, such as modifying the length of the trunk routing or the length of the branch routing, thereby optimizing or changing the topology type of the topology link, providing a more comprehensive topology optimization solution, and improving the performance of topology optimization.

[0105] In some embodiments, in order to minimize circuit changes and optimize performance, a series resistor can be added between the routing of any two components; or, a series resistor can be added to the main routing corresponding to the intersection node between the main routing and the branch routing, wherein the main routing corresponding to the intersection node represents the main routing before the target signal is transmitted to the branch routing.

[0106] In some embodiments, the topological link of the target signal is reconstructed using the second topology information in the following manner:

[0107] Adding the resistance value of the series resistor to the first topology information generates the second topology information, and using the second topology information to reconstruct the topology link of the target signal; wherein the reconstructed topology link includes at least one sub-topology link corresponding to a protocol type;

[0108] The series resistance is located on the routing lines of any two devices in the sub-topology link; and / or,

[0109] The series resistance is located on the trunk routing corresponding to the intersection node between the trunk routing and the branch routing in the sub-topology link, and the trunk routing corresponding to the intersection node represents the trunk routing before the target signal is transmitted to the branch routing.

[0110] In implementation, the first topology information includes at least one sub-topology link of a protocol type. For a sub-topology link of the same protocol type, a series resistor may be added at the following positions of the sub-topology link:

[0111] Case 1) Add a series resistor to the routing of any two devices in the sub-topology link, and optimize the topology link by adjusting the resistance value of the series resistor;

[0112] Case 2) A series resistor is added to the trunk line corresponding to the intersection node of the trunk line and the branch line in the sub-topology link, and the topology link is optimized by adjusting the resistance value of the series resistor.

[0113] The topological link is optimized by adding the string resistance as mentioned above. Since the first topological information is a topological information table in a tabular form, it is only necessary to add the string resistance value in the cell corresponding to the position where the string resistance is to be added in the sub-topological link to generate the second topological information. Therefore, when the topological link is reconstructed and simulated, the reconstructed topological link is optimized by adjusting the size of the added string resistance value.

[0114] This embodiment generates second topology information based on the topology information table of the first topology information. For the convenience of description, the generated second topology information is named as a topology optimization information table, that is, the series resistance value is added to the topology information table to form a topology optimization information table. The topology optimization information table is the key to signal simulation and optimization. The purpose of topology optimization is achieved by modifying some parameters in the topology information table. The formation of the topology optimization information table includes a topology optimization method.

[0115] In some embodiments, parameters that are not allowed to be changed in the topology information table can also be defined. For example, in order to minimize the change of the topology link, the routing impedance on the trunk link can be set not to be changed, the routing length of the trunk link and the branch length of the branch link can not be changed, and only the series resistance value on the trunk link or the series resistance value on the branch link can be modified. Modification of the content of different cells can form multiple different topological structures.

[0116] The topology optimization information table and the topology information table are exactly the same in form, the only difference is that the contents of each cell may be different. Before the first simulation, the contents of the topology optimization information table and the topology information table are exactly the same, that is, the topology link reconstructed during the first simulation is the original topology link extracted from the PCB file. Afterwards, if the signal quality does not meet the standard during the simulation, the topology optimization process is entered, and the resistance value of the series resistance added in the topology optimization information table is adjusted. At this time, the content of the topology optimization information table will change. This embodiment also provides a topology optimization information table for the second topology information, as shown in the following table, in which the resistance value of the series resistance B is modified on the basis of the topology information table, that is, the resistance value of the series resistance B is changed from 0 to a resistance value greater than 0, thereby forming a new topology structure.

[0117] Table 2 Topology optimization information table

[0118]

[0119] In the above table example, the first five columns represent the basic information of the topology link, and the contents of the first five columns in the topology optimization information table and the first five columns in the topology information table are the same. Figure 3 As shown, this embodiment also provides a schematic diagram of optimizing a topology link, and constructs a topology link based on the topology information corresponding to the first protocol type in the above Table 2, that is, constructs a topology link according to the first 5 rows of information in Table 2. Among them, on the basis of the original topology link, taking the sub-topology link corresponding to the first protocol type as an example, a series resistance B is added to the trunk line corresponding to the intersection node of the trunk line and the branch line in the sub-topology link, and the topology link is optimized by adjusting the resistance values ​​of the series resistance A, the series resistance B and the series resistance C.

[0120] During implementation, each part of the topology link is built in sequence according to the information in the topology optimization information table. Figure 4As shown, this embodiment provides a schematic diagram of a topology reconstruction process, and the specific implementation steps are as follows:

[0121] Step 400: Obtain a topology optimization information table of second topology information;

[0122] Step 401, read the first row of topology information in the topology optimization information table;

[0123] Step 402: Select a corresponding component model and assign parameter values ​​in corresponding cells of the component model;

[0124] Among them, according to each row of topology information in the topology optimization information table corresponding to the second topology information, the corresponding component model is called, and the parameter value in the corresponding cell of the component model is assigned; the component model includes but is not limited to: active devices, series resistance, routing, etc.

[0125] Step 403, topologically connecting each component model according to the routing sequence;

[0126] Step 404: read the next row of topology information in the topology optimization information table;

[0127] Step 405: Determine whether the protocol name and the topology name are the same, if yes, execute step 402, otherwise execute step 406;

[0128] Step 406: stop reading the table and obtain the reconstructed topology link;

[0129] During implementation, for each row in the topology optimization information table, it is necessary to determine whether the protocol name and topology name are consistent. If they are consistent, the identical redundant parts (i.e., the first six columns of the table) need to be removed when creating the topology, and the non-identical parts are built into a topology in sequence, and then the next row of topology information in the topology optimization information table is read; if the protocol name and topology name are inconsistent, stop reading the table.

[0130] Step 407: Select corresponding simulation parameters according to the protocol name, and simulate the reconstructed topology link.

[0131] During implementation, corresponding simulation parameters are selected according to the protocol name in the table, including signal rate, random bit sequence, delay between different signals, simulation accuracy step, etc., and the topology link is simulated using the simulation parameters.

[0132] After the topology link is rebuilt and simulated, if the simulation result does not meet the quality standard, it is necessary to enter the process of component parameter optimization. There are many methods for parameter optimization, such as those based on mathematical formulas, machine learning and other algorithms. Optionally, the parameter optimization method provided in this embodiment includes but is not limited to grid search, random search, genetic algorithm tuning, etc.

[0133] Optionally, this embodiment also provides a link optimization method, which is mainly based on the experience of low-speed signal topology optimization and can optimize low-speed signal problems in a targeted manner, thereby reducing the time used for optimization.

[0134] In some embodiments, the reconstructed topology link is optimized by the following steps:

[0135] Simulating the reconstructed topology link to obtain a simulation signal;

[0136] According to the signal quality of the simulation signal, the component parameters in the second topology information are iteratively adjusted until the number of iterations reaches a threshold or the signal quality meets a preset condition, and the adjustment is stopped to obtain the optimized topology link.

[0137] In the implementation, after obtaining the second topology information, the topology link is reconstructed according to the second topology information, the reconstructed topology link is simulated, and the topology link is optimized according to the signal quality of the simulation signal. When the signal quality obtained by the current iterative adjustment does not meet the preset conditions, the component parameters are adjusted for the next iteration until the number of iterations reaches a threshold or the signal quality meets the preset conditions, and the adjustment is stopped to obtain the current optimized topology link.

[0138] like Figure 5 As shown, this embodiment provides an implementation process of a low-speed signal simulation and optimization method, which is specifically as follows:

[0139] Step 500: extracting first topology information of a target signal;

[0140] Step 501: Create a topology information table according to first topology information;

[0141] Step 502: Add component parameters to the topology information table to generate a topology optimization information table;

[0142] The topology optimization information table is a tabular information representation of the second topology information.

[0143] Step 503: Reconstruct the topology link according to the topology optimization information table;

[0144] Step 504: simulate the reconstructed topology link and output a simulation signal;

[0145] Step 505, determine whether the signal quality of the simulation signal meets the preset conditions, if so, execute step 506, otherwise execute step 507;

[0146] Step 506: store the topology link;

[0147] Step 507, determine whether the current number of iterations reaches the threshold, if yes, execute step 508, otherwise execute step 509;

[0148] Step 508: Manually adjust the topology link and execute step 503;

[0149] Step 509 : adjust the component parameters in the topology optimization information table, update the topology optimization information table, and execute step 503 .

[0150] This embodiment uses the circuit schematic and PCB file to extract the low-speed signal topology, and splits and summarizes the topology information into a topology information table for storage. A topology optimization information table is formed by adjusting the values ​​of certain parts at appropriate positions in the topology information table, and the simulation topology is rebuilt in the simulation software based on the topology optimization information table for simulation, and the topology optimization information table is continuously optimized and the topology and simulation are rebuilt until the end condition is met.

[0151] In some embodiments, during each iteration of adjustment, it is necessary to select the component parameters to be adjusted this time from the adjustable component parameters, and the component parameters to be adjusted are determined in the following manner:

[0152] Determine the components to be adjusted according to the predefined priority order of the components;

[0153] According to the components to be adjusted, the parameters of the components to be adjusted in the second topology information are determined, and the reconstructed topology link is optimized by adjusting the component parameters.

[0154] During implementation, first, one component parameter is selected from multiple component parameters in order of priority for iterative adjustment. When the signal quality meets the preset conditions during the iterative adjustment process or the number of iterations reaches a threshold, an optimized topology link is obtained at this time. When the signal quality does not meet the preset conditions during the iterative adjustment process or the number of iterations reaches a threshold, the next component parameter is selected from multiple component parameters for iterative adjustment, and so on, until the number of iterations reaches the threshold or the output signal quality meets the preset conditions.

[0155] In some embodiments, the component includes an adjustable series resistance; the reconstructed topology link includes at least one sub-topology link corresponding to a protocol type;

[0156] The priority of the adjustable series resistance on any two device routings in the sub-topology link is higher than the priority of the adjustable series resistance on the trunk routing corresponding to the intersection node of the trunk routing and the branch routing in the sub-topology link; wherein the trunk routing corresponding to the intersection node represents the trunk routing before the target signal is transmitted to the branch routing.

[0157] In implementation, the priority order of components is defined according to the degree of change to the circuit. The component with the smallest impact on the circuit change has the highest priority, and the component with the largest impact on the circuit change has the lowest priority. Figure 3 Taking the series resistance A, series resistance B and series resistance C in the example, the priority of defining the component parameters is as follows:

[0158] Priority 1: series resistance A and series resistance C, the resistance value is taken from the resistance table;

[0159] Priority 2: Series resistance B, the resistance value is taken from the resistance table.

[0160] Among them, the priority of string resistance A and string resistance C is higher than that of string resistance B. All string resistance values ​​are taken from the resistance table, which is pre-set considering the actual resistance values ​​of the actual resistances used and the topological power consumption. The string resistance values ​​included in the resistance table are set according to the actual resistance and commonly used resistance, such as 0ohm, 33ohm, 49.9ohm, etc.

[0161] According to the priority order of components, the process of optimizing the topology link is as follows:

[0162] Step a: According to the result prompt that the signal quality does not meet the standard (such as level problem, etc.), adjust the values ​​of the string resistance A and the string resistance C according to the corresponding modification rules.

[0163] For example, if the maximum value of the simulation waveform sent from active device A to active device B exceeds the standard requirements, the resistance value of string resistance A is modified; if the edge of the simulation waveform is non-monotonic, the value of string resistance C is modified. After modifying the values ​​of string resistance A and string resistance C, enter the topology reconstruction and simulation, and continuously modify the resistance values ​​of string resistance A and string resistance C until the modification rules have been tried completely (such as traversing all possible resistance values ​​or reaching the maximum number of modifications). If the signal quality problem still cannot be solved, set both string resistance A and string resistance C to 0 and enter step b;

[0164] Step b: modify the resistance value of the series resistor B according to the length of the trunk line A in each row of the topology link of the same protocol type.

[0165] In implementation, when modifying the resistance value of the series resistor B, the resistance value of the series resistor B is modified by modifying the length of the trunk routing, and the length of each trunk routing is guaranteed to be equal as much as possible. Specifically, the difference between the trunk routing A of each row can be calculated, and optionally, the difference between the trunk routings adjacent to each other in sequence can be calculated. Taking Table 2 as an example, the difference between the trunk length 1A and the trunk length 2A is calculated, the difference between the trunk length 1A and the trunk length 3A is calculated, the difference between the trunk length 1A and the trunk length 4A is calculated, the difference between the trunk length 2A and the trunk length 3A is calculated, the difference between the trunk length 2A and the trunk length 4A is calculated, and the difference between the trunk length 3A and the trunk length 4A is calculated. According to each difference, the trunk length with the largest difference from each trunk length is determined. If the trunk lengths between rows differ greatly and exceed the set range, the value of the string resistance B corresponding to the trunk length with the largest difference among the trunk lengths is modified. For example, if the difference between trunk length 1A and other trunk lengths is the largest, the resistance value of the string resistance B corresponding to the row where trunk length 1A is located is modified, and then topology reconstruction and simulation are performed. If the signal quality does not meet the preset conditions, step a is entered.

[0166] Repeat the above steps until the signal quality meets the standard or the number of simulations reaches the set requirement.

[0167] During implementation, first find out the resistance value of the string resistance B corresponding to the trunk length with the largest difference from other trunk lengths, and then iteratively modify the resistance value of the string resistance B corresponding to the trunk length with the largest difference. If the number of iterations reaches a threshold or the signal quality meets the preset conditions, the process stops and the optimized topology link is obtained. Otherwise, the resistance value of the string resistance B modified last time is retained, and the iterative modification of the resistance values ​​of the string resistances A and C is returned until the number of iterations reaches a threshold or the signal quality meets the preset conditions.

[0168] like Figure 6 As shown, Figure 3 Taking the topological link in as an example, this embodiment also provides a method implementation process of topology optimization, which is specifically as follows:

[0169] Step 600, determining that the signal quality after simulation does not meet the judgment result of the preset condition;

[0170] Step 601, modify the resistance values ​​of the string resistor A and the string resistor C according to the modification rule corresponding to the judgment result;

[0171] Among them, the modification rules include resistance requirements, routing length requirements, etc.

[0172] Step 602: Determine whether the modification times have reached the maximum value or the modification rule has been traversed to completion. If so, execute step 603; otherwise, execute step 605.

[0173] The modification rules may be preset, for example, 5 modification rules may be preset, and the modification method of each modification rule may be different or the same.

[0174] Step 603, comparing the lengths of the trunk lines of the sub-topology links of the same protocol type;

[0175] For example, compare the lengths of trunk trace length 1A, trunk trace length 2A, trunk trace length 3A, and trunk trace length 4A;

[0176] Step 604, modifying the series resistance value corresponding to the trunk routing length with the largest difference from other trunk routing lengths;

[0177] The series resistance corresponding to the trunk line length refers to the series resistance on the trunk line corresponding to the intersection node between the trunk line and the branch line, and the trunk line corresponding to the intersection node represents the trunk line before the target signal is transmitted to the branch line. For example, if the trunk line length 1A is the largest difference from the lengths of other trunk lines, then the resistance value of the series resistance B between the trunk line length 1A and the branch line length 1A is modified.

[0178] Step 605: Reconstruct the topology link and perform simulation;

[0179] Step 606, determining whether the signal quality of the simulation signal meets a preset condition or the number of iterations reaches a threshold, if so, executing step 607, otherwise executing step 600;

[0180] Since the topology link will be rebuilt and simulated each time the component parameters are adjusted, the number of iterations can also be understood as the number of simulations.

[0181] Step 607: The simulation optimization ends.

[0182] In some embodiments, the simulation signal is generally presented by a waveform image, and its waveform is constructed based on the correspondence between time and amplitude. The present invention stores the signal waveform in the form of a data sequence of the correspondence between time and amplitude. The data sequence of time and amplitude can be judged according to the protocol to determine whether the waveform of the signal is correct. The signal quality judgment of this embodiment is based on the method of segmented calculation and processing of the digital sequence, and the signal quality of the simulation signal is determined specifically in the following manner:

[0183] First, a data sequence is determined according to the corresponding relationship between time and amplitude contained in the simulation signal;

[0184] Secondly, according to the variation rule of the simulation signal waveform, the data sequence is segmented to obtain a plurality of data segments;

[0185] In implementation, the time and amplitude data sequence is segmented. The segmentation point marks include but are not limited to the high and low levels of the signal and the signal period. Segmentation is performed at the high and low levels. If two consecutive segmentation points are at high or low levels, the time difference between them must be greater than one quarter of the period to ensure that they are not segmented by abnormal signals. The high and low levels and signal period values ​​of the signal are derived from the corresponding protocol regulations. Figure 7 As shown, this embodiment provides a waveform segmentation schematic diagram under an ideal state, in which the waveform is divided into low level, rising edge, high level, and falling edge; when the amplitude of the data sequence is higher than the high level threshold, it is a high level data segment, and when the amplitude is lower than the low level threshold, it is a low level data segment. Figures 8A-8B As shown, a schematic diagram of a problematic waveform provided by this embodiment is shown in FIG. Fig. 8A , the intersection of line 1 and the waveform is not available, and two consecutive segmentation points are both high level. At this time, it is necessary to ensure that the time difference between the two segmentation points is greater than 1 / 4 cycle. Therefore, the intersection of line 1 and the waveform will be ignored, and the segmentation point is determined to be at A to ensure the accuracy of segmentation processing. Figure 8B , the intersection of the dotted line and the waveform is unavailable, and two consecutive segmentation points are both low levels. At this time, it is necessary to ensure that the time difference between the two segmentation points is greater than 1 / 4 cycle, so the intersection of line 1 and the waveform will be ignored, and the segmentation point is determined at A to ensure the accuracy of segmentation processing. Because the intersection of the dotted line and the waveform will cause incorrect segmentation, it is necessary to ensure that the time difference between the segmentation points at the high level threshold (low level threshold) meets a quarter cycle.

[0186] Finally, the signal quality of the simulation signal is determined according to whether the characteristic parameters of the data sequences in different data segments meet the corresponding quality standards.

[0187] In implementation, the characteristics of data sequences of different data segments are different, and the characteristic parameters include but are not limited to: low level, rising edge, high level, falling edge, timing relationship, etc. For example, some data segments are low level, some data segments are high level, some data segments are rising edge, and some data segments are falling edge. In order to distinguish, the segmented data segments can be marked, for example, marked as low level, rising edge, high level and falling edge.

[0188] When the data segment is at a low level, the signal level can be judged, and the maximum and minimum values ​​in the low-level data segment can be calculated respectively to determine whether the maximum and minimum values ​​are within the signal standard range; similarly, when the data segment is at a high level, the signal level can be judged, and the maximum and minimum values ​​in the high-level data segment can be calculated respectively to determine whether the maximum and minimum values ​​are within the signal standard range (preset requirements), thereby determining whether the signal quality meets the standard requirements.

[0189] When the data segment is an edge (including rising edge and / or falling edge), the maximum time difference in the data segment of the rising edge and the difference sequence formed by the difference of adjacent amplitudes in the data segment of the rising edge can be calculated; the maximum time difference in the data segment of the falling edge and the difference sequence formed by the difference of adjacent amplitudes in the data segment of the falling edge can also be calculated. The maximum time difference is used to determine the edge slope. The edge slope value can be calculated according to the calculation formula of the edge slope (the difference between the high and low levels divided by the time difference), so as to determine whether the edge is within the range specified by the protocol. The difference sequence is a difference sequence obtained by subtracting the previous amplitude from the next amplitude in the adjacent amplitudes in the data segment of the edge, which can also be understood as a derivative or tangent operation on the data sequence of the data segment. The amplitude difference sequence is used to determine whether the edge is non-monotonic. When a negative number appears in the difference sequence of the rising edge or a positive number appears in the difference sequence of the falling edge, it indicates that the signal edge is non-monotonic.

[0190] Optionally, the timing relationship can also be determined by calculating the time difference between the rising and falling edge data segments of two signals with a timing relationship, such as data and clock signals, to determine whether the time difference is within the protocol requirements, thereby determining whether there is a signal timing problem.

[0191] like Figures 9A-9C As shown, this embodiment also provides a timing relationship diagram, in which the timing is represented by setup time and hold time, which refers to the time difference between the rising edge (falling edge) of the clock signal and the data signal, that is, the time difference between the two black dots in the figure. Fig. 9A The time difference between the rising edges is the setup time, and the time difference between the falling edges is the hold time. Fig. 9B The timing relationship can be expressed by the time difference between the rising edge of the clock and the falling edge of the data. The time difference between the two edges depends on the requirements of the protocol. Fig. 9C There are four time differences between the falling edges of the data signal and the clock signal, namely A, B, C, and D. C is the minimum time difference between the falling edges of the clock signal and the data signal. The timing relationship can be expressed by the minimum time difference.

[0192] Optionally, the signal quality judgment method in this embodiment may also be a method based on image recognition, which utilizes the image of the signal waveform to recognize and determine whether the signal quality meets a preset condition based on the recognition result.

[0193] like Fig.10As shown, the present embodiment further provides a method implementation flow for signal quality determination, wherein the signal quality is determined for waveform data 1 and waveform data 2 respectively, wherein waveform data 1 is segmented and marked according to high and low level values ​​and signal cycles to obtain high level segments, low level segments, rising edge segments and falling edge segments, and the maximum and minimum values ​​in the respective data segments of the high level segments and the low level segments are calculated for level determination to determine whether they meet the signal quality standard; the slope and difference sequence of the respective data segments of the rising edge segment and the falling edge segment are calculated for edge determination to determine whether they meet the signal quality standard; similarly, waveform data 2 is segmented and marked to obtain high level segments, low level segments, rising edge segments and falling edge segments, and the maximum and minimum values ​​in the respective data segments of the high level segments and the low level segments are calculated for level determination to determine whether they meet the signal quality standard; Flat segment, low level segment, rising edge segment and falling edge segment. For the high level segment and the low level segment, the maximum and minimum values ​​in their respective data segments are calculated for level judgment to determine whether they meet the signal quality standards. For the rising edge segment and the falling edge segment, the slope and difference sequence of their respective data segments are calculated for edge judgment to determine whether they meet the signal quality standards. The time difference between the rising edges of waveform data 1 and waveform data 2, or the time difference between the falling edges of waveform data 1 and waveform data 2, can also be calculated for timing judgment to determine whether they meet the signal quality standard range. If so, the signal simulation optimization process is terminated, otherwise the problem is marked and the simulation optimization process is returned to the simulation optimization process.

[0194] This embodiment can realize autonomous simulation and optimization of the low-speed signal topology of a hardware system and prompt topology risks through topology splitting and reconstruction, topology optimization based on priority setting, and signal waveform data segmentation calculation and processing, solving the problem that the existing low-speed signal simulation and optimization methods require manual operation by designers. This method can effectively balance the conflict between the short development time of the hardware system and the limited energy of the designers, and realize the rapid simulation of the low-speed signal topology.

[0195] This embodiment realizes autonomous insertion of parts that do not exist in the topology and can be used to optimize signal quality by means of topology splitting and reconstruction. The implementation of the topology splitting and reconstruction method is based on the topology information table and the topology optimization information table. The topology information table is used to store the original topology information extracted from the PCB file, and the topology optimization information table is used to reconstruct and optimize the topology for simulation. This embodiment also provides a topology optimization method based on priority setting. This method is based on certain low-speed signal topology simulation optimization experience. The optimization method is simple and can shorten the topology optimization time. This embodiment can also determine whether the signal quality meets the standard by performing segmented calculation processing on the signal waveform data. This method can achieve the judgment of signal quality based on simple comparison and calculation.

[0196] Based on the same inventive concept, an embodiment of the present invention also provides a topology link optimization device. Since the device is the device in the method in the embodiment of the present invention, and the principle of solving the problem by the device is similar to that of the method, the implementation of the device can refer to the implementation of the method, and the repeated parts will not be repeated.

[0197] like Fig.11 As shown, the device comprises:

[0198] A topology extraction unit 1100 is used to extract first topology information of a topology link of a target signal;

[0199] A topology reconstruction unit 1101 is used to add component parameters to the first topology information to generate second topology information, and use the second topology information to reconstruct the topology link of the target signal;

[0200] The topology optimizing unit 1102 is configured to optimize the reconstructed topology link by adjusting the component parameters in the second topology information to obtain the optimized topology link of the target signal.

[0201] As an optional implementation manner, the topology link includes at least one sub-topology link corresponding to a protocol type; the topology extraction unit 1100 is specifically used for:

[0202] According to the position relationship and routing information of the components in each sub-topology link, each sub-topology link is split into a trunk link and at least one branch link connected to the trunk link;

[0203] Extracting topology information of each sub-topology link according to the connection relationship between the trunk link of each sub-topology link and the branch link;

[0204] A topology information table is constructed according to the topology information of each sub-topology link, and the topology information table is determined as the first topology information of the topology link of the target signal.

[0205] As an optional embodiment, the device is used for:

[0206] Add the string resistance value and / or the routing length to the first topology information to generate second topology information;

[0207] By adjusting the string resistance value and / or the routing length in the second topology information, the reconstructed topology link is optimized to obtain the optimized topology link of the target signal.

[0208] As an optional implementation manner, the topology reconstruction unit 1101 is specifically used for:

[0209] Adding the resistance value of the series resistor to the first topology information generates the second topology information, and using the second topology information to reconstruct the topology link of the target signal; wherein the reconstructed topology link includes at least one sub-topology link corresponding to a protocol type;

[0210] The series resistance is located on the routing lines of any two devices in the sub-topology link; and / or,

[0211] The series resistance is located on the trunk routing corresponding to the intersection node between the trunk routing and the branch routing in the sub-topology link, and the trunk routing corresponding to the intersection node represents the trunk routing before the target signal is transmitted to the branch routing.

[0212] As an optional implementation manner, the topology optimization unit 1102 is specifically used for:

[0213] Simulating the reconstructed topology link to obtain a simulation signal;

[0214] According to the signal quality of the simulation signal, the component parameters in the second topology information are iteratively adjusted until the number of iterations reaches a threshold or the signal quality meets a preset condition, and the adjustment is stopped to obtain the optimized topology link.

[0215] As an optional implementation manner, the topology optimization unit 1102 is specifically configured to determine the signal quality of the simulation signal in the following manner:

[0216] Determining a data sequence according to a corresponding relationship between time and amplitude included in the simulation signal;

[0217] According to the variation rule of the simulation signal waveform, the data sequence is segmented to obtain a plurality of data segments;

[0218] The signal quality of the simulation signal is determined according to whether the characteristic parameters of the data sequences in different data segments meet the corresponding quality standards.

[0219] As an optional implementation manner, the topology optimizing unit 1102 is specifically configured to determine the component parameters to be adjusted in the second topology information in the following manner:

[0220] Determine the components to be adjusted according to the predefined priority order of the components;

[0221] According to the components to be adjusted, the parameters of the components to be adjusted in the second topology information are determined, and the reconstructed topology link is optimized by adjusting the component parameters.

[0222] Based on the same inventive concept, an embodiment of the present invention further provides an electronic device. Since the electronic device is the electronic device in the method in the embodiment of the present invention, and the principle of solving the problem by the electronic device is similar to that of the method, the implementation of the electronic device can refer to the implementation of the method, and the repeated parts will not be repeated.

[0223] like Fig.12 As shown, the electronic device includes a processor 1200 and a memory 1201, wherein the memory 1201 is used to store a program executable by the processor 1200, and the processor 1200 is used to read the program in the memory 1201 and perform the following steps:

[0224] Extracting first topology information of a topology link of a target signal;

[0225] Adding component parameters to the first topology information to generate second topology information, and using the second topology information to rebuild the topology link of the target signal;

[0226] The reconstructed topology link is optimized by adjusting the component parameters in the second topology information to obtain the optimized topology link of the target signal.

[0227] As an optional implementation manner, the topology link includes a sub-topology link corresponding to at least one protocol type; and the processor 1200 is specifically configured to execute:

[0228] According to the position relationship and routing information of the components in each sub-topology link, each sub-topology link is split into a trunk link and at least one branch link connected to the trunk link;

[0229] Extracting topology information of each sub-topology link according to the connection relationship between the trunk link of each sub-topology link and the branch link;

[0230] A topology information table is constructed according to the topology information of each sub-topology link, and the topology information table is determined as the first topology information of the topology link of the target signal.

[0231] As an optional implementation manner, the processor 1200 is specifically configured to execute:

[0232] Add the string resistance value and / or the routing length to the first topology information to generate second topology information;

[0233] By adjusting the string resistance value and / or the routing length in the second topology information, the reconstructed topology link is optimized to obtain the optimized topology link of the target signal.

[0234] As an optional implementation manner, the processor 1200 is specifically configured to execute:

[0235] Adding the resistance value of the series resistor to the first topology information generates the second topology information, and using the second topology information to reconstruct the topology link of the target signal; wherein the reconstructed topology link includes at least one sub-topology link corresponding to a protocol type;

[0236] The series resistance is located on the routing lines of any two devices in the sub-topology link; and / or,

[0237] The series resistance is located on the trunk routing corresponding to the intersection node between the trunk routing and the branch routing in the sub-topology link, and the trunk routing corresponding to the intersection node represents the trunk routing before the target signal is transmitted to the branch routing.

[0238] As an optional implementation manner, the processor 1200 is specifically configured to execute:

[0239] Simulating the reconstructed topology link to obtain a simulation signal;

[0240] According to the signal quality of the simulation signal, the component parameters in the second topology information are iteratively adjusted until the number of iterations reaches a threshold or the signal quality meets a preset condition, and the adjustment is stopped to obtain the optimized topology link.

[0241] As an optional implementation manner, the processor 1200 is specifically configured to determine the signal quality of the simulation signal in the following manner:

[0242] Determining a data sequence according to a corresponding relationship between time and amplitude included in the simulation signal;

[0243] According to the variation rule of the simulation signal waveform, the data sequence is segmented to obtain a plurality of data segments;

[0244] The signal quality of the simulation signal is determined according to whether the characteristic parameters of the data sequences in different data segments meet the corresponding quality standards.

[0245] As an optional implementation manner, the processor 1200 is specifically configured to determine the component parameters to be adjusted in the second topology information in the following manner:

[0246] Determine the components to be adjusted according to the predefined priority order of the components;

[0247] According to the components to be adjusted, the parameters of the components to be adjusted in the second topology information are determined, and the reconstructed topology link is optimized by adjusting the component parameters.

[0248] Based on the same inventive concept, an embodiment of the present disclosure provides a computer storage medium, the computer storage medium includes: a computer program code, when the computer program code is executed on a computer, the computer executes any of the topology link optimization methods discussed above. Since the principle of solving the problem by the above-mentioned computer storage medium is similar to that of the topology link optimization method, the implementation of the above-mentioned computer storage medium can refer to the implementation of the method, and the repeated parts will not be repeated.

[0249] In the specific implementation process, the computer storage medium may include: Universal Serial Bus Flash Drive (USB), mobile hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk, and other storage media that can store program codes.

[0250] Based on the same inventive concept, the embodiment of the present disclosure also provides a computer program product, which includes: computer program code, when the computer program code is run on a computer, the computer executes any of the topology link optimization methods discussed above. Since the principle of solving the problem by the above computer program product is similar to that of the topology link optimization method, the implementation of the above computer program product can refer to the implementation of the method, and the repeated parts will not be repeated.

[0251] The computer program product may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination thereof. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more conductors, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0252] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) containing computer-usable program code.

[0253] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that has the functions specified in one or more boxes.

[0254] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0255] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0256] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A topology link optimization method, characterized in that: The method includes: Extracting first topology information of a topology link of a target signal; Adding component parameters to the first topology information to generate second topology information, and using the second topology information to rebuild the topology link of the target signal; The reconstructed topology link is optimized by adjusting the component parameters in the second topology information to obtain the optimized topology link of the target signal.

2. The method according to claim 1, characterized in that The topology link includes at least one sub-topology link corresponding to a protocol type; the first topology information of the topology link for extracting the target signal includes: According to the position relationship and routing information of the components in each sub-topology link, each sub-topology link is split into a trunk link and at least one branch link connected to the trunk link; Extracting topology information of each sub-topology link according to the connection relationship between the trunk link of each sub-topology link and the branch link; A topology information table is constructed according to the topology information of each sub-topology link, and the topology information table is determined as the first topology information of the topology link of the target signal.

3. The method according to claim 1, characterized in that: include: Add the string resistance value and / or the routing length to the first topology information to generate second topology information; By adjusting the string resistance value and / or the routing length in the second topology information, the reconstructed topology link is optimized to obtain the optimized topology link of the target signal.

4. The method according to claim 1, characterized in that Adding component parameters to the first topology information to generate second topology information, and using the second topology information to reconstruct the topology link of the target signal, including: Adding the resistance value of the series resistor to the first topology information generates the second topology information, and using the second topology information to reconstruct the topology link of the target signal; wherein the reconstructed topology link includes at least one sub-topology link corresponding to a protocol type; The series resistance is located on the routing lines of any two devices in the sub-topology link; and / or, The series resistance is located on the trunk routing corresponding to the intersection node between the trunk routing and the branch routing in the sub-topology link, and the trunk routing corresponding to the intersection node represents the trunk routing before the target signal is transmitted to the branch routing.

5. The method according to claim 1, characterized in that The step of optimizing the reconstructed topology link by adjusting the component parameters in the second topology information to obtain the optimized topology link of the target signal includes: Simulating the reconstructed topology link to obtain a simulation signal; According to the signal quality of the simulation signal, the component parameters in the second topology information are iteratively adjusted until the number of iterations reaches a threshold or the signal quality meets a preset condition, and the adjustment is stopped to obtain the optimized topology link.

6. The method according to claim 5, characterized in that The signal quality of the simulated signal is determined by: Determining a data sequence according to a corresponding relationship between time and amplitude included in the simulation signal; According to the variation rule of the simulation signal waveform, the data sequence is segmented to obtain a plurality of data segments; The signal quality of the simulation signal is determined according to whether the characteristic parameters of the data sequences in different data segments meet the corresponding quality standards.

7. The method according to claim 1, characterized in that The component parameters to be adjusted in the second topology information are determined in the following manner: Determine the components to be adjusted according to the predefined priority order of the components; According to the components to be adjusted, the parameters of the components to be adjusted in the second topology information are determined, and the reconstructed topology link is optimized by adjusting the component parameters.

8. A topology link optimization device, characterized in that: The device includes: A topology extraction unit, used to extract first topology information of a topology link of a target signal; A topology reconstruction unit, configured to add component parameters to the first topology information to generate second topology information, and to use the second topology information to reconstruct a topology link of the target signal; The topology optimization unit is used to optimize the reconstructed topology link by adjusting the component parameters in the second topology information to obtain the optimized topology link of the target signal.

9. An electronic device, characterized in that: The electronic device comprises a processor and a memory, wherein the memory is used to store a program executable by the processor, and the processor is used to read the program in the memory and execute the steps of any one of the methods of claims 1 to 7.

10. A computer storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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